29 lines
515 B
Plaintext
29 lines
515 B
Plaintext
library ieee;
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use ieee.std_logic_1164.all;
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use work.genpackage.all;
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entity top is
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port (
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EQ : out std_logic;
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A : in std_logic_vector(12 downto 0);
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B : in std_logic_vector(12 downto 0) );
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end entity top;
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architecture gen of top is
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component CMP_EQ
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generic (
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width : integer );
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port (
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EQ : out std_logic;
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A : in std_logic_vector;
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B : in std_logic_vector );
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end component;
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begin
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I1: CMP_EQ
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generic map (
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width => 13 )
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port map (
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EQ => EQ,
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A => A,
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B => B );
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end architecture gen;
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