60 lines
6.5 KiB
HTML
60 lines
6.5 KiB
HTML
<html>
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<ul id="synthesis-menu" class="treeview" style="padding-left:12;">
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<li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">top_syn (synthesis)</b>
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<ul rel="open" style="font-size:small;">
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<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
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<ul rel="open">
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#compilerReport9" target="srrFrame" title="">Compiler Constraint Applicator</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport20" target="srrFrame" title="">Pre-mapping Report</a>
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<ul rel="open" >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport21" target="srrFrame" title="">Clock Summary</a> </li></ul></li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#mapperReport32" target="srrFrame" title="">Mapper Report</a>
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<ul rel="open" >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#timingReport33" target="srrFrame" title="">Timing Report</a>
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<ul rel="open" >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#performanceSummary34" target="srrFrame" title="">Performance Summary</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockRelationships35" target="srrFrame" title="">Clock Relationships</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#interfaceInfo36" target="srrFrame" title="">Interface Information</a>
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<ul >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#inputPorts37" target="srrFrame" title="">Input Ports</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#outputPorts38" target="srrFrame" title="">Output Ports</a> </li></ul></li>
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<li><a href="file:///#" target="srrFrame" title="">Detailed Report for Clocks</a>
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<ul >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport39" target="srrFrame" title="">Clock: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</a>
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<ul >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#startingSlack56" target="srrFrame" title="">Starting Points with Worst Slack</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#endingSlack57" target="srrFrame" title="">Ending Points with Worst Slack</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#worstPaths58" target="srrFrame" title="">Worst Path Information</a> </li></ul></li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport43" target="srrFrame" title="">Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport47" target="srrFrame" title="">Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport51" target="srrFrame" title="">Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport55" target="srrFrame" title="">Clock: System</a> </li></ul></li></ul></li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (22:49 15-Apr)</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (22:51 15-Apr)</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (22:51 15-Apr)</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#resourceUsage59" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (22:51 15-Apr)</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (22:48 15-Apr)</a>
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<ul >
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#UnconstrainedStartEndPointsCCK60" target="srrFrame" title="">Unconstrained Start/End Points</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#InapplicableconstraintsCCK61" target="srrFrame" title="">Inapplicable constraints</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ApplicableConstraintsWithIssuesCCK62" target="srrFrame" title="">Applicable constraints with issues</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ConstraintsWithMatchingWildcardExpressionsCCK63" target="srrFrame" title="">Constraints with matching wildcard expressions</a> </li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#LibraryReportCCK64" target="srrFrame" title="">Library Report</a> </li></ul></li>
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<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (22:52 15-Apr)</a> </li></ul></li> </ul>
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</li>
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</ul>
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