682 lines
35 KiB
Plaintext
682 lines
35 KiB
Plaintext
#OPTIONS:"|-layerid|0|-orig_srs|E:\\AbhishekV\\rising\\ethernet_tpsram_test\\synthesis\\synwork\\top_comp.srs|-top|top|-prodtype|synplify_pro|-infer_seqShift|-primux|-dspmac|-pqdpadd|-fixsmult|-sdff_counter|-divnmod|-nram|-actel|-I|E:\\AbhishekV\\rising\\ethernet_tpsram_test\\synthesis\\|-I|E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib|-sysv|-devicelib|E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\generic\\acg5.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREJTAGDEBUG_LIB|-lib|COREJTAGDEBUG_LIB|-lib|COREJTAGDEBUG_LIB|-lib|COREJTAGDEBUG_LIB|-lib|work|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|work|-lib|work|-lib|work|-lib|COREAPB3_LIB|-lib|COREAPB3_LIB|-lib|COREAPB3_LIB|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
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#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\bin64\\c_ver.exe":1745943498
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#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\generic\\acg5.v":1745932376
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#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\hypermods.v":1745942006
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#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_objects.v":1745942006
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#CUR:"E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\vlog\\scemi_pipes.svh":1745942006
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\syn_comps.v":1776394635
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_graytobinconv.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_nstagessync.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_async.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_sync.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_fwft.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_sync_scntr.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":1776257511
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\COREFIFO.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREJTAGDEBUG\\4.0.100\\core\\corejtagdebug_bufd.v":1776075072
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREJTAGDEBUG\\4.0.100\\core\\corejtagdebug_uj_jtag.v":1776075072
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREJTAGDEBUG\\4.0.100\\core\\corejtagdebug_ujtag_wrapper.v":1776075072
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREJTAGDEBUG\\4.0.100\\core\\corejtagdebug.v":1776075072
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREJTAGDEBUG_C0\\COREJTAGDEBUG_C0.v":1776096661
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\spi_clockmux.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\spi_chanctrl.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\spi_fifo.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\spi_rf.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\spi_control.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\spi.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORESPI\\5.2.104\\rtl\\vlog\\core\\corespi.v":1776075075
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CORESPI_0\\CORESPI_0.v":1776096664
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORETSE\\4.0.124\\rtl\\vlog\\core_evaluation\\CoreTSE.v":1776075082
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORETSE\\4.0.124\\rtl\\vlog\\core_evaluation\\include.v":1776075082
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORETSE\\4.0.124\\rtl\\vlog\\core_evaluation\\include.v":1776075082
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CORETSE_0\\CORETSE_0.v":1776096672
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CoreAPB3\\4.2.100\\rtl\\vlog\\core\\coreapb3_muxptob3.v":1776075074
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CoreAPB3\\4.2.100\\rtl\\vlog\\core\\coreapb3_iaddr_reg.v":1776075074
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CoreAPB3\\4.2.100\\rtl\\vlog\\core\\coreapb3.v":1776075074
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreAPB3_0\\CoreAPB3_0.v":1776096663
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\Clock_gen.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\Rx_async.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\Tx_async.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\fifo_256x8_g5.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\CoreUART.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\CoreUARTapb.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0.v":1776096673
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\Core_reset_pf\\Core_reset_pf_0\\core\\corereset_pf.v":1776096662
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\Core_reset_pf\\Core_reset_pf.v":1776096662
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_hart_cfg_pkg.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_pkg.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\hart_merged\\miv_rv32_hart_merged.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_subsys_pkg.v":1766140232
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\subsys_merged\\miv_rv32_subsys_merged.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\memory\\miv_rv32_ram_singleport_lp.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\memory\\miv_rv32_ram_singleport_lp_ecc.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\MIV_RV32_C0\\MIV_RV32_C0_0\\rtl\\miv_rv32.v":1776096674
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\MIV_RV32_C0\\MIV_RV32_C0.v":1776096674
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_CCC_0\\PF_CCC_0_0\\PF_CCC_0_PF_CCC_0_0_PF_CCC.v":1776096714
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_CCC_0\\PF_CCC_0.v":1776096714
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORECDR4_CNTL_TIP\\2.0.100\\rtl\\vlog\\core\\corecdr4_cntl_tip.v":1776088270
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_LANECTRL_OVERLAY_0\\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":1776096730
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_RX_N_0\\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":1776096736
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_RX_P_0\\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":1776096742
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_TX_0\\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":1776096747
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_LANECTRL_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096749
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_LANECTRL_0\\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v":1776096749
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_C0.v":1776096750
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREDELAYCODE_TIP\\2.1.100\\rtl\\vlog\\core\\CoreDelayCode_TIP.v":1776087985
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_CCC_0\\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":1776096763
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_CLK_DIV_0\\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v":1776096764
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096766
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v":1776096766
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_IOD_CDR_CCC_C0.v":1776096766
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776384266
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776384266
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\SSDetect.v":1776096660
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776394591
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0_0\\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":1776096718
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0.v":1776096718
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776394606
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#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
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#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
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#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block":1776394710
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#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
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#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block":1776394727
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#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
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#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block":1776394728
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#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
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#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block":1776394730
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#numinternalfiles:4
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#defaultlanguage:verilog
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0 "E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog
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1 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v" verilog
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2 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v" verilog
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3 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v" verilog
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4 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v" verilog
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5 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v" verilog
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6 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v" verilog
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7 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v" verilog
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8 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v" verilog
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9 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v" verilog
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10 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v" verilog
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11 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v" verilog
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12 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v" verilog
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13 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v" verilog
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14 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v" verilog
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15 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v" verilog
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16 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" verilog
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17 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" verilog
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18 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" verilog
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19 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" verilog
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20 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" verilog
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21 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" verilog
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22 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" verilog
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23 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v" verilog
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24 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v" verilog
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25 * "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v" verilog
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26 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v" verilog
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27 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" verilog
|
|
28 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" verilog
|
|
29 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" verilog
|
|
30 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v" verilog
|
|
31 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v" verilog
|
|
32 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v" verilog
|
|
33 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v" verilog
|
|
34 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v" verilog
|
|
35 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v" verilog
|
|
36 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v" verilog
|
|
37 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v" verilog
|
|
38 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v" verilog
|
|
39 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v" verilog
|
|
40 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v" verilog
|
|
41 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v" verilog
|
|
42 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v" verilog
|
|
43 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v" verilog
|
|
44 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v" verilog
|
|
45 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v" verilog
|
|
46 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v" verilog
|
|
47 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v" verilog
|
|
48 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v" verilog
|
|
49 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" verilog
|
|
50 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v" verilog
|
|
51 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v" verilog
|
|
52 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v" verilog
|
|
53 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v" verilog
|
|
54 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v" verilog
|
|
55 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v" verilog
|
|
56 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" verilog
|
|
57 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v" verilog
|
|
58 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v" verilog
|
|
59 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v" verilog
|
|
60 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v" verilog
|
|
61 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v" verilog
|
|
62 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v" verilog
|
|
63 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v" verilog
|
|
64 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v" verilog
|
|
65 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v" verilog
|
|
66 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v" verilog
|
|
67 "E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v" verilog
|
|
68 "E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v" verilog
|
|
69 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v" verilog
|
|
70 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v" verilog
|
|
71 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v" verilog
|
|
#Dependency Lists(Uses List)
|
|
0 -1
|
|
1 -1
|
|
2 -1
|
|
3 2 1
|
|
4 -1
|
|
5 -1
|
|
6 -1
|
|
7 -1
|
|
8 7
|
|
9 6 5 8 4 3
|
|
10 9
|
|
11 -1
|
|
12 11
|
|
13 -1
|
|
14 11 12 13
|
|
15 14
|
|
16 -1
|
|
17 16
|
|
18 -1
|
|
19 -1
|
|
20 -1
|
|
21 19 20 18 17
|
|
22 21
|
|
23 22
|
|
24 25
|
|
25 25
|
|
26 24 25
|
|
27 -1
|
|
28 -1
|
|
29 27 28
|
|
30 29
|
|
31 -1
|
|
32 -1
|
|
33 -1
|
|
34 -1
|
|
35 31 33 32 34
|
|
36 35
|
|
37 36
|
|
38 -1
|
|
39 38
|
|
40 -1
|
|
41 -1
|
|
42 41 40
|
|
43 -1
|
|
44 43 42 45 46
|
|
45 -1
|
|
46 -1
|
|
47 44
|
|
48 47
|
|
49 0
|
|
50 49
|
|
51 -1
|
|
52 0
|
|
53 0
|
|
54 0
|
|
55 0
|
|
56 -1
|
|
57 56 0
|
|
58 51 52 53 54 55 57
|
|
59 -1
|
|
60 0
|
|
61 0
|
|
62 -1
|
|
63 62 0
|
|
64 60 61 59 63
|
|
65 -1
|
|
66 65
|
|
67 -1
|
|
68 -1
|
|
69 0
|
|
70 69
|
|
71 39 30 10 15 23 26 37 68 48 50 70 58 64 66 67
|
|
#Dependency Lists(Users Of)
|
|
0 49 52 53 54 55 57 60 61 63 69
|
|
1 3
|
|
2 3
|
|
3 9
|
|
4 9
|
|
5 9
|
|
6 9
|
|
7 8
|
|
8 9
|
|
9 10
|
|
10 71
|
|
11 12 14
|
|
12 14
|
|
13 14
|
|
14 15
|
|
15 71
|
|
16 17
|
|
17 21
|
|
18 21
|
|
19 21
|
|
20 21
|
|
21 22
|
|
22 23
|
|
23 71
|
|
24 26
|
|
25 24 25 26
|
|
26 71
|
|
27 29
|
|
28 29
|
|
29 30
|
|
30 71
|
|
31 35
|
|
32 35
|
|
33 35
|
|
34 35
|
|
35 36
|
|
36 37
|
|
37 71
|
|
38 39
|
|
39 71
|
|
40 42
|
|
41 42
|
|
42 44
|
|
43 44
|
|
44 47
|
|
45 44
|
|
46 44
|
|
47 48
|
|
48 71
|
|
49 50
|
|
50 71
|
|
51 58
|
|
52 58
|
|
53 58
|
|
54 58
|
|
55 58
|
|
56 57
|
|
57 58
|
|
58 71
|
|
59 64
|
|
60 64
|
|
61 64
|
|
62 63
|
|
63 64
|
|
64 71
|
|
65 66
|
|
66 71
|
|
67 71
|
|
68 71
|
|
69 70
|
|
70 71
|
|
71 -1
|
|
#Design Unit to File Association
|
|
module work APBM 0
|
|
module work APBS 0
|
|
module work BANKCTRLM 0
|
|
module work BANKCTRL_GPIO 0
|
|
module work BANKCTRL_HSIO 0
|
|
module work BANKEN 0
|
|
module work CRN_COMMON 0
|
|
module work CRN_INT 0
|
|
module work CRYPTO 0
|
|
module work CRYPTO_SOC 0
|
|
module work DEBUG 0
|
|
module work DLL 0
|
|
module work DRI 0
|
|
module work ENFORCE 0
|
|
module work GLITCHDETECT 0
|
|
module work GPSS_COMMON 0
|
|
module work HS_IO_CLK 0
|
|
module work ICB_BANKCLK 0
|
|
module work ICB_CLKDIVDELAY 0
|
|
module work ICB_CLKDIV 0
|
|
module work ICB_CLKINT 0
|
|
module work ICB_CLKSTOP_EN 0
|
|
module work ICB_CLKSTOP 0
|
|
module work ICB_INT 0
|
|
module work ICB_MUXING 0
|
|
module work ICB_NGMUX 0
|
|
module work INIT 0
|
|
module work IOD 0
|
|
module work LANECTRL 0
|
|
module work LANERST 0
|
|
module work OSC_RC160MHZ 0
|
|
module work OSC_RC200MHZ 0
|
|
module work OSC_RC2MHZ 0
|
|
module work PCIE_COMMON 0
|
|
module work PCIE 0
|
|
module work PF_SPI 0
|
|
module work PLL 0
|
|
module work QUADRST_PCIE 0
|
|
module work QUADRST 0
|
|
module work SCB 0
|
|
module work SYSCTRL_RESET_STATUS 0
|
|
module work SYSRESET 0
|
|
module work SYS_SERVICES 0
|
|
module work TAMPER 0
|
|
module work TVS 0
|
|
module work TX_PLL 0
|
|
module work UPROM 0
|
|
module work USPI 0
|
|
module work VOLTAGEDETECT 0
|
|
module work VREFBANKDYN 0
|
|
module work VREFCTRL 0
|
|
module work XCVR_64B6XB 0
|
|
module work XCVR_8B10B 0
|
|
module work XCVR_APB_LINK 0
|
|
module work XCVR_APB_LINK_V 0
|
|
module work XCVR_APB_LINK_V2 0
|
|
module work XCVR_DUAL_PCS 0
|
|
module work XCVR_PIPE_AXI0 0
|
|
module work XCVR_PIPE_AXI1 0
|
|
module work XCVR_PIPE 0
|
|
module work XCVR_PMA 0
|
|
module work XCVR_REF_CLK_N 0
|
|
module work XCVR_REF_CLK_P 0
|
|
module work XCVR_REF_CLK 0
|
|
module work XCVR_TEST 0
|
|
module work XCVR_VV 0
|
|
module work XCVR 0
|
|
module work CORELNKTMR_V 0
|
|
module work PFSOC_SCSM 0
|
|
module work MCHP_BLIC 0
|
|
module work CLKBUF_DIFF 0
|
|
module work CLKBUF_DIFF_ODT 0
|
|
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv 1
|
|
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync 2
|
|
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_async 3
|
|
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_sync 4
|
|
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft 5
|
|
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr 6
|
|
module work COREFIFO_C0_COREFIFO_C0_0_LSRAM_top 7
|
|
module work COREFIFO_C0_COREFIFO_C0_0_ram_wrapper 8
|
|
module work COREFIFO_C0_COREFIFO_C0_0_COREFIFO 9
|
|
module work COREFIFO_C0 10
|
|
module work COREJTAGDEBUG_C0 15
|
|
module work CORESPI_0 23
|
|
module work CORETSE 24
|
|
module work CTSE_SELF_DESTRUCT 24
|
|
module work CTSE_CORETSE_TOP 24
|
|
module work CTSE_RX4096X36_PF 24
|
|
module work CTSE_PF_RxTPSRAM_7 24
|
|
module work CTSE_PF_RxTPSRAM_8 24
|
|
module work CTSE_PF_RxTPSRAM_9 24
|
|
module work CTSE_PF_RxTPSRAM_10 24
|
|
module work CTSE_PF_RxTPSRAM_11 24
|
|
module work CTSE_PF_RxTPSRAM_12 24
|
|
module work CTSE_PF_RxTPSRAM_13 24
|
|
module work CTSE_PF_RxTPSRAM_14 24
|
|
module work CTSE_TX2048X40_PF 24
|
|
module work CTSE_PF_TxTPSRAM_6 24
|
|
module work CTSE_PF_TxTPSRAM_7 24
|
|
module work CTSE_PF_TxTPSRAM_8 24
|
|
module work CTSE_PF_TxTPSRAM_9 24
|
|
module work CTSE_PF_TxTPSRAM_10 24
|
|
module work CTSE_PF_TxTPSRAM_11 24
|
|
module work CTSE_PF_TxTPSRAM_12 24
|
|
module work CTSE_PF_TxTPSRAM_13 24
|
|
module work CTSE_RX8192X36_PF2 24
|
|
module work CTSE_PF2_RxRAM_ECC_7 24
|
|
module work CTSE_PF2_RxRAM_ECC_8 24
|
|
module work CTSE_PF2_RxRAM_ECC_9 24
|
|
module work CTSE_PF2_RxRAM_ECC_10 24
|
|
module work CTSE_PF2_RxRAM_ECC_11 24
|
|
module work CTSE_PF2_RxRAM_ECC_12 24
|
|
module work CTSE_PF2_RxRAM_ECC_13 24
|
|
module work CTSE_PF2_RxRAM_ECC_14 24
|
|
module work CTSE_TX4096X40_PF2 24
|
|
module work CTSE_PF2_TxRAM_ECC_6 24
|
|
module work CTSE_PF2_TxRAM_ECC_7 24
|
|
module work CTSE_PF2_TxRAM_ECC_8 24
|
|
module work CTSE_PF2_TxRAM_ECC_9 24
|
|
module work CTSE_PF2_TxRAM_ECC_10 24
|
|
module work CTSE_PF2_TxRAM_ECC_11 24
|
|
module work CTSE_PF2_TxRAM_ECC_12 24
|
|
module work CTSE_PF2_TxRAM_ECC_13 24
|
|
module work CTSE_RX4096X36_RTG4 24
|
|
module work CTSE_RXMEM_7 24
|
|
module work CTSE_RXMEM_8 24
|
|
module work CTSE_RXMEM_9 24
|
|
module work CTSE_RXMEM_10 24
|
|
module work CTSE_RXMEM_11 24
|
|
module work CTSE_RXMEM_12 24
|
|
module work CTSE_RXMEM_13 24
|
|
module work CTSE_RXMEM_14 24
|
|
module work CTSE_TX2048X40_RTG4 24
|
|
module work CTSE_TXMEM_6 24
|
|
module work CTSE_TXMEM_7 24
|
|
module work CTSE_TXMEM_8 24
|
|
module work CTSE_TXMEM_9 24
|
|
module work CTSE_TXMEM_10 24
|
|
module work CTSE_TXMEM_11 24
|
|
module work CTSE_TXMEM_12 24
|
|
module work CTSE_TXMEM_13 24
|
|
module work CTSE_CLKRST 24
|
|
module work CTSE_TSMAC_TOP 24
|
|
module work CTSE_TX2048X40 24
|
|
module work CTSE_RX4096X36 24
|
|
module work CTSE_MSGMII_CORE 24
|
|
module work CTSE_ECC 24
|
|
module work CTSE_REGISTERSLICE 24
|
|
module work CTSE_MAPBE_HST_CNV 24
|
|
module work CTSE_DECODER 24
|
|
module work CTSE_TSM_SYSREG 24
|
|
module work OiOI1 24
|
|
module work CTSE_PE_MCXMAC 24
|
|
module work CTSE_SIB_SYNC_PULSE 24
|
|
module work CTSE_PEMSTAT 24
|
|
module work CTSE_MMCXWOL 24
|
|
module work CTSE_SIB_SYNC_2FLP 24
|
|
module work CTSE_SI_SAL 24
|
|
module work CTSE_AMCXTFIF_FAB 24
|
|
module work CTSE_AMCXTFIF_SYS 24
|
|
module work CTSE_AMCXRFIF_FAB 24
|
|
module work CTSE_AMCXRFIF_SYS 24
|
|
module work CTSE_AMCXTFIF_WTM 24
|
|
module work CTSE_AMCXFIF_HST 24
|
|
module work CTSE_AMCXFIF_CLKRST 24
|
|
module work CTSE_PEMSTAT_LINC_ECC 24
|
|
module work CTSE_MSGMII_CNVRXI 24
|
|
module work CTSE_MSGMII_CNVRXO 24
|
|
module work CTSE_MSGMII_CNVTXI 24
|
|
module work CTSE_MSGMII_CNVTXO 24
|
|
module work CTSE_MSGMII_TBI 24
|
|
module work CTSE_MSGMII_PEANX_TOP 24
|
|
module work CTSE_PEANX_SYNC 24
|
|
module work CTSE_PETEX_TOP 24
|
|
module work CTSE_PEREX_PMA 24
|
|
module work CTSE_PEREX_PCS 24
|
|
module work CTSE_PETBM 24
|
|
module work CTSE_PETCR 24
|
|
module work CTSE_PE_MCXMAC_CORE 24
|
|
module work CTSE_PEMGT 24
|
|
module work CTSE_PEHST 24
|
|
module work CTSE_PECAR 24
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module work CTSE_PETMC_TOP 24
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module work CTSE_PETFN_TOP 24
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module work CTSE_PERFN_TOP 24
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module work CTSE_PERMC_TOP 24
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module work CTSE_PECRC 24
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module work CTSE_PEMSTAT_CNTRL 24
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module work CTSE_PEMSTAT_STORE 24
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module work CTSE_PEMSTAT_EIM 24
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module work CTSE_PEMSTAT_LADD 24
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module work CTSE_PEMSTAT_LINC 24
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module work CTSE_PEMSTAT_SADD 24
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module work CTSE_PEMSTAT_SINC 24
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module work CTSE_PEMSTAT_SINCHD 24
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module work CTSE_PEMSTAT_SINCNF 24
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module work CTSE_R10B8B 24
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module work CTSE_T8B10B 24
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module work CTSE_REGSLICEFULL 24
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module work CORETSE_0 26
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module work CoreAPB3_0 30
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module work CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen 31
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module work CoreUARTapb_0_CoreUARTapb_0_0_Rx_async 32
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module work CoreUARTapb_0_CoreUARTapb_0_0_Tx_async 33
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module work CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8 34
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module work CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256 34
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module work CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5 34
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module work CoreUARTapb_0_CoreUARTapb_0_0_COREUART 35
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module work CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb 36
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module work CoreUARTapb_0 37
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module work Core_reset_pf_Core_reset_pf_0_CORERESET_PF 38
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module work Core_reset_pf 39
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package work miv_rv32_hart_cfg_pkg 40
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package work miv_rv32_pkg 41
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module work miv_rv32_common_buffer_behav 42
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package work work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit 42
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module work miv_rv32_bcu 42
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module work miv_rv32_hart 42
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module work miv_rv32_fetch_unit 42
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module work miv_rv32_lsu 42
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module work miv_rv32_expipe 42
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module work miv_rv32_csr_decode 42
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module work miv_rv32_csr_privarch 42
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module work miv_rv32_priv_irq 42
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module work miv_rv32_csr_gpr_state_reg 42
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module work miv_rv32_gpr 42
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module work miv_rv32_gpr_ram 42
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module work miv_rv32_gpr_ram_init 42
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module work miv_rv32_gpr_ram_mux 42
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module work miv_rv32_gpr_ecc_enc_dec 42
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module work miv_rv32_gpr_ram_array 42
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module work miv_rv32_irq_reg 42
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module work miv_rv32_idecode 42
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module work miv_rv32_exu 42
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module work miv_rv32_mul 42
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module work miv_rv32_fpnew_top 42
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module work miv_rv32_ifu_iab 42
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module work miv_rv32_bistdualdata_behav 42
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module work miv_rv32_bistmux 42
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module work miv_rv32_bistdual_behav 42
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module work miv_rv32_bistdual_eccw 42
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module work miv_rv32_bist_err_inject 42
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module work miv_rv32_bist_ecc 42
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module work miv_rv32_bistdual_err_mask 42
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module work miv_rv32_bistdual_pl_enable 42
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module work miv_rv32_bistdual_ram_init 42
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module work miv_rv32_bistdual_ram_stabilizer 42
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module work miv_rv32_logic_mux_behav_v2 42
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module work miv_rv32_bist_decode 42
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module work miv_rv32_bist_ecc_empty 42
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module work miv_rv32_bist_ecc_core 42
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module work miv_rv32_bist_ecc_write 42
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module work miv_rv32_bist_ecc_read 42
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module work miv_rv32_bist_pipeline 42
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module work miv_rv32_bist_template_dual_behav 42
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module work miv_rv32_ram_dport_reg 42
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module work miv_rv32_dpr_hqa_dual_storage_bistw_behav 42
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module work miv_rv32_dpr_hqa_dual_storage_rbcw 42
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module work miv_rv32_gpr_ecc_bist_template 42
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module work miv_rv32_gpr_ecc_enc_dec_bistw_behav 42
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module work miv_rv32_fpnew_opgroup_block 42
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module work miv_rv32_rr_arb_tree 42
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module work miv_rv32_control_mvp 42
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module work miv_rv32_iteration_div_sqrt_mvp 42
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module work miv_rv32_div_sqrt_top_mvp 42
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module work miv_rv32_preprocess_mvp 42
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module work miv_rv32_nrbd_nrsc_mvp 42
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module work miv_rv32_norm_div_sqrt_mvp 42
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module work miv_rv32_fpnew_sdotp_multi_wrapper 42
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module work miv_rv32_fpnew_sdotp_multi 42
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module work miv_rv32_fpnew_classifier 42
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module work miv_rv32_lzc 42
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module work miv_rv32_fpnew_rounding 42
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module work miv_rv32_fpnew_cast_multi 42
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module work miv_rv32_fpnew_divsqrt_multi 42
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module work miv_rv32_fpnew_fma 42
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module work miv_rv32_fpnew_fma_multi 42
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module work miv_rv32_fpnew_noncomp 42
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module work miv_rv32_fpnew_opgroup_fmt_slice 42
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module work miv_rv32_fpnew_opgroup_multifmt_slice 42
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module work miv_rv32_fpnew_divsqrt_th_32 42
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module work miv_rv32_popcount 42
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module work miv_rv32_pa_fdsu_top 42
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module work miv_rv32_pa_fpu_dp 42
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module work miv_rv32_pa_fpu_frbus 42
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module work miv_rv32_gated_clk_cell 42
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module work miv_rv32_pa_fdsu_ctrl 42
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module work miv_rv32_pa_fdsu_ff1 42
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module work miv_rv32_pa_fdsu_pack_single 42
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module work miv_rv32_pa_fdsu_prepare 42
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module work miv_rv32_pa_fdsu_round_single 42
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module work miv_rv32_pa_fdsu_special 42
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module work miv_rv32_pa_fdsu_srt_single 42
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module work miv_rv32_pa_fpu_src_type 42
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package work miv_rv32_subsys_pkg 43
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package work work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit 44
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module work miv_rv32_ipcore 44
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module work miv_rv32_subsys_debug 44
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module work miv_rv32_subsys_interconnect 44
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module work miv_rv32_subsys_apb_initiator 44
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module work miv_rv32_subsys_tcm_tas_apb_target 44
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module work miv_rv32_subsys_tcm 44
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module work miv_rv32_subsys_axi_initiator 44
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module work miv_rv32_subsys_ahb_initiator 44
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module work miv_rv32_subsys_udma 44
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module work miv_rv32_subsys_mtime_irq 44
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module work miv_rv32_subsys_icache 44
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module work miv_rv32_buffer 44
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module work miv_rv32_subsys_regs 44
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module work miv_rv32_rr_pri_arb 44
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module work miv_rv32_strb_to_addr 44
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module work miv_rv32_axi_rchan 44
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module work miv_rv32_axi_wchan 44
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module work miv_rv32_axi_egress_buffer 44
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module work miv_rv32_axi_egress_slip_buffer 44
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module work miv_rv32_axi_ingress_buffer 44
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module work miv_rv32_axi_xaddr_buffer 44
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module work miv_rv32_axi_xaddr_buffer_slot 44
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module work miv_rv32_fixed_arb 44
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module work miv_rv32_ram_singleport_addreg 44
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module work miv_rv32_ram_singleport_lp_ecc 46
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module work miv_rv32_ram_singleport_lp 45
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module work miv_rv32_bootrom 44
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module work miv_rv32_icache_ram_init 44
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module work miv_rv32_icache_ram_mux 44
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module work miv_rv32_icache_array 44
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module work miv_rv32_debug_dtm_jtag 44
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module work miv_rv32_debug_fifo 44
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module work miv_rv32_debug_du 44
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module work miv_rv32_debug_sba 44
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module work MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32 47
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module work MIV_RV32_C0 48
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module work PF_CCC_0_PF_CCC_0_0_PF_CCC 49
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module work PF_CCC_0 50
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module work CORECDR4_CNTL_TIP 51
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module work PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD 52
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module work PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD 53
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module work PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD 54
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module work PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD 55
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module work PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC 56
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module work PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL 57
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module work PF_IOD_CDR_C0 58
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module work COREDELAYCODE_TIP 59
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module work PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC 60
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module work PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV 61
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|
module work PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC 62
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|
module work PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL 63
|
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module work PF_IOD_CDR_CCC_C0 64
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module work PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM 65
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module work PF_TPSRAM_C0 66
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module work SSDetect 67
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module work fifo_to_tpsram_bridge 68
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|
module work pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR 69
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module work pf_init_monitor_0 70
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|
module work top 71
|
|
module COREJTAGDEBUG_LIB corejtagdebug_bufd 11
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|
module COREJTAGDEBUG_LIB COREJTAGDEBUG_UJ_JTAG 12
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|
module COREJTAGDEBUG_LIB UJTAG_WRAPPER 13
|
|
module COREJTAGDEBUG_LIB COREJTAGDEBUG 14
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|
module CORESPI_LIB spi_clockmux 16
|
|
module CORESPI_LIB spi_chanctrl 17
|
|
module CORESPI_LIB spi_fifo 18
|
|
module CORESPI_LIB spi_rf 19
|
|
module CORESPI_LIB spi_control 20
|
|
module CORESPI_LIB spi 21
|
|
module CORESPI_LIB CORESPI 22
|
|
module COREAPB3_LIB COREAPB3_MUXPTOB3 27
|
|
module COREAPB3_LIB coreapb3_iaddr_reg 28
|
|
module COREAPB3_LIB CoreAPB3 29
|
|
|
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#identified top module
|
|
top_module top
|