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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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1378
synthesis/dm/layer0.xdm
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1335
synthesis/rpt_top.areasrr
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1338
synthesis/rpt_top_areasrr.htm
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2
synthesis/run_options.txt
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@@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version V-2023.09M-5
#-- Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\run_options.txt
#-- Written on Wed Apr 15 22:44:56 2026
#-- Written on Fri Apr 17 08:27:18 2026
#project files

157
synthesis/syng0a42304 Normal file
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@@ -0,0 +1,157 @@
-- $Header: //synplicity/map400rc/mappers/xilinx/lib/gen_spartan3/cmp_eq.vhd#1 $
library ieee;
use ieee.std_logic_1164.all;
entity eq_element is
port(a0, b0, a1, b1, ltin : in std_logic;
ltout: out std_logic);
end eq_element;
architecture eqn of eq_element is
signal t1 : std_logic;
component MUXCY_L
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
--attribute syn_black_box of MUXCY_L : component is true;
begin
t1 <= (a1 xnor b1) and (a0 xnor b0);
mux_inst : MUXCY_L
port map(S => t1,
LO => ltout,
CI => ltin,
DI => '1');
end eqn;
library ieee;
use ieee.std_logic_1164.all;
entity eq_element_onebit is
port(a0, b0, ltin : in std_logic;
ltout: out std_logic);
end eq_element_onebit;
architecture eqn of eq_element_onebit is
signal t1 : std_logic;
component MUXCY_L
port (
LO : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
--attribute syn_black_box of MUXCY_L : component is true;
begin
t1 <= (a0 xnor b0);
mux_inst : MUXCY_L
port map(S => t1,
LO => ltout,
CI => ltin,
DI => '1');
end eqn;
library ieee;
use ieee.std_logic_1164.all;
entity CMP_EQ is
generic(width : integer :=1);
port(A: in std_logic_vector(width -1 downto 0);
B: in std_logic_vector(width -1 downto 0);
EQ : out std_logic);
end CMP_EQ;
architecture cell_level of CMP_EQ is
function func_error(eq_width : integer) return string is
begin
if ((eq_width >= 12) and (eq_width <= 64)) then
return("");
else
return("error");
end if;
end func_error;
attribute generator_report : string;
attribute generator_report of cell_level : architecture is func_error(width);
constant iteration : integer := (width)/2;
constant remainder : integer := (width) mod 2;
signal data_tmp : std_logic_vector (width - 1 downto 0);
signal NEQ : std_logic;
component eq_element is
port(a0, b0, a1, b1, ltin: in std_logic;
ltout : out std_logic);
end component;
component eq_element_onebit is
port(a0, b0, ltin: in std_logic;
ltout : out std_logic);
end component;
begin
U0 : if( width > 1) generate
begin
U01 : eq_element
port map(
a0 => A(0),
b0 => B(0),
a1 => A(1),
b1 => B(1),
ltin => '0',
ltout => data_tmp(0));
end generate;
U1 : if( width = 1) generate
begin
NEQ <= A(0) xnor B(0);
end generate;
U2 : for bit_index in 1 to (iteration - 1) generate
begin
U21 : eq_element
port map(
a0 => A(2*bit_index),
b0 => B(2*bit_index),
a1 => A(2*bit_index + 1),
b1 => B(2*bit_index + 1),
ltin => data_tmp(bit_index - 1),
ltout => data_tmp(bit_index));
end generate;
U3 : if( remainder = 1 and width > 1) generate
begin
U31 : eq_element_onebit
port map(
a0 => A(width -1),
b0 => B(width - 1),
ltin =>data_tmp(iteration - 1),
ltout => NEQ);
end generate;
U4 : if(remainder = 0 and width > 1) generate
begin
NEQ <= data_tmp(iteration - 1);
end generate;
U5: EQ <= not(NEQ);
end cell_level;

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synthesis/synlog/report/metrics.db
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2
synthesis/synlog/report/top_compiler_errors.txt Normal file
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@@ -0,0 +1,2 @@
@E: CG389 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v":109:38:109:51|Reference to undefined module PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM

2
synthesis/synlog/report/top_compiler_notes.txt
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@@ -226,7 +226,7 @@
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|Trying to extract state machine for register state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":65:4:65:9|Trying to extract state machine for register state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":286:0:286:5|Trying to extract state machine for register rx_state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Trying to extract state machine for register xmit_state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Trying to extract state machine for register mtx_state.

4
synthesis/synlog/report/top_compiler_runstatus.xml
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@@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Real Time">
<data>00h:02m:53s</data>
<data>00h:04m:18s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1776273469</data>
<data type="timestamp">1776394897</data>
</info>
</job_info>
</job_run_status>

8
synthesis/synlog/report/top_fpga_mapper_area_report.xml
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@@ -13,10 +13,10 @@ The file contains the area information from mapper to be displayed as part of th
<title>Hierarchical Area Report</title>
</report_link>
<parameter tooltip="Total Carry Cells used" name="Carry Cells">
<data>2335</data>
<data>2263</data>
</parameter>
<parameter tooltip="Total Sequential Cells used" name="Sequential Cells">
<data>7316</data>
<data>7208</data>
</parameter>
<parameter tcl_name="dsp_used" tooltip="Total DSP Blocks used" name="DSP Blocks">
<data>0</data>
@@ -28,12 +28,12 @@ The file contains the area information from mapper to be displayed as part of th
<data>7</data>
</parameter>
<parameter tcl_name="v_ram" tooltip="Total RAM1K20 used" name="RAM1K20">
<data>34</data>
<data>36</data>
</parameter>
<parameter tcl_name="v_ram" tooltip="Total RAM64x12 used" name="RAM64x12">
<data>11</data>
</parameter>
<parameter tcl_name="total_luts" tooltip="Total LUTs used" name="LUTs">
<data>15992</data>
<data>15852</data>
</parameter>
</report_table>

164
synthesis/synlog/report/top_fpga_mapper_hier_area.csv
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@@ -1,15 +1,15 @@
. Module name, SLE, CFG, ARI1, BUFFER, MACC_PA, RAM1K20, RAM64X12, GLOBAL, IO
. top, 7316, 13657, 2335, 102, 0, 34, 11, 7, 50
. . COREFIFO_C0, 148, 90, 58, 0, 0, 2, 0, 0, 0
. . . COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2, 148, 90, 58, 0, 0, 2, 0, 0, 0
. top, 7208, 13589, 2263, 102, 0, 36, 11, 7, 50
. . COREFIFO_C0, 148, 89, 57, 0, 0, 2, 0, 0, 0
. . . COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2, 148, 89, 57, 0, 0, 2, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4, 68, 38, 0, 0, 0, 0, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3, 45, 17, 58, 0, 0, 0, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3, 45, 16, 57, 0, 0, 0, 0, 0, 0
. . . . COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . . . . COREFIFO_C0_COREFIFO_C0_0_LSRAM_top, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . COREJTAGDEBUG_C0, 17, 117, 0, 102, 0, 0, 0, 2, 0
. . . COREJTAGDEBUG_Z5, 17, 117, 0, 102, 0, 0, 0, 2, 0
. . . . COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0, 17, 114, 0, 68, 0, 0, 0, 0, 0
. . COREJTAGDEBUG_C0, 17, 118, 0, 102, 0, 0, 0, 2, 0
. . . COREJTAGDEBUG_Z5, 17, 118, 0, 102, 0, 0, 0, 2, 0
. . . . COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0, 17, 115, 0, 68, 0, 0, 0, 0, 0
. . . . . corejtagdebug_bufd_34s, 0, 0, 0, 34, 0, 0, 0, 0, 0
. . . . . corejtagdebug_bufd_34s_0, 0, 0, 0, 34, 0, 0, 0, 0, 0
. . . . corejtagdebug_bufd_34s_2, 0, 0, 0, 34, 0, 0, 0, 0, 0
@@ -22,11 +22,11 @@
. . . . . spi_fifo_16s_32s_5_0, 18, 29, 6, 0, 0, 0, 2, 0, 0
. . . . . spi_fifo_16s_32s_5_1, 18, 31, 6, 0, 0, 0, 2, 0, 0
. . . . . spi_rf_32s_16s_0, 43, 84, 0, 0, 0, 0, 0, 0, 0
. . CORETSE_0, 4601, 6488, 1370, 0, 0, 12, 0, 0, 0
. . . CORETSE_Z11, 4601, 6488, 1370, 0, 0, 12, 0, 0, 0
. . . . CTSE_CORETSE_TOP_Z10, 4497, 6431, 1302, 0, 0, 12, 0, 0, 0
. . CORETSE_0, 4491, 6369, 1297, 0, 0, 12, 0, 0, 0
. . . CORETSE_Z11, 4491, 6369, 1297, 0, 0, 12, 0, 0, 0
. . . . CTSE_CORETSE_TOP_Z10, 4387, 6312, 1229, 0, 0, 12, 0, 0, 0
. . . . . CTSE_CLKRST_26s_1s, 14, 7, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_ECC_0s_26s_16s, 44, 20, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_ECC_0s_26s_16s, 44, 21, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s, 8, 2, 0, 0, 0, 0, 0, 0, 0
@@ -41,31 +41,31 @@
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_4, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_5, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_MSGMII_CORE_26s_0s_18s_0s, 1041, 1814, 113, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVRXI_26s, 208, 188, 7, 0, 0, 0, 0, 0, 0
. . . . . CTSE_MSGMII_CORE_26s_0s_18s_0s, 1041, 1795, 106, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVRXI_26s, 208, 183, 7, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVRXO_26s, 18, 22, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVTXI_26s, 108, 108, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVTXI_26s, 108, 109, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_CNVTXO_26s, 24, 12, 8, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_TBI_26s_0s_0s_1s, 681, 1483, 98, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_MSGMII_PEANX_TOP_1s_26s, 231, 194, 67, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MSGMII_TBI_26s_0s_0s_1s, 681, 1468, 91, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_MSGMII_PEANX_TOP_1s_26s, 231, 191, 67, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEANX_SYNC_1s_26s, 60, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEREX_PCS_0s_26s_1s, 121, 553, 27, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_R10B8B_0, 0, 131, 21, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_R10B8B_1, 0, 158, 6, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4, 103, 307, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETBM_26s_0s_1s, 124, 181, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEREX_PCS_0s_26s_1s, 121, 551, 20, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_R10B8B_0, 0, 133, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_R10B8B_1, 0, 161, 8, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4, 103, 306, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETBM_26s_0s_1s, 124, 177, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETCR_26s_1s, 5, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETEX_TOP_26s_0s_1s, 97, 245, 4, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_T8B10B, 0, 112, 4, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PETEX_TOP_26s_0s_1s, 97, 240, 4, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_T8B10B, 0, 106, 4, 0, 0, 0, 0, 0, 0
. . . . . CTSE_RX4096X36_12s_26s_1s_1s_4s, 0, 0, 0, 0, 0, 8, 0, 0, 0
. . . . . CTSE_TSMAC_TOP_Z9, 3378, 4590, 1189, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s, 231, 257, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_DECODER, 0, 82, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_TSM_SYSREG_26s_1s_0s, 230, 171, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_TSMAC_TOP_Z9, 3268, 4489, 1123, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s, 231, 253, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_DECODER, 0, 79, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_TSM_SYSREG_26s_1s_0s, 230, 170, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_MMCXWOL_1s_26s, 52, 93, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_PEMSTAT_26s, 764, 1447, 606, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_CNTRL_1s_26s, 65, 121, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_EIM_26s_1s_0s, 51, 589, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_PEMSTAT_26s, 764, 1448, 606, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_CNTRL_1s_26s, 65, 124, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_EIM_26s_1s_0s, 51, 587, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMSTAT_STORE_26s, 648, 737, 606, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LADD_1s_26s, 25, 28, 24, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_LADD_1s_26s_0, 25, 27, 24, 0, 0, 0, 0, 0, 0
@@ -109,15 +109,15 @@
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_7, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_8, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_9, 13, 15, 12, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_PE_MCXMAC_26s_0_0s_0s, 1046, 1569, 266, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_PE_MCXMAC_26s_0_0s_0s, 1046, 1565, 266, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PECAR_26s_1s, 13, 9, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEHST_1s_26s, 222, 71, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEHST_1s_26s, 222, 64, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PEMGT_1s_26s, 111, 209, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PE_MCXMAC_CORE_26s_0_0s_0s, 700, 1264, 266, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PERFN_TOP_26s_0s_0_1s, 223, 362, 128, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_PE_MCXMAC_CORE_26s_0_0s_0s, 700, 1267, 266, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PERFN_TOP_26s_0s_0_1s, 223, 364, 128, 0, 0, 0, 0, 0, 0
. . . . . . . . . CTSE_PECRC_1s_26s_1, 32, 78, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PERMC_TOP_1s_26s, 117, 177, 23, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PETFN_TOP_26s_0s_0_1s, 324, 610, 79, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PETFN_TOP_26s_0s_0_1s, 324, 611, 79, 0, 0, 0, 0, 0, 0
. . . . . . . . . CTSE_PECRC_1s_26s_0, 32, 163, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . CTSE_PETMC_TOP_1s_26s, 36, 114, 36, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
@@ -128,21 +128,21 @@
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . CTSE_SI_SAL_26s, 3, 115, 0, 0, 0, 0, 0, 0, 0
. . . . . . OiOI1_26s_11s_12s_32s_2s_0s, 1263, 683, 317, 0, 0, 0, 0, 0, 0
. . . . . . OiOI1_26s_11s_12s_32s_2s_0s, 1153, 597, 251, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXFIF_CLKRST_26s_1s, 10, 5, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXFIF_HST_Z8, 266, 68, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s, 238, 176, 33, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s, 303, 188, 62, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s, 152, 86, 60, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s, 198, 121, 88, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXFIF_HST_Z8, 266, 63, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s, 197, 128, 33, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s, 303, 190, 62, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s, 98, 56, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s, 183, 116, 82, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0, 90, 39, 74, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . CTSE_TX2048X40_11s_26s_1s_1s_4s, 0, 0, 0, 0, 0, 4, 0, 0, 0
. . . . CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12, 104, 57, 68, 0, 0, 0, 0, 0, 0
. . CoreAPB3_0, 0, 15, 0, 0, 0, 0, 0, 0, 0
. . . CoreAPB3_Z1, 0, 15, 0, 0, 0, 0, 0, 0, 0
. . . . COREAPB3_MUXPTOB3, 0, 11, 0, 0, 0, 0, 0, 0, 0
. . CoreAPB3_0, 0, 16, 0, 0, 0, 0, 0, 0, 0
. . . CoreAPB3_Z1, 0, 16, 0, 0, 0, 0, 0, 0, 0
. . . . COREAPB3_MUXPTOB3, 0, 12, 0, 0, 0, 0, 0, 0, 0
. . CoreUARTapb_0, 114, 134, 19, 0, 0, 0, 0, 0, 0
. . . CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13, 114, 134, 19, 0, 0, 0, 0, 0, 0
. . . . CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s, 90, 107, 19, 0, 0, 0, 0, 0, 0
@@ -151,15 +151,15 @@
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s, 21, 23, 5, 0, 0, 0, 0, 0, 0
. . Core_reset_pf, 16, 2, 0, 0, 0, 0, 0, 0, 0
. . . Core_reset_pf_Core_reset_pf_0_CORERESET_PF, 16, 2, 0, 0, 0, 0, 0, 0, 0
. . MIV_RV32_C0, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
. . . MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
. . . . miv_rv32_ipcore_Z19, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
. . . . . miv_rv32_hart_Z17, 1001, 4216, 580, 0, 0, 0, 6, 0, 0
. . . . . . miv_rv32_expipe_Z16, 759, 3565, 546, 0, 0, 0, 6, 0, 0
. . . . . . . miv_rv32_bcu, 0, 47, 92, 0, 0, 0, 0, 0, 0
. . MIV_RV32_C0, 2069, 6299, 765, 0, 0, 18, 7, 0, 0
. . . MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22, 2069, 6299, 765, 0, 0, 18, 7, 0, 0
. . . . miv_rv32_ipcore_Z19, 2069, 6299, 765, 0, 0, 18, 7, 0, 0
. . . . . miv_rv32_hart_Z17, 1001, 4261, 580, 0, 0, 0, 6, 0, 0
. . . . . . miv_rv32_expipe_Z16, 759, 3616, 546, 0, 0, 0, 6, 0, 0
. . . . . . . miv_rv32_bcu, 0, 53, 92, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_decode_1s_1s_0s, 0, 38, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_privarch_Z15, 254, 697, 32, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_decode_0s_1s_0s, 0, 66, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_privarch_Z15, 254, 724, 32, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_decode_0s_1s_0s, 0, 64, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_0, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_1, 1, 0, 0, 0, 0, 0, 0, 0, 0
@@ -169,13 +169,13 @@
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12, 1, 5, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12_0, 1, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_5, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_7, 1, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_7, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4, 1, 339, 32, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4, 1, 358, 32, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_30s_1s_536870913, 30, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_31s_0s_0s, 31, 32, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_0, 32, 0, 0, 0, 0, 0, 0, 0, 0
@@ -185,36 +185,36 @@
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968, 32, 66, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_3s_1s_0s_0, 3, 5, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_csr_gpr_state_reg_5s_1s_0, 5, 8, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . miv_rv32_priv_irq_2s_0_0, 2, 23, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . . miv_rv32_irq_reg_0s, 1, 9, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . . miv_rv32_irq_reg_0s_0, 1, 3, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1, 202, 1599, 422, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_gpr_ram_0s_0_0s_32s, 20, 42, 0, 0, 0, 0, 6, 0, 0
. . . . . . . . miv_rv32_priv_irq_2s_0_0, 2, 31, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . . miv_rv32_irq_reg_0s, 1, 7, 0, 0, 0, 0, 0, 0, 0
. . . . . . . . . miv_rv32_irq_reg_0s_0, 1, 15, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1, 202, 1588, 422, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_gpr_ram_0s_0_0s_32s, 20, 41, 0, 0, 0, 0, 6, 0, 0
. . . . . . . . miv_rv32_gpr_ram_array_32s_6s_32s, 0, 6, 0, 0, 0, 0, 6, 0, 0
. . . . . . . miv_rv32_idecode_1_1s_1s_0s, 0, 1044, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14, 220, 453, 30, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_ifu_iab_32s_2s_3s_2s_0s, 215, 213, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_lsu_32s_2s_1s_2s_2s, 22, 198, 4, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5, 115, 172, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_rr_pri_arb_2s_1s_1s, 4, 18, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_debug_1s, 664, 1043, 40, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_dtm_jtag_1s, 109, 207, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_du, 379, 738, 40, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_debug_sba, 166, 670, 40, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_fifo_34s_1s_1s, 80, 45, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_idecode_1_1s_1s_0s, 0, 1072, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14, 220, 456, 30, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_ifu_iab_32s_2s_3s_2s_0s, 215, 219, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_lsu_32s_2s_1s_2s_2s, 22, 189, 4, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5, 115, 171, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_rr_pri_arb_2s_1s_1s, 4, 19, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_debug_1s, 664, 1040, 40, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_dtm_jtag_1s, 109, 201, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_du, 379, 740, 40, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_debug_sba, 166, 672, 40, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_fifo_34s_1s_1s, 80, 46, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_debug_fifo_41s_1s_1s, 96, 53, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_interconnect_Z18, 55, 373, 0, 0, 0, 0, 1, 0, 0
. . . . . miv_rv32_subsys_interconnect_Z18, 55, 359, 0, 0, 0, 0, 1, 0, 0
. . . . . . miv_rv32_buffer_11s_2s_1s_1s, 29, 19, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_buffer_6s_2s_1s_1s, 17, 13, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_buffer_6s_2s_1s_1s, 17, 11, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s, 9, 28, 0, 0, 0, 0, 1, 0, 0
. . . . . . . miv_rv32_buffer_7s_2s_1s_1s, 5, 13, 0, 0, 0, 0, 1, 0, 0
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s, 1, 2, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_0, 1, 0, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_1, 1, 1, 0, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820, 176, 270, 145, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_tcm_Z20, 58, 169, 0, 0, 0, 18, 0, 0, 0
. . . . . miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820, 176, 271, 145, 0, 0, 0, 0, 0, 0
. . . . . miv_rv32_subsys_tcm_Z20, 58, 164, 0, 0, 0, 18, 0, 0, 0
. . . . . . miv_rv32_ram_singleport_lp_Z21, 0, 22, 0, 0, 0, 18, 0, 0, 0
. . . . . . miv_rv32_rr_pri_arb_3s_1s_1s, 3, 147, 0, 0, 0, 0, 0, 0, 0
. . . . . . miv_rv32_rr_pri_arb_3s_1s_1s, 3, 142, 0, 0, 0, 0, 0, 0, 0
. . . . . . . miv_rv32_fixed_arb_3s_2, 0, 81, 0, 0, 0, 0, 0, 0, 0
. . PF_CCC_0, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . . PF_CCC_0_PF_CCC_0_0_PF_CCC, 0, 0, 0, 0, 0, 0, 0, 1, 0
@@ -230,9 +230,9 @@
. . . PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . . PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV, 0, 0, 0, 0, 0, 0, 0, 1, 0
. . . PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . PF_TPSRAM_C0, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . . PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM, 0, 0, 0, 0, 0, 2, 0, 0, 0
. . PF_TPSRAM_C0, 0, 0, 0, 0, 0, 4, 0, 0, 0
. . . PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM, 0, 0, 0, 0, 0, 4, 0, 0, 0
. . SSDetect, 2, 7, 0, 0, 0, 0, 0, 0, 0
. . fifo_to_tpsram_bridge, 12, 5, 11, 0, 0, 0, 0, 0, 0
. . fifo_to_tpsram_bridge, 14, 33, 13, 0, 0, 0, 0, 0, 0
. . pf_init_monitor_0, 0, 0, 0, 0, 0, 0, 0, 0, 0
. . . pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR, 0, 0, 0, 0, 0, 0, 0, 0, 0
1 . Module name SLE CFG ARI1 BUFFER MACC_PA RAM1K20 RAM64X12 GLOBAL IO
2 . top 7316 7208 13657 13589 2335 2263 102 0 34 36 11 7 50
3 . . COREFIFO_C0 148 90 89 58 57 0 0 2 0 0 0
4 . . . COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 148 90 89 58 57 0 0 2 0 0 0
5 . . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 68 38 0 0 0 0 0 0 0
6 . . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 45 17 16 58 57 0 0 0 0 0 0
7 . . . . COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s 0 0 0 0 0 2 0 0 0
8 . . . . . COREFIFO_C0_COREFIFO_C0_0_LSRAM_top 0 0 0 0 0 2 0 0 0
9 . . COREJTAGDEBUG_C0 17 117 118 0 102 0 0 0 2 0
10 . . . COREJTAGDEBUG_Z5 17 117 118 0 102 0 0 0 2 0
11 . . . . COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 17 114 115 0 68 0 0 0 0 0
12 . . . . . corejtagdebug_bufd_34s 0 0 0 34 0 0 0 0 0
13 . . . . . corejtagdebug_bufd_34s_0 0 0 0 34 0 0 0 0 0
14 . . . . corejtagdebug_bufd_34s_2 0 0 0 34 0 0 0 0 0
15 . . CORESPI_0 247 345 30 0 0 0 4 0 0
22 . . . . . spi_fifo_16s_32s_5_1 18 31 6 0 0 0 2 0 0
23 . . . . . spi_rf_32s_16s_0 43 84 0 0 0 0 0 0 0
24 . . CORETSE_0 4601 4491 6488 6369 1370 1297 0 0 12 0 0 0
25 . . . CORETSE_Z11 4601 4491 6488 6369 1370 1297 0 0 12 0 0 0
26 . . . . CTSE_CORETSE_TOP_Z10 4497 4387 6431 6312 1302 1229 0 0 12 0 0 0
27 . . . . . CTSE_CLKRST_26s_1s 14 7 0 0 0 0 0 0 0
28 . . . . . CTSE_ECC_0s_26s_16s 44 20 21 0 0 0 0 0 0 0
29 . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_0 3 0 0 0 0 0 0 0 0
30 . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_1 3 0 0 0 0 0 0 0 0
31 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s 8 2 0 0 0 0 0 0 0
32 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_1 3 0 0 0 0 0 0 0 0
41 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_4 3 0 0 0 0 0 0 0 0
42 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_5 3 0 0 0 0 0 0 0 0
43 . . . . . CTSE_MSGMII_CORE_26s_0s_18s_0s 1041 1814 1795 113 106 0 0 0 0 0 0
44 . . . . . . CTSE_MSGMII_CNVRXI_26s 208 188 183 7 0 0 0 0 0 0
45 . . . . . . CTSE_MSGMII_CNVRXO_26s 18 22 0 0 0 0 0 0 0
46 . . . . . . CTSE_MSGMII_CNVTXI_26s 108 108 109 0 0 0 0 0 0 0
47 . . . . . . CTSE_MSGMII_CNVTXO_26s 24 12 8 0 0 0 0 0 0
48 . . . . . . CTSE_MSGMII_TBI_26s_0s_0s_1s 681 1483 1468 98 91 0 0 0 0 0 0
49 . . . . . . . CTSE_MSGMII_PEANX_TOP_1s_26s 231 194 191 67 0 0 0 0 0 0
50 . . . . . . . . CTSE_PEANX_SYNC_1s_26s 60 2 0 0 0 0 0 0 0
51 . . . . . . . CTSE_PEREX_PCS_0s_26s_1s 121 553 551 27 20 0 0 0 0 0 0
52 . . . . . . . . CTSE_R10B8B_0 0 131 133 21 12 0 0 0 0 0 0
53 . . . . . . . . CTSE_R10B8B_1 0 158 161 6 8 0 0 0 0 0 0
54 . . . . . . . CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 103 307 306 0 0 0 0 0 0 0
55 . . . . . . . CTSE_PETBM_26s_0s_1s 124 181 177 0 0 0 0 0 0 0
56 . . . . . . . CTSE_PETCR_26s_1s 5 3 0 0 0 0 0 0 0
57 . . . . . . . CTSE_PETEX_TOP_26s_0s_1s 97 245 240 4 0 0 0 0 0 0
58 . . . . . . . . CTSE_T8B10B 0 112 106 4 0 0 0 0 0 0
59 . . . . . CTSE_RX4096X36_12s_26s_1s_1s_4s 0 0 0 0 0 8 0 0 0
60 . . . . . CTSE_TSMAC_TOP_Z9 3378 3268 4590 4489 1189 1123 0 0 0 0 0 0
61 . . . . . . CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s 231 257 253 0 0 0 0 0 0 0
62 . . . . . . . CTSE_DECODER 0 82 79 0 0 0 0 0 0 0
63 . . . . . . . CTSE_TSM_SYSREG_26s_1s_0s 230 171 170 0 0 0 0 0 0 0
64 . . . . . . CTSE_MMCXWOL_1s_26s 52 93 0 0 0 0 0 0 0
65 . . . . . . CTSE_PEMSTAT_26s 764 1447 1448 606 0 0 0 0 0 0
66 . . . . . . . CTSE_PEMSTAT_CNTRL_1s_26s 65 121 124 0 0 0 0 0 0 0
67 . . . . . . . CTSE_PEMSTAT_EIM_26s_1s_0s 51 589 587 0 0 0 0 0 0 0
68 . . . . . . . CTSE_PEMSTAT_STORE_26s 648 737 606 0 0 0 0 0 0
69 . . . . . . . . CTSE_PEMSTAT_LADD_1s_26s 25 28 24 0 0 0 0 0 0
70 . . . . . . . . CTSE_PEMSTAT_LADD_1s_26s_0 25 27 24 0 0 0 0 0 0
71 . . . . . . . . CTSE_PEMSTAT_LINC_1s_26s 19 22 18 0 0 0 0 0 0
109 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_8 13 15 12 0 0 0 0 0 0
110 . . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_9 13 15 12 0 0 0 0 0 0
111 . . . . . . CTSE_PE_MCXMAC_26s_0_0s_0s 1046 1569 1565 266 0 0 0 0 0 0
112 . . . . . . . CTSE_PECAR_26s_1s 13 9 0 0 0 0 0 0 0
113 . . . . . . . CTSE_PEHST_1s_26s 222 71 64 0 0 0 0 0 0 0
114 . . . . . . . CTSE_PEMGT_1s_26s 111 209 0 0 0 0 0 0 0
115 . . . . . . . CTSE_PE_MCXMAC_CORE_26s_0_0s_0s 700 1264 1267 266 0 0 0 0 0 0
116 . . . . . . . . CTSE_PERFN_TOP_26s_0s_0_1s 223 362 364 128 0 0 0 0 0 0
117 . . . . . . . . . CTSE_PECRC_1s_26s_1 32 78 0 0 0 0 0 0 0
118 . . . . . . . . CTSE_PERMC_TOP_1s_26s 117 177 23 0 0 0 0 0 0
119 . . . . . . . . CTSE_PETFN_TOP_26s_0s_0_1s 324 610 611 79 0 0 0 0 0 0
120 . . . . . . . . . CTSE_PECRC_1s_26s_0 32 163 0 0 0 0 0 0 0
121 . . . . . . . . CTSE_PETMC_TOP_1s_26s 36 114 36 0 0 0 0 0 0
122 . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_1 3 0 0 0 0 0 0 0 0
123 . . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_0 8 2 0 0 0 0 0 0 0
128 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_0 3 0 0 0 0 0 0 0 0
129 . . . . . . CTSE_SI_SAL_26s 3 115 0 0 0 0 0 0 0
130 . . . . . . OiOI1_26s_11s_12s_32s_2s_0s 1263 1153 683 597 317 251 0 0 0 0 0 0
131 . . . . . . . CTSE_AMCXFIF_CLKRST_26s_1s 10 5 0 0 0 0 0 0 0
132 . . . . . . . CTSE_AMCXFIF_HST_Z8 266 68 63 0 0 0 0 0 0 0
133 . . . . . . . CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s 238 197 176 128 33 0 0 0 0 0 0
134 . . . . . . . CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s 303 188 190 62 0 0 0 0 0 0
135 . . . . . . . CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s 152 98 86 56 60 0 0 0 0 0 0 0
136 . . . . . . . CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s 198 183 121 116 88 82 0 0 0 0 0 0
137 . . . . . . . CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 90 39 74 0 0 0 0 0 0
138 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8 3 0 0 0 0 0 0 0 0
139 . . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_0 3 0 0 0 0 0 0 0 0
140 . . . . . CTSE_TX2048X40_11s_26s_1s_1s_4s 0 0 0 0 0 4 0 0 0
141 . . . . CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 104 57 68 0 0 0 0 0 0
142 . . CoreAPB3_0 0 15 16 0 0 0 0 0 0 0
143 . . . CoreAPB3_Z1 0 15 16 0 0 0 0 0 0 0
144 . . . . COREAPB3_MUXPTOB3 0 11 12 0 0 0 0 0 0 0
145 . . CoreUARTapb_0 114 134 19 0 0 0 0 0 0
146 . . . CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 114 134 19 0 0 0 0 0 0
147 . . . . CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s 90 107 19 0 0 0 0 0 0
148 . . . . . CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s 19 10 14 0 0 0 0 0 0
151 . . Core_reset_pf 16 2 0 0 0 0 0 0 0
152 . . . Core_reset_pf_Core_reset_pf_0_CORERESET_PF 16 2 0 0 0 0 0 0 0
153 . . MIV_RV32_C0 2069 6278 6299 765 0 0 18 7 0 0
154 . . . MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 2069 6278 6299 765 0 0 18 7 0 0
155 . . . . miv_rv32_ipcore_Z19 2069 6278 6299 765 0 0 18 7 0 0
156 . . . . . miv_rv32_hart_Z17 1001 4216 4261 580 0 0 0 6 0 0
157 . . . . . . miv_rv32_expipe_Z16 759 3565 3616 546 0 0 0 6 0 0
158 . . . . . . . miv_rv32_bcu 0 47 53 92 0 0 0 0 0 0
159 . . . . . . . miv_rv32_csr_decode_1s_1s_0s 0 38 0 0 0 0 0 0 0
160 . . . . . . . miv_rv32_csr_privarch_Z15 254 697 724 32 0 0 0 0 0 0
161 . . . . . . . . miv_rv32_csr_decode_0s_1s_0s 0 66 64 0 0 0 0 0 0 0
162 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s 1 0 0 0 0 0 0 0 0
163 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_0 1 0 0 0 0 0 0 0 0
164 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_1 1 0 0 0 0 0 0 0 0
165 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_2 1 0 0 0 0 0 0 0 0
169 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12_0 1 3 0 0 0 0 0 0 0
170 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_5 1 0 0 0 0 0 0 0 0
171 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_7 1 3 2 0 0 0 0 0 0 0
172 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9 1 2 0 0 0 0 0 0 0
173 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0 1 1 2 0 0 0 0 0 0 0
174 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1 1 0 1 0 0 0 0 0 0 0
175 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2 1 0 1 0 0 0 0 0 0 0
176 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3 1 0 1 0 0 0 0 0 0 0
177 . . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4 1 339 358 32 0 0 0 0 0 0
178 . . . . . . . . miv_rv32_csr_gpr_state_reg_30s_1s_536870913 30 1 0 0 0 0 0 0 0
179 . . . . . . . . miv_rv32_csr_gpr_state_reg_31s_0s_0s 31 32 0 0 0 0 0 0 0
180 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_0 32 0 0 0 0 0 0 0 0
181 . . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_1 32 33 0 0 0 0 0 0 0
185 . . . . . . . . miv_rv32_csr_gpr_state_reg_3s_1s_0s_0 3 5 0 0 0 0 0 0 0
186 . . . . . . . . miv_rv32_csr_gpr_state_reg_5s_1s_0 5 8 0 0 0 0 0 0 0
187 . . . . . . . . miv_rv32_priv_irq_2s_0_0 2 23 31 0 0 0 0 0 0 0
188 . . . . . . . . . miv_rv32_irq_reg_0s 1 9 7 0 0 0 0 0 0 0
189 . . . . . . . . . miv_rv32_irq_reg_0s_0 1 3 15 0 0 0 0 0 0 0
190 . . . . . . . miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 202 1599 1588 422 0 0 0 0 0 0
191 . . . . . . . miv_rv32_gpr_ram_0s_0_0s_32s 20 42 41 0 0 0 0 6 0 0
192 . . . . . . . . miv_rv32_gpr_ram_array_32s_6s_32s 0 6 0 0 0 0 6 0 0
193 . . . . . . . miv_rv32_idecode_1_1s_1s_0s 0 1044 1072 0 0 0 0 0 0 0
194 . . . . . . miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 220 453 456 30 0 0 0 0 0 0
195 . . . . . . . miv_rv32_ifu_iab_32s_2s_3s_2s_0s 215 213 219 0 0 0 0 0 0 0
196 . . . . . . miv_rv32_lsu_32s_2s_1s_2s_2s 22 198 189 4 0 0 0 0 0 0
197 . . . . . miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 115 172 171 0 0 0 0 0 0 0
198 . . . . . . miv_rv32_rr_pri_arb_2s_1s_1s 4 18 19 0 0 0 0 0 0 0
199 . . . . . miv_rv32_subsys_debug_1s 664 1043 1040 40 0 0 0 0 0 0
200 . . . . . . miv_rv32_debug_dtm_jtag_1s 109 207 201 0 0 0 0 0 0 0
201 . . . . . . miv_rv32_debug_du 379 738 740 40 0 0 0 0 0 0
202 . . . . . . . miv_rv32_debug_sba 166 670 672 40 0 0 0 0 0 0
203 . . . . . . miv_rv32_debug_fifo_34s_1s_1s 80 45 46 0 0 0 0 0 0 0
204 . . . . . . miv_rv32_debug_fifo_41s_1s_1s 96 53 0 0 0 0 0 0 0
205 . . . . . miv_rv32_subsys_interconnect_Z18 55 373 359 0 0 0 0 1 0 0
206 . . . . . . miv_rv32_buffer_11s_2s_1s_1s 29 19 0 0 0 0 0 0 0
207 . . . . . . miv_rv32_buffer_6s_2s_1s_1s 17 13 11 0 0 0 0 0 0 0
208 . . . . . . miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s 9 28 0 0 0 0 1 0 0
209 . . . . . . . miv_rv32_buffer_7s_2s_1s_1s 5 13 0 0 0 0 1 0 0
210 . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s 1 2 0 0 0 0 0 0 0
211 . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_0 1 0 0 0 0 0 0 0 0
212 . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_1 1 1 0 0 0 0 0 0 0
213 . . . . . miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 176 270 271 145 0 0 0 0 0 0
214 . . . . . miv_rv32_subsys_tcm_Z20 58 169 164 0 0 0 18 0 0 0
215 . . . . . . miv_rv32_ram_singleport_lp_Z21 0 22 0 0 0 18 0 0 0
216 . . . . . . miv_rv32_rr_pri_arb_3s_1s_1s 3 147 142 0 0 0 0 0 0 0
217 . . . . . . . miv_rv32_fixed_arb_3s_2 0 81 0 0 0 0 0 0 0
218 . . PF_CCC_0 0 0 0 0 0 0 0 1 0
219 . . . PF_CCC_0_PF_CCC_0_0_PF_CCC 0 0 0 0 0 0 0 1 0
220 . . PF_IOD_CDR_C0 59 153 74 0 0 0 0 2 2
230 . . . PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV 0 0 0 0 0 0 0 1 0
231 . . . PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL 0 0 0 0 0 0 0 0 0
232 . . PF_TPSRAM_C0 0 0 0 0 0 2 4 0 0 0
233 . . . PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM 0 0 0 0 0 2 4 0 0 0
234 . . SSDetect 2 7 0 0 0 0 0 0 0
235 . . fifo_to_tpsram_bridge 12 14 5 33 11 13 0 0 0 0 0 0
236 . . pf_init_monitor_0 0 0 0 0 0 0 0 0 0
237 . . . pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR 0 0 0 0 0 0 0 0 0
238

220
synthesis/synlog/report/top_fpga_mapper_hier_area_report.xml
View File

@@ -18,20 +18,20 @@ The file contains the information about resource utilization per module to be di
</column_headers>
<module>
<data>top</data>
<data>7316</data>
<data>13657</data>
<data>2335</data>
<data>7208</data>
<data>13589</data>
<data>2263</data>
<data>102</data>
<data>0</data>
<data>34</data>
<data>36</data>
<data>11</data>
<data>7</data>
<data>50</data>
<module>
<data>COREFIFO_C0</data>
<data>148</data>
<data>90</data>
<data>58</data>
<data>89</data>
<data>57</data>
<data>0</data>
<data>0</data>
<data>2</data>
@@ -41,8 +41,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2</data>
<data>148</data>
<data>90</data>
<data>58</data>
<data>89</data>
<data>57</data>
<data>0</data>
<data>0</data>
<data>2</data>
@@ -64,8 +64,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3</data>
<data>45</data>
<data>17</data>
<data>58</data>
<data>16</data>
<data>57</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -102,7 +102,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>COREJTAGDEBUG_C0</data>
<data>17</data>
<data>117</data>
<data>118</data>
<data>0</data>
<data>102</data>
<data>0</data>
@@ -113,7 +113,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>COREJTAGDEBUG_Z5</data>
<data>17</data>
<data>117</data>
<data>118</data>
<data>0</data>
<data>102</data>
<data>0</data>
@@ -124,7 +124,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0</data>
<data>17</data>
<data>114</data>
<data>115</data>
<data>0</data>
<data>68</data>
<data>0</data>
@@ -281,9 +281,9 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>CORETSE_0</data>
<data>4601</data>
<data>6488</data>
<data>1370</data>
<data>4491</data>
<data>6369</data>
<data>1297</data>
<data>0</data>
<data>0</data>
<data>12</data>
@@ -292,9 +292,9 @@ The file contains the information about resource utilization per module to be di
<data>0</data>
<module>
<data>CORETSE_Z11</data>
<data>4601</data>
<data>6488</data>
<data>1370</data>
<data>4491</data>
<data>6369</data>
<data>1297</data>
<data>0</data>
<data>0</data>
<data>12</data>
@@ -303,9 +303,9 @@ The file contains the information about resource utilization per module to be di
<data>0</data>
<module>
<data>CTSE_CORETSE_TOP_Z10</data>
<data>4497</data>
<data>6431</data>
<data>1302</data>
<data>4387</data>
<data>6312</data>
<data>1229</data>
<data>0</data>
<data>0</data>
<data>12</data>
@@ -327,7 +327,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_ECC_0s_26s_16s</data>
<data>44</data>
<data>20</data>
<data>21</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -507,8 +507,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_MSGMII_CORE_26s_0s_18s_0s</data>
<data>1041</data>
<data>1814</data>
<data>113</data>
<data>1795</data>
<data>106</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -518,7 +518,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_MSGMII_CNVRXI_26s</data>
<data>208</data>
<data>188</data>
<data>183</data>
<data>7</data>
<data>0</data>
<data>0</data>
@@ -542,7 +542,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_MSGMII_CNVTXI_26s</data>
<data>108</data>
<data>108</data>
<data>109</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -566,8 +566,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_MSGMII_TBI_26s_0s_0s_1s</data>
<data>681</data>
<data>1483</data>
<data>98</data>
<data>1468</data>
<data>91</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -577,7 +577,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_MSGMII_PEANX_TOP_1s_26s</data>
<data>231</data>
<data>194</data>
<data>191</data>
<data>67</data>
<data>0</data>
<data>0</data>
@@ -601,8 +601,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PEREX_PCS_0s_26s_1s</data>
<data>121</data>
<data>553</data>
<data>27</data>
<data>551</data>
<data>20</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -612,8 +612,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_R10B8B_0</data>
<data>0</data>
<data>131</data>
<data>21</data>
<data>133</data>
<data>12</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -624,8 +624,8 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_R10B8B_1</data>
<data>0</data>
<data>158</data>
<data>6</data>
<data>161</data>
<data>8</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -637,7 +637,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4</data>
<data>103</data>
<data>307</data>
<data>306</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -649,7 +649,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PETBM_26s_0s_1s</data>
<data>124</data>
<data>181</data>
<data>177</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -673,7 +673,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PETEX_TOP_26s_0s_1s</data>
<data>97</data>
<data>245</data>
<data>240</data>
<data>4</data>
<data>0</data>
<data>0</data>
@@ -684,7 +684,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_T8B10B</data>
<data>0</data>
<data>112</data>
<data>106</data>
<data>4</data>
<data>0</data>
<data>0</data>
@@ -710,9 +710,9 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>CTSE_TSMAC_TOP_Z9</data>
<data>3378</data>
<data>4590</data>
<data>1189</data>
<data>3268</data>
<data>4489</data>
<data>1123</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -722,7 +722,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s</data>
<data>231</data>
<data>257</data>
<data>253</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -733,7 +733,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_DECODER</data>
<data>0</data>
<data>82</data>
<data>79</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -745,7 +745,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_TSM_SYSREG_26s_1s_0s</data>
<data>230</data>
<data>171</data>
<data>170</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -770,7 +770,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PEMSTAT_26s</data>
<data>764</data>
<data>1447</data>
<data>1448</data>
<data>606</data>
<data>0</data>
<data>0</data>
@@ -781,7 +781,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PEMSTAT_CNTRL_1s_26s</data>
<data>65</data>
<data>121</data>
<data>124</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -793,7 +793,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PEMSTAT_EIM_26s_1s_0s</data>
<data>51</data>
<data>589</data>
<data>587</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1322,7 +1322,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PE_MCXMAC_26s_0_0s_0s</data>
<data>1046</data>
<data>1569</data>
<data>1565</data>
<data>266</data>
<data>0</data>
<data>0</data>
@@ -1345,7 +1345,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PEHST_1s_26s</data>
<data>222</data>
<data>71</data>
<data>64</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1369,7 +1369,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PE_MCXMAC_CORE_26s_0_0s_0s</data>
<data>700</data>
<data>1264</data>
<data>1267</data>
<data>266</data>
<data>0</data>
<data>0</data>
@@ -1380,7 +1380,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PERFN_TOP_26s_0s_0_1s</data>
<data>223</data>
<data>362</data>
<data>364</data>
<data>128</data>
<data>0</data>
<data>0</data>
@@ -1416,7 +1416,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_PETFN_TOP_26s_0s_0_1s</data>
<data>324</data>
<data>610</data>
<data>611</data>
<data>79</data>
<data>0</data>
<data>0</data>
@@ -1549,9 +1549,9 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>OiOI1_26s_11s_12s_32s_2s_0s</data>
<data>1263</data>
<data>683</data>
<data>317</data>
<data>1153</data>
<data>597</data>
<data>251</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1573,7 +1573,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_AMCXFIF_HST_Z8</data>
<data>266</data>
<data>68</data>
<data>63</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1584,8 +1584,8 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s</data>
<data>238</data>
<data>176</data>
<data>197</data>
<data>128</data>
<data>33</data>
<data>0</data>
<data>0</data>
@@ -1597,7 +1597,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s</data>
<data>303</data>
<data>188</data>
<data>190</data>
<data>62</data>
<data>0</data>
<data>0</data>
@@ -1608,9 +1608,9 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s</data>
<data>152</data>
<data>86</data>
<data>60</data>
<data>98</data>
<data>56</data>
<data>0</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1620,9 +1620,9 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s</data>
<data>198</data>
<data>121</data>
<data>88</data>
<data>183</data>
<data>116</data>
<data>82</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1698,7 +1698,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CoreAPB3_0</data>
<data>0</data>
<data>15</data>
<data>16</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1709,7 +1709,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>CoreAPB3_Z1</data>
<data>0</data>
<data>15</data>
<data>16</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1720,7 +1720,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>COREAPB3_MUXPTOB3</data>
<data>0</data>
<data>11</data>
<data>12</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -1830,7 +1830,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>MIV_RV32_C0</data>
<data>2069</data>
<data>6278</data>
<data>6299</data>
<data>765</data>
<data>0</data>
<data>0</data>
@@ -1841,7 +1841,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22</data>
<data>2069</data>
<data>6278</data>
<data>6299</data>
<data>765</data>
<data>0</data>
<data>0</data>
@@ -1852,7 +1852,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_ipcore_Z19</data>
<data>2069</data>
<data>6278</data>
<data>6299</data>
<data>765</data>
<data>0</data>
<data>0</data>
@@ -1863,7 +1863,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_hart_Z17</data>
<data>1001</data>
<data>4216</data>
<data>4261</data>
<data>580</data>
<data>0</data>
<data>0</data>
@@ -1874,7 +1874,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_expipe_Z16</data>
<data>759</data>
<data>3565</data>
<data>3616</data>
<data>546</data>
<data>0</data>
<data>0</data>
@@ -1885,7 +1885,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_bcu</data>
<data>0</data>
<data>47</data>
<data>53</data>
<data>92</data>
<data>0</data>
<data>0</data>
@@ -1909,7 +1909,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_privarch_Z15</data>
<data>254</data>
<data>697</data>
<data>724</data>
<data>32</data>
<data>0</data>
<data>0</data>
@@ -1920,7 +1920,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_decode_0s_1s_0s</data>
<data>0</data>
<data>66</data>
<data>64</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2040,7 +2040,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_gpr_state_reg_1s_1s_0s_7</data>
<data>1</data>
<data>3</data>
<data>2</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2064,7 +2064,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0</data>
<data>1</data>
<data>1</data>
<data>2</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2076,7 +2076,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1</data>
<data>1</data>
<data>0</data>
<data>1</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2088,7 +2088,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2</data>
<data>1</data>
<data>0</data>
<data>1</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2100,7 +2100,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3</data>
<data>1</data>
<data>0</data>
<data>1</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2112,7 +2112,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4</data>
<data>1</data>
<data>339</data>
<data>358</data>
<data>32</data>
<data>0</data>
<data>0</data>
@@ -2232,7 +2232,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_priv_irq_2s_0_0</data>
<data>2</data>
<data>23</data>
<data>31</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2243,7 +2243,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_irq_reg_0s</data>
<data>1</data>
<data>9</data>
<data>7</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2255,7 +2255,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_irq_reg_0s_0</data>
<data>1</data>
<data>3</data>
<data>15</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2269,7 +2269,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1</data>
<data>202</data>
<data>1599</data>
<data>1588</data>
<data>422</data>
<data>0</data>
<data>0</data>
@@ -2281,7 +2281,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_gpr_ram_0s_0_0s_32s</data>
<data>20</data>
<data>42</data>
<data>41</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2305,7 +2305,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_idecode_1_1s_1s_0s</data>
<data>0</data>
<data>1044</data>
<data>1072</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2318,7 +2318,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14</data>
<data>220</data>
<data>453</data>
<data>456</data>
<data>30</data>
<data>0</data>
<data>0</data>
@@ -2329,7 +2329,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_ifu_iab_32s_2s_3s_2s_0s</data>
<data>215</data>
<data>213</data>
<data>219</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2342,7 +2342,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_lsu_32s_2s_1s_2s_2s</data>
<data>22</data>
<data>198</data>
<data>189</data>
<data>4</data>
<data>0</data>
<data>0</data>
@@ -2355,7 +2355,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5</data>
<data>115</data>
<data>172</data>
<data>171</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2366,7 +2366,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_rr_pri_arb_2s_1s_1s</data>
<data>4</data>
<data>18</data>
<data>19</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2379,7 +2379,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_subsys_debug_1s</data>
<data>664</data>
<data>1043</data>
<data>1040</data>
<data>40</data>
<data>0</data>
<data>0</data>
@@ -2390,7 +2390,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_debug_dtm_jtag_1s</data>
<data>109</data>
<data>207</data>
<data>201</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2402,7 +2402,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_debug_du</data>
<data>379</data>
<data>738</data>
<data>740</data>
<data>40</data>
<data>0</data>
<data>0</data>
@@ -2413,7 +2413,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_debug_sba</data>
<data>166</data>
<data>670</data>
<data>672</data>
<data>40</data>
<data>0</data>
<data>0</data>
@@ -2426,7 +2426,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_debug_fifo_34s_1s_1s</data>
<data>80</data>
<data>45</data>
<data>46</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2451,7 +2451,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_subsys_interconnect_Z18</data>
<data>55</data>
<data>373</data>
<data>359</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2474,7 +2474,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_buffer_6s_2s_1s_1s</data>
<data>17</data>
<data>13</data>
<data>11</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2547,7 +2547,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820</data>
<data>176</data>
<data>270</data>
<data>271</data>
<data>145</data>
<data>0</data>
<data>0</data>
@@ -2559,7 +2559,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_subsys_tcm_Z20</data>
<data>58</data>
<data>169</data>
<data>164</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2582,7 +2582,7 @@ The file contains the information about resource utilization per module to be di
<module>
<data>miv_rv32_rr_pri_arb_3s_1s_1s</data>
<data>3</data>
<data>147</data>
<data>142</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2782,7 +2782,7 @@ The file contains the information about resource utilization per module to be di
<data>0</data>
<data>0</data>
<data>0</data>
<data>2</data>
<data>4</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2793,7 +2793,7 @@ The file contains the information about resource utilization per module to be di
<data>0</data>
<data>0</data>
<data>0</data>
<data>2</data>
<data>4</data>
<data>0</data>
<data>0</data>
<data>0</data>
@@ -2813,9 +2813,9 @@ The file contains the information about resource utilization per module to be di
</module>
<module>
<data>fifo_to_tpsram_bridge</data>
<data>12</data>
<data>5</data>
<data>11</data>
<data>14</data>
<data>33</data>
<data>13</data>
<data>0</data>
<data>0</data>
<data>0</data>

13
synthesis/synlog/report/top_fpga_mapper_notes.txt
View File

@@ -22,8 +22,7 @@
@N: MF179 :|Found 17 by 17 bit equality operator ('==') un13_IIIIo (in view: work.CTSE_PETFN_TOP_26s_0s_0_1s(verilog))
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\clock_gen.v":283:6:283:11|Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0]
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":31:4:31:9|Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[9:0]
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":49:4:49:9|Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[10:0]
@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)).
@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0]
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[2:0] is 2 words by 3 bits.
@@ -76,17 +75,17 @@
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0]
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":8721:2:8721:7|Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z16(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9395:2:9395:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[5] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_apb\.u_apb_initiator_0.u_apb_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances.
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances.
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4035
@N: FP130 |Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4036
@N: FP130 |Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4037
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4038
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4374
@N: FP130 |Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4375
@N: FP130 |Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4376
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4377
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF
@N: MT615 |Found clock REF_CLK_0 with period 20.00ns

24
synthesis/synlog/report/top_fpga_mapper_resourceusage.rpt
View File

@@ -18,19 +18,19 @@ OR4 1344 uses
PLL 2 uses
RCLKINT 1 use
UJTAG 1 use
CFG1 110 uses
CFG2 1957 uses
CFG3 3420 uses
CFG4 8170 uses
CFG1 109 uses
CFG2 1853 uses
CFG3 3347 uses
CFG4 8280 uses
Carry cells:
ARI1 2102 uses - used for arithmetic functions
ARI1 233 uses - used for Wide-Mux implementation
Total ARI1 2335 uses
ARI1 2037 uses - used for arithmetic functions
ARI1 226 uses - used for Wide-Mux implementation
Total ARI1 2263 uses
Sequential Cells:
SLE 7316 uses
SLE 7208 uses
DSP Blocks: 0 of 924 (0%)
@@ -45,15 +45,15 @@ OUTBUF_DIFF 1 use
Global Clock Buffers: 7
Total LUTs: 15992
Total LUTs: 15852
Extra resources required for RAM and MACC_PA interface logic during P&R:
RAM64X12 Interface Logic : SLEs = 132; LUTs = 132;
RAM1K20 Interface Logic : SLEs = 1224; LUTs = 1224;
RAM1K20 Interface Logic : SLEs = 1296; LUTs = 1296;
MACC_PA Interface Logic : SLEs = 0; LUTs = 0;
MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0;
Total number of SLEs after P&R: 7316 + 132 + 1224 + 0 = 8672;
Total number of LUTs after P&R: 15992 + 132 + 1224 + 0 = 17348;
Total number of SLEs after P&R: 7208 + 132 + 1296 + 0 = 8636;
Total number of LUTs after P&R: 15852 + 132 + 1296 + 0 = 17280;

10
synthesis/synlog/report/top_fpga_mapper_runstatus.xml
View File

@@ -13,7 +13,7 @@ The file contains the job information from mapper to be displayed as part of the
</job_status>
<job_info>
<info name="Notes">
<data>103</data>
<data>102</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_notes.txt</data>
</report_link>
@@ -31,16 +31,16 @@ The file contains the job information from mapper to be displayed as part of the
</report_link>
</info>
<info name="CPU Time">
<data>0h:03m:51s</data>
<data>0h:03m:58s</data>
</info>
<info name="Real Time">
<data>0h:03m:54s</data>
<data>0h:04m:02s</data>
</info>
<info name="Peak Memory">
<data>521MB</data>
<data>564MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1776273723</data>
<data type="timestamp">1776395162</data>
</info>
</job_info>
</job_run_status>

8
synthesis/synlog/report/top_fpga_mapper_timing_report.xml
View File

@@ -23,8 +23,8 @@ Max Top 5 critical clocks will be reported. For rest user needs to refer to Deta
<row>
<data>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</data>
<data>80.0 MHz</data>
<data>55.0 MHz</data>
<data>-5.671</data>
<data>55.1 MHz</data>
<data>-5.638</data>
</row>
<row>
<data>PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</data>
@@ -65,8 +65,8 @@ Max Top 5 critical clocks will be reported. For rest user needs to refer to Deta
<row>
<data>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</data>
<data>125.0 MHz</data>
<data>230.3 MHz</data>
<data>3.659</data>
<data>225.1 MHz</data>
<data>3.557</data>
</row>
<row>
<data>PHY_MDC_CLOCK</data>

1
synthesis/synlog/report/top_premap_notes.txt
View File

@@ -58,7 +58,6 @@
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.

10
synthesis/synlog/report/top_premap_runstatus.xml
View File

@@ -13,7 +13,7 @@ The file contains the job information from mapper to be displayed as part of the
</job_status>
<job_info>
<info name="Notes">
<data>65</data>
<data>64</data>
<report_link name="more">
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_notes.txt</data>
</report_link>
@@ -31,16 +31,16 @@ The file contains the job information from mapper to be displayed as part of the
</report_link>
</info>
<info name="CPU Time">
<data>0h:00m:13s</data>
<data>0h:00m:15s</data>
</info>
<info name="Real Time">
<data>0h:00m:13s</data>
<data>0h:00m:15s</data>
</info>
<info name="Peak Memory">
<data>365MB</data>
<data>366MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1776273488</data>
<data type="timestamp">1776394919</data>
</info>
</job_info>
</job_run_status>

433
synthesis/synlog/top_compiler.srr
View File

@@ -327,19 +327,17 @@ Synopsys Verilog Compiler, Version comp202309synp1, Build 540R, Built Apr 29 202
@I::"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v" (library work)
Verilog syntax check successful!
File E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v changed - recompiling
File E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v changed - recompiling
File E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v changed - recompiling
File E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v changed - recompiling
File E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v changed - recompiling
File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_30884_initial_block changed - recompiling
File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_30884_initial_block changed - recompiling
File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_30884_initial_block changed - recompiling
File miv_rv32_buffer_6s_2s_1s_1s_buff_data_30884_initial_block changed - recompiling
File miv_rv32_buffer_6s_2s_1s_1s_buff_data_30884_initial_block changed - recompiling
File miv_rv32_buffer_11s_2s_1s_1s_buff_data_30884_initial_block changed - recompiling
File miv_rv32_buffer_11s_2s_1s_1s_buff_data_30884_initial_block changed - recompiling
File miv_rv32_buffer_7s_2s_1s_1s_buff_data_30884_initial_block changed - recompiling
File miv_rv32_buffer_7s_2s_1s_1s_buff_data_30884_initial_block changed - recompiling
File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_48508_initial_block changed - recompiling
File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_48508_initial_block changed - recompiling
File miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_48508_initial_block changed - recompiling
File miv_rv32_buffer_6s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling
File miv_rv32_buffer_6s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling
File miv_rv32_buffer_11s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling
File miv_rv32_buffer_11s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling
File miv_rv32_buffer_7s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling
File miv_rv32_buffer_7s_2s_1s_1s_buff_data_48508_initial_block changed - recompiling
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v":70:8:70:28|Synthesizing module miv_rv32_hart_cfg_pkg in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":73:8:73:19|Synthesizing module miv_rv32_pkg in library work.
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v":69:8:69:26|Synthesizing module miv_rv32_subsys_pkg in library work.
@@ -695,10 +693,10 @@ Finished optimization stage 1 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Me
NUM_TRAIL_PAD_BITS=8'b00000000
Generated name = COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0
Running optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 .......
Finished optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":489:7:489:12|Synthesizing module CLKINT in library work.
Running optimization stage 1 on CLKINT .......
Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|Removing wire UTRSTB, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|Removing wire UTMS, as there is no assignment to it.
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":169:8:169:52|Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it.
@@ -709,10 +707,10 @@ Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used curren
Running optimization stage 1 on COREJTAGDEBUG_Z5 .......
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|*Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|*Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v":56:7:56:22|Synthesizing module COREJTAGDEBUG_C0 in library work.
Running optimization stage 1 on COREJTAGDEBUG_C0 .......
Finished optimization stage 1 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB)
Finished optimization stage 1 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":31:7:31:12|Synthesizing module spi_rf in library CORESPI_LIB.
APB_DWIDTH=32'b00000000000000000000000000100000
@@ -820,9 +818,9 @@ Finished optimization stage 1 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used
Running optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s .......
Finished optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB)
Running optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s .......
Finished optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB)
Finished optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 243MB)
Running optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s .......
Finished optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 242MB peak: 243MB)
Finished optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 244MB)
Running optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s .......
Finished optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 245MB)
Running optimization stage 1 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s .......
@@ -844,73 +842,73 @@ Finished optimization stage 1 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Mem
Running optimization stage 1 on CTSE_PECRC_1s_26s .......
Finished optimization stage 1 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 247MB peak: 256MB)
Running optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s .......
Finished optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 248MB peak: 256MB)
Finished optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 249MB peak: 256MB)
Running optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s .......
Finished optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 261MB)
Finished optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 262MB)
Running optimization stage 1 on CTSE_PERMC_TOP_1s_26s .......
Finished optimization stage 1 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 263MB)
Finished optimization stage 1 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s .......
Finished optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 263MB)
Finished optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMGT_1s_26s .......
Finished optimization stage 1 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEHST_1s_26s .......
Finished optimization stage 1 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PECAR_26s_1s .......
Finished optimization stage 1 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s .......
Finished optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s .......
Finished optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_STORE_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s .......
Finished optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_26s .......
Finished optimization stage 1 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_MMCXWOL_1s_26s .......
Finished optimization stage 1 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_SI_SAL_26s .......
Finished optimization stage 1 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_TSMAC_TOP_Z9 .......
Finished optimization stage 1 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_CLKRST_26s_1s .......
Finished optimization stage 1 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s .......
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_ECC_0s_26s_16s .......
Only the first 100 messages of id 'CL190' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL190' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL190} -count unlimited' in the Tcl shell.
Finished optimization stage 1 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s .......
Finished optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB)
Finished optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 264MB)
Running optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s .......
Finished optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB)
Finished optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB)
Running optimization stage 1 on CTSE_MSGMII_CNVTXI_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB)
Running optimization stage 1 on CTSE_MSGMII_CNVTXO_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 264MB)
Running optimization stage 1 on CTSE_T8B10B .......
Finished optimization stage 1 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 263MB)
Finished optimization stage 1 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 264MB)
Running optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s .......
Finished optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 263MB)
Finished optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 264MB)
Running optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 .......
Finished optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 263MB)
Finished optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 264MB)
Running optimization stage 1 on CTSE_R10B8B .......
Finished optimization stage 1 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 263MB)
Finished optimization stage 1 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 264MB)
Running optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s .......
Finished optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB)
Running optimization stage 1 on CTSE_PEANX_SYNC_1s_26s .......
@@ -924,28 +922,28 @@ Finished optimization stage 1 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory
Running optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s .......
Finished optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Running optimization stage 1 on CTSE_MSGMII_CNVRXI_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_MSGMII_CNVRXO_26s .......
Finished optimization stage 1 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s .......
Finished optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_CORETSE_TOP_Z10 .......
Finished optimization stage 1 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 .......
Finished optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
Running optimization stage 1 on CORETSE_Z11 .......
Finished optimization stage 1 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":31:7:31:15|Synthesizing module CORETSE_0 in library work.
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":270:0:270:10|Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
Running optimization stage 1 on CORETSE_0 .......
Finished optimization stage 1 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 269MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v":38:7:38:45|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work.
BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s .......
Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB)
Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB)
@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work.
SYNC_RESET=32'b00000000000000000000000000000000
@@ -1034,14 +1032,14 @@ Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used cu
LOG2_BUFF_DEPTH=32'b00000000000000000000000000000010
MI_I_MEM=32'b00000000000000000000000000000000
Generated name = miv_rv32_ifu_iab_32s_2s_3s_2s_0s
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory .
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory .
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory .
Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s .......
Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 270MB)
Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 271MB)
I_ADDR_WIDTH=32'b00000000000000000000000000100000
l_core_reset_vector=32'b10000000000000000000000000000000
@@ -1055,7 +1053,7 @@ Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:0
IFU_PARITY_ERROR_BIT=32'b00000000000000000000000000000001
Generated name = miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14
Running optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 .......
Finished optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 270MB)
Finished optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 271MB)
D_ADDR_WIDTH=32'b00000000000000000000000000100000
REQ_BUFF_DEPTH=32'b00000000000000000000000000000010
@@ -1342,24 +1340,24 @@ Finished optimization stage 1 on miv_rv32_hart_Z17 (CPU Time 0h:00m:00s, Memory
PTR_SIZE=32'b00000000000000000000000000000001
BUFF_MAX=32'b00000000000000000000000000000001
Generated name = miv_rv32_buffer_6s_2s_1s_1s
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB)
BUFF_WIDTH=32'b00000000000000000000000000001011
BUFF_SIZE=32'b00000000000000000000000000000010
PTR_SIZE=32'b00000000000000000000000000000001
BUFF_MAX=32'b00000000000000000000000000000001
Generated name = miv_rv32_buffer_11s_2s_1s_1s
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB)
WIDTH=32'b00000000000000000000000000100000
FIELD_RESET_EN=32'b00000000000000000000000000000001
@@ -1373,9 +1371,9 @@ Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 (CPU
PTR_SIZE=32'b00000000000000000000000000000001
BUFF_MAX=32'b00000000000000000000000000000001
Generated name = miv_rv32_buffer_7s_2s_1s_1s
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block from directory .
Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_49312_initial_block from directory .
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
Running optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB)
@@ -1539,17 +1537,17 @@ Running optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s .......
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB)
Running optimization stage 1 on miv_rv32_debug_sba .......
Finished optimization stage 1 on miv_rv32_debug_sba (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_debug_sba (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
Running optimization stage 1 on miv_rv32_debug_du .......
@W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001
Generated name = miv_rv32_subsys_debug_1s
Running optimization stage 1 on miv_rv32_subsys_debug_1s .......
Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
NUM_REQS=32'b00000000000000000000000000000010
USE_FORMAL=32'b00000000000000000000000000000001
@@ -1559,9 +1557,9 @@ Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s,
NUM_REQS=32'b00000000000000000000000000000010
Generated name = miv_rv32_fixed_arb_2s
Running optimization stage 1 on miv_rv32_fixed_arb_2s .......
Finished optimization stage 1 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
Running optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s .......
Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
APB_ADDR_WIDTH=32'b00000000000000000000000000100000
APB_REGISTER_IO=32'b00000000000000000000000000000001
@@ -1575,7 +1573,7 @@ Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:0
Generated name = miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6281:36:6281:48|Removing redundant assignment.
Running optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 .......
Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
NUM_REQS=32'b00000000000000000000000000000011
USE_FORMAL=32'b00000000000000000000000000000001
@@ -1585,9 +1583,9 @@ Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_
NUM_REQS=32'b00000000000000000000000000000011
Generated name = miv_rv32_fixed_arb_3s
Running optimization stage 1 on miv_rv32_fixed_arb_3s .......
Finished optimization stage 1 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
Running optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s .......
Finished optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB)
Finished optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 298MB peak: 330MB)
FAMILY=32'b00000000000000000000000000011010
UDMA_PRESENT=32'b00000000000000000000000000000000
@@ -1626,7 +1624,7 @@ Finished optimization stage 1 on CFG3 (CPU Time 0h:00m:00s, Memory Used current:
Running optimization stage 1 on OR2 .......
Finished optimization stage 1 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB)
Running optimization stage 1 on INV .......
Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 319MB peak: 330MB)
Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 320MB peak: 330MB)
RAM_DEPTH=32'b00000000000000000010010000000000
ADDR_WIDTH=32'b00000000000000000000000000001110
@@ -2199,40 +2197,40 @@ State machine has 4 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on pf_init_monitor_0 .......
Finished optimization stage 2 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR .......
Finished optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on BANKEN .......
Finished optimization stage 2 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on INIT .......
Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on PF_CCC_0 .......
Finished optimization stage 2 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC .......
Finished optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on PLL .......
Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on MIV_RV32_C0 .......
Finished optimization stage 2 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 .......
Finished optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Running optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 .......
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13005:27:13005:40|Input mtime_count_in is unused.
Finished optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 .......
Finished optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on INV .......
Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on OR2 .......
Finished optimization stage 2 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on CFG3 .......
Finished optimization stage 2 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on CFG2 .......
Finished optimization stage 2 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on OR4 .......
Finished optimization stage 2 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_subsys_tcm_Z20 .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Trying to extract state machine for register cpu_d_wr_rd_state.
Extracted state machine for register cpu_d_wr_rd_state
@@ -2277,9 +2275,9 @@ State machine has 3 reachable states with original encodings of:
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10885:49:10885:66|Input tcm_tas_resp_ready is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10890:49:10890:61|Input tcm_ram_sb_in is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10891:49:10891:71|Input tcm_ecc_error_injection is unused.
Finished optimization stage 2 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_fixed_arb_3s .......
Finished optimization stage 2 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
Extracted state machine for register hipri_req_ptr
@@ -2291,7 +2289,7 @@ State machine has 7 reachable states with original encodings of:
101
110
111
Finished optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Trying to extract state machine for register gen_apb_byte_shim.apb_st.
Extracted state machine for register gen_apb_byte_shim.apb_st
@@ -2309,9 +2307,9 @@ State machine has 6 reachable states with original encodings of:
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6080:49:6080:68|Input cpu_d_req_rd_byte_en is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6083:49:6083:64|Input cpu_d_req_addr_p is unused.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6087:49:6087:64|Input cpu_d_resp_ready is unused.
Finished optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_fixed_arb_2s .......
Finished optimization stage 2 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
Extracted state machine for register hipri_req_ptr
@@ -2319,9 +2317,9 @@ State machine has 3 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_subsys_debug_1s .......
Finished optimization stage 2 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 354MB)
Running optimization stage 2 on miv_rv32_debug_du .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14736:0:14736:8|Trying to extract state machine for register debug_state.
Extracted state machine for register debug_state
@@ -2334,7 +2332,7 @@ State machine has 6 reachable states with original encodings of:
100000
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Trying to extract state machine for register command_reg_state.
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13800:39:13800:52|Input dmi_resp_ready is unused.
Finished optimization stage 2 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB)
Finished optimization stage 2 on miv_rv32_debug_du (CPU Time 0h:00m:01s, Memory Used current: 335MB peak: 354MB)
Running optimization stage 2 on miv_rv32_debug_sba .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|Trying to extract state machine for register sba_state.
Extracted state machine for register sba_state
@@ -2343,7 +2341,7 @@ State machine has 4 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on miv_rv32_debug_sba (CPU Time 0h:00m:01s, Memory Used current: 350MB peak: 355MB)
Finished optimization stage 2 on miv_rv32_debug_sba (CPU Time 0h:00m:02s, Memory Used current: 350MB peak: 355MB)
Running optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s .......
Finished optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB)
Running optimization stage 2 on miv_rv32_debug_fifo_41s_1s_1s .......
@@ -2464,33 +2462,33 @@ Finished optimization stage 2 on miv_rv32_gpr_ram_array_32s_6s_32s (CPU Time 0h:
Running optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s .......
Finished optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB)
Running optimization stage 2 on miv_rv32_expipe_Z16 .......
Finished optimization stage 2 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:01s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:02s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_privarch_Z15 .......
@W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":1854:60:1854:72|Input port bit 1 of excpt_trigger[1:0] is unused
Finished optimization stage 2 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_priv_irq_2s_0_0 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@@ -2498,18 +2496,18 @@ Running optimization stage 2 on miv_rv32_priv_irq_2s_0_0 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6896:43:6896:57|Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_irq_reg_0s .......
Finished optimization stage 2 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_bcu .......
Finished optimization stage 2 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB)
Finished optimization stage 2 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 365MB)
Running optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 .......
@W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:02s, Memory Used current: 377MB peak: 397MB)
Finished optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:03s, Memory Used current: 376MB peak: 397MB)
Running optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s .......
Finished optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Finished optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 376MB peak: 397MB)
Running optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s .......
Finished optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB)
Finished optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 376MB peak: 397MB)
Running optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s .......
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@@ -2527,11 +2525,12 @@ Finished optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:0
Running optimization stage 2 on INBUF_DIFF .......
Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on fifo_to_tpsram_bridge .......
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|Trying to extract state machine for register state.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":65:4:65:9|Trying to extract state machine for register state.
Extracted state machine for register state
State machine has 2 reachable states with original encodings of:
State machine has 3 reachable states with original encodings of:
00
01
10
Finished optimization stage 2 on fifo_to_tpsram_bridge (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CoreUARTapb_0 .......
Finished optimization stage 2 on CoreUARTapb_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
@@ -2582,9 +2581,9 @@ Finished optimization stage 2 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory
Running optimization stage 2 on CTSE_PETBM_26s_0s_1s .......
Finished optimization stage 2 on CTSE_PETBM_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s .......
Finished optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 397MB)
Finished optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEANX_SYNC_1s_26s .......
Finished optimization stage 2 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 397MB)
Finished optimization stage 2 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s .......
Extracted state machine for register lI101
State machine has 4 reachable states with original encodings of:
@@ -2592,65 +2591,65 @@ State machine has 4 reachable states with original encodings of:
01
10
11
Finished optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_R10B8B .......
Finished optimization stage 2 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 .......
Finished optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s .......
Finished optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_T8B10B .......
Finished optimization stage 2 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MSGMII_CNVTXO_26s .......
Finished optimization stage 2 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MSGMII_CNVTXI_26s .......
Finished optimization stage 2 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s .......
Finished optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s .......
Finished optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_CORETSE_TOP_Z10 .......
Finished optimization stage 2 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_ECC_0s_26s_16s .......
Finished optimization stage 2 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s .......
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_CLKRST_26s_1s .......
Finished optimization stage 2 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_SI_SAL_26s .......
Finished optimization stage 2 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_MMCXWOL_1s_26s .......
Finished optimization stage 2 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s .......
Finished optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_STORE_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s .......
Finished optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s .......
Finished optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_TSMAC_TOP_Z9 .......
Finished optimization stage 2 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s .......
Finished optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PECAR_26s_1s .......
Finished optimization stage 2 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEHST_1s_26s .......
Finished optimization stage 2 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PEMGT_1s_26s .......
Extracted state machine for register l0i11
State machine has 32 reachable states with original encodings of:
@@ -2686,31 +2685,31 @@ State machine has 32 reachable states with original encodings of:
11101
11110
11111
Finished optimization stage 2 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s .......
Finished optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PERMC_TOP_1s_26s .......
Finished optimization stage 2 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s .......
Finished optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB)
Finished optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB)
Running optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s .......
Finished optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:01s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_PECRC_1s_26s .......
Finished optimization stage 2 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_PETMC_TOP_1s_26s .......
Finished optimization stage 2 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s .......
Finished optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s .......
Finished optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s .......
Finished optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXFIF_HST_Z8 .......
Finished optimization stage 2 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 .......
Finished optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s .......
Finished optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s .......
Extracted state machine for register genblk1.O0Il1
State machine has 5 reachable states with original encodings of:
@@ -2719,24 +2718,24 @@ State machine has 5 reachable states with original encodings of:
1100
1110
1111
Finished optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s .......
Finished optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s .......
Finished optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s .......
Finished optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s .......
Finished optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CTSE_DECODER .......
Finished optimization stage 2 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CORESPI_0 .......
Finished optimization stage 2 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CORESPI_Z7 .......
Finished optimization stage 2 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_chanctrl_Z6 .......
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Trying to extract state machine for register mtx_state.
@@ -2748,66 +2747,66 @@ State machine has 6 reachable states with original encodings of:
0111
1000
1001
Finished optimization stage 2 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_clockmux .......
Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_fifo_16s_32s_5 .......
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=1
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=16
Finished optimization stage 2 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_control_16s .......
Finished optimization stage 2 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on spi_rf_32s_16s_0 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREJTAGDEBUG_C0 .......
Finished optimization stage 2 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CLKINT .......
Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 .......
Finished optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on BUFD .......
Finished optimization stage 2 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on corejtagdebug_bufd_34s .......
Finished optimization stage 2 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on UJTAG .......
Finished optimization stage 2 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREJTAGDEBUG_Z5 .......
Finished optimization stage 2 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0 .......
Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on VCC .......
Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on GND .......
Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on RAM1K20 .......
Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 .......
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CoreAPB3_0 .......
Finished optimization stage 2 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on CoreAPB3_Z1 .......
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on COREAPB3_MUXPTOB3 .......
Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on Core_reset_pf .......
Finished optimization stage 2 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF .......
@N: CL135 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":58:0:58:5|Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on BIBUF .......
Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
Running optimization stage 2 on AND2 .......
Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB)
Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 397MB)
For a summary of runtime per design unit, please see file:
==========================================================
@@ -2815,12 +2814,12 @@ For a summary of runtime per design unit, please see file:
At c_ver Exit (Real Time elapsed 0h:02m:47s; CPU Time elapsed 0h:02m:47s; Memory used current: 381MB peak: 398MB)
At c_ver Exit (Real Time elapsed 0h:04m:12s; CPU Time elapsed 0h:04m:12s; Memory used current: 380MB peak: 397MB)
Process took 0h:02m:47s realtime, 0h:02m:47s cputime
Process took 0h:04m:12s realtime, 0h:04m:12s cputime
Process completed successfully.
# Wed Apr 15 22:47:45 2026
# Fri Apr 17 08:31:33 2026
###########################################################]
###########################################################[
@@ -2842,12 +2841,12 @@ Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 540R, Built Apr
@N|Running in 64-bit mode
File E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 137MB peak: 138MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 82MB peak: 133MB)
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
Process completed successfully.
# Wed Apr 15 22:47:48 2026
# Fri Apr 17 08:31:37 2026
###########################################################]
@@ -2857,11 +2856,11 @@ For a summary of runtime and memory usage for all design units, please see file:
@END
At c_hdl Exit (Real Time elapsed 0h:02m:51s; CPU Time elapsed 0h:02m:50s; Memory used current: 23MB peak: 24MB)
At c_hdl Exit (Real Time elapsed 0h:04m:17s; CPU Time elapsed 0h:04m:16s; Memory used current: 15MB peak: 24MB)
Process took 0h:02m:51s realtime, 0h:02m:50s cputime
Process took 0h:04m:17s realtime, 0h:04m:16s cputime
Process completed successfully.
# Wed Apr 15 22:47:49 2026
# Fri Apr 17 08:31:37 2026
###########################################################]

BIN
synthesis/synlog/top_compiler.srr.db
View File

Binary file not shown.

1989
synthesis/synlog/top_fpga_mapper.srr
View File

File diff suppressed because it is too large Load Diff

BIN
synthesis/synlog/top_fpga_mapper.srr.db
View File

Binary file not shown.

BIN
synthesis/synlog/top_fpga_mapper.szr
View File

Binary file not shown.

6
synthesis/synlog/top_multi_srs_gen.srr
View File

@@ -17,11 +17,11 @@ Synopsys Synopsys Netlist Linker, Version comp202309synp1, Build 540R, Built Apr
@N|Running in 64-bit mode
File E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 156MB peak: 157MB)
At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 157MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
Process completed successfully.
# Wed Apr 15 22:47:53 2026
# Fri Apr 17 08:31:42 2026
###########################################################]

42
synthesis/synlog/top_premap.srr
View File

@@ -1,4 +1,4 @@
# Wed Apr 15 22:47:54 2026
# Fri Apr 17 08:31:43 2026
Copyright (C) 1994-2023 Synopsys, Inc.
@@ -19,7 +19,7 @@ Synopsys Microchip Technology Pre-mapping, Version map202309act, Build 395R, Bui
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB)
Done reading skeleton netlist (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB)
Reading constraint file: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc
@L: E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt
@@ -31,10 +31,10 @@ See clock summary report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top
Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 261MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB)
Mapper Initialization Complete (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB)
Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 265MB peak: 265MB)
Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 265MB peak: 265MB)
Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 266MB peak: 267MB)
@@ -65,10 +65,10 @@ NConnInternalConnection caching is on
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture.
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture.
Starting HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 338MB)
Starting HSTDM IP insertion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 338MB)
Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 339MB)
Finished HSTDM IP insertion (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB)
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
@@ -81,10 +81,10 @@ Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:0
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":32:8:32:11|Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":31:8:31:13|Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
Started DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB)
Started DisTri Cleanup (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 339MB peak: 339MB)
Finished DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 340MB)
Finished DisTri Cleanup (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 339MB peak: 340MB)
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
@@ -121,7 +121,7 @@ Finished DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:0
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9245:6:9245:11|Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top
Finished netlist restructuring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 348MB peak: 348MB)
Finished netlist restructuring (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 348MB peak: 348MB)
Some data will not be shown as it is part of encrypted module
@@ -133,7 +133,7 @@ Clock Summary
Level Clock Frequency Period Type Group Load
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 5011
1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 4979
2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0
0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1
@@ -163,7 +163,7 @@ Clock Load Summary
Clock Load Pin Seq Example Seq Example Comb Example
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - -
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 5011 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 4979 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
PHY_MDC_CLOCK 0 - - - -
REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF)
@@ -191,7 +191,7 @@ PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 2 PF_IOD_CDR
Finished Pre Mapping Phase.
@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
Starting constraint checker (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 333MB peak: 349MB)
Starting constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 334MB peak: 349MB)
Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog))
original code -> new code
@@ -263,11 +263,11 @@ original code -> new code
10 -> 10
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
Encoding state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog))
Encoding state machine state[2:0] (in view: work.fifo_to_tpsram_bridge(verilog))
original code -> new code
00 -> 0
01 -> 1
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
00 -> 00
01 -> 01
10 -> 10
Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
original code -> new code
0000 -> 0000000000000001
@@ -350,17 +350,17 @@ original code -> new code
11 -> 11
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 341MB peak: 349MB)
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 342MB peak: 349MB)
@W: MF511 |Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .
Finished constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 351MB peak: 365MB)
Finished constraint checker (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 351MB peak: 366MB)
Pre-mapping successful!
At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 249MB peak: 365MB)
At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:14s; Memory used current: 249MB peak: 366MB)
Process took 0h:00m:13s realtime, 0h:00m:13s cputime
# Wed Apr 15 22:48:08 2026
Process took 0h:00m:15s realtime, 0h:00m:15s cputime
# Fri Apr 17 08:31:59 2026
###########################################################]

BIN
synthesis/synlog/top_premap.srr.db
View File

Binary file not shown.

BIN
synthesis/synlog/top_premap.szr
View File

Binary file not shown.

30
synthesis/synplify.log
View File

@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 22:44:55 2026
Date: Fri Apr 17 08:27:18 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -45,26 +45,26 @@ Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 22:44:56 2026
# Fri Apr 17 08:27:19 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 22:44:56 2026
# Fri Apr 17 08:27:19 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 22:44:56 2026
# Fri Apr 17 08:27:19 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 22:47:50 2026
# Fri Apr 17 08:31:39 2026
Return Code: 0
Run Time:00h:02m:53s
Run Time:00h:04m:18s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 22:47:50 2026
# Fri Apr 17 08:31:39 2026
multi_srs_gen completed
# Wed Apr 15 22:47:53 2026
# Fri Apr 17 08:31:42 2026
Return Code: 0
Run Time:00h:00m:03s
@@ -72,28 +72,28 @@ Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs t
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 22:47:53 2026
# Fri Apr 17 08:31:42 2026
premap completed with warnings
# Wed Apr 15 22:48:08 2026
# Fri Apr 17 08:31:59 2026
Return Code: 1
Run Time:00h:00m:15s
Run Time:00h:00m:17s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 22:48:08 2026
# Fri Apr 17 08:32:00 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 22:48:08 2026
# Fri Apr 17 08:32:00 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 22:52:04 2026
# Fri Apr 17 08:36:03 2026
Return Code: 1
Run Time:00h:03m:55s
Run Time:00h:04m:02s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"

30
synthesis/synplify.log.bak
View File

@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 21:56:01 2026
Date: Fri Apr 17 07:27:23 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -45,26 +45,26 @@ Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 21:56:02 2026
# Fri Apr 17 07:27:24 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 21:56:02 2026
# Fri Apr 17 07:27:24 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 21:56:02 2026
# Fri Apr 17 07:27:24 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 21:59:08 2026
# Fri Apr 17 07:30:40 2026
Return Code: 0
Run Time:00h:03m:05s
Run Time:00h:03m:15s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 21:59:08 2026
# Fri Apr 17 07:30:40 2026
multi_srs_gen completed
# Wed Apr 15 21:59:11 2026
# Fri Apr 17 07:30:43 2026
Return Code: 0
Run Time:00h:00m:03s
@@ -72,28 +72,28 @@ Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs t
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 21:59:11 2026
# Fri Apr 17 07:30:43 2026
premap completed with warnings
# Wed Apr 15 21:59:27 2026
# Fri Apr 17 07:30:59 2026
Return Code: 1
Run Time:00h:00m:15s
Run Time:00h:00m:16s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 21:59:27 2026
# Fri Apr 17 07:30:59 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 21:59:27 2026
# Fri Apr 17 07:30:59 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 22:03:19 2026
# Fri Apr 17 07:34:55 2026
Return Code: 1
Run Time:00h:03m:52s
Run Time:00h:03m:56s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"

30
synthesis/synplify.log.bak.1
View File

@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 20:20:12 2026
Date: Fri Apr 17 06:30:17 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -45,26 +45,26 @@ Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
# Fri Apr 17 06:30:18 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
# Fri Apr 17 06:30:18 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 20:20:13 2026
# Fri Apr 17 06:30:18 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 20:23:56 2026
# Fri Apr 17 06:34:36 2026
Return Code: 0
Run Time:00h:03m:42s
Run Time:00h:04m:17s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 20:23:56 2026
# Fri Apr 17 06:34:36 2026
multi_srs_gen completed
# Wed Apr 15 20:23:59 2026
# Fri Apr 17 06:34:39 2026
Return Code: 0
Run Time:00h:00m:03s
@@ -72,28 +72,28 @@ Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs t
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 20:23:59 2026
# Fri Apr 17 06:34:39 2026
premap completed with warnings
# Wed Apr 15 20:24:13 2026
# Fri Apr 17 06:34:56 2026
Return Code: 1
Run Time:00h:00m:14s
Run Time:00h:00m:17s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 20:24:13 2026
# Fri Apr 17 06:34:56 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 20:24:13 2026
# Fri Apr 17 06:34:56 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 20:28:51 2026
# Fri Apr 17 06:38:46 2026
Return Code: 1
Run Time:00h:04m:38s
Run Time:00h:03m:50s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"

32
synthesis/synplify.log.bak.2
View File

@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 19:30:13 2026
Date: Fri Apr 17 05:35:19 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -45,55 +45,55 @@ Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 19:30:14 2026
# Fri Apr 17 05:35:20 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 19:30:14 2026
# Fri Apr 17 05:35:20 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 19:30:14 2026
# Fri Apr 17 05:35:20 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
compiler completed
# Wed Apr 15 19:33:17 2026
# Fri Apr 17 05:39:25 2026
Return Code: 0
Run Time:00h:03m:02s
Run Time:00h:04m:03s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 19:33:17 2026
# Fri Apr 17 05:39:25 2026
multi_srs_gen completed
# Wed Apr 15 19:33:21 2026
# Fri Apr 17 05:39:28 2026
Return Code: 0
Run Time:00h:00m:04s
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 19:33:21 2026
# Fri Apr 17 05:39:28 2026
premap completed with warnings
# Wed Apr 15 19:33:37 2026
# Fri Apr 17 05:39:44 2026
Return Code: 1
Run Time:00h:00m:15s
Run Time:00h:00m:16s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 19:33:37 2026
# Fri Apr 17 05:39:44 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 19:33:37 2026
# Fri Apr 17 05:39:44 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 19:37:27 2026
# Fri Apr 17 05:43:22 2026
Return Code: 1
Run Time:00h:03m:50s
Run Time:00h:03m:37s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
TCL script complete: "top_syn.tcl"

61
synthesis/synplify.log.bak.3
View File

@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Wed Apr 15 18:31:21 2026
Date: Fri Apr 17 05:29:17 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -45,58 +45,29 @@ Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Wed Apr 15 18:31:22 2026
# Fri Apr 17 05:29:18 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Wed Apr 15 18:31:22 2026
# Fri Apr 17 05:29:18 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Wed Apr 15 18:31:22 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
# Fri Apr 17 05:29:18 2026
compiler exited with errors
Job failed on: top_syn|synthesis
compiler completed
# Wed Apr 15 18:34:18 2026
Job: "compiler" terminated with error status: 2
See log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr"
# Fri Apr 17 05:32:18 2026
Return Code: 0
Run Time:00h:02m:55s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Wed Apr 15 18:34:18 2026
multi_srs_gen completed
# Wed Apr 15 18:34:22 2026
Return Code: 0
Run Time:00h:00m:04s
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srs
Return Code: 2
Run Time:00h:03m:00s
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Wed Apr 15 18:34:22 2026
premap completed with warnings
# Wed Apr 15 18:34:37 2026
Return Code: 1
Run Time:00h:00m:15s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Wed Apr 15 18:34:37 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Wed Apr 15 18:34:37 2026
Copied E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm
fpga_mapper completed with warnings
# Wed Apr 15 18:38:40 2026
Return Code: 1
Run Time:00h:04m:03s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
Error: At line 2 while processing "top_syn.tcl"
2
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
TCL script had errors: "top_syn.tcl"
exit status=9
exit status=9
License checkin: synplifypro_actel

68
synthesis/synplify.log.bak.4
View File

@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Mon Apr 13 21:43:58 2026
Date: Fri Apr 17 05:21:33 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -36,66 +36,38 @@ License Option: actel_oem
Running in Vendor Mode
Implementation not found: synthesis
log file: "E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr"
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
# Fri Apr 17 05:21:34 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
# Fri Apr 17 05:21:34 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
# Fri Apr 17 05:21:34 2026
compiler exited with errors
Job failed on: top_syn|synthesis
compiler completed
# Mon Apr 13 21:47:56 2026
Job: "compiler" terminated with error status: 2
See log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr"
# Fri Apr 17 05:25:49 2026
Return Code: 0
Run Time:00h:03m:56s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Mon Apr 13 21:47:56 2026
multi_srs_gen completed
# Mon Apr 13 21:47:59 2026
Return Code: 0
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
Return Code: 2
Run Time:00h:04m:14s
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Mon Apr 13 21:47:59 2026
premap completed with warnings
# Mon Apr 13 21:48:16 2026
Return Code: 1
Run Time:00h:00m:17s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Mon Apr 13 21:48:16 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Mon Apr 13 21:48:16 2026
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srm
fpga_mapper completed with warnings
# Mon Apr 13 21:52:16 2026
Return Code: 1
Run Time:00h:04m:00s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\backup\top.srr
Error: At line 2 while processing "top_syn.tcl"
2
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
TCL script had errors: "top_syn.tcl"
exit status=9
exit status=9
License checkin: synplifypro_actel

73
synthesis/synplify.log.bak.5 Normal file
View File

@@ -0,0 +1,73 @@
Synplify Pro (R)
Version V-2023.09M-5 for win64 - Apr 29, 2025
Copyright (c) 1988 - 2025 Synopsys, Inc.
This software and the associated documentation are proprietary to Synopsys,
Inc. This software may only be used in accordance with the terms and conditions
of a written license agreement with Synopsys, Inc. All other use, reproduction,
or distribution of this software is strictly prohibited. Licensed Products
communicate with Synopsys servers for the purpose of providing software
updates, detecting software piracy and verifying that customers are using
Licensed Products in conformity with the applicable License Key for such
Licensed Products. Synopsys will use information gathered in connection with
this process to deliver software updates and pursue software pirates and
infringers.
Inclusivity & Diversity - Visit SolvNetPlus to read the "Synopsys Statement on
Inclusivity and Diversity" (Refer to article 000036315 at
https://solvnetplus.synopsys.com)
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Fri Apr 17 05:11:24 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
ProductType: synplify_pro
License checkout: synplifypro_actel
License: synplifypro_actel node-locked
Licensed Vendor: actel
License Option: actel_oem
Running in Vendor Mode
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Fri Apr 17 05:11:25 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Fri Apr 17 05:11:25 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Fri Apr 17 05:11:25 2026
compiler exited with errors
Job failed on: top_syn|synthesis
Job: "compiler" terminated with error status: 2
See log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr"
# Fri Apr 17 05:15:38 2026
Return Code: 2
Run Time:00h:04m:13s
Complete: Compile Process on top_syn|synthesis
Complete: Compile on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
Error: At line 2 while processing "top_syn.tcl"
2
TCL script complete: "top_syn.tcl"
TCL script had errors: "top_syn.tcl"
exit status=9
exit status=9
License checkin: synplifypro_actel

52
synthesis/synplify_job.log
View File

@@ -1,38 +1,38 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "22:52:04 15-Apr-2026",
"Date" : "08:36:03 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "22:44:56",
"Runtime" : "07m:08s",
"Executable Run Time" : "07m:05s",
"Start Time" : "08:27:19",
"Runtime" : "08m:44s",
"Executable Run Time" : "08m:40s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "22:44:56",
"Runtime" : "07m:08s",
"Executable Run Time" : "07m:05s",
"Start Time" : "08:27:19",
"Runtime" : "08m:44s",
"Executable Run Time" : "08m:40s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "22:44:56",
"Runtime" : "03m:12s",
"Executable Run Time" : "03m:11s",
"Start Time" : "08:27:19",
"Runtime" : "04m:40s",
"Executable Run Time" : "04m:38s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "22:44:56",
"Runtime" : "02m:57s",
"Executable Run Time" : "02m:56s",
"Start Time" : "08:27:19",
"Runtime" : "04m:23s",
"Executable Run Time" : "04m:21s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "22:44:56",
"Run Time" : "02m:54s",
"Exe Run Time" : "02m:53s",
"Run Start Time" : "08:27:19",
"Run Time" : "04m:20s",
"Exe Run Time" : "04m:18s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
@@ -42,7 +42,7 @@
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "22:47:50",
"Run Start Time" : "08:31:39",
"Run Time" : "03s",
"Exe Run Time" : "03s",
"Memory Usage" : "-",
@@ -55,27 +55,27 @@
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "22:47:53",
"Run Time" : "15s",
"Exe Run Time" : "15s",
"Run Start Time" : "08:31:42",
"Run Time" : "17s",
"Exe Run Time" : "17s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "22:48:08",
"Runtime" : "03m:56s",
"Executable Run Time" : "03m:54s",
"Start Time" : "08:32:00",
"Runtime" : "04m:03s",
"Executable Run Time" : "04m:02s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "22:48:08",
"Run Time" : "03m:56s",
"Exe Run Time" : "03m:54s",
"Run Start Time" : "08:32:00",
"Run Time" : "04m:03s",
"Exe Run Time" : "04m:02s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}

50
synthesis/synplify_job.log.bak
View File

@@ -1,38 +1,38 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "22:03:19 15-Apr-2026",
"Date" : "07:34:55 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "21:56:02",
"Runtime" : "07m:17s",
"Executable Run Time" : "07m:15s",
"Start Time" : "07:27:24",
"Runtime" : "07m:31s",
"Executable Run Time" : "07m:30s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "21:56:02",
"Runtime" : "07m:17s",
"Executable Run Time" : "07m:15s",
"Start Time" : "07:27:24",
"Runtime" : "07m:31s",
"Executable Run Time" : "07m:30s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "21:56:02",
"Runtime" : "03m:25s",
"Executable Run Time" : "03m:23s",
"Start Time" : "07:27:24",
"Runtime" : "03m:35s",
"Executable Run Time" : "03m:34s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "21:56:02",
"Runtime" : "03m:09s",
"Executable Run Time" : "03m:08s",
"Start Time" : "07:27:24",
"Runtime" : "03m:19s",
"Executable Run Time" : "03m:18s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "21:56:02",
"Run Time" : "03m:06s",
"Exe Run Time" : "03m:05s",
"Run Start Time" : "07:27:24",
"Run Time" : "03m:16s",
"Exe Run Time" : "03m:15s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
@@ -42,7 +42,7 @@
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "21:59:08",
"Run Start Time" : "07:30:40",
"Run Time" : "03s",
"Exe Run Time" : "03s",
"Memory Usage" : "-",
@@ -55,27 +55,27 @@
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "21:59:11",
"Run Start Time" : "07:30:43",
"Run Time" : "16s",
"Exe Run Time" : "15s",
"Exe Run Time" : "16s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "21:59:27",
"Runtime" : "03m:52s",
"Executable Run Time" : "03m:52s",
"Start Time" : "07:30:59",
"Runtime" : "03m:56s",
"Executable Run Time" : "03m:56s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "21:59:27",
"Run Time" : "03m:52s",
"Exe Run Time" : "03m:52s",
"Run Start Time" : "07:30:59",
"Run Time" : "03m:56s",
"Exe Run Time" : "03m:56s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}

52
synthesis/synplify_job.log.bak.1
View File

@@ -1,38 +1,38 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "20:28:51 15-Apr-2026",
"Date" : "06:38:46 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "20:20:13",
"Runtime" : "08m:38s",
"Executable Run Time" : "08m:36s",
"Start Time" : "06:30:18",
"Runtime" : "08m:28s",
"Executable Run Time" : "08m:27s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "20:20:13",
"Runtime" : "08m:38s",
"Executable Run Time" : "08m:36s",
"Start Time" : "06:30:18",
"Runtime" : "08m:28s",
"Executable Run Time" : "08m:27s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "20:20:13",
"Runtime" : "04m:00s",
"Executable Run Time" : "03m:59s",
"Start Time" : "06:30:18",
"Runtime" : "04m:38s",
"Executable Run Time" : "04m:37s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "20:20:13",
"Runtime" : "03m:46s",
"Executable Run Time" : "03m:45s",
"Start Time" : "06:30:18",
"Runtime" : "04m:21s",
"Executable Run Time" : "04m:20s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "20:20:13",
"Run Time" : "03m:43s",
"Exe Run Time" : "03m:42s",
"Run Start Time" : "06:30:18",
"Run Time" : "04m:18s",
"Exe Run Time" : "04m:17s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
@@ -42,7 +42,7 @@
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "20:23:56",
"Run Start Time" : "06:34:36",
"Run Time" : "03s",
"Exe Run Time" : "03s",
"Memory Usage" : "-",
@@ -55,27 +55,27 @@
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "20:23:59",
"Run Time" : "14s",
"Exe Run Time" : "14s",
"Run Start Time" : "06:34:39",
"Run Time" : "17s",
"Exe Run Time" : "17s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "20:24:13",
"Runtime" : "04m:38s",
"Executable Run Time" : "04m:37s",
"Start Time" : "06:34:56",
"Runtime" : "03m:50s",
"Executable Run Time" : "03m:50s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "20:24:13",
"Run Time" : "04m:38s",
"Exe Run Time" : "04m:37s",
"Run Start Time" : "06:34:56",
"Run Time" : "03m:50s",
"Exe Run Time" : "03m:50s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}

54
synthesis/synplify_job.log.bak.2
View File

@@ -1,38 +1,38 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "19:37:27 15-Apr-2026",
"Date" : "05:43:22 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "19:30:14",
"Runtime" : "07m:13s",
"Executable Run Time" : "07m:11s",
"Start Time" : "05:35:20",
"Runtime" : "08m:02s",
"Executable Run Time" : "07m:59s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "19:30:14",
"Runtime" : "07m:13s",
"Executable Run Time" : "07m:11s",
"Start Time" : "05:35:20",
"Runtime" : "08m:02s",
"Executable Run Time" : "07m:59s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "19:30:14",
"Runtime" : "03m:23s",
"Executable Run Time" : "03m:21s",
"Start Time" : "05:35:20",
"Runtime" : "04m:24s",
"Executable Run Time" : "04m:22s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "19:30:14",
"Runtime" : "03m:07s",
"Executable Run Time" : "03m:06s",
"Start Time" : "05:35:20",
"Runtime" : "04m:08s",
"Executable Run Time" : "04m:06s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "19:30:14",
"Run Time" : "03m:03s",
"Exe Run Time" : "03m:02s",
"Run Start Time" : "05:35:20",
"Run Time" : "04m:05s",
"Exe Run Time" : "04m:03s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
@@ -42,9 +42,9 @@
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "19:33:17",
"Run Time" : "04s",
"Exe Run Time" : "04s",
"Run Start Time" : "05:39:25",
"Run Time" : "03s",
"Exe Run Time" : "03s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
@@ -55,27 +55,27 @@
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "19:33:21",
"Run Start Time" : "05:39:28",
"Run Time" : "16s",
"Exe Run Time" : "15s",
"Exe Run Time" : "16s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "19:33:37",
"Runtime" : "03m:50s",
"Executable Run Time" : "03m:50s",
"Start Time" : "05:39:44",
"Runtime" : "03m:38s",
"Executable Run Time" : "03m:37s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "19:33:37",
"Run Time" : "03m:50s",
"Exe Run Time" : "03m:50s",
"Run Start Time" : "05:39:44",
"Run Time" : "03m:38s",
"Exe Run Time" : "03m:37s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}

76
synthesis/synplify_job.log.bak.3
View File

@@ -1,50 +1,50 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "18:38:40 15-Apr-2026",
"Date" : "05:32:18 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "18:31:22",
"Runtime" : "07m:18s",
"Executable Run Time" : "07m:17s",
"Start Time" : "05:29:18",
"Runtime" : "03m:00s",
"Executable Run Time" : "03m:00s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "18:31:22",
"Runtime" : "07m:18s",
"Executable Run Time" : "07m:17s",
"Start Time" : "05:29:18",
"Runtime" : "03m:00s",
"Executable Run Time" : "03m:00s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "18:31:22",
"Runtime" : "03m:15s",
"Executable Run Time" : "03m:14s",
"Start Time" : "05:29:18",
"Runtime" : "03m:00s",
"Executable Run Time" : "03m:00s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "18:31:22",
"Start Time" : "05:29:18",
"Runtime" : "03m:00s",
"Executable Run Time" : "02m:59s",
"Executable Run Time" : "03m:00s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "18:31:22",
"Run Time" : "02m:56s",
"Exe Run Time" : "02m:55s",
"Return Code" : "2",
"Has Errors" : "yes",
"Run Start Time" : "05:29:18",
"Run Time" : "03m:00s",
"Exe Run Time" : "03m:00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
"multi_srs_gen" : {
"executable" : "bin64/syn_nfilter.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "18:34:18",
"Run Time" : "04s",
"Exe Run Time" : "04s",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "03s",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
@@ -52,30 +52,30 @@
"premap" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "18:34:22",
"Run Time" : "15s",
"Exe Run Time" : "15s",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "16s (16s UI processing)",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "18:34:37",
"Runtime" : "04m:03s",
"Executable Run Time" : "04m:03s",
"Start Time" : "-",
"Runtime" : "00s",
"Executable Run Time" : "00s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "18:34:37",
"Run Time" : "04m:03s",
"Exe Run Time" : "04m:03s",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "03m:48s (03m:48s UI processing)",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}

86
synthesis/synplify_job.log.bak.4
View File

@@ -1,81 +1,81 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "21:52:16 13-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/synthesis",
"Date" : "05:25:49 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "21:43:59",
"Runtime" : "08m:17s",
"Executable Run Time" : "08m:16s",
"Start Time" : "05:21:34",
"Runtime" : "04m:15s",
"Executable Run Time" : "04m:14s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "21:43:59",
"Runtime" : "08m:17s",
"Executable Run Time" : "08m:16s",
"Start Time" : "05:21:34",
"Runtime" : "04m:15s",
"Executable Run Time" : "04m:14s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "21:43:59",
"Runtime" : "04m:17s",
"Executable Run Time" : "04m:16s",
"Start Time" : "05:21:34",
"Runtime" : "04m:15s",
"Executable Run Time" : "04m:14s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "21:43:59",
"Runtime" : "04m:00s",
"Executable Run Time" : "03m:59s",
"Start Time" : "05:21:34",
"Runtime" : "04m:15s",
"Executable Run Time" : "04m:14s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/synthesis",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "21:43:59",
"Run Time" : "03m:57s",
"Exe Run Time" : "03m:56s",
"Return Code" : "2",
"Has Errors" : "yes",
"Run Start Time" : "05:21:34",
"Run Time" : "04m:15s",
"Exe Run Time" : "04m:14s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
"multi_srs_gen" : {
"executable" : "bin64/syn_nfilter.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/synthesis",
"Run State" : "Complete",
"Return Code" : "0",
"Has Errors" : "no",
"Run Start Time" : "21:47:56",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "03s",
"Exe Run Time" : "03s",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"premap" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "21:47:59",
"Run Time" : "17s",
"Exe Run Time" : "17s",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "16s (16s UI processing)",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "21:48:16",
"Runtime" : "04m:00s",
"Executable Run Time" : "04m:00s",
"Start Time" : "-",
"Runtime" : "00s",
"Executable Run Time" : "00s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/synthesis",
"Run State" : "Complete",
"Return Code" : "1",
"Has Errors" : "no",
"Run Start Time" : "21:48:16",
"Run Time" : "04m:00s",
"Exe Run Time" : "04m:00s",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "03m:48s (03m:48s UI processing)",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}

85
synthesis/synplify_job.log.bak.5 Normal file
View File

@@ -0,0 +1,85 @@
{
"Synplify Pro (R) Job Log" : {
"Date" : "05:15:39 17-Apr-2026",
"Working Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Install" : "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Synplify_Pro"
},
"synthesis" :{
"Job Flow" : "Sequential",
"Start Time" : "05:11:25",
"Runtime" : "04m:14s",
"Executable Run Time" : "04m:13s",
"synthesis" : {
"Job Flow" : "Sequential",
"Start Time" : "05:11:25",
"Runtime" : "04m:14s",
"Executable Run Time" : "04m:13s",
"compile" : {
"Job Flow" : "Sequential",
"Start Time" : "05:11:25",
"Runtime" : "04m:14s",
"Executable Run Time" : "04m:13s",
"compile_flow" : {
"Job Flow" : "Sequential",
"Start Time" : "05:11:25",
"Runtime" : "04m:14s",
"Executable Run Time" : "04m:13s",
"compiler" : {
"executable" : "bin64/c_hdl.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Complete",
"Return Code" : "2",
"Has Errors" : "yes",
"Run Start Time" : "05:11:25",
"Run Time" : "04m:14s",
"Exe Run Time" : "04m:13s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
},
"multi_srs_gen" : {
"executable" : "bin64/syn_nfilter.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "03s",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"premap" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "16s (16s UI processing)",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
},
"map" : {
"Job Flow" : "Sequential",
"Start Time" : "-",
"Runtime" : "00s",
"Executable Run Time" : "00s",
"fpga_mapper" : {
"executable" : "bin64/m_generic.exe",
"Run Directory" : "E:/AbhishekV/rising/ethernet_tpsram_test/synthesis",
"Run State" : "Canceled",
"Return Code" : "-",
"Has Errors" : "yes",
"Run Start Time" : "-",
"Run Time" : "03m:48s (03m:48s UI processing)",
"Exe Run Time" : "00s",
"Memory Usage" : "-",
"Up-to-date (run skipped)" : "no"
}
}
}
}
}

16
synthesis/syntmp/cmdrec_compiler.log
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File diff suppressed because one or more lines are too long

20
synthesis/syntmp/cmdrec_fpga_mapper.log
View File

@@ -1,15 +1,15 @@
E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -sap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -otap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.tap -omap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -multisrs -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -sap ..\top.sap -otap ..\top.tap -omap ..\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile ..\scratchproject.prs -multisrs -ovm ..\top.vm -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_prem.srd -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\top.srm -prjdir ..\ -prjname top_syn -log ..\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
rc:1 success:1 runtime:236
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
rc:1 success:1 runtime:243
file:..\top.sap|io:o|time:1776394919|size:51527|exec:0|csum:
file:..\top.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\top.map|io:o|time:1776273723|size:28|exec:0|csum:
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\top.vm|io:o|time:1776273719|size:6264001|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_prem.srd|io:i|time:1776273483|size:1522539|exec:0|csum:DB252AC6E8654F85B7F9005EEC2CBE52
file:..\top.map|io:o|time:1776395162|size:28|exec:0|csum:
file:..\scratchproject.prs|io:o|time:1776384319|size:12250|exec:0|csum:
file:..\top.vm|io:o|time:1776395157|size:6235009|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776394635|size:5771|exec:0|csum:9EDD738B22E99016375E4F77A1872003
file:..\synwork\top_prem.srd|io:i|time:1776394914|size:1529678|exec:0|csum:91328E69BFC4CE6776C8382E8503965D
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273723|size:4727|exec:0|csum:
file:..\top.srm|io:o|time:1776273714|size:28753|exec:0|csum:
file:..\synlog\top_fpga_mapper.srr|io:o|time:1776273723|size:628611|exec:0|csum:
file:top.plg|io:o|time:1776395162|size:4727|exec:0|csum:
file:..\top.srm|io:o|time:1776395151|size:29573|exec:0|csum:
file:..\synlog\top_fpga_mapper.srr|io:o|time:1776395162|size:618665|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6

6
synthesis/syntmp/cmdrec_multi_srs_gen.log
View File

@@ -1,7 +1,7 @@
E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_comp.srs -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_multi_srs_gen.srr
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\syn_nfilter.exe -link -top top -multisrs ..\synwork\top_comp.srs -osyn ..\synwork\top_mult.srs -log ..\synlog\top_multi_srs_gen.srr
rc:0 success:1 runtime:3
file:..\synwork\top_comp.srs|io:i|time:1776273468|size:2498683|exec:0|csum:D55B0D932EA25F21DF76D09F4D077B94
file:..\synwork\top_mult.srs|io:o|time:1776273473|size:16492|exec:0|csum:
file:..\synlog\top_multi_srs_gen.srr|io:o|time:1776273473|size:1172|exec:0|csum:
file:..\synwork\top_comp.srs|io:i|time:1776394897|size:2499581|exec:0|csum:34E574B8FDFA67D505F4D20299B516A9
file:..\synwork\top_mult.srs|io:o|time:1776394902|size:16470|exec:0|csum:
file:..\synlog\top_multi_srs_gen.srr|io:o|time:1776394902|size:1172|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\syn_nfilter.exe|io:i|time:1745943928|size:10549248|exec:1|csum:0E24E2994826988AAC59CDBFBC24908C

22
synthesis/syntmp/cmdrec_premap.log
View File

@@ -1,15 +1,15 @@
E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -flow prepass -gcc_prepass -osrd E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -qsap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -conchk_prepass E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile ..\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -flow prepass -gcc_prepass -osrd ..\synwork\top_prem.srd -qsap ..\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm ..\top.vm -conchk_prepass ..\top_cck.rpt -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_mult.srs -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\synwork\top_prem.srd -prjdir ..\ -prjname top_syn -log ..\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
rc:1 success:1 runtime:15
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
file:..\top.vm|io:o|time:1776270794|size:6521569|exec:0|csum:
file:..\top_cck.rpt|io:o|time:1776273487|size:16263|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_mult.srs|io:i|time:1776273473|size:16492|exec:0|csum:8A8FBA27CAD8D4F9ABE7B311078B4CA3
rc:1 success:1 runtime:17
file:..\scratchproject.prs|io:o|time:1776384319|size:12250|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776394914|size:1529678|exec:0|csum:
file:..\top.sap|io:o|time:1776394919|size:51527|exec:0|csum:
file:..\top.vm|io:o|time:1776391490|size:6226755|exec:0|csum:
file:..\top_cck.rpt|io:o|time:1776394918|size:16263|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776394635|size:5771|exec:0|csum:9EDD738B22E99016375E4F77A1872003
file:..\synwork\top_mult.srs|io:i|time:1776394902|size:16470|exec:0|csum:A940EB393DE3FFFAE7080C27C1364F80
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273475|size:0|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\synlog\top_premap.srr|io:o|time:1776273488|size:50209|exec:0|csum:
file:top.plg|io:o|time:1776394904|size:0|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776394914|size:1529678|exec:0|csum:
file:..\synlog\top_premap.srr|io:o|time:1776394919|size:49976|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6

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@@ -0,0 +1,4 @@
library ieee;
use ieee.std_logic_1164.all;
package genpackage is
end package genpackage;

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@@ -0,0 +1,28 @@
library ieee;
use ieee.std_logic_1164.all;
use work.genpackage.all;
entity top is
port (
EQ : out std_logic;
A : in std_logic_vector(12 downto 0);
B : in std_logic_vector(12 downto 0) );
end entity top;
architecture gen of top is
component CMP_EQ
generic (
width : integer );
port (
EQ : out std_logic;
A : in std_logic_vector;
B : in std_logic_vector );
end component;
begin
I1: CMP_EQ
generic map (
width => 13 )
port map (
EQ => EQ,
A => A,
B => B );
end architecture gen;

2
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<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
</pre></samp></body></html>

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###########################################################[
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09M-5
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
OS: Windows 10 or later
Hostname: SOFTWARE-PC
Implementation : synthesis
Synopsys VHDL Compiler, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @
@N|Running in 64-bit mode
@I:: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\genpkg2735a42304"
@I:: "syng0a42304"
@I:: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp2735a42304"
VHDL syntax check successful!

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2
synthesis/syntmp/run_option.xml
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@@ -3,7 +3,7 @@
Synopsys, Inc.
Version V-2023.09M-5
Project file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\run_option.xml
Written on Wed Apr 15 22:44:56 2026
Written on Fri Apr 17 08:27:18 2026
-->

38
synthesis/syntmp/statusReport.html
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@@ -37,36 +37,36 @@
<td>403</td>
<td>0</td>
<td>-</td>
<td>02m:53s</td>
<td>04m:18s</td>
<td>-</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td>
</tr>
<tr>
<td class="optionTitle"> (premap)</td><td>Complete</td>
<td>65</td>
<td>64</td>
<td>15</td>
<td>0</td>
<td>0m:13s</td>
<td>0m:13s</td>
<td>365MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:48 PM</font></td>
<td>0m:15s</td>
<td>0m:15s</td>
<td>366MB</td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td>
</tr>
<tr>
<td class="optionTitle"> (fpga_mapper)</td><td>Complete</td>
<td>103</td>
<td>102</td>
<td>120</td>
<td>0</td>
<td>03m:51s</td>
<td>03m:54s</td>
<td>521MB</td>
<td><font size="-1">4/15/2026</font><br/><font size="-2">10:52 PM</font></td>
<td>03m:58s</td>
<td>04m:02s</td>
<td>564MB</td>
<td><font size="-1">4/17/2026</font><br/><font size="-2">8:36 AM</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/15/2026</font><br/><font size="-2">10:47 PM</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>00m:03s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">4/17/2026</font><br/><font size="-2">8:31 AM</font></td> </tbody>
</table>
<br>
<table width="100%" border="1" cellspacing= "0" cellpadding= "0" >
@@ -74,8 +74,8 @@
<tfoot> <tr> <td class="optionTitle" colspan="2"></td><td class="optionTitle" colspan="2"></td></tr>
</tfoot>
<tbody> <tr>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2335</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7316</td>
<td title ="Total Carry Cells used" class="optionTitle" align="left">Carry Cells</td> <td>2263</td>
<td title ="Total Sequential Cells used" class="optionTitle" align="left">Sequential Cells</td> <td>7208</td>
</tr>
<tr>
<td title ="Total DSP Blocks used" class="optionTitle" align="left">DSP Blocks
@@ -85,13 +85,13 @@
<tr>
<td title ="Total Global Clock Buffers used" class="optionTitle" align="left">Global Clock Buffers</td> <td>7</td>
<td title ="Total RAM1K20 used" class="optionTitle" align="left">RAM1K20
(v_ram)</td> <td>34</td>
(v_ram)</td> <td>36</td>
</tr>
<tr>
<td title ="Total RAM64x12 used" class="optionTitle" align="left">RAM64x12
(v_ram)</td> <td>11</td>
<td title ="Total LUTs used" class="optionTitle" align="left">LUTs
(total_luts)</td> <td>15992</td>
(total_luts)</td> <td>15852</td>
</tr>
</tbody>
@@ -103,14 +103,14 @@
<tbody>
<tr><th class="optionTitle" align= "left ">Clock Name</th><th class="optionTitle" align= "left ">Req Freq</th><th class="optionTitle" align= "left ">Est Freq</th><th class="optionTitle" align= "left ">Slack</th></tr>
<tr> <td align="left">COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</td><td align="left">100.0 MHz</td><td align="left">13.4 MHz</td><td align="left">-32.246</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.0 MHz</td><td align="left">-5.671</td></tr>
<tr> <td align="left">PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</td><td align="left">80.0 MHz</td><td align="left">55.1 MHz</td><td align="left">-5.638</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</td><td align="left">125.0 MHz</td><td align="left">116.7 MHz</td><td align="left">-0.228</td></tr>
<tr> <td align="left">PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</td><td align="left">100.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</td><td align="left">625.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">230.3 MHz</td><td align="left">3.659</td></tr>
<tr> <td align="left">PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</td><td align="left">125.0 MHz</td><td align="left">225.1 MHz</td><td align="left">3.557</td></tr>
<tr> <td align="left">PHY_MDC_CLOCK</td><td align="left">2.9 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REFCLK_P</td><td align="left">125.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>
<tr> <td align="left">REF_CLK_0</td><td align="left">50.0 MHz</td><td align="left">NA</td><td align="left">NA</td></tr>

18
synthesis/syntmp/top.plg
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@@ -4,11 +4,11 @@
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Estimated Period : 74.491
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Requested Period : 10.000
@P: COREJTAGDEBUG_Z5|iUDRCK_inferred_clock - Slack : -32.246
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Frequency : 55.0 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Frequency : 55.1 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Frequency : 80.0 MHz
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Period : 18.171
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Estimated Period : 18.138
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Requested Period : 12.500
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Slack : -5.671
@P: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 - Slack : -5.638
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Frequency : 116.7 MHz
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Requested Frequency : 125.0 MHz
@P: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R - Estimated Period : 8.569
@@ -39,11 +39,11 @@
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Estimated Period : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Requested Period : 1.600
@P: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 - Slack : NA
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Frequency : 230.3 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Frequency : 225.1 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Frequency : 125.0 MHz
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Period : 4.341
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Estimated Period : 4.443
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Requested Period : 8.000
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Slack : 3.659
@P: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV - Slack : 3.557
@P: PHY_MDC_CLOCK - Estimated Frequency : NA
@P: PHY_MDC_CLOCK - Requested Frequency : 2.9 MHz
@P: PHY_MDC_CLOCK - Estimated Period : NA
@@ -70,9 +70,9 @@
@P: System - Requested Period : 10.000
@P: System - Slack : -27.793
@P: top Part : mpf300tfcg1152-1
@P: top Register bits : 7316
@P: top Register bits : 7208
@P: top DSP Blocks : 0
@P: top I/O primitives : 50
@P: top RAM1K20 : 34
@P: top RAM1K20 : 36
@P: top RAM64x12 : 11
@P: CPU Time : 0h:03m:50s
@P: CPU Time : 0h:03m:58s

4
synthesis/syntmp/top_cck_rpt.htm
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@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
@@ -14,7 +14,7 @@ Hostname: SOFTWARE-PC
Implementation : synthesis
# Written on Wed Apr 15 22:48:07 2026
# Written on Fri Apr 17 08:31:58 2026
##### DESIGN INFO #######################################################

2
synthesis/syntmp/top_dsp_rpt_txt.htm
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@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
##### START OF DSP REPORT #####

6
synthesis/syntmp/top_fanout_rpt_txt.htm
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@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
######## REPORT FOR HIGH FANOUT NETS ########
@@ -9,8 +9,8 @@ GLOBAL THRESHOLD - 5000
NET NAME CLOCK LOADS ASYNC RST LOADS SYNC RST LOADS ENABLE LOADS DATA LOADS TOTAL FANOUT GLOBAL BUFFER PRESENT
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
PF_CCC_0_0_OUT0_FABCLK_0 4701 0 0 0 0 4701 YES
PF_IOD_CDR_CCC_C0_0_TX_CLK_G 1288 0 0 0 0 1288 YES
PF_CCC_0_0_OUT0_FABCLK_0 4612 0 0 0 0 4612 YES
PF_IOD_CDR_CCC_C0_0_TX_CLK_G 1273 0 0 0 0 1273 YES
PF_IOD_CDR_C0_0_RX_CLK_R 1252 0 0 0 0 1252 YES
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0_TGT_TCK_0_i 205 0 0 0 0 205 YES
COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK 17 0 0 0 1 18 YES

12
synthesis/syntmp/top_ram_rpt_txt.htm
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@@ -1,5 +1,5 @@
<html><body><samp><pre>
<!@TC:1776273296>
<!@TC:1776394639>
##### START OF RAM REPORT #####
@@ -14,7 +14,7 @@ NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_4 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_5 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_6 4KX5_4KX5 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.rx4096x36_1.oi0Io_oi0Io_0_7 4KX4_4KX4 0 0 1(1/1/1) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
NO CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io[39:0] RAM DEFAULT CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_0 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST) RAM instance meets the required threshold for mapping using LSRAM.
CORETSE_0_inst_0.CORETSE_0_0.CoreTSE_TOP_INST.lOIO1\.tx2048x40_1.oi0Io_oi0Io_0_1 2KX10_2KX10 0 0 0(0/0/0) 0(0/0/0) (WRITE_FIRST/WRITE_FIRST)
@@ -61,9 +61,13 @@ YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0
YES MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 NA NA MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0 512X40_512X40 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 1KX20_1KX20 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
YES PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 NA NA PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 2KX10_2KX10 NA 0 0(0/0/0) 0(0/0/0) (NO_CHANGE/NO_CHANGE)
=====================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================
##### URAM REPORT #####

4368
synthesis/syntmp/top_srr.htm
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12
synthesis/syntmp/top_toc.htm
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@@ -38,19 +38,19 @@
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport47" target="srrFrame" title="">Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport51" target="srrFrame" title="">Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#clockReport55" target="srrFrame" title="">Clock: System</a> </li></ul></li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (22:49 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_dsp_rpt_txt.htm" target="srrFrame" title="">DSP Report (08:33 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_ram_rpt_txt.htm" target="srrFrame" title="">RAM Report (08:35 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_fanout_rpt_txt.htm" target="srrFrame" title="">Fanout Report (08:35 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_srr.htm#resourceUsage59" target="srrFrame" title="">Resource Utilization</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (22:51 15-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (22:48 15-Apr)</a>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\highrel_rpt.htm" target="srrFrame" title="">High Reliability Report (08:35 17-Apr)</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.tgl" target="srrFrame" title="">Constraint Checker Report (08:31 17-Apr)</a>
<ul >
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#UnconstrainedStartEndPointsCCK60" target="srrFrame" title="">Unconstrained Start/End Points</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#InapplicableconstraintsCCK61" target="srrFrame" title="">Inapplicable constraints</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ApplicableConstraintsWithIssuesCCK62" target="srrFrame" title="">Applicable constraints with issues</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#ConstraintsWithMatchingWildcardExpressionsCCK63" target="srrFrame" title="">Constraints with matching wildcard expressions</a> </li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top_cck_rpt.htm#LibraryReportCCK64" target="srrFrame" title="">Library Report</a> </li></ul></li>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (22:52 15-Apr)</a> </li></ul></li> </ul>
<li><a href="file:///E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\rpt_top_areasrr.htm" target="srrFrame" title="">Hierarchical Area Report(top) (08:36 17-Apr)</a> </li></ul></li> </ul>
</li>
</ul>

54
synthesis/syntmp/traplog.tlg
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@@ -1,24 +1,24 @@
@N: CD630 :"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp4998a42256":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a42256":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a42256":92:11:92:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@N: CD630 :"syng0a42256":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a42256":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a42256":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
@N: CD630 :"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\gentmp4998a38936":4:7:4:9|Synthesizing work.top.gen.
@N: CD630 :"syng0a38936":69:7:69:12|Synthesizing work.cmp_eq.cell_level.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 16 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 17 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 18 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 19 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 20 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 21 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 22 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 23 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 24 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 25 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 26 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 27 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 28 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 29 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 30 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@W: CD796 :"syng0a38936":92:11:92:18|Bit 31 of signal data_tmp is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit.
@N: CD630 :"syng0a38936":6:7:6:16|Synthesizing work.eq_element.eqn.
@W: CD280 :"syng0a38936":15:11:15:17|Unbound component MUXCY_L mapped to black box
@N: CD630 :"syng0a38936":15:11:15:17|Synthesizing work.muxcy_l.syn_black_box.
Post processing for work.muxcy_l.syn_black_box
Running optimization stage 1 on MUXCY_L .......
Finished optimization stage 1 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
@@ -27,15 +27,15 @@ Running optimization stage 1 on eq_element .......
Finished optimization stage 1 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Post processing for work.cmp_eq.cell_level
Running optimization stage 1 on CMP_EQ .......
Finished optimization stage 1 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 1 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Post processing for work.top.gen
Running optimization stage 1 on top .......
Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on MUXCY_L .......
Finished optimization stage 2 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on MUXCY_L (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on eq_element .......
Finished optimization stage 2 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on eq_element (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on CMP_EQ .......
Finished optimization stage 2 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on CMP_EQ (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)
Running optimization stage 2 on top .......
Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 90MB)
Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 89MB peak: 91MB)

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synthesis/syntmp/traplog.tlg.db
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47
synthesis/syntmp/vhdlsyn1992a31412_top_wrapper.vhd Normal file
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@@ -0,0 +1,47 @@
--
-- Synopsys
-- Vhdl wrapper for top level design, written on Fri Apr 17 07:31:32 2026
--
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genpackage.all;
entity wrapper_for_top is
port (
EQ : out std_logic;
A : in std_logic_vector(9 downto 0);
B : in std_logic_vector(9 downto 0)
);
end wrapper_for_top;
architecture gen of wrapper_for_top is
component top
port (
EQ : out std_logic;
A : in std_logic_vector (9 downto 0);
B : in std_logic_vector (9 downto 0)
);
end component;
signal tmp_EQ : std_logic;
signal tmp_A : std_logic_vector (9 downto 0);
signal tmp_B : std_logic_vector (9 downto 0);
begin
EQ <= tmp_EQ;
tmp_A <= A;
tmp_B <= B;
u1: top port map (
EQ => tmp_EQ,
A => tmp_A,
B => tmp_B
);
end gen;

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