head tail filter testing done

This commit is contained in:
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions

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m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dE:/AbhishekV/rising/ethernet_tpsram_test/simulation

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m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dE:/AbhishekV/rising/ethernet_tpsram_test/simulation

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m255
K4
z2
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
dE:/AbhishekV/rising/ethernet_tpsram_test/simulation

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AMBA BFM Compiler (BETA Version 2.1.107 04Feb09)
Reading
Processing ./coreapb3_usertb_master.bfm
Enumerating
Assigning
Checking
Checking Complete
31 Global localconstants Defined
42 Global localvariables Defined
Writing Vectors ./coreapb3_usertb_master.vec
Commands Generated 201
Vectors Generated 666
Vector CheckSum cd447d4c
BFM Compiler Completed Okay

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41
simulation/run.do Normal file
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quietly set ACTELLIBNAME PolarFire
quietly set PROJECT_DIR "E:/AbhishekV/rising/ethernet_tpsram_test"
source "${PROJECT_DIR}/simulation/bfmtovec_compile.tcl";
if {[file exists ../designer/top/simulation/postlayout/_info]} {
echo "INFO: Simulation library ../designer/top/simulation/postlayout already exists"
} else {
file delete -force ../designer/top/simulation/postlayout
vlib ../designer/top/simulation/postlayout
}
vmap postlayout ../designer/top/simulation/postlayout
vmap PolarFire "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire"
if {[file exists COREAPB3_LIB/_info]} {
echo "INFO: Simulation library COREAPB3_LIB already exists"
} else {
file delete -force COREAPB3_LIB
vlib COREAPB3_LIB
}
vmap COREAPB3_LIB "COREAPB3_LIB"
if {[file exists COREJTAGDEBUG_LIB/_info]} {
echo "INFO: Simulation library COREJTAGDEBUG_LIB already exists"
} else {
file delete -force COREJTAGDEBUG_LIB
vlib COREJTAGDEBUG_LIB
}
vmap COREJTAGDEBUG_LIB "COREJTAGDEBUG_LIB"
if {[file exists CORESPI_LIB/_info]} {
echo "INFO: Simulation library CORESPI_LIB already exists"
} else {
file delete -force CORESPI_LIB
vlib CORESPI_LIB
}
vmap CORESPI_LIB "CORESPI_LIB"
vlog -sv -work postlayout "${PROJECT_DIR}/designer/top/top_ba.v"
vsim -L PolarFire -L postlayout -L COREAPB3_LIB -L COREJTAGDEBUG_LIB -L CORESPI_LIB -t 1ps -pli E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll -sdfmax /top=${PROJECT_DIR}/designer/top/top_slow_lv_ht_ba.sdf +transport_path_delays postlayout.top
# The following lines are commented because no testbench is associated with the project
# add wave /testbench/*
# run 1000ns

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# Reading pref.tcl
# do run.do
# --- Using Windows Actel DirectCore AMBA BFM compiler
# --- Compiling Actel DirectCore AMBA BFM source files ...
#
# AMBA BFM Compiler (BETA Version 2.1.107 04Feb09)
# Reading
# Processing ./coreapb3_usertb_master.bfm
# Enumerating
# Assigning
# Checking
# Checking Complete
# 31 Global localconstants Defined
# 42 Global localvariables Defined
# Writing Vectors ./coreapb3_usertb_master.vec
# Commands Generated 201
# Vectors Generated 666
# Vector CheckSum cd447d4c
#
# BFM Compiler Completed Okay
# --- Done Compiling Actel DirectCore AMBA BFM source files.
# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
# vmap postlayout ../designer/top/simulation/postlayout
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
# vmap PolarFire E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
# vmap COREAPB3_LIB COREAPB3_LIB
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
# vmap COREJTAGDEBUG_LIB COREJTAGDEBUG_LIB
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vmap 2024.3 Lib Mapping Utility 2024.09 Sep 11 2024
# vmap CORESPI_LIB CORESPI_LIB
# Modifying modelsim.ini
# Model Technology ModelSim Microsemi Pro vlog 2024.3 Compiler 2024.09 Sep 11 2024
# Start time: 11:58:37 on Apr 16,2026
# vlog -reportprogress 300 -sv -work postlayout E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v
# -- Compiling module top
#
# Top level modules:
# top
# End time: 11:58:42 on Apr 16,2026, Elapsed time: 0:00:05
# Errors: 0, Warnings: 0
# vsim -L PolarFire -L postlayout -L COREAPB3_LIB -L COREJTAGDEBUG_LIB -L CORESPI_LIB -t 1ps -pli "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll" -sdfmax "/top=E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_slow_lv_ht_ba.sdf" "+transport_path_delays" postlayout.top
# Start time: 11:58:43 on Apr 16,2026
# // ModelSim Microsemi Pro 2024.3 Sep 11 2024
# //
# // Unpublished work. Copyright 2024 Siemens
# //
# // This material contains trade secrets or otherwise confidential information
# // owned by Siemens Industry Software Inc. or its affiliates (collectively,
# // "SISW"), or its licensors. Access to and use of this information is strictly
# // limited as set forth in the Customer's applicable agreements with SISW.
# //
# // This material may not be copied, distributed, or otherwise disclosed outside
# // of the Customer's facilities without the express written permission of SISW,
# // and may not be used in any way not expressly authorized by SISW.
# //
# Loading sv_std.std
# Loading postlayout.top
# Loading PolarFire.CFG4
# Loading PolarFire.SLE
# Loading PolarFire.SLE_Prim
# Loading PolarFire.CFG3
# Loading PolarFire.ARI1_CC
# Loading PolarFire.CFG4_IP_ABCD
# Loading PolarFire.BUFF
# Loading PolarFire.INV_BA
# Loading PolarFire.RAM64x12_IP
# Loading PolarFire.OUTPUT_PMOS
# Loading PolarFire.INPUT_BUF
# Loading PolarFire.CFG2
# Loading PolarFire.RAM1K20_IP
# Loading PolarFire.RAM_DLY
# Loading PolarFire.ECC_PIPELINE
# Loading PolarFire.SLE_IP_EN
# Loading PolarFire.IOTRI_OB_EB
# Loading PolarFire.CC_CONFIG
# Loading PolarFire.CFG1
# Loading PolarFire.CFG4A
# Loading PolarFire.IOPAD_IN
# Loading PolarFire.IOPAD_TRI
# Loading PolarFire.FCEND_BUFF_CC
# Loading PolarFire.RGB
# Loading PolarFire.ICB_CLKINT
# Loading PolarFire.HS_IO_CLK
# Loading PolarFire.IOPADN_IN
# Loading PolarFire.IOBI_IB_OB_EB
# Loading PolarFire.IOIN_IB_E
# Loading PolarFire.PLL_DELAY
# Loading PolarFire.PLL_DELAY_IP
# Loading PolarFire.DLL_DELAY_BLOCK
# Loading PolarFire.IO_DIFF
# Loading PolarFire.PLL_IP
# Loading PolarFire.PLL_DRI_REGISTERS
# Loading PolarFire.pll_lp_vco
# Loading PolarFire.CCC_RF_DIV
# Loading PolarFire.Freq_Divider
# Loading PolarFire.Even_Divider
# Loading PolarFire.Odd_Divider
# Loading PolarFire.CCC_FB_DIV
# Loading PolarFire.frac_divider
# Loading PolarFire.freq_multiplier
# Loading PolarFire.CCC_PLL
# Loading PolarFire.ABISCB82
# Loading PolarFire.ABI_PLL_FRONT
# Loading PolarFire.refstop
# Loading PolarFire.Divide_2
# Loading PolarFire.ABI_PHASE
# Loading PolarFire.PLL_PHASE_SELECT
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_postdiv_pd_sync
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_divsw8
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_tff_st1x_loadb
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_cmosdiv_2to127
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_ffbrx1cstm
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_latchx1cstmb
# Loading PolarFire.PF_PLLUM28HLPMFFRAC_ffqbibrbx1cstm
# Loading PolarFire.CCC_POST_DIV
# Loading PolarFire.CCC_POSTDIVEN_SYNC
# Loading PolarFire.div2
# Loading PolarFire.CCC_8X1_MUX
# Loading PolarFire.CCC_2X1_MUX
# Loading PolarFire.GB
# Loading PolarFire.IOPADP_IN
# Loading PolarFire.ICB_CLKDIV
# Loading PolarFire.ICB_CLKDIVDELAY
# Loading PolarFire.clk_div_3p5
# Loading PolarFire.clk_div_5
# Loading PolarFire.LANECTRL
# Loading PolarFire.IOD_IP
# Loading PolarFire.IOPADN_TRI
# Loading PolarFire.IOPAD_BI
# Loading PolarFire.BANKEN
# Loading PolarFire.IOPADP_TRI
# Loading PolarFire.CFG0
# Loading PolarFire.GND
# Loading PolarFire.VCC
# SDF 2024.3 Compiler 2024.09 Sep 11 2024
#
# Loading instances from E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_slow_lv_ht_ba.sdf
# Loading PolarFire.UDP_MUX2
# Loading PolarFire.UDP_DFF
# Loading PolarFire.UDP_DL
# Loading PolarFire.UDP_GBLAT_T
# Loading PolarFire.UDP_GBLAT
# Loading E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll
# Loading timing data from E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_slow_lv_ht_ba.sdf
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Instance: /top File: E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top_ba.v