42 lines
1.7 KiB
Plaintext
42 lines
1.7 KiB
Plaintext
quietly set ACTELLIBNAME PolarFire
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quietly set PROJECT_DIR "E:/AbhishekV/rising/ethernet_tpsram_test"
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source "${PROJECT_DIR}/simulation/bfmtovec_compile.tcl";
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if {[file exists ../designer/top/simulation/postlayout/_info]} {
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echo "INFO: Simulation library ../designer/top/simulation/postlayout already exists"
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} else {
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file delete -force ../designer/top/simulation/postlayout
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vlib ../designer/top/simulation/postlayout
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}
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vmap postlayout ../designer/top/simulation/postlayout
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vmap PolarFire "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire"
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if {[file exists COREAPB3_LIB/_info]} {
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echo "INFO: Simulation library COREAPB3_LIB already exists"
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} else {
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file delete -force COREAPB3_LIB
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vlib COREAPB3_LIB
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}
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vmap COREAPB3_LIB "COREAPB3_LIB"
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if {[file exists COREJTAGDEBUG_LIB/_info]} {
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echo "INFO: Simulation library COREJTAGDEBUG_LIB already exists"
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} else {
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file delete -force COREJTAGDEBUG_LIB
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vlib COREJTAGDEBUG_LIB
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}
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vmap COREJTAGDEBUG_LIB "COREJTAGDEBUG_LIB"
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if {[file exists CORESPI_LIB/_info]} {
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echo "INFO: Simulation library CORESPI_LIB already exists"
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} else {
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file delete -force CORESPI_LIB
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vlib CORESPI_LIB
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}
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vmap CORESPI_LIB "CORESPI_LIB"
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vlog -sv -work postlayout "${PROJECT_DIR}/designer/top/top_ba.v"
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vsim -L PolarFire -L postlayout -L COREAPB3_LIB -L COREJTAGDEBUG_LIB -L CORESPI_LIB -t 1ps -pli E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll -sdfmax /top=${PROJECT_DIR}/designer/top/top_slow_lv_ht_ba.sdf +transport_path_delays postlayout.top
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# The following lines are commented because no testbench is associated with the project
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# add wave /testbench/*
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# run 1000ns
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