269 lines
11 KiB
Python
269 lines
11 KiB
Python
"""Seed the database with the launch content (products, founders, blog)."""
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from django.db import migrations
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from django.utils import timezone
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PRODUCTS = [
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{
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"slug": "ai-inference-ip",
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"name": "AI Inference IP Core",
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"category": "ai",
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"tagline": "Parallel inference at the edge — deterministic, quantised, portable.",
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"summary": (
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"A parallel-compute IP core for running quantised neural networks on FPGA "
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"or ASIC. Built for vision, sensor fusion, and on-orbit inference."
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),
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"description": (
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"Our AI Inference IP Core is designed for workloads where GPUs are too "
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"power-hungry and general-purpose NPUs are too opaque. It runs INT8 / INT4 "
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"quantised networks with deterministic latency, ports cleanly from FPGA "
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"prototype to ASIC tape-out, and is verifiable end-to-end."
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),
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"benefits": [
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"Higher throughput-per-watt than CPU / GPU at the edge",
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"Deterministic latency for real-time control loops",
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"INT8 / INT4 quantisation-aware datapath",
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"Synthesises on standard FPGA tooling",
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"Same RTL portable from FPGA to ASIC",
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],
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"features": [
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"Parameterised RTL",
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"Reference compiler for an ONNX subset",
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"FPGA reference design",
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"Integration guide & testbench",
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],
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"spec_table": [
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{"label": "Interface", "value": "AXI4 / AXI-Stream"},
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{"label": "Precision", "value": "INT8 / INT4"},
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{"label": "Targets", "value": "Xilinx UltraScale+, Intel Agilex, 28nm ASIC"},
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{"label": "Verification", "value": "UVM testbench included"},
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],
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"primary_cta_label": "Request evaluation",
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"sort_order": 1,
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},
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{
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"slug": "cybersecurity-ip",
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"name": "Cybersecurity IP Core",
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"category": "security",
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"tagline": "Hardware-accelerated cryptography — side-channel hardened.",
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"summary": (
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"A drop-in hardware accelerator for symmetric and asymmetric cryptography "
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"and secure boot — built for defense electronics and secure-element SoCs."
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),
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"description": (
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"Hardware acceleration for AES, SHA, ECC and RSA primitives, plus a secure "
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"boot block. Designed constant-time and side-channel hardened from the "
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"first line of RTL — security is not a wrapper, it's the architecture."
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),
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"benefits": [
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"Constant-time implementation",
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"Side-channel hardened",
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"FIPS-aligned algorithm set",
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"Low gate count for embedded targets",
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],
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"features": [
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"AES-128 / 256, SHA-2 / 3",
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"ECC (P-256, P-384), RSA-2048 / 4096",
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"True random number generator interface",
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"AXI / AHB wrappers",
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"Security white paper",
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],
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"spec_table": [
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{"label": "Interface", "value": "AXI4-Lite / AHB-Lite"},
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{"label": "Algorithms", "value": "AES, SHA-2/3, ECC, RSA"},
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{"label": "Targets", "value": "FPGA + 28/40nm ASIC"},
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{"label": "Compliance", "value": "FIPS-aligned"},
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],
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"primary_cta_label": "Request evaluation",
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"sort_order": 2,
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},
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{
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"slug": "communication-ip",
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"name": "Communication Protocol IP",
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"category": "comms",
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"tagline": "Space- and avionics-grade communication blocks. Flight-proven.",
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"summary": (
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"SpaceWire, CAN, UART/SPI/I2C and custom satellite payload buses — "
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"low gate-count, well-documented, and flight-proven on operational missions."
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),
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"description": (
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"Our communication IP catalogue is the most battle-tested part of our "
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"stack — variants of these cores have flown on operational satellite "
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"missions. We licence the same blocks to ground systems, payload "
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"integrators, and avionics OEMs."
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),
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"benefits": [
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"Space-qualified design practice",
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"Low gate-count for power-constrained targets",
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"Flight-heritage documentation",
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"Comprehensive verification IP",
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],
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"features": [
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"SpaceWire / SpaceFibre",
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"CAN-FD",
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"UART / SPI / I2C masters & slaves",
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"Custom satellite payload buses",
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"Reference designs + integration guide",
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],
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"spec_table": [
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{"label": "Protocols", "value": "SpaceWire, CAN-FD, UART, SPI, I2C"},
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{"label": "Heritage", "value": "Flown on operational satellite missions"},
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{"label": "Verification", "value": "Protocol-compliant testbenches"},
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],
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"primary_cta_label": "Request evaluation",
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"sort_order": 3,
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},
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]
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FOUNDERS = [
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{
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"name": "Ali Murabbi",
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"role": "Co-founder · VLSI & Robotics Engineer",
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"domain": "RTL / FPGA design · robotics control hardware · motion and sensor-fusion blocks",
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"bio": (
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"Hardware designer specialising in RTL and FPGA for robotics and motion "
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"systems. At SSPACE, IIST, contributed to onboard compute blocks for "
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"satellite payloads and now leads RisingCompute's communication-protocol "
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"and robotics IP work."
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),
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"sort_order": 1,
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},
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{
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"name": "Bhavy Savani",
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"role": "Co-founder · VLSI & AI Engineer",
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"domain": "RTL / FPGA design · quantised neural-network accelerators · verification",
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"bio": (
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"VLSI engineer focused on AI accelerator architectures and verification. "
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"At SSPACE, IIST, designed and verified compute IP that has flown in "
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"space; at RisingCompute, leads the AI Inference IP Core and the "
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"Cybersecurity IP Core."
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),
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"sort_order": 2,
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},
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{
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"name": "Abhishek Verma",
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"role": "Co-founder · System Engineer & Project Manager",
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"domain": "System architecture · integration · project delivery · GTM",
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"bio": (
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"Systems engineer and programme lead. Brings the IP, the engineering "
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"team, and the customer programme together — sets architecture, owns "
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"project delivery, and runs partner and customer conversations."
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),
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"sort_order": 3,
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},
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]
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BLOG_POSTS = [
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{
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"slug": "why-we-started-risingcompute",
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"title": "Why we started RisingCompute",
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"excerpt": (
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"Two years inside a satellite-software lab taught us something simple: "
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"the difference between what a research team can do with AI and what most "
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"engineers can do comes down to compute. We started RisingCompute to close "
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"that gap."
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),
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"category": "company",
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"author_name": "Abhishek Verma",
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"read_time_minutes": 4,
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"body": (
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"## A note from the founders\n\n"
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"RisingCompute was born inside the SSPACE lab at IIST. We spent two "
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"years building computation systems for satellites — IP that has since "
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"flown in space. What we kept noticing was the gap between what a "
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"research team can do with the right hardware and what a typical "
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"product team can do with whatever GPU they could afford.\n\n"
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"Our bet is that closing that gap is a hardware problem, not a "
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"software one. Parallel architectures, well-designed IP cores, and a "
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"vendor that ships datasheets you can actually read."
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),
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},
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{
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"slug": "what-flight-heritage-means-for-ip",
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"title": "What flight heritage actually means for IP cores",
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"excerpt": (
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"\"Flight-heritage\" is one of the most over-claimed phrases in the IP "
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"industry. Here's what it means to us, what it doesn't, and what to "
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"ask the next vendor that uses the term."
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),
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"category": "space",
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"author_name": "Ali Murabbi",
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"read_time_minutes": 6,
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"body": (
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"## What counts, and what doesn't\n\n"
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"Flight heritage is not just \"this RTL was synthesised onto a flight "
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"FPGA once.\" Real heritage is end-to-end: a documented chain from RTL "
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"to verification artifacts to a specific board, on a specific mission, "
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"with a specific telemetry track."
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),
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},
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{
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"slug": "int8-inference-without-accuracy-loss",
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"title": "Designing AI inference cores for INT8 without accuracy loss",
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"excerpt": (
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"Quantisation is a free lunch — until it isn't. A practical walk "
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"through the datapath choices that decide whether INT8 inference is "
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"production-ready or just a benchmark trick."
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),
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"category": "ai",
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"author_name": "Bhavy Savani",
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"read_time_minutes": 8,
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"body": (
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"## The two failure modes\n\n"
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"Most INT8 implementations fail in one of two ways: accuracy collapse "
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"from poor calibration, or throughput collapse from naive datapath "
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"layout. We walk through how we designed around both."
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),
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},
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{
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"slug": "indian-sovereign-ip-stack",
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"title": "An Indian sovereign IP stack — and why it matters now",
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"excerpt": (
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"\"Make in India\" content rules are reshaping defense and space "
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"procurement. A founder note on what an Indian-origin IP stack should "
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"look like — and what it shouldn't."
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),
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"category": "company",
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"author_name": "Abhishek Verma",
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"read_time_minutes": 5,
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"body": (
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"## Sovereign doesn't mean isolated\n\n"
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"Sovereign IP should mean Indian-origin design, Indian-origin "
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"verification, and an Indian-origin support chain. It does not mean "
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"rejecting global tooling or global customers."
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),
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},
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]
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def seed(apps, schema_editor):
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Product = apps.get_model("api", "Product")
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Founder = apps.get_model("api", "Founder")
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BlogPost = apps.get_model("api", "BlogPost")
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for row in PRODUCTS:
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Product.objects.update_or_create(slug=row["slug"], defaults=row)
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for row in FOUNDERS:
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Founder.objects.update_or_create(name=row["name"], defaults=row)
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for row in BLOG_POSTS:
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BlogPost.objects.update_or_create(
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slug=row["slug"],
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defaults={**row, "published_at": timezone.now()},
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)
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def unseed(apps, schema_editor):
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Product = apps.get_model("api", "Product")
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Founder = apps.get_model("api", "Founder")
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BlogPost = apps.get_model("api", "BlogPost")
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Product.objects.filter(slug__in=[r["slug"] for r in PRODUCTS]).delete()
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Founder.objects.filter(name__in=[r["name"] for r in FOUNDERS]).delete()
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BlogPost.objects.filter(slug__in=[r["slug"] for r in BLOG_POSTS]).delete()
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class Migration(migrations.Migration):
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dependencies = [("api", "0001_initial")]
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operations = [migrations.RunPython(seed, unseed)]
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