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RisingCompute — Website Design Document (Final)

Status: Complete. This is the build-ready spec for the RisingCompute marketing website. Every section has been finalised from the company brief; revisions tracked in §0.

0. Revision History

Version	Date	Author	Notes
0.1	18 May 2026	Abhishek Verma	Initial fill-in of company sections
1.0	19 May 2026	Abhishek Verma	Final document — all sections completed, target launch revised
1.1	19 May 2026	Abhishek Verma	Added founders section (§2.6); updated About page brief (§9.2) and stakeholder table (§20)

1. Project Snapshot

Field	Answer
Company name	RisingCompute
Legal entity name	RisingCompute Pvt Ltd
Primary domain	risingcompute.in
Working title for the project	RisingCompute Website Design
Target launch date	30 June 2026 (revised from 15 May 2026)
Budget range	Bootstrapped / built in-house — out-of-pocket cost target under ₹20,000 (domain, photography, third-party SaaS)
Document owner	Abhishek Verma — contact@risingcompute.in
Last updated	19 May 2026

2. Company Overview

2.1 Who we are

What we do (one sentence): RisingCompute designs parallel computer architectures and IP cores that accelerate AI, space, and robotics workloads at the hardware layer.
Tagline / one-liner: Accelerating the compute.
Elevator pitch: RisingCompute is a deep-tech semiconductor company building parallel computer architectures that accelerate AI workflows at the hardware level. Our IP cores power applications in AI, space, and robotics — including cybersecurity acceleration, AI inference, and space-qualified communication protocols. Born out of two years of satellite computation research at IIST, we are taking the same compute privilege researchers enjoy and packaging it into scalable, reusable hardware blocks. The long-term roadmap is custom AI ASICs for specific application classes.

2.2 Mission, vision, values

Mission: Accelerate compute for AI, space, and robotics.
Vision: Make computing better for the future — affordable, scalable, and accessible.
Core values: Fast · Reliable · Robust.

2.3 Company facts

Founded: 2026
Headquarters: Surat, Gujarat, India
Other offices / coverage areas: STIIC (Space Technology Incubation & Innovation Cell), IIST — Indian Institute of Space Science and Technology, Thiruvananthapuram
Team size: 5
Industry / sector: Semiconductors · AI hardware
Stage: [x] Pre-revenue [ ] Early revenue [ ] Growth [ ] Established

2.4 Our story

RisingCompute began in 2026 inside the SSPACE lab at IIST, where our founding team spent two years building computation systems for satellites — IP that has since flown in space. Working at that level taught us something simple: the difference between what a research team can do with AI and what most engineers and companies can do comes down to the compute they have access to. We started RisingCompute to close that gap. By building parallel hardware architectures and re-usable IP cores, we make accelerated compute scalable and easy to integrate — so an aerospace OEM, a robotics startup, or a defense electronics lab can get research-grade performance without rebuilding the stack from scratch.

2.5 Key milestones / achievements

2 years of satellite-software research at SSPACE, IIST.
IP cores flown on operational satellite missions.
Independent IP cores for cybersecurity, AI inference, and communication protocols — currently in testing.
Incubated at STIIC, IIST.

2.6 Founders

RisingCompute is founded by a three-person engineering team that has worked together inside the SSPACE lab at IIST. Each founder owns a clear technical domain, and together they cover the full stack from system architecture down to silicon.

Founder	Role	Domain
Ali Murabbi	Co-founder · VLSI & Robotics Engineer	RTL / FPGA design, robotics control hardware, motion and sensor-fusion blocks. Leads the Communication Protocol IP and robotics-facing inference work.
Bhavy Savani	Co-founder · VLSI & AI Engineer	RTL / FPGA design, quantised neural-network accelerators, verification. Leads the AI Inference IP Core and the Cybersecurity IP Core.
Abhishek Verma	Co-founder · System Engineer & Project Manager	System architecture, integration, project delivery, GTM, and external relationships. Document owner; primary point of contact at contact@risingcompute.in.

Short bios (used on the About page and press kit):

Ali Murabbi — Co-founder, VLSI & Robotics Engineer. Hardware designer specialising in RTL and FPGA for robotics and motion systems. At SSPACE, IIST, contributed to onboard compute blocks for satellite payloads and now leads RisingCompute's communication-protocol and robotics IP work.
Bhavy Savani — Co-founder, VLSI & AI Engineer. VLSI engineer focused on AI accelerator architectures and verification. At SSPACE, IIST, designed and verified compute IP that has flown in space; at RisingCompute, leads the AI Inference IP Core and the Cybersecurity IP Core.
Abhishek Verma — Co-founder, System Engineer & Project Manager. Systems engineer and programme lead. Brings the IP, the engineering team, and the customer programme together — sets architecture, owns project delivery, and runs partner and customer conversations.

3. Target Audience

3.1 Primary audience

Who they are: VLSI / FPGA design engineers, system architects, and R&D heads at organisations building flight, defense, robotics, or AI-edge hardware. Plus procurement leads at primes who licence IP cores rather than build in-house.
Where they're based: Primary — India (Bengaluru, Hyderabad, Thiruvananthapuram, Ahmedabad, Pune). Expansion — APAC (Singapore, Japan), then US and EU.
Age range: 26–55
Job titles / roles: VLSI engineer, FPGA engineer, ASIC designer, system architect, CTO, head of R&D, hardware lead, payload engineer, principal investigator, head of procurement.
Industries: Aerospace, defense electronics, space systems, robotics, AI compute / edge AI, semiconductors, automotive, telecom.

3.2 Audience personas

Persona 1 — "ASIC Arjun"

Role / background: Senior VLSI engineer at a satellite-payload company. ~8 years experience. Verilog/SystemVerilog daily, comfortable with FPGAs, occasional ASIC tape-outs.
Goals: Hit payload power and latency targets without re-inventing protocol blocks; reduce design schedule risk.
Pain points: Western IP vendors are expensive, slow to support, and rarely qualified for space environments; reinventing in-house eats 6–12 months per project.
What they need from our site: Datasheets, performance numbers, FPGA/ASIC support details, flight heritage evidence, an obvious "request evaluation" path.
Triggers to convert: Verified flight heritage, downloadable datasheet, response within 24 hours to an evaluation request.

Persona 2 — "Research Riya"

Role / background: R&D head at a robotics or edge-AI startup, ~10 years experience, ex-academia. Pushes vision and control loops to the edge.
Goals: Run larger models on the same power budget; shorten inference latency.
Pain points: GPU power draw is impossible at the edge; existing NPU IP is opaque, locked, expensive.
What they need from our site: Clear architecture story, benchmarks vs. common baselines (Jetson, Coral, Hailo), licence model, partnership channel.
Triggers to convert: Credible benchmark numbers, a technical blog post that respects her intelligence, a 30-min architect call.

Persona 3 — "Procurement Deepak"

Role / background: Strategic procurement / programme manager at a defense electronics prime. Buys IP and outsources design.
Goals: De-risk supply chain by sourcing Indian-origin IP for defense / DRDO programmes; meet "Make in India" content rules.
Pain points: Few credible Indian semiconductor IP vendors; uncertainty around long-term support and security certification.
What they need from our site: Company legitimacy (incubation, founders, address), security and compliance posture, a formal contact path.
Triggers to convert: Credentialed founders, government incubation badge, a phone-able address and direct email.

3.3 What we want visitors to do

Priority order:

[x] Contact sales / request evaluation — start an IP licensing or pilot conversation.
[x] Download a resource — datasheets, architecture whitepapers, benchmark briefs (lead-gated).
[x] Learn / build brand awareness — read about the company, founders, IIST heritage.
[x] Sign up for the newsletter — quarterly technical update.
[x] Apply for a job — careers page open from launch.
[x] Request a demo / consultation — 30-minute architect call.

Buy a product or service (not applicable — long-cycle B2B sales, no online checkout)

4. Goals, KPIs & Success Metrics

4.1 Business goals for this website

Generate 15–20 qualified IP-licensing or evaluation enquiries per quarter by Q4 2026.
Establish RisingCompute as the most credible India-origin semiconductor IP vendor for AI, space, and robotics.
Support fundraising and grant applications with a public, professional presence (founder bios, traction, press, technical depth).
Build an inbound talent funnel — receive 5+ relevant applications per open role per month.

4.2 Measurable KPIs

KPI	Current baseline	6-month target (Dec 2026)
Monthly unique visitors	0	3,000
Conversion rate (visit → lead)	0%	2.0%
Average session duration	0	1 min 30 sec
Demo / contact form submissions / month	0	15–20
Datasheet downloads / month	0	80
Organic search traffic / month	0	1,000
Career applications / month	0	10

4.3 What "success" looks like 12 months after launch

By May 2027, risingcompute.in is the default search result for "India IP core for AI / space / robotics." It has driven 80+ qualified inbound conversations, supported a pre-seed raise with credible founder and traction pages, on-boarded the first three paying pilot customers, and built a 500-subscriber technical newsletter.

5. Competitor & Inspiration Landscape

5.1 Direct competitors

Competitor	URL	What they do well	Where they fall short
Arm	arm.com	Dominant IP brand, deep documentation, huge ecosystem	Generic — no flight heritage, expensive for startups, opaque licensing
Synopsys DesignWare	synopsys.com	Breadth of IP, strong verification	Enterprise-only feel, no AI-specialist narrative
SiFive	sifive.com	Clean modern brand, strong RISC-V narrative, developer-friendly	US-centric, AI-edge story is recent
Hailo	hailo.ai	Sharp AI-accelerator positioning, benchmarks-forward	Focused on edge vision; closed architecture
VeriSilicon	verisilicon.com	Broad IP catalogue and ASIC services	Site feels dated; hard to navigate
Mythic / BrainChip	mythic.ai · brainchip.com	Differentiated architecture story	Narrow application focus

5.2 Sites we love (and why)

linear.app — confident dark theme, restrained motion, exceptional typography, copy that respects the reader.
stripe.com — editorial layout, gradient mesh imagery, "products" architecture we should learn from.
groq.com — closest peer in tone: hardware-AI company, technical without being a wall of PDFs.
sifive.com — RISC-V IP peer with a developer-respecting site.
vercel.com — fast, minimal, technical-but-warm voice.

5.3 Sites we want to look nothing like

Generic semiconductor-incumbent sites that are 1000-link mega-menus, stock photos of handshakes, and PDFs from 2014.

5.4 Our differentiators

Space-flight heritage from day one — our IP has flown; few startups can say this.
India-origin sovereign-stack IP — meaningful for ISRO ecosystem, DRDO supply chains, and "Make in India" content rules.
One vendor across cybersecurity, AI inference, and communication IP — adjacent blocks that are usually sourced from three different vendors.
Founder-led technical engagement — every evaluation request lands with an engineer, not a sales rep.

6. Products & Services

Offering 1 — AI Inference IP Core

What it is: A parallel-compute IP core for running quantised neural networks on FPGA / ASIC — targeted at vision, sensor fusion, and on-orbit inference.
Who it's for: Edge-AI product teams, robotics R&D, satellite payload engineers.
Key benefits:
- Higher throughput per watt than CPU/GPU at the edge.
- Deterministic latency — important for control loops and real-time payloads.
- Quantisation-aware data path (INT8 / INT4) without accuracy collapse.
- Synthesises on standard FPGA tooling.
- Same RTL portable from FPGA prototype to ASIC tape-out.
Features / what's included: Parameterised RTL, testbench, reference compiler for ONNX subset, integration guide, FPGA reference design.
Pricing model: [x] Custom quote (per-project licence)
Price points: Disclosed under NDA after a qualification call.
Primary CTA: "Request evaluation"
Supporting proof: Flight-heritage record from satellite missions; benchmark brief vs. Jetson / Coral / Hailo.

Offering 2 — Cybersecurity IP Core

What it is: Hardware accelerator for symmetric / asymmetric cryptography and secure boot — drop-in block for SoC designs.
Who it's for: Defense electronics, secure-element designers, comms equipment OEMs.
Key benefits: Constant-time implementation, side-channel hardened, FIPS-aligned, low gate count.
Features / what's included: RTL block, integration AXI/AHB wrappers, verification plan, test vectors, security white paper.
Pricing model: [x] Custom quote
Price points: Disclosed under NDA.
Primary CTA: "Request evaluation"
Supporting proof: Independent test reports, founder credentials.

Offering 3 — Communication Protocol IP Cores

What it is: Space- and avionics-grade communication protocol IP — SpaceWire, CAN, UART/SPI/I2C, and custom satellite payload buses.
Who it's for: Satellite primes, payload integrators, avionics OEMs.
Key benefits: Space-qualified, low gate-count, well-documented, flight-proven.
Features / what's included: RTL block, verification IP, integration guide, optional support contract.
Pricing model: [x] Custom quote
Price points: Disclosed under NDA.
Primary CTA: "Request evaluation"
Supporting proof: Flight heritage on operational satellites.

Offering 4 (Roadmap) — Custom AI ASIC Design Services

What it is: Custom silicon design for application-specific AI workloads. Not part of the launch site as a sellable product; presented on the Technology / Roadmap page as forward direction.

7. Brand Identity

7.1 Logo

[x] We need a logo designed — wordmark + symbol mark; symbol should reference parallelism / acceleration / orbit without being literal.

7.2 Color palette

Role	Color	Hex	Notes
Primary	Deep Space Indigo	`#0B1437`	Dominant background; conveys depth, space, technical seriousness
Secondary	Slate Navy	`#1A2347`	Cards, secondary surfaces
Accent	Accelerate Cyan	`#00E5FF`	CTAs, links, highlights, data viz
Neutral dark	Graphite	`#0E1118`	Headings on light, primary text on light
Neutral light	Mist	`#F4F6FB`	Light-theme background, large surfaces
Mid neutral	Steel	`#8A93A6`	Secondary text, captions, dividers
Success	Signal Green	`#22C55E`	Form success, status pills
Warning	Amber	`#F59E0B`	Inline warnings
Error	Critical Red	`#EF4444`	Form errors

Default theme: dark. A light theme is generated automatically (CSS variables) but is secondary.

7.3 Typography

Heading font: Inter (700 / 600)
Body font: Inter (400 / 500)
Monospace: JetBrains Mono — used for code blocks, datasheet numbers, and small "spec" pills

Type scale (rem): 0.75 · 0.875 · 1.0 · 1.125 · 1.25 · 1.5 · 1.875 · 2.25 · 3.0 · 3.75 · 4.5. Line-height 1.5 for body, 1.15 for display.

7.4 Imagery & illustration style

[x] Custom illustration — minimal, technical line art: chips, parallel data paths, orbital arcs. Two-tone (indigo + cyan).
[x] 3D renders — clean studio renders of chip / wafer hero visuals.
[x] Photography — small set of team photos (real, not staged) for the About page.
[x] Icon-led — stroke-style icons (Lucide) sized 16/20/24 px.

7.5 Voice & tone

Top adjectives (5): [x] Authoritative · [x] Technical · [x] Direct · [x] Bold · [x] Calm

Example phrases we'd say:

"Accelerating the compute." "Our IP has flown. Yours can too." "Built in India, qualified in orbit."

Example phrases we'd never say:

"Synergy," "best-in-class," "leveraging cutting-edge solutions," "revolutionary game-changer."

7.6 Existing brand assets

Brand guidelines doc — to be produced from this document.
Logo files — to be designed.
Photography library — initial team shoot scheduled.
Existing website copy — none; greenfield.

8. Site Structure (Information Architecture)

8.1 Sitemap

[x] Home
[x] About — story, team, values
- [x] Team / Leadership (sub-section on About)
- [x] Careers (linked from About and footer)
[x] Products — overview
- [x] AI Inference IP Core
- [x] Cybersecurity IP Core
- [x] Communication Protocol IP Cores
[x] Technology — architecture explainers, benchmarks, whitepapers
[x] Blog / Insights — technical posts, company news
- [x] Article template
- [x] Category pages (AI · Space · Robotics · Engineering · Company)
[x] Press / News
[x] Contact — also serves as "Request evaluation"
[x] 404 page
[x] Thank-you pages (post-form)
[x] Privacy Policy
[x] Terms of Service
[x] Cookie Policy
Pricing (out of scope — quote-based, no public pricing)
Partners (out of scope at launch; revisit when partner programme is real)
FAQ (folded into product pages)
Book a demo (folded into the Contact / Request evaluation form)

Products
Technology
About
Careers
CTA button — "Talk to us"

8.3 Footer

[x] Mini sitemap — Products · Technology · About · Careers · Blog · Contact
[x] Contact info — Surat HQ address, STIIC/IIST address, contact@risingcompute.in
[x] Social links — LinkedIn, X (Twitter), GitHub, YouTube (YouTube placeholder until content exists)
[x] Newsletter signup — single email field
[x] Legal links — Privacy · Terms · Cookies
[x] Company registration — "RisingCompute Pvt Ltd · CIN to be added · GSTIN to be added"
[x] Incubation badge — "Incubated at STIIC · IIST"

9. Page-by-Page Content Brief

9.1 Home

Hero headline: Accelerating the compute.
Hero sub-headline: Parallel hardware architectures and IP cores for AI, space, and robotics — designed in India, flown in orbit.
Primary CTA: "Talk to us" → /contact
Secondary CTA: "Read the architecture brief" → /technology
Sections (in order):
1. [x] Hero with 3D chip render + animated parallel data paths
2. [x] Social proof bar — IIST · STIIC · "Flight-heritage IP" pill
3. [x] What we do — three product highlights (AI · Cybersecurity · Comms)
4. [x] Why us / differentiators — flight heritage, sovereign IP, one-vendor stack
5. [x] How it works — Evaluate → Integrate → Tape-out
6. [x] Featured proof point — "Our IP has flown" with mission strip
7. [x] Recent blog posts (3)
8. [x] Final CTA block — "Start an evaluation" → /contact
Key visuals needed: Hero 3D chip render; animated SVG of parallel datapath; mission strip; engineer-at-workstation photo (Surat or IIST lab).

9.2 About

Origin story: Reuse §2.4 with photography of IIST and team.
Founders section: Three founder cards at the top of the team area — Ali Murabbi, Bhavy Savani, Abhishek Verma — each with portrait, role, domain, 80-word bio (see §2.6), and LinkedIn link.
Team intro: [x] Full team grid — 5 photos (3 founders + 2 early engineers), names, role, one-line bio, LinkedIn link.
Values block: §2.2 — Fast · Reliable · Robust as three icon cards.
Office / culture photos: [x] Yes — Surat office and STIIC/IIST.
Press / awards row: [x] Yes — placeholder slots until content exists.

9.3 Products / Services

Each product page follows the same template:

Hero with the offering name + one-liner
The problem it solves (3 sentences)
How it works — block diagram + 4–6 features
What's included — bulleted deliverables (RTL, testbench, integration guide, etc.)
Indicative specs table (interface, throughput, gate count, target nodes / FPGAs)
"Request evaluation" CTA + secondary "Download datasheet" (gated)
3-question FAQ specific to this product

9.4 Case Studies / Work

Number of case studies at launch: 0 published case studies; instead, a "Flight heritage" strip on the home and About pages noting that IP authored by the founding team has flown on satellite missions. Full case studies to be added as customers grant permission.

9.5 Pricing

[x] "Contact us" only — all IP is quote-based; pricing disclosed under NDA after a qualification call. No public pricing page.

9.6 Blog / Insights

Launch with: 4 posts.
1. "Why we started RisingCompute" — founder note
2. "What flight heritage actually means for IP cores"
3. "Designing AI inference cores for INT8 without accuracy loss"
4. "An Indian sovereign IP stack — and why it matters now"
Categories: AI · Space · Robotics · Engineering · Company
Authors shown: [x] Yes
Comments enabled: [ ] No — out of scope at launch
Newsletter signup on every post: [x] Yes

9.7 Contact

[x] Contact form — fields: Name, Work email, Company, Role, Country, Interest (dropdown: AI Inference IP · Cybersecurity IP · Communication IP · Custom ASIC · Careers · Press · Other), Message, How did you hear about us?
[x] Direct email — contact@risingcompute.in
[x] Physical address + map — Surat HQ + STIIC/IIST
[x] Office hours — Mon–Fri, 09:30–18:30 IST
Phone number (not at launch; emails go to founder inbox)
Calendly / booking link (post-launch — added once a sales rhythm exists)
Live chat widget (not at launch)

9.8 Other pages

Technology page: Architecture overview, benchmarks summary, links to downloadable whitepapers (gated).
Careers page: Mission, values, what it's like to work here, currently open roles (markdown-driven so non-engineers can edit), generic "no role but interested?" form.
Press page: Logos / awards / media mentions strip; downloadable press kit (logo pack + boilerplate).
404: Branded with a one-liner ("Lost in orbit. Let's get you back.") and links to top sections.
Thank-you pages: Per form (contact, newsletter, datasheet) with next-step suggestions.

10. Features & Functionality

Lead capture & forms

[x] Contact / "Request evaluation" form
[x] Datasheet download (gated — email required)
[x] Newsletter signup
[x] Careers application form (with file upload for CV)
Demo request form (folded into contact form)
Multi-step / progressive forms (simple single-step at launch)

Content & engagement

[x] Blog with categories & tags
[x] Search (across blog + technology pages)
[x] Filtering on blog by category
[x] Social share buttons (X, LinkedIn, copy link)
[x] RSS feed
Comments (not at launch)

Booking & scheduling

Calendly / Cal.com embed (post-launch)
Custom booking flow (out of scope)
Event RSVPs (out of scope)

Commerce / payments — entirely out of scope

Authentication / portal

Client login area (post-launch — when first paying customer onboards)
Document sharing portal (post-launch)

Interactivity

[x] Subtle animations / scroll effects
[x] Animated SVG datapath in hero
Video backgrounds (too heavy at launch)
Live chat / chatbot (not at launch)

Localization

[x] English only at launch; codebase prepared for future Hindi + Japanese.

Other

[x] Dark theme default with light-theme toggle
[x] Code-block syntax highlighting for technical blog posts
[x] OG image generation per post

11. Design Direction

11.1 Mood

Top 3: Technical · Bold · Futuristic (with a strong supporting layer of Calm and Spacious).

11.2 Layout preferences

Density: [x] Balanced — spacious hero and product pages; denser technology and blog pages where engineers expect signal.
Width: [x] Contained (max ~1280px) with full-bleed feature bands.
Page rhythm: [x] One idea per scroll-section on marketing pages; magazine-style for blog index.

11.3 Motion & interactivity

[x] Subtle (fade-ins, hover states) + one moderate scroll-triggered hero animation. No parallax, no auto-play video, no WebGL at launch — performance and accessibility come first.

11.4 Devices to prioritize

[x] Equal weight mobile and desktop. Desktop is primary for B2B procurement reading; mobile must still render the home / product hero cleanly because LinkedIn traffic lands there.
Browser support: Modern evergreen — latest 2 versions of Chrome, Safari, Firefox, Edge. No IE.

12. Tech Stack

12.1 Frontend framework

[x] Next.js 15 (App Router, React 19) — the recommended choice; gives us per-route SSG/ISR, an excellent SEO story, image optimisation, and easy integration with MDX for the blog and datasheets.

12.2 Styling

[x] Tailwind CSS with a small set of CSS variables for the colour palette so a light theme is a single token swap. Component primitives via class-variance-authority and clsx.

12.3 CMS / Content management

[x] Markdown / MDX in the repo — fastest at this team size; product pages, blog, careers all editable in the repo. We will graduate to Sanity when the non-technical team is large enough to need an editor UI (revisit in 6 months).

12.4 Hosting & deployment

[x] Vercel — Next.js native, preview URLs per pull request, edge caching, free tier sufficient at launch.

12.5 Domain & DNS

Existing domain: risingcompute.in
Registrar: GoDaddy (to be confirmed)
DNS provider: [x] Cloudflare — moved from registrar to Cloudflare for free DNS, CDN, DDoS, and analytics.
Email hosting: Google Workspace — contact@risingcompute.in + individual founder addresses.

12.6 Forms backend

[x] Next.js API route + Resend for transactional email; submissions also posted to a Slack webhook for instant team visibility. Submissions stored in a Postgres table on Neon (free tier).
Spam protection via [x] Cloudflare Turnstile (privacy-friendlier than reCAPTCHA).

12.7 Repository & CI

Code host: [x] GitHub (organisation: risingcompute)
CI/CD: [x] Vercel built-in for the site; GitHub Actions for type-check, lint, and Lighthouse CI on every PR.
Branching: main is production; PR previews on every branch.

13. Integrations

Analytics & attribution

[x] Plausible — privacy-friendly, GDPR-ready out of the box, no cookie banner needed for analytics.
[x] Microsoft Clarity — free heatmaps & session recordings (with a clear privacy notice).
Google Analytics 4 (skipped — privacy posture and cookie banner overhead)

Marketing & CRM

[x] Beehiiv — newsletter (clean editor, generous free tier, good analytics).
HubSpot / Salesforce / Pipedrive (deferred — form submissions go to a Notion CRM until volume justifies a real tool)

Communication

[x] Slack notifications on form submits via webhook.
Live chat / Intercom (not at launch)

Booking & payments

Calendly / Cal.com (post-launch)
Stripe / PayPal (out of scope — quote-based sales)