"""Seed the database with the launch content (products, founders, blog).""" from django.db import migrations from django.utils import timezone PRODUCTS = [ { "slug": "ai-inference-ip", "name": "AI Inference IP Core", "category": "ai", "tagline": "Parallel inference at the edge — deterministic, quantised, portable.", "summary": ( "A parallel-compute IP core for running quantised neural networks on FPGA " "or ASIC. Built for vision, sensor fusion, and on-orbit inference." ), "description": ( "Our AI Inference IP Core is designed for workloads where GPUs are too " "power-hungry and general-purpose NPUs are too opaque. It runs INT8 / INT4 " "quantised networks with deterministic latency, ports cleanly from FPGA " "prototype to ASIC tape-out, and is verifiable end-to-end." ), "benefits": [ "Higher throughput-per-watt than CPU / GPU at the edge", "Deterministic latency for real-time control loops", "INT8 / INT4 quantisation-aware datapath", "Synthesises on standard FPGA tooling", "Same RTL portable from FPGA to ASIC", ], "features": [ "Parameterised RTL", "Reference compiler for an ONNX subset", "FPGA reference design", "Integration guide & testbench", ], "spec_table": [ {"label": "Interface", "value": "AXI4 / AXI-Stream"}, {"label": "Precision", "value": "INT8 / INT4"}, {"label": "Targets", "value": "Xilinx UltraScale+, Intel Agilex, 28nm ASIC"}, {"label": "Verification", "value": "UVM testbench included"}, ], "primary_cta_label": "Request evaluation", "sort_order": 1, }, { "slug": "cybersecurity-ip", "name": "Cybersecurity IP Core", "category": "security", "tagline": "Hardware-accelerated cryptography — side-channel hardened.", "summary": ( "A drop-in hardware accelerator for symmetric and asymmetric cryptography " "and secure boot — built for defense electronics and secure-element SoCs." ), "description": ( "Hardware acceleration for AES, SHA, ECC and RSA primitives, plus a secure " "boot block. Designed constant-time and side-channel hardened from the " "first line of RTL — security is not a wrapper, it's the architecture." ), "benefits": [ "Constant-time implementation", "Side-channel hardened", "FIPS-aligned algorithm set", "Low gate count for embedded targets", ], "features": [ "AES-128 / 256, SHA-2 / 3", "ECC (P-256, P-384), RSA-2048 / 4096", "True random number generator interface", "AXI / AHB wrappers", "Security white paper", ], "spec_table": [ {"label": "Interface", "value": "AXI4-Lite / AHB-Lite"}, {"label": "Algorithms", "value": "AES, SHA-2/3, ECC, RSA"}, {"label": "Targets", "value": "FPGA + 28/40nm ASIC"}, {"label": "Compliance", "value": "FIPS-aligned"}, ], "primary_cta_label": "Request evaluation", "sort_order": 2, }, { "slug": "communication-ip", "name": "Communication Protocol IP", "category": "comms", "tagline": "Space- and avionics-grade communication blocks. Flight-proven.", "summary": ( "SpaceWire, CAN, UART/SPI/I2C and custom satellite payload buses — " "low gate-count, well-documented, and flight-proven on operational missions." ), "description": ( "Our communication IP catalogue is the most battle-tested part of our " "stack — variants of these cores have flown on operational satellite " "missions. We licence the same blocks to ground systems, payload " "integrators, and avionics OEMs." ), "benefits": [ "Space-qualified design practice", "Low gate-count for power-constrained targets", "Flight-heritage documentation", "Comprehensive verification IP", ], "features": [ "SpaceWire / SpaceFibre", "CAN-FD", "UART / SPI / I2C masters & slaves", "Custom satellite payload buses", "Reference designs + integration guide", ], "spec_table": [ {"label": "Protocols", "value": "SpaceWire, CAN-FD, UART, SPI, I2C"}, {"label": "Heritage", "value": "Flown on operational satellite missions"}, {"label": "Verification", "value": "Protocol-compliant testbenches"}, ], "primary_cta_label": "Request evaluation", "sort_order": 3, }, ] FOUNDERS = [ { "name": "Ali Murabbi", "role": "Co-founder · VLSI & Robotics Engineer", "domain": "RTL / FPGA design · robotics control hardware · motion and sensor-fusion blocks", "bio": ( "Hardware designer specialising in RTL and FPGA for robotics and motion " "systems. At SSPACE, IIST, contributed to onboard compute blocks for " "satellite payloads and now leads RisingCompute's communication-protocol " "and robotics IP work." ), "sort_order": 1, }, { "name": "Bhavy Savani", "role": "Co-founder · VLSI & AI Engineer", "domain": "RTL / FPGA design · quantised neural-network accelerators · verification", "bio": ( "VLSI engineer focused on AI accelerator architectures and verification. " "At SSPACE, IIST, designed and verified compute IP that has flown in " "space; at RisingCompute, leads the AI Inference IP Core and the " "Cybersecurity IP Core." ), "sort_order": 2, }, { "name": "Abhishek Verma", "role": "Co-founder · System Engineer & Project Manager", "domain": "System architecture · integration · project delivery · GTM", "bio": ( "Systems engineer and programme lead. Brings the IP, the engineering " "team, and the customer programme together — sets architecture, owns " "project delivery, and runs partner and customer conversations." ), "sort_order": 3, }, ] BLOG_POSTS = [ { "slug": "why-we-started-risingcompute", "title": "Why we started RisingCompute", "excerpt": ( "Two years inside a satellite-software lab taught us something simple: " "the difference between what a research team can do with AI and what most " "engineers can do comes down to compute. We started RisingCompute to close " "that gap." ), "category": "company", "author_name": "Abhishek Verma", "read_time_minutes": 4, "body": ( "## A note from the founders\n\n" "RisingCompute was born inside the SSPACE lab at IIST. We spent two " "years building computation systems for satellites — IP that has since " "flown in space. What we kept noticing was the gap between what a " "research team can do with the right hardware and what a typical " "product team can do with whatever GPU they could afford.\n\n" "Our bet is that closing that gap is a hardware problem, not a " "software one. Parallel architectures, well-designed IP cores, and a " "vendor that ships datasheets you can actually read." ), }, { "slug": "what-flight-heritage-means-for-ip", "title": "What flight heritage actually means for IP cores", "excerpt": ( "\"Flight-heritage\" is one of the most over-claimed phrases in the IP " "industry. Here's what it means to us, what it doesn't, and what to " "ask the next vendor that uses the term." ), "category": "space", "author_name": "Ali Murabbi", "read_time_minutes": 6, "body": ( "## What counts, and what doesn't\n\n" "Flight heritage is not just \"this RTL was synthesised onto a flight " "FPGA once.\" Real heritage is end-to-end: a documented chain from RTL " "to verification artifacts to a specific board, on a specific mission, " "with a specific telemetry track." ), }, { "slug": "int8-inference-without-accuracy-loss", "title": "Designing AI inference cores for INT8 without accuracy loss", "excerpt": ( "Quantisation is a free lunch — until it isn't. A practical walk " "through the datapath choices that decide whether INT8 inference is " "production-ready or just a benchmark trick." ), "category": "ai", "author_name": "Bhavy Savani", "read_time_minutes": 8, "body": ( "## The two failure modes\n\n" "Most INT8 implementations fail in one of two ways: accuracy collapse " "from poor calibration, or throughput collapse from naive datapath " "layout. We walk through how we designed around both." ), }, { "slug": "indian-sovereign-ip-stack", "title": "An Indian sovereign IP stack — and why it matters now", "excerpt": ( "\"Make in India\" content rules are reshaping defense and space " "procurement. A founder note on what an Indian-origin IP stack should " "look like — and what it shouldn't." ), "category": "company", "author_name": "Abhishek Verma", "read_time_minutes": 5, "body": ( "## Sovereign doesn't mean isolated\n\n" "Sovereign IP should mean Indian-origin design, Indian-origin " "verification, and an Indian-origin support chain. It does not mean " "rejecting global tooling or global customers." ), }, ] def seed(apps, schema_editor): Product = apps.get_model("api", "Product") Founder = apps.get_model("api", "Founder") BlogPost = apps.get_model("api", "BlogPost") for row in PRODUCTS: Product.objects.update_or_create(slug=row["slug"], defaults=row) for row in FOUNDERS: Founder.objects.update_or_create(name=row["name"], defaults=row) for row in BLOG_POSTS: BlogPost.objects.update_or_create( slug=row["slug"], defaults={**row, "published_at": timezone.now()}, ) def unseed(apps, schema_editor): Product = apps.get_model("api", "Product") Founder = apps.get_model("api", "Founder") BlogPost = apps.get_model("api", "BlogPost") Product.objects.filter(slug__in=[r["slug"] for r in PRODUCTS]).delete() Founder.objects.filter(name__in=[r["name"] for r in FOUNDERS]).delete() BlogPost.objects.filter(slug__in=[r["slug"] for r in BLOG_POSTS]).delete() class Migration(migrations.Migration): dependencies = [("api", "0001_initial")] operations = [migrations.RunPython(seed, unseed)]