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abhishek
2026-05-26 11:53:33 +00:00
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frontend/dist/assets/TechnologyView-Cqvgd6K3.js vendored Executable file
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import{_ as d,f as i,i as n,b as a,F as l,l as p,g as v,q as h,u as y,R as u,j as o,t as s,h as _}from"./index-igTJW-fG.js";import{S as m}from"./SectionHero-CZI787yI.js";const b={class:"section"},g={class:"container"},f={class:"grid grid--2 pillars"},w={class:"pillar__num mono"},S={class:"muted"},I={class:"section text-center"},A={class:"container"},T={__name:"TechnologyView",setup(k){const r=[{title:"Parallel by design",body:"Datapaths are parallel from the first line of RTL. The architecture is not a serial CPU that we widened — it is parallel-native."},{title:"Verification-first",body:"Every block ships with UVM testbenches, a coverage plan, and traceable test vectors. Heritage you can audit, not heritage you have to take on faith."},{title:"FPGA → ASIC portability",body:"The same RTL synthesises on Xilinx UltraScale+, Intel Agilex, and standard 28nm / 40nm ASIC libraries. Prototype fast, ship slow, but with the same code."},{title:"Security as architecture",body:"Constant-time datapaths, side-channel-aware routing, and a security white paper per release — not a checklist bolted on at integration time."}];return(C,e)=>(o(),i(l,null,[n(m,{eyebrow:"Technology",title:"An architecture built for AI, space, and robotics — in that order.",subtitle:"A short tour of the design principles that show up in every block we ship. If you want the spec-sheet version, request a datasheet."}),a("section",b,[a("div",g,[a("div",f,[(o(),i(l,null,p(r,(t,c)=>a("article",{key:t.title,class:"pillar"},[a("span",w,s(String(c+1).padStart(2,"0")),1),a("h3",null,s(t.title),1),a("p",S,s(t.body),1)])),64))])])]),e[3]||(e[3]=v('<section class="section diagram-section" data-v-11122e52><div class="container" data-v-11122e52><div class="section-head" data-v-11122e52><span class="eyebrow" data-v-11122e52>System view</span><h2 data-v-11122e52>The stack, at a glance.</h2><p class="muted" data-v-11122e52>Three product blocks. One shared verification toolchain. Same RTL from FPGA to ASIC.</p></div><div class="stack-diagram" data-v-11122e52><div class="layer layer--top" data-v-11122e52><span class="layer__title" data-v-11122e52>Customer SoC / FPGA</span><span class="layer__sub mono" data-v-11122e52>Your design</span></div><div class="layer__pipe" data-v-11122e52></div><div class="layer-row" data-v-11122e52><div class="layer layer--block" data-v-11122e52><span class="layer__title" data-v-11122e52>AI Inference IP</span><span class="layer__sub mono" data-v-11122e52>INT8 / INT4</span></div><div class="layer layer--block" data-v-11122e52><span class="layer__title" data-v-11122e52>Cybersecurity IP</span><span class="layer__sub mono" data-v-11122e52>AES · SHA · ECC</span></div><div class="layer layer--block" data-v-11122e52><span class="layer__title" data-v-11122e52>Communication IP</span><span class="layer__sub mono" data-v-11122e52>SpaceWire · CAN · UART</span></div></div><div class="layer__pipe" data-v-11122e52></div><div class="layer layer--base" data-v-11122e52><span class="layer__title" data-v-11122e52>Verification &amp; Integration Toolchain</span><span class="layer__sub mono" data-v-11122e52>UVM · Reference designs · Integration guides</span></div></div></div></section>',1)),a("section",I,[a("div",A,[e[1]||(e[1]=a("h2",null,"Want the long version?",-1)),e[2]||(e[2]=a("p",{class:"muted"},"Request a technical brief or schedule a 30-minute architect call.",-1)),n(y(u),{to:"/contact",class:"btn btn--primary"},{default:h(()=>[...e[0]||(e[0]=[_("Request the brief",-1)])]),_:1})])])],64))}},R=d(T,[["__scopeId","data-v-11122e52"]]);export{R as default};