48 lines
795 B
VHDL
48 lines
795 B
VHDL
--
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-- Synopsys
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-- Vhdl wrapper for top level design, written on Wed Apr 15 22:00:10 2026
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--
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.genpackage.all;
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entity wrapper_for_top is
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port (
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EQ : out std_logic;
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A : in std_logic_vector(14 downto 0);
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B : in std_logic_vector(14 downto 0)
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);
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end wrapper_for_top;
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architecture gen of wrapper_for_top is
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component top
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port (
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EQ : out std_logic;
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A : in std_logic_vector (14 downto 0);
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B : in std_logic_vector (14 downto 0)
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);
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end component;
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signal tmp_EQ : std_logic;
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signal tmp_A : std_logic_vector (14 downto 0);
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signal tmp_B : std_logic_vector (14 downto 0);
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begin
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EQ <= tmp_EQ;
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tmp_A <= A;
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tmp_B <= B;
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u1: top port map (
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EQ => tmp_EQ,
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A => tmp_A,
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B => tmp_B
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);
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end gen;
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