367 lines
49 KiB
Plaintext
367 lines
49 KiB
Plaintext
# Wed Apr 15 22:47:54 2026
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Copyright (C) 1994-2023 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: V-2023.09M-5
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Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
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OS: Windows 10 or later
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Hostname: SOFTWARE-PC
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Implementation : synthesis
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Synopsys Microchip Technology Pre-mapping, Version map202309act, Build 395R, Built Apr 29 2025 06:36:49, @
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)
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Done reading skeleton netlist (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 210MB peak: 210MB)
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Reading constraint file: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc
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@L: E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt
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See clock summary report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_scck.rpt"
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@N: MF916 |Option synthesis_strategy=base is enabled.
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@N: MF248 |Running in 64-bit mode.
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@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 261MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 261MB peak: 262MB)
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Start loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 265MB peak: 265MB)
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Finished loading timing files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 266MB peak: 267MB)
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Vector Gate Optimization Enabled: Optimizing Partial Hanging Logic.
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NConnInternalConnection caching is on
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@W: FX1183 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\core_reset_pf\core_reset_pf_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_addr_req[0][31:0] is being ignored due to limitations in architecture.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[2].buff_entry_addr_req[2][31:0] is being ignored due to limitations in architecture.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[1].buff_entry_addr_req[1][31:0] is being ignored due to limitations in architecture.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11493:2:11493:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_result_reg_int[64:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11473:2:11473:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.quotient[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_fflags_flags.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[1].buff_data[1][5:0] is being ignored due to limitations in architecture.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data[0][5:0] is being ignored due to limitations in architecture.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[1].buff_data[1][10:0] is being ignored due to limitations in architecture.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data[0][10:0] is being ignored due to limitations in architecture.
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@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture.
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@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture.
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Starting HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 338MB)
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Finished HSTDM IP insertion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 338MB peak: 339MB)
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":169:8:169:52|Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":176:8:176:52|Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":183:8:183:52|Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":190:8:190:52|Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":32:8:32:11|Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
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@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":31:8:31:13|Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
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Started DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 339MB)
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Finished DisTri Cleanup (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 338MB peak: 340MB)
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7016:2:7016:23|Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2565:4:2565:35|Removing instance u_csr_gpr_state_reg_fflags_flags (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4653:2:4653:23|Removing instance u_subsys_parity_en_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4904:4:4904:42|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4923:4:4923:44|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
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|
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_lanectrl_0\pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v":107:12:107:32|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_ccc_c0\pf_lanectrl_core_reader_0\pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v":93:46:93:66|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance fifo_write (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance clear_parity_en (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[4:0] (in view: work.miv_rv32_csr_gpr_state_reg_5s_1s_0s(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
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@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2594:4:2594:30|Removing instance u_csr_gpr_state_reg_frm_frm (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10461:2:10461:7|Removing sequential instance sel_reg[1:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|Removing sequential instance genblk8\.afull_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6376:4:6376:9|Removing sequential instance q2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[2:0] (in view: work.miv_rv32_csr_gpr_state_reg_3s_1s_0s_1(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6361:2:6361:7|Removing sequential instance paddr_p (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_valid_reg (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[0\]\.buff_data\[0\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[1\]\.buff_data\[1\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Removing sequential instance mem_xf_2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_sel_reg[5:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":438:3:438:8|Removing sequential instance genblk6\.almostemptyi (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16308:7:16308:15|Removing sequential instance genblk3\.shift_active_high\.shift_active_low\.dr_tdo (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":630:0:630:5|Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
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@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
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|
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9245:6:9245:11|Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
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@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top
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Finished netlist restructuring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 348MB peak: 348MB)
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Some data will not be shown as it is part of encrypted module
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Clock Summary
|
|
******************
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Start Requested Requested Clock Clock Clock
|
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Level Clock Frequency Period Type Group Load
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--------------------------------------------------------------------------------------------------------------------------------------------------------------------
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0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1
|
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1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 5011
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2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0
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0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT0_GRP 3
|
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2 .. PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 8.000 generated (from REFCLK_P) Y_DIV_GRP 1410
|
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT1_GRP 1
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT2_GRP 1
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1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT3_GRP 1
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0 - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 8.000 declared SGMII_CDR_0_0_CLK_OUT_GRP 1323
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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0 - TCK 10.0 MHz 100.000 declared JTAG_Async_2 0
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0 - COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0_3 184
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0 - PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 100.0 MHz 10.000 inferred Inferred_clkgroup_0_1 2
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====================================================================================================================================================================
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Clock Load Summary
|
|
***********************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
|
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Clock Load Pin Seq Example Seq Example Comb Example
|
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
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REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - -
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PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 5011 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) PF_TPSRAM_C0_0.PF_TPSRAM_C0_0.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1.B_CLK - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG)
|
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PHY_MDC_CLOCK 0 - - - -
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REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF)
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 3 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT0(PLL) PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.A - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_3.A(HS_IO_CLK)
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PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 1410 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.Y_DIV(ICB_CLKDIV) PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1:0].C - -
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT1(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_7.A(HS_IO_CLK)
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT2(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.REF_CLK(DLL)
|
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PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT3(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_15.A(HS_IO_CLK)
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PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 1323 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R(LANECTRL) SSDetect_0.rx_start[1:0].C - PF_IOD_CDR_C0_0.RCLKINT_0.A(RCLKINT)
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System 0 - - - -
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TCK 0 TCK(port) - - -
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COREJTAGDEBUG_Z5|iUDRCK_inferred_clock 184 COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst.UDRCK(UJTAG) MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.genblk1\.rst_synch_reg[1:0].C - MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.un1_jtag_tck.I[0](inv)
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PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop 2 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK(LANECTRL) PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.CDR_CLK - -
|
|
===========================================================================================================================================================================================================================================================================================================================================================================================================================
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@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_iod_cdr_rx_n_0\pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v":48:53:48:59|Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance.
|
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@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug_uj_jtag.v":215:0:215:5|Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock which controls 184 sequential elements including COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance.
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@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
|
Finished Pre Mapping Phase.
|
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@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
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Starting constraint checker (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 333MB peak: 349MB)
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Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog))
|
|
original code -> new code
|
|
0000 -> 000001
|
|
0001 -> 000010
|
|
0010 -> 000100
|
|
0111 -> 001000
|
|
1000 -> 010000
|
|
1001 -> 100000
|
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Encoding state machine genblk1\.O0Il1[4:0] (in view: work.CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog))
|
|
original code -> new code
|
|
0000 -> 00001
|
|
1000 -> 00010
|
|
1100 -> 00100
|
|
1110 -> 01000
|
|
1111 -> 10000
|
|
Encoding state machine l0i11[31:0] (in view: work.CTSE_PEMGT_1s_26s(verilog))
|
|
original code -> new code
|
|
00000 -> 00000000000000000000000000000001
|
|
00001 -> 00000000000000000000000000000010
|
|
00010 -> 00000000000000000000000000000100
|
|
00011 -> 00000000000000000000000000001000
|
|
00100 -> 00000000000000000000000000010000
|
|
00101 -> 00000000000000000000000000100000
|
|
00110 -> 00000000000000000000000001000000
|
|
00111 -> 00000000000000000000000010000000
|
|
01000 -> 00000000000000000000000100000000
|
|
01001 -> 00000000000000000000001000000000
|
|
01010 -> 00000000000000000000010000000000
|
|
01011 -> 00000000000000000000100000000000
|
|
01100 -> 00000000000000000001000000000000
|
|
01101 -> 00000000000000000010000000000000
|
|
01110 -> 00000000000000000100000000000000
|
|
01111 -> 00000000000000001000000000000000
|
|
10000 -> 00000000000000010000000000000000
|
|
10001 -> 00000000000000100000000000000000
|
|
10010 -> 00000000000001000000000000000000
|
|
10011 -> 00000000000010000000000000000000
|
|
10100 -> 00000000000100000000000000000000
|
|
10101 -> 00000000001000000000000000000000
|
|
10110 -> 00000000010000000000000000000000
|
|
10111 -> 00000000100000000000000000000000
|
|
11000 -> 00000001000000000000000000000000
|
|
11001 -> 00000010000000000000000000000000
|
|
11010 -> 00000100000000000000000000000000
|
|
11011 -> 00001000000000000000000000000000
|
|
11100 -> 00010000000000000000000000000000
|
|
11101 -> 00100000000000000000000000000000
|
|
11110 -> 01000000000000000000000000000000
|
|
11111 -> 10000000000000000000000000000000
|
|
Encoding state machine lI101_1[3:0] (in view: work.CTSE_PEREX_PCS_0s_26s_1s(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
Encoding state machine xmit_state[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog))
|
|
original code -> new code
|
|
00000000000000000000000000000000 -> 000001
|
|
00000000000000000000000000000001 -> 000010
|
|
00000000000000000000000000000010 -> 000100
|
|
00000000000000000000000000000011 -> 001000
|
|
00000000000000000000000000000100 -> 010000
|
|
00000000000000000000000000000101 -> 100000
|
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Encoding state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog))
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|
original code -> new code
|
|
00 -> 00
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|
01 -> 01
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|
10 -> 10
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11 -> 11
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@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
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Encoding state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog))
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|
original code -> new code
|
|
00 -> 0
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01 -> 1
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@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
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Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
|
|
original code -> new code
|
|
0000 -> 0000000000000001
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|
0001 -> 0000000000000010
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|
0010 -> 0000000000000100
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|
0011 -> 0000000000001000
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|
0100 -> 0000000000010000
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|
0101 -> 0000000000100000
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|
0110 -> 0000000001000000
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|
0111 -> 0000000010000000
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|
1000 -> 0000000100000000
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|
1001 -> 0000001000000000
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|
1010 -> 0000010000000000
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|
1011 -> 0000100000000000
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1100 -> 0001000000000000
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|
1101 -> 0010000000000000
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1110 -> 0100000000000000
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1111 -> 1000000000000000
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Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
|
|
Encoding state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
|
|
Encoding state machine debug_state[5:0] (in view: work.miv_rv32_debug_du(verilog))
|
|
original code -> new code
|
|
000001 -> 000001
|
|
000010 -> 000010
|
|
000100 -> 000100
|
|
001000 -> 001000
|
|
010000 -> 010000
|
|
100000 -> 100000
|
|
Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog))
|
|
original code -> new code
|
|
01 -> 00
|
|
10 -> 01
|
|
11 -> 10
|
|
Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog))
|
|
original code -> new code
|
|
000 -> 000001
|
|
001 -> 000010
|
|
010 -> 000100
|
|
011 -> 001000
|
|
100 -> 010000
|
|
101 -> 100000
|
|
Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog))
|
|
original code -> new code
|
|
001 -> 0000001
|
|
010 -> 0000010
|
|
011 -> 0000100
|
|
100 -> 0001000
|
|
101 -> 0010000
|
|
110 -> 0100000
|
|
111 -> 1000000
|
|
Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_subsys_tcm_Z20(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
|
|
Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog))
|
|
original code -> new code
|
|
00 -> 00
|
|
01 -> 01
|
|
10 -> 10
|
|
11 -> 11
|
|
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
|
|
|
|
Finished constraint checker preprocessing (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 341MB peak: 349MB)
|
|
|
|
@W: MF511 |Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .
|
|
|
|
Finished constraint checker (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 351MB peak: 365MB)
|
|
|
|
Pre-mapping successful!
|
|
|
|
At Mapper Exit (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 249MB peak: 365MB)
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|
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|
Process took 0h:00m:13s realtime, 0h:00m:13s cputime
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# Wed Apr 15 22:48:08 2026
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###########################################################]
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