654 lines
25 KiB
Verilog
654 lines
25 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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// Created by SmartDesign Wed Apr 15 22:44:24 2026
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// Version: 2025.1 2025.1.0.14
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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// top
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module top(
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// Inputs
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REFCLK_N,
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REFCLK_P,
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REF_CLK_0,
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RESET_N,
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RX,
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RX_N,
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RX_P,
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SPISDI,
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TCK,
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TDI,
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TMS,
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TRSTB,
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// Outputs
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LINK_OK,
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PHY_MDC,
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PHY_RST,
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RD_BC_ERROR,
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REF_CLK_SEL,
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R_DATA,
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SPISCLKO,
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SPISDO,
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SPISS,
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TDO,
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TX,
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TX_N,
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TX_P,
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coma_mode,
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// Inouts
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PHY_MDIO
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);
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//--------------------------------------------------------------------
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// Input
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//--------------------------------------------------------------------
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input REFCLK_N;
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input REFCLK_P;
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input REF_CLK_0;
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input RESET_N;
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input RX;
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input RX_N;
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input RX_P;
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input SPISDI;
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input TCK;
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input TDI;
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input TMS;
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input TRSTB;
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//--------------------------------------------------------------------
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// Output
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//--------------------------------------------------------------------
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output LINK_OK;
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output PHY_MDC;
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output PHY_RST;
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output RD_BC_ERROR;
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output REF_CLK_SEL;
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output [31:0] R_DATA;
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output SPISCLKO;
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output SPISDO;
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output SPISS;
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output TDO;
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output TX;
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output TX_N;
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output TX_P;
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output coma_mode;
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//--------------------------------------------------------------------
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// Inout
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//--------------------------------------------------------------------
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inout PHY_MDIO;
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//--------------------------------------------------------------------
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// Nets
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//--------------------------------------------------------------------
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wire AND2_2_Y;
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wire BIBUF_0_Y;
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wire Core_reset_pf_0_PLL_POWERDOWN_B;
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wire CoreAPB3_0_0_APBmslave0_PENABLE;
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wire [31:0] CoreAPB3_0_0_APBmslave0_PRDATA;
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wire CoreAPB3_0_0_APBmslave0_PREADY;
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wire CoreAPB3_0_0_APBmslave0_PSELx;
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wire CoreAPB3_0_0_APBmslave0_PSLVERR;
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wire CoreAPB3_0_0_APBmslave0_PWRITE;
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wire CoreAPB3_0_0_APBmslave1_PREADY;
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wire CoreAPB3_0_0_APBmslave1_PSELx;
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wire CoreAPB3_0_0_APBmslave1_PSLVERR;
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wire [31:0] CoreAPB3_0_0_APBmslave2_PRDATA;
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wire CoreAPB3_0_0_APBmslave2_PREADY;
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wire CoreAPB3_0_0_APBmslave2_PSELx;
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wire CoreAPB3_0_0_APBmslave2_PSLVERR;
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wire COREFIFO_C0_0_EMPTY;
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wire [31:0] COREFIFO_C0_0_Q;
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wire COREJTAGDEBUG_C0_0_TGT_TCK_0;
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wire COREJTAGDEBUG_C0_0_TGT_TDI_0;
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wire COREJTAGDEBUG_C0_0_TGT_TMS_0;
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wire COREJTAGDEBUG_C0_0_TGT_TRSTN_0;
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wire CORETSE_0_MDO;
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wire CORETSE_0_MDOEN;
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wire [1:0] CORETSE_0_MRXBYTEVALID;
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wire [31:0] CORETSE_0_MRXDAT;
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wire CORETSE_0_MRXEOF;
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wire CORETSE_0_MRXRDY;
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wire CORETSE_0_MRXSOF;
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wire CORETSE_0_MTXACPT;
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wire [9:0] CORETSE_0_TCG;
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wire fifo_to_tpsram_bridge_0_fifo_rd_en;
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wire [9:0] fifo_to_tpsram_bridge_0_ram_w_addr_1;
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wire [31:0] fifo_to_tpsram_bridge_0_ram_w_data;
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wire fifo_to_tpsram_bridge_0_ram_w_en;
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wire INBUF_DIFF_0_Y;
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wire [8:8] LINK_OK_net_0;
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wire [31:0] MIV_RV32_C0_0_APB_INITIATOR_PADDR;
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wire MIV_RV32_C0_0_APB_INITIATOR_PENABLE;
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wire [31:0] MIV_RV32_C0_0_APB_INITIATOR_PRDATA;
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wire MIV_RV32_C0_0_APB_INITIATOR_PREADY;
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wire MIV_RV32_C0_0_APB_INITIATOR_PSELx;
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wire MIV_RV32_C0_0_APB_INITIATOR_PSLVERR;
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wire [31:0] MIV_RV32_C0_0_APB_INITIATOR_PWDATA;
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wire MIV_RV32_C0_0_APB_INITIATOR_PWRITE;
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wire MIV_RV32_C0_0_JTAG_TDO;
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wire PF_CCC_0_0_OUT0_FABCLK_0;
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wire PF_CCC_0_0_PLL_LOCK_0;
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wire pf_init_monitor_0_0_BANK_6_VDDI_STATUS;
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wire pf_init_monitor_0_0_DEVICE_INIT_DONE;
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wire pf_init_monitor_0_0_FABRIC_POR_N;
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wire PF_IOD_CDR_C0_0_RX_CLK_R;
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wire [9:0] PF_IOD_CDR_C0_0_RX_DATA;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_CDR_START;
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wire [6:0] PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_LOCK;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_VALID_CODE;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_180;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_270;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_90;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_PAUSE;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_PLL_LOCK;
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wire PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_TX_CLK_G;
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wire PF_IOD_CDR_CCC_C0_0_TX_CLK_G;
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wire PHY_MDC_net_0;
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wire PHY_MDIO;
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wire PHY_RST_net_0;
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wire [31:0] R_DATA_net_0;
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wire RD_BC_ERROR_net_0;
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wire REF_CLK_0;
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wire REFCLK_N;
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wire REFCLK_P;
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wire RESET_N;
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wire RX;
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wire RX_N;
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wire RX_P;
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wire SPISCLKO_net_0;
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wire SPISDI;
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wire SPISDO_net_0;
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wire [0:0] SPISS_net_0;
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wire SSDetect_0_stream_start;
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wire TCK;
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wire TDI;
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wire TDO_net_0;
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wire TMS;
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wire TRSTB;
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wire TX_net_0;
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wire TX_N_net_0;
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wire TX_P_net_0;
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wire LINK_OK_net_1;
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wire PHY_MDC_net_1;
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wire PHY_RST_net_1;
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wire RD_BC_ERROR_net_1;
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wire RESET_N_net_0;
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wire SPISCLKO_net_1;
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wire SPISDO_net_1;
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wire SPISS_net_1;
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wire TDO_net_1;
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wire TX_N_net_1;
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wire TX_P_net_1;
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wire TX_net_1;
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wire [31:0] R_DATA_net_1;
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wire [1:1] SPISS_slice_0;
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wire [2:2] SPISS_slice_1;
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wire [3:3] SPISS_slice_2;
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wire [4:4] SPISS_slice_3;
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wire [5:5] SPISS_slice_4;
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wire [6:6] SPISS_slice_5;
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wire [7:7] SPISS_slice_6;
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wire [0:0] ANX_STATE_slice_0;
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wire [1:1] ANX_STATE_slice_1;
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wire [2:2] ANX_STATE_slice_2;
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wire [3:3] ANX_STATE_slice_3;
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wire [4:4] ANX_STATE_slice_4;
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wire [5:5] ANX_STATE_slice_5;
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wire [6:6] ANX_STATE_slice_6;
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wire [7:7] ANX_STATE_slice_7;
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wire [9:9] ANX_STATE_slice_8;
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wire [7:0] SPISS_net_2;
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wire [9:0] ANX_STATE_net_0;
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//--------------------------------------------------------------------
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// TiedOff Nets
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//--------------------------------------------------------------------
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wire GND_net;
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wire VCC_net;
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wire [9:0] R_ADDR_const_net_0;
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//--------------------------------------------------------------------
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// Inverted Nets
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//--------------------------------------------------------------------
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wire RESET_N_net_1;
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wire coma_mode_OUT_PRE_INV0_0;
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//--------------------------------------------------------------------
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// Bus Interface Nets Declarations - Unequal Pin Widths
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//--------------------------------------------------------------------
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wire [31:0] CoreAPB3_0_0_APBmslave0_PADDR;
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wire [4:0] CoreAPB3_0_0_APBmslave0_PADDR_0;
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wire [4:0] CoreAPB3_0_0_APBmslave0_PADDR_0_4to0;
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wire [6:0] CoreAPB3_0_0_APBmslave0_PADDR_1;
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wire [6:0] CoreAPB3_0_0_APBmslave0_PADDR_1_6to0;
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wire [31:0] CoreAPB3_0_0_APBmslave0_PWDATA;
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wire [7:0] CoreAPB3_0_0_APBmslave0_PWDATA_0;
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wire [7:0] CoreAPB3_0_0_APBmslave0_PWDATA_0_7to0;
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wire [7:0] CoreAPB3_0_0_APBmslave1_PRDATA;
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wire [31:0] CoreAPB3_0_0_APBmslave1_PRDATA_0;
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wire [31:8] CoreAPB3_0_0_APBmslave1_PRDATA_0_31to8;
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wire [7:0] CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0;
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//--------------------------------------------------------------------
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// Constant assignments
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//--------------------------------------------------------------------
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assign GND_net = 1'b0;
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assign VCC_net = 1'b1;
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assign R_ADDR_const_net_0 = 10'h000;
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//--------------------------------------------------------------------
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// Inversions
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//--------------------------------------------------------------------
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assign RESET_N_net_1 = ~ coma_mode_OUT_PRE_INV0_0;
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//--------------------------------------------------------------------
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// Top level output port assignments
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//--------------------------------------------------------------------
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assign LINK_OK_net_1 = LINK_OK_net_0[8];
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assign LINK_OK = LINK_OK_net_1;
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assign PHY_MDC_net_1 = PHY_MDC_net_0;
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assign PHY_MDC = PHY_MDC_net_1;
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assign PHY_RST_net_1 = PHY_RST_net_0;
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assign PHY_RST = PHY_RST_net_1;
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assign RD_BC_ERROR_net_1 = RD_BC_ERROR_net_0;
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assign RD_BC_ERROR = RD_BC_ERROR_net_1;
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assign RESET_N_net_0 = RESET_N;
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assign REF_CLK_SEL = RESET_N_net_0;
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assign SPISCLKO_net_1 = SPISCLKO_net_0;
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assign SPISCLKO = SPISCLKO_net_1;
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assign SPISDO_net_1 = SPISDO_net_0;
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assign SPISDO = SPISDO_net_1;
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assign SPISS_net_1 = SPISS_net_0[0];
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assign SPISS = SPISS_net_1;
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assign TDO_net_1 = TDO_net_0;
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assign TDO = TDO_net_1;
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assign TX_N_net_1 = TX_N_net_0;
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assign TX_N = TX_N_net_1;
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assign TX_P_net_1 = TX_P_net_0;
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assign TX_P = TX_P_net_1;
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assign TX_net_1 = TX_net_0;
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assign TX = TX_net_1;
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assign coma_mode_OUT_PRE_INV0_0 = RESET_N;
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assign coma_mode = RESET_N_net_1;
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assign R_DATA_net_1 = R_DATA_net_0;
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assign R_DATA[31:0] = R_DATA_net_1;
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//--------------------------------------------------------------------
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// Slices assignments
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//--------------------------------------------------------------------
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assign LINK_OK_net_0[8] = ANX_STATE_net_0[8:8];
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assign SPISS_net_0[0] = SPISS_net_2[0:0];
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assign SPISS_slice_0[1] = SPISS_net_2[1:1];
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assign SPISS_slice_1[2] = SPISS_net_2[2:2];
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assign SPISS_slice_2[3] = SPISS_net_2[3:3];
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assign SPISS_slice_3[4] = SPISS_net_2[4:4];
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assign SPISS_slice_4[5] = SPISS_net_2[5:5];
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assign SPISS_slice_5[6] = SPISS_net_2[6:6];
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assign SPISS_slice_6[7] = SPISS_net_2[7:7];
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assign ANX_STATE_slice_0[0] = ANX_STATE_net_0[0:0];
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assign ANX_STATE_slice_1[1] = ANX_STATE_net_0[1:1];
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assign ANX_STATE_slice_2[2] = ANX_STATE_net_0[2:2];
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assign ANX_STATE_slice_3[3] = ANX_STATE_net_0[3:3];
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assign ANX_STATE_slice_4[4] = ANX_STATE_net_0[4:4];
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assign ANX_STATE_slice_5[5] = ANX_STATE_net_0[5:5];
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assign ANX_STATE_slice_6[6] = ANX_STATE_net_0[6:6];
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assign ANX_STATE_slice_7[7] = ANX_STATE_net_0[7:7];
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assign ANX_STATE_slice_8[9] = ANX_STATE_net_0[9:9];
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//--------------------------------------------------------------------
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// Bus Interface Nets Assignments - Unequal Pin Widths
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//--------------------------------------------------------------------
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assign CoreAPB3_0_0_APBmslave0_PADDR_0 = { CoreAPB3_0_0_APBmslave0_PADDR_0_4to0 };
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assign CoreAPB3_0_0_APBmslave0_PADDR_0_4to0 = CoreAPB3_0_0_APBmslave0_PADDR[4:0];
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assign CoreAPB3_0_0_APBmslave0_PADDR_1 = { CoreAPB3_0_0_APBmslave0_PADDR_1_6to0 };
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assign CoreAPB3_0_0_APBmslave0_PADDR_1_6to0 = CoreAPB3_0_0_APBmslave0_PADDR[6:0];
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assign CoreAPB3_0_0_APBmslave0_PWDATA_0 = { CoreAPB3_0_0_APBmslave0_PWDATA_0_7to0 };
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assign CoreAPB3_0_0_APBmslave0_PWDATA_0_7to0 = CoreAPB3_0_0_APBmslave0_PWDATA[7:0];
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assign CoreAPB3_0_0_APBmslave1_PRDATA_0 = { CoreAPB3_0_0_APBmslave1_PRDATA_0_31to8, CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0 };
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assign CoreAPB3_0_0_APBmslave1_PRDATA_0_31to8 = 24'h0;
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assign CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0 = CoreAPB3_0_0_APBmslave1_PRDATA[7:0];
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//--------------------------------------------------------------------
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// Component instances
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//--------------------------------------------------------------------
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//--------AND2
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AND2 AND2_2(
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// Inputs
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.A ( PHY_RST_net_0 ),
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.B ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_PLL_LOCK ),
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// Outputs
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.Y ( AND2_2_Y )
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);
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//--------BIBUF
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BIBUF BIBUF_0(
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// Inputs
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.D ( CORETSE_0_MDO ),
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.E ( CORETSE_0_MDOEN ),
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// Outputs
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.Y ( BIBUF_0_Y ),
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// Inouts
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.PAD ( PHY_MDIO )
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);
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//--------Core_reset_pf
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Core_reset_pf Core_reset_pf_0(
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// Inputs
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.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
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.EXT_RST_N ( RESET_N ),
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.BANK_x_VDDI_STATUS ( pf_init_monitor_0_0_BANK_6_VDDI_STATUS ),
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.BANK_y_VDDI_STATUS ( pf_init_monitor_0_0_BANK_6_VDDI_STATUS ),
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.PLL_LOCK ( PF_CCC_0_0_PLL_LOCK_0 ),
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.SS_BUSY ( GND_net ),
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.INIT_DONE ( pf_init_monitor_0_0_DEVICE_INIT_DONE ),
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.FF_US_RESTORE ( GND_net ),
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.FPGA_POR_N ( pf_init_monitor_0_0_FABRIC_POR_N ),
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// Outputs
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.PLL_POWERDOWN_B ( Core_reset_pf_0_PLL_POWERDOWN_B ),
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.FABRIC_RESET_N ( PHY_RST_net_0 )
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);
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//--------CoreAPB3_0
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CoreAPB3_0 CoreAPB3_0_0(
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// Inputs
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.PSEL ( MIV_RV32_C0_0_APB_INITIATOR_PSELx ),
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.PENABLE ( MIV_RV32_C0_0_APB_INITIATOR_PENABLE ),
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.PWRITE ( MIV_RV32_C0_0_APB_INITIATOR_PWRITE ),
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.PREADYS0 ( CoreAPB3_0_0_APBmslave0_PREADY ),
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.PSLVERRS0 ( CoreAPB3_0_0_APBmslave0_PSLVERR ),
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.PREADYS1 ( CoreAPB3_0_0_APBmslave1_PREADY ),
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.PSLVERRS1 ( CoreAPB3_0_0_APBmslave1_PSLVERR ),
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.PREADYS2 ( CoreAPB3_0_0_APBmslave2_PREADY ),
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.PSLVERRS2 ( CoreAPB3_0_0_APBmslave2_PSLVERR ),
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.PADDR ( MIV_RV32_C0_0_APB_INITIATOR_PADDR ),
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.PWDATA ( MIV_RV32_C0_0_APB_INITIATOR_PWDATA ),
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.PRDATAS0 ( CoreAPB3_0_0_APBmslave0_PRDATA ),
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.PRDATAS1 ( CoreAPB3_0_0_APBmslave1_PRDATA_0 ),
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.PRDATAS2 ( CoreAPB3_0_0_APBmslave2_PRDATA ),
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// Outputs
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.PREADY ( MIV_RV32_C0_0_APB_INITIATOR_PREADY ),
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.PSLVERR ( MIV_RV32_C0_0_APB_INITIATOR_PSLVERR ),
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.PSELS0 ( CoreAPB3_0_0_APBmslave0_PSELx ),
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.PENABLES ( CoreAPB3_0_0_APBmslave0_PENABLE ),
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.PWRITES ( CoreAPB3_0_0_APBmslave0_PWRITE ),
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.PSELS1 ( CoreAPB3_0_0_APBmslave1_PSELx ),
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.PSELS2 ( CoreAPB3_0_0_APBmslave2_PSELx ),
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.PRDATA ( MIV_RV32_C0_0_APB_INITIATOR_PRDATA ),
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.PADDRS ( CoreAPB3_0_0_APBmslave0_PADDR ),
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.PWDATAS ( CoreAPB3_0_0_APBmslave0_PWDATA )
|
|
);
|
|
|
|
//--------COREFIFO_C0
|
|
COREFIFO_C0 COREFIFO_C0_0(
|
|
// Inputs
|
|
.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.RESET_N ( AND2_2_Y ),
|
|
.WE ( CORETSE_0_MRXRDY ),
|
|
.RE ( fifo_to_tpsram_bridge_0_fifo_rd_en ),
|
|
.DATA ( CORETSE_0_MRXDAT ),
|
|
// Outputs
|
|
.FULL ( ),
|
|
.EMPTY ( COREFIFO_C0_0_EMPTY ),
|
|
.Q ( COREFIFO_C0_0_Q )
|
|
);
|
|
|
|
//--------COREJTAGDEBUG_C0
|
|
COREJTAGDEBUG_C0 COREJTAGDEBUG_C0_0(
|
|
// Inputs
|
|
.TRSTB ( TRSTB ),
|
|
.TCK ( TCK ),
|
|
.TMS ( TMS ),
|
|
.TDI ( TDI ),
|
|
.TGT_TDO_0 ( MIV_RV32_C0_0_JTAG_TDO ),
|
|
// Outputs
|
|
.TDO ( TDO_net_0 ),
|
|
.TGT_TCK_0 ( COREJTAGDEBUG_C0_0_TGT_TCK_0 ),
|
|
.TGT_TMS_0 ( COREJTAGDEBUG_C0_0_TGT_TMS_0 ),
|
|
.TGT_TDI_0 ( COREJTAGDEBUG_C0_0_TGT_TDI_0 ),
|
|
.TGT_TRSTN_0 ( COREJTAGDEBUG_C0_0_TGT_TRSTN_0 )
|
|
);
|
|
|
|
//--------CORESPI_0
|
|
CORESPI_0 CORESPI_0_0(
|
|
// Inputs
|
|
.PCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.PRESETN ( PHY_RST_net_0 ),
|
|
.SPISSI ( VCC_net ),
|
|
.SPISDI ( SPISDI ),
|
|
.SPICLKI ( GND_net ),
|
|
.PSEL ( CoreAPB3_0_0_APBmslave2_PSELx ),
|
|
.PENABLE ( CoreAPB3_0_0_APBmslave0_PENABLE ),
|
|
.PWRITE ( CoreAPB3_0_0_APBmslave0_PWRITE ),
|
|
.PADDR ( CoreAPB3_0_0_APBmslave0_PADDR_1 ),
|
|
.PWDATA ( CoreAPB3_0_0_APBmslave0_PWDATA ),
|
|
// Outputs
|
|
.SPIINT ( ),
|
|
.SPIRXAVAIL ( ),
|
|
.SPITXRFM ( ),
|
|
.SPISCLKO ( SPISCLKO_net_0 ),
|
|
.SPIOEN ( ),
|
|
.SPISDO ( SPISDO_net_0 ),
|
|
.SPIMODE ( ),
|
|
.PREADY ( CoreAPB3_0_0_APBmslave2_PREADY ),
|
|
.PSLVERR ( CoreAPB3_0_0_APBmslave2_PSLVERR ),
|
|
.SPISS ( SPISS_net_2 ),
|
|
.PRDATA ( CoreAPB3_0_0_APBmslave2_PRDATA )
|
|
);
|
|
|
|
//--------CORETSE_0
|
|
CORETSE_0 CORETSE_0_inst_0(
|
|
// Inputs
|
|
.MTXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.MTXRDY ( CORETSE_0_MRXRDY ),
|
|
.MTXSOF ( CORETSE_0_MRXSOF ),
|
|
.MTXEOF ( CORETSE_0_MRXEOF ),
|
|
.MRXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.MRXACPT ( CORETSE_0_MTXACPT ),
|
|
.TXCLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
|
|
.RXCLK ( PF_IOD_CDR_C0_0_RX_CLK_R ),
|
|
.TBI_TX_CLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
|
|
.TBI_RX_CLK ( PF_IOD_CDR_C0_0_RX_CLK_R ),
|
|
.SIGNAL_DETECT ( VCC_net ),
|
|
.MDI ( BIBUF_0_Y ),
|
|
.PCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.PRESETN ( AND2_2_Y ),
|
|
.PENABLE ( CoreAPB3_0_0_APBmslave0_PENABLE ),
|
|
.PWRITE ( CoreAPB3_0_0_APBmslave0_PWRITE ),
|
|
.PSEL ( CoreAPB3_0_0_APBmslave0_PSELx ),
|
|
.MTXDAT ( CORETSE_0_MRXDAT ),
|
|
.MTXBYTEVALID ( CORETSE_0_MRXBYTEVALID ),
|
|
.RCG ( PF_IOD_CDR_C0_0_RX_DATA ),
|
|
.PADDR ( CoreAPB3_0_0_APBmslave0_PADDR ),
|
|
.PWDATA ( CoreAPB3_0_0_APBmslave0_PWDATA ),
|
|
// Outputs
|
|
.MTXACPT ( CORETSE_0_MTXACPT ),
|
|
.MTXHWM ( ),
|
|
.MRXRDY ( CORETSE_0_MRXRDY ),
|
|
.MRXSOF ( CORETSE_0_MRXSOF ),
|
|
.MRXEOF ( CORETSE_0_MRXEOF ),
|
|
.TBI_TX_VALID ( ),
|
|
.SYNC ( ),
|
|
.RCG_ERROR ( RD_BC_ERROR_net_0 ),
|
|
.MDC ( PHY_MDC_net_0 ),
|
|
.MDO ( CORETSE_0_MDO ),
|
|
.MDOEN ( CORETSE_0_MDOEN ),
|
|
.PSLVERR ( CoreAPB3_0_0_APBmslave0_PSLVERR ),
|
|
.PREADY ( CoreAPB3_0_0_APBmslave0_PREADY ),
|
|
.MRXDAT ( CORETSE_0_MRXDAT ),
|
|
.MRXBYTEVALID ( CORETSE_0_MRXBYTEVALID ),
|
|
.TCG ( CORETSE_0_TCG ),
|
|
.ANX_STATE ( ANX_STATE_net_0 ),
|
|
.TSM_CONTROL ( ),
|
|
.TSM_TX_INTR ( ),
|
|
.TSM_RX_INTR ( ),
|
|
.PRDATA ( CoreAPB3_0_0_APBmslave0_PRDATA )
|
|
);
|
|
|
|
//--------CoreUARTapb_0
|
|
CoreUARTapb_0 CoreUARTapb_0_inst_0(
|
|
// Inputs
|
|
.PCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.PRESETN ( PHY_RST_net_0 ),
|
|
.RX ( RX ),
|
|
.PSEL ( CoreAPB3_0_0_APBmslave1_PSELx ),
|
|
.PENABLE ( CoreAPB3_0_0_APBmslave0_PENABLE ),
|
|
.PWRITE ( CoreAPB3_0_0_APBmslave0_PWRITE ),
|
|
.PADDR ( CoreAPB3_0_0_APBmslave0_PADDR_0 ),
|
|
.PWDATA ( CoreAPB3_0_0_APBmslave0_PWDATA_0 ),
|
|
// Outputs
|
|
.TXRDY ( ),
|
|
.RXRDY ( ),
|
|
.PARITY_ERR ( ),
|
|
.OVERFLOW ( ),
|
|
.TX ( TX_net_0 ),
|
|
.FRAMING_ERR ( ),
|
|
.PREADY ( CoreAPB3_0_0_APBmslave1_PREADY ),
|
|
.PSLVERR ( CoreAPB3_0_0_APBmslave1_PSLVERR ),
|
|
.PRDATA ( CoreAPB3_0_0_APBmslave1_PRDATA )
|
|
);
|
|
|
|
//--------fifo_to_tpsram_bridge
|
|
fifo_to_tpsram_bridge fifo_to_tpsram_bridge_0(
|
|
// Inputs
|
|
.clk ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.reset_n ( AND2_2_Y ),
|
|
.fifo_data_out ( COREFIFO_C0_0_Q ),
|
|
.fifo_empty ( COREFIFO_C0_0_EMPTY ),
|
|
.transfer_enable ( VCC_net ),
|
|
// Outputs
|
|
.fifo_rd_en ( fifo_to_tpsram_bridge_0_fifo_rd_en ),
|
|
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
|
|
.ram_w_data ( fifo_to_tpsram_bridge_0_ram_w_data ),
|
|
.ram_w_en ( fifo_to_tpsram_bridge_0_ram_w_en ),
|
|
.buffer_full ( )
|
|
);
|
|
|
|
//--------INBUF_DIFF
|
|
INBUF_DIFF INBUF_DIFF_0(
|
|
// Inputs
|
|
.PADP ( REFCLK_P ),
|
|
.PADN ( REFCLK_N ),
|
|
// Outputs
|
|
.Y ( INBUF_DIFF_0_Y )
|
|
);
|
|
|
|
//--------MIV_RV32_C0
|
|
MIV_RV32_C0 MIV_RV32_C0_0(
|
|
// Inputs
|
|
.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.RESETN ( PHY_RST_net_0 ),
|
|
.APB_PREADY ( MIV_RV32_C0_0_APB_INITIATOR_PREADY ),
|
|
.APB_PSLVERR ( MIV_RV32_C0_0_APB_INITIATOR_PSLVERR ),
|
|
.JTAG_TRSTN ( COREJTAGDEBUG_C0_0_TGT_TRSTN_0 ),
|
|
.JTAG_TCK ( COREJTAGDEBUG_C0_0_TGT_TCK_0 ),
|
|
.JTAG_TDI ( COREJTAGDEBUG_C0_0_TGT_TDI_0 ),
|
|
.JTAG_TMS ( COREJTAGDEBUG_C0_0_TGT_TMS_0 ),
|
|
.EXT_IRQ ( GND_net ),
|
|
.APB_PRDATA ( MIV_RV32_C0_0_APB_INITIATOR_PRDATA ),
|
|
// Outputs
|
|
.EXT_RESETN ( ),
|
|
.APB_PENABLE ( MIV_RV32_C0_0_APB_INITIATOR_PENABLE ),
|
|
.APB_PWRITE ( MIV_RV32_C0_0_APB_INITIATOR_PWRITE ),
|
|
.APB_PSEL ( MIV_RV32_C0_0_APB_INITIATOR_PSELx ),
|
|
.JTAG_TDO ( MIV_RV32_C0_0_JTAG_TDO ),
|
|
.JTAG_TDO_DR ( ),
|
|
.TIME_COUNT_OUT ( ),
|
|
.APB_PADDR ( MIV_RV32_C0_0_APB_INITIATOR_PADDR ),
|
|
.APB_PWDATA ( MIV_RV32_C0_0_APB_INITIATOR_PWDATA )
|
|
);
|
|
|
|
//--------PF_CCC_0
|
|
PF_CCC_0 PF_CCC_0_0(
|
|
// Inputs
|
|
.REF_CLK_0 ( REF_CLK_0 ),
|
|
.PLL_POWERDOWN_N_0 ( Core_reset_pf_0_PLL_POWERDOWN_B ),
|
|
// Outputs
|
|
.OUT0_FABCLK_0 ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.PLL_LOCK_0 ( PF_CCC_0_0_PLL_LOCK_0 )
|
|
);
|
|
|
|
//--------pf_init_monitor_0
|
|
pf_init_monitor_0 pf_init_monitor_0_0(
|
|
// Outputs
|
|
.FABRIC_POR_N ( pf_init_monitor_0_0_FABRIC_POR_N ),
|
|
.PCIE_INIT_DONE ( ),
|
|
.USRAM_INIT_DONE ( ),
|
|
.SRAM_INIT_DONE ( ),
|
|
.DEVICE_INIT_DONE ( pf_init_monitor_0_0_DEVICE_INIT_DONE ),
|
|
.BANK_6_VDDI_STATUS ( pf_init_monitor_0_0_BANK_6_VDDI_STATUS ),
|
|
.XCVR_INIT_DONE ( ),
|
|
.USRAM_INIT_FROM_SNVM_DONE ( ),
|
|
.USRAM_INIT_FROM_UPROM_DONE ( ),
|
|
.USRAM_INIT_FROM_SPI_DONE ( ),
|
|
.SRAM_INIT_FROM_SNVM_DONE ( ),
|
|
.SRAM_INIT_FROM_UPROM_DONE ( ),
|
|
.SRAM_INIT_FROM_SPI_DONE ( ),
|
|
.AUTOCALIB_DONE ( )
|
|
);
|
|
|
|
//--------PF_IOD_CDR_C0
|
|
PF_IOD_CDR_C0 PF_IOD_CDR_C0_0(
|
|
// Inputs
|
|
.RX_P ( RX_P ),
|
|
.RX_N ( RX_N ),
|
|
.TX_CLK_G ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_TX_CLK_G ),
|
|
.HS_IO_CLK_0 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 ),
|
|
.HS_IO_CLK_90 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_90 ),
|
|
.HS_IO_CLK_180 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_180 ),
|
|
.HS_IO_CLK_270 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_270 ),
|
|
.HS_IO_CLK_PAUSE ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_PAUSE ),
|
|
.PLL_LOCK ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_PLL_LOCK ),
|
|
.DLL_LOCK ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_LOCK ),
|
|
.DLL_VALID_CODE ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_VALID_CODE ),
|
|
.CDR_START ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_CDR_START ),
|
|
.STREAM_START ( SSDetect_0_stream_start ),
|
|
.RST_N ( AND2_2_Y ),
|
|
.DLL_DELAY_CODE ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE ),
|
|
.TX_DATA ( CORETSE_0_TCG ),
|
|
// Outputs
|
|
.TX_P ( TX_P_net_0 ),
|
|
.TX_N ( TX_N_net_0 ),
|
|
.RX_CLK_R ( PF_IOD_CDR_C0_0_RX_CLK_R ),
|
|
.RX_VAL ( ),
|
|
.RX_DATA ( PF_IOD_CDR_C0_0_RX_DATA )
|
|
);
|
|
|
|
//--------PF_IOD_CDR_CCC_C0
|
|
PF_IOD_CDR_CCC_C0 PF_IOD_CDR_CCC_C0_0(
|
|
// Inputs
|
|
.REF_CLK ( INBUF_DIFF_0_Y ),
|
|
.ARST_N ( PHY_RST_net_0 ),
|
|
// Outputs
|
|
.TX_CLK_G_TO_CDR ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_TX_CLK_G ),
|
|
.HS_IO_CLK_270 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_270 ),
|
|
.HS_IO_CLK_0 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 ),
|
|
.HS_IO_CLK_90 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_90 ),
|
|
.HS_IO_CLK_180 ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_180 ),
|
|
.HS_IO_CLK_PAUSE ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_PAUSE ),
|
|
.PLL_LOCK ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_PLL_LOCK ),
|
|
.DLL_LOCK ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_LOCK ),
|
|
.DLL_VALID_CODE ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_VALID_CODE ),
|
|
.CDR_START ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_CDR_START ),
|
|
.TX_CLK_G ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
|
|
.DLL_DELAY_CODE ( PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_DLL_DELAY_CODE )
|
|
);
|
|
|
|
//--------PF_TPSRAM_C0
|
|
PF_TPSRAM_C0 PF_TPSRAM_C0_0(
|
|
// Inputs
|
|
.W_EN ( fifo_to_tpsram_bridge_0_ram_w_en ),
|
|
.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
|
|
.W_DATA ( fifo_to_tpsram_bridge_0_ram_w_data ),
|
|
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
|
|
.R_ADDR ( R_ADDR_const_net_0 ),
|
|
// Outputs
|
|
.R_DATA ( R_DATA_net_0 )
|
|
);
|
|
|
|
//--------SSDetect
|
|
SSDetect SSDetect_0(
|
|
// Inputs
|
|
.rst_b ( AND2_2_Y ),
|
|
.rck ( PF_IOD_CDR_C0_0_RX_CLK_R ),
|
|
.rx_data ( PF_IOD_CDR_C0_0_RX_DATA ),
|
|
// Outputs
|
|
.stream_start ( SSDetect_0_stream_start )
|
|
);
|
|
|
|
|
|
endmodule
|