158 lines
3.3 KiB
Plaintext
158 lines
3.3 KiB
Plaintext
-- $Header: //synplicity/map400rc/mappers/xilinx/lib/gen_spartan3/cmp_eq.vhd#1 $
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library ieee;
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use ieee.std_logic_1164.all;
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entity eq_element is
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port(a0, b0, a1, b1, ltin : in std_logic;
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ltout: out std_logic);
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end eq_element;
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architecture eqn of eq_element is
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signal t1 : std_logic;
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component MUXCY_L
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port (
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LO : out std_logic;
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CI : in std_logic;
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DI : in std_logic;
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S : in std_logic
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);
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end component;
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--attribute syn_black_box of MUXCY_L : component is true;
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begin
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t1 <= (a1 xnor b1) and (a0 xnor b0);
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mux_inst : MUXCY_L
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port map(S => t1,
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LO => ltout,
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CI => ltin,
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DI => '1');
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end eqn;
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library ieee;
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use ieee.std_logic_1164.all;
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entity eq_element_onebit is
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port(a0, b0, ltin : in std_logic;
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ltout: out std_logic);
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end eq_element_onebit;
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architecture eqn of eq_element_onebit is
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signal t1 : std_logic;
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component MUXCY_L
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port (
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LO : out std_logic;
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CI : in std_logic;
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DI : in std_logic;
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S : in std_logic
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);
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end component;
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--attribute syn_black_box of MUXCY_L : component is true;
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begin
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t1 <= (a0 xnor b0);
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mux_inst : MUXCY_L
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port map(S => t1,
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LO => ltout,
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CI => ltin,
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DI => '1');
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end eqn;
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library ieee;
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use ieee.std_logic_1164.all;
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entity CMP_EQ is
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generic(width : integer :=1);
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port(A: in std_logic_vector(width -1 downto 0);
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B: in std_logic_vector(width -1 downto 0);
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EQ : out std_logic);
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end CMP_EQ;
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architecture cell_level of CMP_EQ is
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function func_error(eq_width : integer) return string is
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begin
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if ((eq_width >= 12) and (eq_width <= 64)) then
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return("");
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else
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return("error");
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end if;
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end func_error;
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attribute generator_report : string;
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attribute generator_report of cell_level : architecture is func_error(width);
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constant iteration : integer := (width)/2;
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constant remainder : integer := (width) mod 2;
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signal data_tmp : std_logic_vector (width - 1 downto 0);
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signal NEQ : std_logic;
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component eq_element is
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port(a0, b0, a1, b1, ltin: in std_logic;
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ltout : out std_logic);
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end component;
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component eq_element_onebit is
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port(a0, b0, ltin: in std_logic;
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ltout : out std_logic);
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end component;
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begin
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U0 : if( width > 1) generate
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begin
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U01 : eq_element
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port map(
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a0 => A(0),
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b0 => B(0),
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a1 => A(1),
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b1 => B(1),
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ltin => '0',
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ltout => data_tmp(0));
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end generate;
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U1 : if( width = 1) generate
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begin
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NEQ <= A(0) xnor B(0);
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end generate;
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U2 : for bit_index in 1 to (iteration - 1) generate
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begin
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U21 : eq_element
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port map(
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a0 => A(2*bit_index),
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b0 => B(2*bit_index),
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a1 => A(2*bit_index + 1),
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b1 => B(2*bit_index + 1),
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ltin => data_tmp(bit_index - 1),
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ltout => data_tmp(bit_index));
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end generate;
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U3 : if( remainder = 1 and width > 1) generate
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begin
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U31 : eq_element_onebit
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port map(
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a0 => A(width -1),
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b0 => B(width - 1),
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ltin =>data_tmp(iteration - 1),
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ltout => NEQ);
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end generate;
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U4 : if(remainder = 0 and width > 1) generate
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begin
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NEQ <= data_tmp(iteration - 1);
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end generate;
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U5: EQ <= not(NEQ);
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end cell_level;
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