2643 lines
136 KiB
Plaintext
2643 lines
136 KiB
Plaintext
KEY LIBERO "2025.1"
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KEY CAPTURE "2025.1.0.14"
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KEY DEFAULT_IMPORT_LOC "C:\Actelprj\A3P_Verilog_labs\lab2"
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KEY DEFAULT_OPEN_LOC ""
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KEY ProjectID "0"
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KEY HDLTechnology "VERILOG"
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KEY VERILOGMODE "SYSTEMVERILOG"
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KEY VHDLMODE "VHDL2008"
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KEY SYSTEMVERILOGMFCU "FALSE"
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KEY UseConstraintFlowTechnology "TRUE"
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KEY VendorTechnology_Family "PolarFire"
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KEY VendorTechnology_Die "PA5M300TS"
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KEY VendorTechnology_Package "fcg1152"
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KEY VendorTechnology_Speed "-1"
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KEY VendorTechnology_DieVoltage "1.05"
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KEY VendorTechnology_PART_RANGE "IND"
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KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE ""
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KEY VendorTechnology_IO_DEFT_STD "LVCMOS18"
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KEY VendorTechnology_OPCONR ""
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KEY VendorTechnology_PLL_SUPPLY ""
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KEY VendorTechnology_RAD_EXPOSURE ""
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KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
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KEY VendorTechnology_RESTRICTPROBEPINS "1"
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KEY VendorTechnology_RESTRICTSPIPINS "0"
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KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE "0"
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KEY VendorTechnology_TARGETDEVICESFORMIGRATION "PA5M300TS"
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KEY VendorTechnology_TEMPR "IND"
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KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
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KEY VendorTechnology_VCCI_1.2_VOLTR "IND"
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KEY VendorTechnology_VCCI_1.5_VOLTR "IND"
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KEY VendorTechnology_VCCI_1.8_VOLTR "IND"
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KEY VendorTechnology_VCCI_2.5_VOLTR "IND"
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KEY VendorTechnology_VCCI_3.3_VOLTR "IND"
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KEY VendorTechnology_VOLTR "IND"
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KEY ProjectLocation "E:\AbhishekV\rising\ethernet_tpsram_test"
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KEY ProjectDescription ""
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KEY UseRootLocationForLinkedFiles "FALSE"
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KEY RootLocationENVForLinkedFiles ""
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KEY RootLocationForLinkedFiles ""
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KEY GlobalIncludePaths ""
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KEY Pa4PeripheralNewSeq "GOOD"
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KEY MemoryMapDrcSeverity "FALSE"
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KEY LossOfDataDRCSeverity "TRUE"
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KEY IdWidthMismatchDRCSeverity "TRUE"
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KEY SimulationType "VERILOG"
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KEY Vendor "Actel"
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KEY ActiveRoot "top::work"
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LIST REVISIONS
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VALUE="Impl1",NUM=1
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CURREV=1
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ENDLIST
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LIST LIBRARIES
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COREAPB3_LIB
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COREJTAGDEBUG_LIB
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CORESPI_LIB
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ENDLIST
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LIST LIBRARY_COREAPB3_LIB
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ALIAS=COREAPB3_LIB
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COMPILE_OPTION=COMPILE
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CUSTOMPATH=false
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ENDLIST
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LIST LIBRARY_COREJTAGDEBUG_LIB
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ALIAS=COREJTAGDEBUG_LIB
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COMPILE_OPTION=COMPILE
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CUSTOMPATH=false
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ENDLIST
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LIST LIBRARY_CORESPI_LIB
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ALIAS=CORESPI_LIB
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COMPILE_OPTION=COMPILE
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CUSTOMPATH=false
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ENDLIST
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LIST GlobalIncludeFileList
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ENDLIST
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LIST FileManager
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096663"
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SIZE="2736"
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PARENT="<project>\component\work\CoreAPB3_0\CoreAPB3_0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
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STATE="utd"
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TIME="1776096663"
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SIZE="1284"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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IS_INCLUDED="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
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STATE="utd"
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TIME="1776075074"
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SIZE="912"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="4645"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="9100"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="25147"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="36284"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="122465"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v,hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="29701"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v,hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="4465"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v,hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="5708"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
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STATE="utd"
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TIME="1776075074"
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SIZE="23813"
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LIBRARY="COREAPB3_LIB"
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PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
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MODULE_UNDER_TEST="testbench"
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SIMULATION_TIME="-all"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\CORECDR4_CNTL_TIP.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096724"
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SIZE="487"
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PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v,hdl"
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STATE="utd"
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TIME="1776088270"
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SIZE="9425"
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PARENT="<project>\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\CORECDR4_CNTL_TIP.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\COREDELAYCODE_TIP.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096764"
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SIZE="487"
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PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v,hdl"
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STATE="utd"
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TIME="1776087985"
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SIZE="5136"
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PARENT="<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\COREDELAYCODE_TIP.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776257512"
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SIZE="1298"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="697"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="13955"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="22096"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="3801"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="2194"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="2287"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
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STATE="utd"
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TIME="1776225025"
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SIZE="1981"
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PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096661"
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SIZE="1916"
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PARENT="<project>\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v,hdl"
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STATE="utd"
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TIME="1776075072"
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SIZE="24714"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v,hdl"
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STATE="utd"
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TIME="1776075072"
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SIZE="1033"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v,hdl"
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STATE="utd"
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TIME="1776075072"
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SIZE="6203"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v,hdl"
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STATE="utd"
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TIME="1776075072"
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SIZE="18296"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
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STATE="utd"
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TIME="1776075072"
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SIZE="1934"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
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TIME="1776075072"
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SIZE="9726"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
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STATE="utd"
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TIME="1776075072"
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SIZE="11170"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
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STATE="utd"
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TIME="1776075072"
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SIZE="13990"
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LIBRARY="COREJTAGDEBUG_LIB"
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PARENT="<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf"
|
|
MODULE_UNDER_TEST="COREJTAGDEBUG_TESTBENCH"
|
|
SIMULATION_TIME="-all"
|
|
IS_READONLY="TRUE"
|
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORERESET_PF\2.3.100\CORERESET_PF.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096662"
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SIZE="485"
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PARENT="<project>\component\work\Core_reset_pf\Core_reset_pf.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096664"
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SIZE="2961"
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PARENT="<project>\component\work\CORESPI_0\CORESPI_0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
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STATE="utd"
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TIME="1776075075"
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SIZE="922"
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
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STATE="utd"
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TIME="1776075075"
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SIZE="3399"
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
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STATE="utd"
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TIME="1776075075"
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SIZE="6496"
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LIBRARY="CORESPI_LIB"
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
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STATE="utd"
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TIME="1776075075"
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SIZE="9225"
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LIBRARY="CORESPI_LIB"
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
|
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
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STATE="utd"
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TIME="1776075075"
|
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SIZE="197644"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="40025"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
|
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IS_READONLY="TRUE"
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IS_INCLUDED="TRUE"
|
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v,hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="4698"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v,hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="13098"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v,hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="42389"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
|
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v,hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="1034"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
|
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IS_READONLY="TRUE"
|
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v,hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="3070"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v,hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="6157"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v,hdl"
|
|
STATE="utd"
|
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TIME="1776075075"
|
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SIZE="9209"
|
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LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
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STATE="utd"
|
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TIME="1776075075"
|
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SIZE="6648"
|
|
LIBRARY="CORESPI_LIB"
|
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PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
|
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MODULE_UNDER_TEST="testbench"
|
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SIMULATION_TIME="-all"
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IS_READONLY="TRUE"
|
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf,actgen_cxf"
|
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STATE="utd"
|
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TIME="1776096671"
|
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SIZE="1844"
|
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PARENT="<project>\component\work\CORETSE_0\CORETSE_0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
|
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STATE="utd"
|
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TIME="1776075082"
|
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SIZE="8117"
|
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PARENT="<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v,hdl"
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STATE="utd"
|
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TIME="1776075082"
|
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SIZE="3205609"
|
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PARENT="<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v,hdl"
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STATE="utd"
|
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TIME="1776075082"
|
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SIZE="9488"
|
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PARENT="<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf"
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IS_READONLY="TRUE"
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IS_INCLUDED="TRUE"
|
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776075082"
|
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SIZE="44632"
|
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PARENT="<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
|
STATE="utd"
|
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TIME="1776075082"
|
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SIZE="44626"
|
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PARENT="<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
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STATE="utd"
|
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TIME="1776075082"
|
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SIZE="10253"
|
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PARENT="<project>\component\Actel\DirectCore\CORETSE\4.0.124\CORETSE.cxf"
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MODULE_UNDER_TEST="testbench"
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SIMULATION_TIME="-all"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Actel\DirectCore\CoreUARTapb\5.7.100\CoreUARTapb.cxf,actgen_cxf"
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STATE="utd"
|
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TIME="1776096673"
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SIZE="779"
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PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_CCC\2.2.220\PF_CCC.cxf,actgen_cxf"
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STATE="utd"
|
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TIME="1776096763"
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SIZE="279"
|
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PARENT="<project>\component\work\PF_CCC_0\PF_CCC_0.cxf"
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PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_CLK_DIV\1.0.103\PF_CLK_DIV.cxf,actgen_cxf"
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STATE="utd"
|
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TIME="1776096764"
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SIZE="247"
|
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PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_INIT_MONITOR\2.0.308\PF_INIT_MONITOR.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096718"
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SIZE="288"
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PARENT="<project>\component\work\pf_init_monitor_0\pf_init_monitor_0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_IOD\1.0.218\PF_IOD.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776096747"
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SIZE="243"
|
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PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_LANECTRL\2.0.102\PF_LANECTRL.cxf,actgen_cxf"
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STATE="utd"
|
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TIME="1776096766"
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SIZE="364"
|
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PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
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PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_TPSRAM\1.1.108\PF_TPSRAM.cxf,actgen_cxf"
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STATE="utd"
|
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TIME="1776384266"
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SIZE="246"
|
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PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v,hdl"
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STATE="utd"
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TIME="1776075084"
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SIZE="2231213"
|
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PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v,hdl"
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STATE="utd"
|
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TIME="1776075084"
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SIZE="2646538"
|
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PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v,hdl"
|
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STATE="utd"
|
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TIME="1776075084"
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SIZE="2731825"
|
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PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf,actgen_cxf"
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STATE="utd"
|
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TIME="1776096674"
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SIZE="1084"
|
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PARENT="<project>\component\work\MIV_RV32_C0\MIV_RV32_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776075084"
|
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SIZE="8274"
|
|
PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v,hdl"
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|
STATE="utd"
|
|
TIME="1776075084"
|
|
SIZE="91878"
|
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PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v,hdl"
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|
STATE="utd"
|
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TIME="1766140232"
|
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SIZE="18418"
|
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PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
|
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v,hdl"
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|
STATE="utd"
|
|
TIME="1776075084"
|
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SIZE="769533"
|
|
PARENT="<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\MIV_RV32.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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|
VALUE "<project>\component\work\CoreAPB3_0\CoreAPB3_0.cxf,actgen_cxf"
|
|
STATE="utd"
|
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TIME="1776096663"
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SIZE="12115"
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ENDFILE
|
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VALUE "<project>\component\work\CoreAPB3_0\CoreAPB3_0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096663"
|
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SIZE="13295"
|
|
PARENT="<project>\component\work\CoreAPB3_0\CoreAPB3_0.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf,actgen_cxf"
|
|
STATE="utd"
|
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TIME="1776257514"
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SIZE="4447"
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ENDFILE
|
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
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SIZE="5479"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
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IS_READONLY="TRUE"
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ENDFILE
|
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="3861"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
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ENDFILE
|
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="997"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
|
|
IS_INCLUDED="TRUE"
|
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="23"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="3286"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="71458"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="55032"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="4400"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257511"
|
|
SIZE="2224"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
|
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="13313"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="2549"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="2332"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="33348"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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|
IS_READONLY="TRUE"
|
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ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="23539"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="19026"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
MODULE_UNDER_TEST="testbench"
|
|
SIMULATION_TIME=" -all"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776257512"
|
|
SIZE="401"
|
|
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
|
IS_READONLY="TRUE"
|
|
IS_INCLUDED="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096662"
|
|
SIZE="6915"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096661"
|
|
SIZE="12057"
|
|
PARENT="<project>\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CORESPI_0\CORESPI_0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096664"
|
|
SIZE="6540"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CORESPI_0\CORESPI_0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096664"
|
|
SIZE="5974"
|
|
PARENT="<project>\component\work\CORESPI_0\CORESPI_0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CORETSE_0\CORETSE_0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096672"
|
|
SIZE="10177"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CORETSE_0\CORETSE_0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096672"
|
|
SIZE="11479"
|
|
PARENT="<project>\component\work\CORETSE_0\CORETSE_0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="6009"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="5286"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="605"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
IS_INCLUDED="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="4142"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="1011"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="2034"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="8118"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="11270"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="2521"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="48870"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="4665"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="9162"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="25217"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="36333"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="4728"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="122543"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="13262"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="14320"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="13967"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="8300"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="21171"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="8868"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="8984"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
MODULE_UNDER_TEST="testbench"
|
|
SIMULATION_TIME="-all"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096662"
|
|
SIZE="3362"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096662"
|
|
SIZE="3396"
|
|
PARENT="<project>\component\work\Core_reset_pf\Core_reset_pf.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096662"
|
|
SIZE="2663"
|
|
PARENT="<project>\component\work\Core_reset_pf\Core_reset_pf_0\Core_reset_pf_Core_reset_pf_0_CORERESET_PF.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\Core_reset_pf_Core_reset_pf_0_CORERESET_PF.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096662"
|
|
SIZE="867"
|
|
PARENT="<project>\component\work\Core_reset_pf\Core_reset_pf.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
|
STATE="utd"
|
|
TIME="1776096662"
|
|
SIZE="5487"
|
|
PARENT="<project>\component\work\Core_reset_pf\Core_reset_pf_0\Core_reset_pf_Core_reset_pf_0_CORERESET_PF.cxf"
|
|
MODULE_UNDER_TEST="corereset_pf_tb"
|
|
SIMULATION_TIME="-all"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\MIV_RV32_C0\MIV_RV32_C0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096674"
|
|
SIZE="10880"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\MIV_RV32_C0\MIV_RV32_C0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096674"
|
|
SIZE="15029"
|
|
PARENT="<project>\component\work\MIV_RV32_C0\MIV_RV32_C0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\MIV_RV32_C0\MIV_RV32_C0_0\MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096674"
|
|
SIZE="492"
|
|
PARENT="<project>\component\work\MIV_RV32_C0\MIV_RV32_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096674"
|
|
SIZE="33259"
|
|
PARENT="<project>\component\work\MIV_RV32_C0\MIV_RV32_C0_0\MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_CCC_0\PF_CCC_0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096714"
|
|
SIZE="18345"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_CCC_0\PF_CCC_0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096714"
|
|
SIZE="10298"
|
|
PARENT="<project>\component\work\PF_CCC_0\PF_CCC_0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096714"
|
|
SIZE="475"
|
|
PARENT="<project>\component\work\PF_CCC_0\PF_CCC_0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096714"
|
|
SIZE="3889"
|
|
PARENT="<project>\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\pf_init_monitor_0\pf_init_monitor_0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096718"
|
|
SIZE="9435"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\pf_init_monitor_0\pf_init_monitor_0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096718"
|
|
SIZE="9508"
|
|
PARENT="<project>\component\work\pf_init_monitor_0\pf_init_monitor_0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096718"
|
|
SIZE="529"
|
|
PARENT="<project>\component\work\pf_init_monitor_0\pf_init_monitor_0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096718"
|
|
SIZE="1917"
|
|
PARENT="<project>\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096751"
|
|
SIZE="8576"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096750"
|
|
SIZE="113118"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096730"
|
|
SIZE="523"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096730"
|
|
SIZE="4134"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096736"
|
|
SIZE="499"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096736"
|
|
SIZE="3762"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096742"
|
|
SIZE="499"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096742"
|
|
SIZE="3814"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096747"
|
|
SIZE="495"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096747"
|
|
SIZE="6088"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096749"
|
|
SIZE="621"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096749"
|
|
SIZE="4824"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096749"
|
|
SIZE="3696"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096763"
|
|
SIZE="489"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096763"
|
|
SIZE="6887"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096764"
|
|
SIZE="505"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096764"
|
|
SIZE="425"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096767"
|
|
SIZE="6815"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096766"
|
|
SIZE="10422"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776096766"
|
|
SIZE="653"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096766"
|
|
SIZE="4449"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096766"
|
|
SIZE="3712"
|
|
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776384267"
|
|
SIZE="4881"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776384266"
|
|
SIZE="3681"
|
|
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776384266"
|
|
SIZE="772"
|
|
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776384266"
|
|
SIZE="7800"
|
|
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\top\top.cxf,actgen_cxf"
|
|
STATE="utd"
|
|
TIME="1776394606"
|
|
SIZE="7212"
|
|
ENDFILE
|
|
VALUE "<project>\component\work\top\top.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776394606"
|
|
SIZE="26020"
|
|
PARENT="<project>\component\work\top\top.cxf"
|
|
IS_READONLY="TRUE"
|
|
ENDFILE
|
|
VALUE "<project>\constraint\io\io_constraints.pdc,io_pdc"
|
|
STATE="utd"
|
|
TIME="1776096819"
|
|
SIZE="3913"
|
|
ENDFILE
|
|
VALUE "<project>\constraint\timing_user_constraints.sdc,sdc"
|
|
STATE="utd"
|
|
TIME="1776096825"
|
|
SIZE="2342"
|
|
ENDFILE
|
|
VALUE "<project>\constraint\top_derived_constraints.sdc,sdc"
|
|
STATE="utd"
|
|
TIME="1776096825"
|
|
SIZE="4809"
|
|
ENDFILE
|
|
VALUE "<project>\hdl\fifo_to_tpsram_bridge.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776394591"
|
|
SIZE="3691"
|
|
ENDFILE
|
|
VALUE "<project>\hdl\SSDetect.v,hdl"
|
|
STATE="utd"
|
|
TIME="1776096660"
|
|
SIZE="1303"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\bfmtovec_compile.log,log"
|
|
STATE="utd"
|
|
TIME="1776320914"
|
|
SIZE="407"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
|
|
STATE="utd"
|
|
TIME="1776075074"
|
|
SIZE="1229"
|
|
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
|
|
STATE="utd"
|
|
TIME="1776075074"
|
|
SIZE="8016"
|
|
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\CoreAPB3.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="2906"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
|
|
STATE="utd"
|
|
TIME="1776096673"
|
|
SIZE="13597"
|
|
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\run.do,do"
|
|
STATE="utd"
|
|
TIME="1776320890"
|
|
SIZE="1760"
|
|
ENDFILE
|
|
VALUE "<project>\simulation\user_tb.bfm,sim"
|
|
STATE="utd"
|
|
TIME="1776075075"
|
|
SIZE="7303"
|
|
PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
|
|
ENDFILE
|
|
VALUE "<project>\synthesis\synwork\layer0.so,so"
|
|
STATE="utd"
|
|
TIME="1776384138"
|
|
SIZE="159"
|
|
ENDFILE
|
|
VALUE "<project>\synthesis\top.so,so"
|
|
STATE="utd"
|
|
TIME="1776395162"
|
|
SIZE="221"
|
|
ENDFILE
|
|
VALUE "<project>\synthesis\top.vm,syn_vm"
|
|
STATE="utd"
|
|
TIME="1776395157"
|
|
SIZE="6235009"
|
|
ENDFILE
|
|
VALUE "<project>\synthesis\top_syn.prj,prj"
|
|
STATE="utd"
|
|
TIME="1776395163"
|
|
SIZE="12159"
|
|
ENDFILE
|
|
VALUE "<project>\synthesis\top_vm.sdc,syn_sdc"
|
|
STATE="utd"
|
|
TIME="1776395158"
|
|
SIZE="6962"
|
|
ENDFILE
|
|
ENDLIST
|
|
LIST UsedFile
|
|
ENDLIST
|
|
LIST NewModulesInfo
|
|
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work"
|
|
FILE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work"
|
|
FILE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CORETSE::work"
|
|
FILE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work"
|
|
FILE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
|
|
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "top::work"
|
|
FILE "<project>\component\work\top\top.v,hdl"
|
|
LIST SynthesisConstraints
|
|
VALUE "<project>\constraint\top_derived_constraints.sdc,sdc"
|
|
VALUE "<project>\constraint\timing_user_constraints.sdc,sdc"
|
|
ENDLIST
|
|
LIST TimingConstraints
|
|
VALUE "<project>\constraint\top_derived_constraints.sdc,sdc"
|
|
VALUE "<project>\constraint\timing_user_constraints.sdc,sdc"
|
|
ENDLIST
|
|
LIST PNRConstraints
|
|
VALUE "<project>\constraint\top_derived_constraints.sdc,sdc"
|
|
VALUE "<project>\constraint\timing_user_constraints.sdc,sdc"
|
|
VALUE "<project>\constraint\io\io_constraints.pdc,io_pdc"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSYNTHESIS(<project>\synthesis\top.vm,syn_vm)=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CoreAPB3::COREAPB3_LIB"
|
|
FILE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
|
|
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB"
|
|
FILE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CORESPI::CORESPI_LIB"
|
|
FILE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v,hdl"
|
|
LIST Other_Association
|
|
VALUE "<project>\simulation\user_tb.bfm,sim"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST AssociatedStimulus
|
|
LIST COREJTAGDEBUG
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST CORESPI
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST CORETSE
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
|
ENDLIST
|
|
LIST CoreAPB3
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
ENDLIST
|
|
LIST Core_reset_pf_Core_reset_pf_0_CORERESET_PF
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST Other_Association
|
|
LIST COREFIFO_C0_COREFIFO_C0_0_COREFIFO
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
|
|
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
|
|
ENDLIST
|
|
LIST COREJTAGDEBUG
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
|
|
ENDLIST
|
|
LIST CORESPI
|
|
VALUE "<project>\simulation\user_tb.bfm,sim"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
|
|
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
|
|
ENDLIST
|
|
LIST CORETSE
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
|
|
ENDLIST
|
|
LIST CoreAPB3
|
|
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
|
|
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
|
|
ENDLIST
|
|
LIST CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb
|
|
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
|
|
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
|
|
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
|
|
ENDLIST
|
|
LIST Core_reset_pf_Core_reset_pf_0_CORERESET_PF
|
|
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST SimulationOptions
|
|
UseAutomaticDoFile=true
|
|
IncludeWaveDo=false
|
|
Type=max
|
|
RunTime=1000ns
|
|
Resolution=1ps
|
|
VsimOpt=
|
|
EntityName=testbench
|
|
TopInstanceName=<top>_0
|
|
DoFileName=
|
|
DoFileName2=wave.do
|
|
DoFileParams=
|
|
DisplayDUTWave=false
|
|
LogAllSignals=false
|
|
DisablePulseFiltering=false
|
|
DumpVCD=false
|
|
VCDFileName=power.vcd
|
|
VHDL2008=false
|
|
Verilog2001=false
|
|
SystemVerilog=false
|
|
TimeUnit=1
|
|
TimeUnitBase=ns
|
|
Precision=100
|
|
PrecisionBase=ps
|
|
SdfCorner=slow_lv_ht
|
|
PliPath=E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll
|
|
UseCustomPliPath=false
|
|
ENDLIST
|
|
LIST ModelSimLibPath
|
|
UseCustomPath=FALSE
|
|
LibraryPath=
|
|
ENDLIST
|
|
LIST GlobalFlowOptions
|
|
GenerateHDLAfterSynthesis=FALSE
|
|
GenerateHDLAfterPhySynthesis=FALSE
|
|
RunDRCAfterSynthesis=FALSE
|
|
AutoCheckConstraints=TRUE
|
|
UpdateModelSimIni=TRUE
|
|
NoIOMode=FALSE
|
|
PeriInitStandalone=FALSE
|
|
OnDemandBuildDH=TRUE
|
|
EnableViewDraw=FALSE
|
|
UpdateViewDrawIni=TRUE
|
|
GenerateHDLFromSchematic=TRUE
|
|
VmNetlistFlowOn=TRUE
|
|
EnableDesignSeparationOn=FALSE
|
|
EnableSETMitigationOn=FALSE
|
|
DisplayFanoutLimit=10
|
|
AbortFlowOnPDCErrorsOn=TRUE
|
|
AbortFlowOnSDCErrorsOn=TRUE
|
|
AbortFlowOn3.3V_IO_ON=FALSE
|
|
InstantiateInSmartDesign=TRUE
|
|
FlashProInputFile=pdb
|
|
SmartGenCompileReport=T
|
|
ENDLIST
|
|
LIST PhySynthesisOptions
|
|
ENDLIST
|
|
LIST Profiles
|
|
NAME="SoftConsole"
|
|
FUNCTION="SoftwareIDE"
|
|
TOOL="SoftConsole"
|
|
LOCATION="eclipse.exe"
|
|
PARAM=""
|
|
BATCH=0
|
|
LICENSE=""
|
|
IS32BIT="1"
|
|
EndProfile
|
|
NAME="Synplify Pro ME"
|
|
FUNCTION="Synthesis"
|
|
TOOL="Synplify Pro ME"
|
|
LOCATION="E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin\synplify_pro.exe"
|
|
PARAM=""
|
|
BATCH=0
|
|
LICENSE=""
|
|
IS32BIT="1"
|
|
EndProfile
|
|
NAME="ModelSim ME Pro"
|
|
FUNCTION="Simulation"
|
|
TOOL="ModelSim Pro Edition"
|
|
LOCATION="E:\Microchip\Libero_SoC_2025.1\Libero_SoC\ModelSim_Pro\win32acoem\modelsim.exe"
|
|
PARAM=""
|
|
BATCH=0
|
|
LICENSE=""
|
|
IS32BIT="1"
|
|
EndProfile
|
|
NAME="Identify Debugger"
|
|
FUNCTION="IdentifyDebugger"
|
|
TOOL="Identify Debugger"
|
|
LOCATION="E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Identify\bin\identify_debugger.exe"
|
|
PARAM=""
|
|
BATCH=0
|
|
LICENSE=""
|
|
IS32BIT="1"
|
|
EndProfile
|
|
ENDLIST
|
|
LIST ProjectState5.1
|
|
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work"
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CORETSE::work"
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work"
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "top::work"
|
|
LIST Impl1
|
|
ideSYNTHESIS(<project>\synthesis\top.vm,syn_vm)=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CoreAPB3::COREAPB3_LIB"
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB"
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST "CORESPI::CORESPI_LIB"
|
|
LIST Impl1
|
|
ideSTIMULUS=StateSuccess
|
|
LIST FlowOptions
|
|
UsePhySynth=FALSE
|
|
UseSynth=TRUE
|
|
UseFhbAutoInst=FALSE
|
|
ENDLIST
|
|
Used_File_List
|
|
ENDUsed_File_List
|
|
ENDLIST
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST ExcludePackageForSimulation
|
|
ENDLIST
|
|
LIST ExcludePackageForSynthesis
|
|
ENDLIST
|
|
LIST IncludeModuleForSimulation
|
|
ENDLIST
|
|
LIST CDBOrder
|
|
ENDLIST
|
|
LIST UserCustomizedFileList
|
|
ENDLIST
|
|
LIST OpenedFileList
|
|
ORIENTATION;HORIZONTAL
|
|
StartPage;StartPage;0
|
|
ACTIVEVIEW;StartPage
|
|
ENDLIST
|
|
LIST ModuleSubBlockList
|
|
LIST "Core_reset_pf::work","component\work\Core_reset_pf\Core_reset_pf.v","TRUE","FALSE"
|
|
SUBBLOCK "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work","component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work","component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreAPB3_0::work","component\work\CoreAPB3_0\CoreAPB3_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CORECDR4_CNTL_TIP::work","component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREDELAYCODE_TIP::work","component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0::work","component\work\COREFIFO_C0\COREFIFO_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_async::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_ram_wrapper::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_async::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_LSRAM_top::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG_C0::work","component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "COREJTAGDEBUG::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CORESPI_0::work","component\work\CORESPI_0\CORESPI_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CORESPI::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CORETSE::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CORETSE_0::work","component\work\CORETSE_0\CORETSE_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CORETSE::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0::work","component\work\CoreUARTapb_0\CoreUARTapb_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_COREUART::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_Rx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_Tx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_ram_wrapper::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v","FALSE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_LSRAM_top::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_COREUART::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Rx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Tx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_xaddr_buffer_slot::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_decode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_privarch::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_priv_irq::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_decode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_debug_fifo::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_expipe::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_decode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_privarch::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_exu::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ram::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_idecode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bcu::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_exu::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_top::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_mul::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fetch_unit::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_ifu_iab::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fixed_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ram::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ram_array::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ecc_enc_dec::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ram_mux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ram_array::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_hart::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_expipe::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fetch_unit::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lsu::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_idecode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_ifu_iab::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_ipcore::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_hart::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_interconnect::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_mtime_irq::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_tcm::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_ahb_initiator::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_apb_initiator::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_axi_initiator::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_debug::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_icache::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_tcm_tas_apb_target::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_udma::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_priv_irq::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_irq_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_ram_singleport_lp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fixed_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_interconnect::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_subsys_regs::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_mtime_irq::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_regs::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_tcm::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_ram_singleport_lp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bootrom::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_rbcw::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_ram_singleport_addreg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_ram_singleport_lp_ecc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_decode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_debug_fifo::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "fifo_to_tpsram_bridge::work","hdl\fifo_to_tpsram_bridge.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_egress_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_egress_slip_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_ingress_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_rchan::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_axi_egress_slip_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_axi_ingress_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_wchan::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_axi_egress_slip_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_axi_xaddr_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_axi_xaddr_buffer_slot::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bcu::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_decode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_ecc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_ecc_core::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_ecc_empty::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_ecc_core::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_ecc_read::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_ecc_write::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_ecc_empty::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_ecc_read::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_decode::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_ecc_write::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_err_inject::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_pipeline::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bist_template_dual_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_pipeline::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_pl_enable::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_ram_stabilizer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdualdata_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdual_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdual_eccw::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_ecc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_err_inject::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_err_mask::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdual_err_mask::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdual_pl_enable::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdual_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "pmc_sync_flop_behav_v3::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdual_ram_stabilizer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistdualdata_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_logic_mux_behav_v2::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "pmc_logic_mux_behav::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_bootrom::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "MIV_RV32_C0::work","component\work\MIV_RV32_C0\MIV_RV32_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32::work","component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32::work","component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_ipcore::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_common_buffer_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_control_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_iteration_div_sqrt_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_debug_dtm_jtag::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_debug_du::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_debug_sba::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_debug_sba::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_div_sqrt_top_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_norm_div_sqrt_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_nrbd_nrsc_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_preprocess_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_dpr256x32_hqa_dual_storage_bistw::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_dpr_hqa_dual_storage_bistw_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_template_dual_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_eccw::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_ram_dport_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_dpr_hqa_dual_storage_bistw_dft::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_dpr_hqa_dual_storage_bistw_fpga::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_dpr_hqa_dual_storage_rbcw::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "RAM_BIST_ERROR:ASIC_view_does_not_exist_in_miv_rv32_dpr_hqa_dual_storage_rbcw::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr256x32_hqa_dual_storage_bistw::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_bistw_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_bistw_dft::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_bistw_fpga::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fixed_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_cast_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_classifier::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_rounding::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_classifier::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_divsqrt_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_div_sqrt_top_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_divsqrt_th_32::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_top::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fpu_dp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fpu_frbus::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_fma::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_classifier::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_rounding::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_fma_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_classifier::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_rounding::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_noncomp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_classifier::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_opgroup_block::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_opgroup_fmt_slice::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_opgroup_multifmt_slice::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_arb_tree::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_opgroup_fmt_slice::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_fma::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_noncomp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_opgroup_multifmt_slice::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_cast_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_divsqrt_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_divsqrt_th_32::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_fma_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_sdotp_multi_wrapper::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_rounding::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_sdotp_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_classifier::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_rounding::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_sdotp_multi_wrapper::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_sdotp_multi::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_fpnew_top::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fpnew_opgroup_block::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_arb_tree::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gated_clk_cell::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ecc_bist_template::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bist_pipeline::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_pl_enable::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_ram_stabilizer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdualdata_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ecc_enc_dec::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "RAM_BIST_ERROR:ASIC_view_does_not_exist_in_miv_rv32_dpr_hqa_dual_storage_rbcw::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr256x32_hqa_dual_storage_bistw::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_bistw_dft::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_bistw_fpga::work","","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ecc_enc_dec_bistw_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ecc_enc_dec_bistw_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_bistdual_eccw::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ecc_bist_template::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gpr_ram_array::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ram_array::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_gpr_ram_mux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_hart_cfg_pkg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_icache_array::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_icache_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_icache_ram_mux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_irq_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_iteration_div_sqrt_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_logic_mux_behav_v2::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_lsu::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_mul::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_norm_div_sqrt_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_nrbd_nrsc_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_control_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_ctrl::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gated_clk_cell::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_ff1::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_pack_single::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_prepare::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_ff1::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_round_single::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gated_clk_cell::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_special::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_srt_single::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gated_clk_cell::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fdsu_top::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_ctrl::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_pack_single::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_prepare::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_round_single::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_special::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fdsu_srt_single::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fpu_dp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_gated_clk_cell::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_pa_fpu_src_type::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fpu_frbus::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pa_fpu_src_type::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_pkg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_preprocess_mvp::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_ram_dport_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_ram_singleport_addreg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_ram_singleport_lp_ecc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_rr_arb_tree::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_lzc::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_fixed_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_strb_to_addr::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_ahb_initiator::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_apb_initiator::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_rr_pri_arb::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_axi_initiator::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_axi_rchan::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_axi_wchan::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_strb_to_addr::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_debug::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_debug_fifo::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_debug_fifo::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_debug_dtm_jtag::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_debug_du::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_icache::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_dpr_hqa_dual_storage_rbcw::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_icache_array::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_icache_ram_init::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
SUBBLOCK "miv_rv32_icache_ram_mux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_pkg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_tcm_tas_apb_target::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "miv_rv32_subsys_udma::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_CCC_0::work","component\work\PF_CCC_0\PF_CCC_0.v","TRUE","FALSE"
|
|
SUBBLOCK "PF_CCC_0_PF_CCC_0_0_PF_CCC::work","component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_CCC_0_PF_CCC_0_0_PF_CCC::work","component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "pf_init_monitor_0::work","component\work\pf_init_monitor_0\pf_init_monitor_0.v","TRUE","FALSE"
|
|
SUBBLOCK "pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR::work","component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR::work","component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "CORECDR4_CNTL_TIP::work","component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL::work","component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL::work","component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC::work","component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC::work","component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_CCC_C0::work","component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "COREDELAYCODE_TIP::work","component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC::work","component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV::work","component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL::work","component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC::work","component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV::work","component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL::work","component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v","FALSE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC::work","component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC::work","component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_TPSRAM_C0::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "pmc_logic_mux_behav::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "pmc_sync_flop_behav_v3::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "RAM_BIST_ERROR:ASIC_view_does_not_exist_in_miv_rv32_dpr_hqa_dual_storage_rbcw::work","","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "SSDetect::work","hdl\SSDetect.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "top::work","component\work\top\top.v","TRUE","FALSE"
|
|
SUBBLOCK "COREFIFO_C0::work","component\work\COREFIFO_C0\COREFIFO_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "COREJTAGDEBUG_C0::work","component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "CORESPI_0::work","component\work\CORESPI_0\CORESPI_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CORETSE_0::work","component\work\CORETSE_0\CORETSE_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CoreAPB3_0::work","component\work\CoreAPB3_0\CoreAPB3_0.v","TRUE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0::work","component\work\CoreUARTapb_0\CoreUARTapb_0.v","TRUE","FALSE"
|
|
SUBBLOCK "Core_reset_pf::work","component\work\Core_reset_pf\Core_reset_pf.v","TRUE","FALSE"
|
|
SUBBLOCK "MIV_RV32_C0::work","component\work\MIV_RV32_C0\MIV_RV32_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "PF_CCC_0::work","component\work\PF_CCC_0\PF_CCC_0.v","TRUE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_C0::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "PF_IOD_CDR_CCC_C0::work","component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "PF_TPSRAM_C0::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v","TRUE","FALSE"
|
|
SUBBLOCK "SSDetect::work","hdl\SSDetect.v","FALSE","FALSE"
|
|
SUBBLOCK "fifo_to_tpsram_bridge::work","hdl\fifo_to_tpsram_bridge.v","FALSE","FALSE"
|
|
SUBBLOCK "pf_init_monitor_0::work","component\work\pf_init_monitor_0\pf_init_monitor_0.v","TRUE","FALSE"
|
|
ENDLIST
|
|
LIST "clock_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "corereset_pf_tb::work","component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v","FALSE","TRUE"
|
|
SUBBLOCK "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work","component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CoreTSE_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
|
SUBBLOCK "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
SUBBLOCK "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBL::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBLAPB::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBSLAVE::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBSLAVEEXT::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APB2APB::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APBSLAVE::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APBSLAVEEXT::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APBSLAVEEXT::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreTSE_AXI4S_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
SUBBLOCK "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
SUBBLOCK "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBSLAVEEXT::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APB::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "fifo_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "fifo_monitor::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "g4_dp_ext_mem::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v","FALSE","TRUE"
|
|
SUBBLOCK "MEM_WgtR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v","FALSE","TRUE"
|
|
SUBBLOCK "MEM_WltR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v","FALSE","TRUE"
|
|
SUBBLOCK "MEM_WeqR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "MEM_WeqR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "MEM_WgtR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "MEM_WltR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "testbench::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v","FALSE","TRUE"
|
|
SUBBLOCK "CORETSE::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreTSE_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreTSE_AXI4S_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "testbench::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
|
|
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
|
|
SUBBLOCK "clock_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v","FALSE","TRUE"
|
|
SUBBLOCK "fifo_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v","FALSE","TRUE"
|
|
SUBBLOCK "fifo_monitor::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v","FALSE","TRUE"
|
|
SUBBLOCK "g4_dp_ext_mem::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "testbench::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v","FALSE","FALSE"
|
|
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APB::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
|
|
SUBBLOCK "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v","FALSE","FALSE"
|
|
SUBBLOCK "coreapb3_iaddr_reg::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "coreapb3_iaddr_reg::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREAPB3_MUXPTOB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREAPB3_BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
|
SUBBLOCK "COREAPB3_BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
SUBBLOCK "COREAPB3_BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREAPB3_BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
|
|
SUBBLOCK "COREAPB3_BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREAPB3_BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREAPB3_BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREAPB3_BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "testbench::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
|
|
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v","FALSE","FALSE"
|
|
SUBBLOCK "COREAPB3_BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
|
SUBBLOCK "COREAPB3_BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v","FALSE","FALSE"
|
|
SUBBLOCK "COREJTAGDEBUG_UJ_JTAG::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v","FALSE","FALSE"
|
|
SUBBLOCK "UJTAG_WRAPPER::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v","FALSE","FALSE"
|
|
SUBBLOCK "corejtagdebug_bufd::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "corejtagdebug_bufd::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG_UJ_JTAG::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v","FALSE","FALSE"
|
|
SUBBLOCK "corejtagdebug_bufd::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "corejtagdebug_bufd::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "UJTAG_WRAPPER::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG_HOST_EMULATOR::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "COREJTAGDEBUG_JTAG_TAP::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CORESPI::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v","FALSE","FALSE"
|
|
SUBBLOCK "spi::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "spi::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v","FALSE","FALSE"
|
|
SUBBLOCK "spi_chanctrl::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v","FALSE","FALSE"
|
|
SUBBLOCK "spi_fifo::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v","FALSE","FALSE"
|
|
SUBBLOCK "spi_rf::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v","FALSE","FALSE"
|
|
SUBBLOCK "spi_control::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v","FALSE","FALSE"
|
|
SUBBLOCK "spi_control::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "spi_chanctrl::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v","FALSE","FALSE"
|
|
SUBBLOCK "spi_clockmux::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "spi_fifo::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "spi_rf::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "spi_clockmux::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "spi_control::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "CORESPI_BFM_AHB2APB::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CORESPI_BFM_APB::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
|
SUBBLOCK "CORESPI_BFM_AHB2APB::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
|
SUBBLOCK "CORESPI_BFM_MAIN::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "CORESPI_BFM_MAIN::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
|
ENDLIST
|
|
LIST "spi_control::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v","FALSE","FALSE"
|
|
ENDLIST
|
|
LIST "testbench::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
|
|
SUBBLOCK "CORESPI::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v","FALSE","FALSE"
|
|
SUBBLOCK "CORESPI_BFM_APB::CORESPI_LIB","component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
|
ENDLIST
|
|
ENDLIST
|
|
LIST ActiveTestBenchList
|
|
ENDLIST
|
|
LIST IOTabList
|
|
VALUE "constraint\io\io_constraints.pdc"
|
|
ENDLIST
|
|
LIST FPTabList
|
|
ENDLIST
|
|
LIST TimingTabList
|
|
VALUE "constraint\top_derived_constraints.sdc"
|
|
VALUE "constraint\timing_user_constraints.sdc"
|
|
ENDLIST
|
|
LIST FDCTabList
|
|
ENDLIST
|