E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe  -prodtype  synplify_pro  -encrypt  -pro  -rundir  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis  -sap  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap  -otap  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.tap  -omap  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.map   -part MPF300T  -package FCG1152  -grade -1    -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0  -top_level_module  top  -implementation  synthesis  -licensetype  synplifypro_actel  -flow mapping  -mp  4  -prjfile  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs  -multisrs  -ovm  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm   -freq 100.000   -tcl  E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd  -devicelib  E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v  -ologparam  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg  -osyn  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srm  -prjdir  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\  -prjname  top_syn  -log  E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr  -sn  2023.09  -jobname  "fpga_mapper" 
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -sap ..\top.sap -otap ..\top.tap -omap ..\top.map -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_fpga_mapper.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -licensetype synplifypro_actel -flow mapping -mp 4 -prjfile ..\scratchproject.prs -multisrs -ovm ..\top.vm -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_prem.srd -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\top.srm -prjdir ..\ -prjname top_syn -log ..\synlog\top_fpga_mapper.srr -sn 2023.09 -jobname "fpga_mapper"
rc:1 success:1 runtime:236
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
file:..\top.tap|io:o|time:0|size:-1|exec:0|csum:
file:..\top.map|io:o|time:1776273723|size:28|exec:0|csum:
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\top.vm|io:o|time:1776273719|size:6264001|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_prem.srd|io:i|time:1776273483|size:1522539|exec:0|csum:DB252AC6E8654F85B7F9005EEC2CBE52
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273723|size:4727|exec:0|csum:
file:..\top.srm|io:o|time:1776273714|size:28753|exec:0|csum:
file:..\synlog\top_fpga_mapper.srr|io:o|time:1776273723|size:628611|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6