Project Settings
Project Name top_syn Device Name synthesis: Microchip PolarFire : MPF300T
Implementation Name synthesis Top Module top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 236 403 0 - 04m:18s - 4/17/2026
8:31 AM
(premap)Complete 64 15 0 0m:15s 0m:15s 366MB 4/17/2026
8:31 AM
(fpga_mapper)Complete 102 120 0 03m:58s 04m:02s 564MB 4/17/2026
8:36 AM
Multi-srs Generator Complete00m:03s4/17/2026
8:31 AM

Area Summary
Carry Cells 2263 Sequential Cells 7208
DSP Blocks (dsp_used) 0 I/O Cells 50
Global Clock Buffers 7 RAM1K20 (v_ram) 36
RAM64x12 (v_ram) 11 LUTs (total_luts) 15852

Timing Summary
Clock NameReq FreqEst FreqSlack
COREJTAGDEBUG_Z5|iUDRCK_inferred_clock100.0 MHz13.4 MHz-32.246
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT080.0 MHz55.1 MHz-5.638
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R125.0 MHz116.7 MHz-0.228
PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop100.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV125.0 MHz225.1 MHz3.557
PHY_MDC_CLOCK2.9 MHzNANA
REFCLK_P125.0 MHzNANA
REF_CLK_050.0 MHzNANA
TCK10.0 MHzNANA
System100.0 MHz26.5 MHz-27.793