# Microchip NMAT TXT File

# Version: 2025.1 2025.1.0.14

# Design Name: top 

# Input Netlist Format: EDIF 

# Family: PolarFire , Die: MPF300TS , Package: FCG1152 , Speed grade: -1 

# Date generated: Fri Apr 17 08:49:04 2026 


#
# I/O constraints
#

set_io LINK_OK D25
set_io PHY_MDC Y12
set_io PHY_MDIO Y13
set_io PHY_RST U11
set_io RD_BC_ERROR F22
set_io REFCLK_N U5
set_io REFCLK_P U4
set_io REF_CLK_0 E25
set_io REF_CLK_SEL AA10
set_io RESET_N K22
set_io RX H18
set_io RX_N U1
set_io RX_P U2
set_io R_DATA[0] AH9
set_io R_DATA[1] AJ9
set_io R_DATA[2] AK8
set_io R_DATA[3] AK5
set_io R_DATA[4] AK7
set_io R_DATA[5] AH8
set_io R_DATA[6] AJ5
set_io R_DATA[7] AH6
set_io R_DATA[8] AG9
set_io R_DATA[9] AF13
set_io R_DATA[10] AF10
set_io R_DATA[11] AG10
set_io R_DATA[12] AE13
set_io R_DATA[13] AF8
set_io R_DATA[14] AF9
set_io R_DATA[15] AE10
set_io R_DATA[16] AJ8
set_io R_DATA[17] AE11
set_io R_DATA[18] AD14
set_io R_DATA[19] AD13
set_io R_DATA[20] AJ6
set_io R_DATA[21] AD10
set_io R_DATA[22] AH7
set_io R_DATA[23] AD11
set_io R_DATA[24] AF12
set_io R_DATA[25] AE12
set_io R_DATA[26] AE8
set_io R_DATA[27] AG6
set_io R_DATA[28] AG7
set_io R_DATA[29] AE7
set_io R_DATA[30] AD6
set_io R_DATA[31] AF7
set_io SPISCLKO K21
set_io SPISDI L20
set_io SPISDO K20
set_io SPISS J20
set_io TX G17
set_io TX_N V2
set_io TX_P V1
set_io coma_mode U12

#
# Core cell constraints
#

set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[1] 697 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[4] 713 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[10] 564 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IO1Oo_0[0] 200 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_4 431 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_int_sn_m7 810 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[17] 467 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[7] 710 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1151 814 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lI0i1_0_0 296 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[9] 785 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[0] 464 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[5] 133 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_119 790 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[1] 398 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iiiI1 437 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[1] 725 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[12] 877 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0[1] 724 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[2] 397 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[8] 733 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[15] 892 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[6] 321 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[7] 207 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[5] 379 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01_0_sqmuxa_0 164 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m[7] 848 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[2] 472 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[5] 281 187
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[20] 83 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_15 695 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[2] 155 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[23] 619 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIio1_RNO 95 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[0] 502 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_470 760 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2[8] 113 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[38] 958 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_820 754 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1111 72 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[16] 299 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNIKCAA3[15] 654 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[6] 635 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[21] 846 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex[0] 728 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[26] 714 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt[2] 601 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[5] 673 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1166 640 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[1] 740 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iii11 349 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[30] 516 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0_RNO_0 790 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[1] 359 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[0] 715 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[2] 478 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] 521 214
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO[3] 558 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_301 724 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[2] 353 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_306 712 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_m3[0] 670 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[18] 909 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[13] 315 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_RNIF8OSC3 775 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_2[4] 849 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[10] 971 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[3] 859 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[6] 164 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIJ5GUI[8] 887 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_iII01 361 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb7_i_o3 767 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[6] 169 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_shift_op_completing_ex 784 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[3] 371 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[15] 796 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[2] 707 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[9] 844 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIRD2R7[14] 75 195
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[0] 35 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_52[11] 384 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[21] 525 184
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2[0] 486 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[8] 391 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_518 766 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[0] 350 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[4] 223 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utimeh_sw_rd_sel 817 144
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0 20 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[12] 720 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_masked_2[1] 779 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oiOo1 184 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[26] 473 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911 698 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1247 685 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_4_0[0] 835 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[36] 720 127
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_rxfifo_5 602 192
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[2] 33 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4957 702 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001 201 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[1] 404 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_642 704 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[18] 724 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[6] 138 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[8] 237 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_547 711 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[6] 216 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[8] 191 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[12] 123 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sba_rd_req_cmb_1 810 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[21] 995 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[6] 418 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un86_OilI1[17] 413 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[9] 247 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[39] 394 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[1] 239 225
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_13_iv_i[1] 571 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliOo_6 212 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[3] 483 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_4_RNI7JRPJO3 800 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[3] 514 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m10 34 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[5] 345 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[20] 732 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[7] 232 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[4] 440 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/IilI1 349 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[27] 869 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Oio01 108 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/OloIo 522 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_trap_ret_ex_2 836 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[8] 311 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/un1_iOI01_1_i_0 327 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[25] 465 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_o0I01_5_1.CO1 300 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_24 735 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l1I01_2 383 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[4] 477 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2[13] 238 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[10] 325 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2[1] 353 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[8] 429 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[22] 467 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[39] 731 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[9] 442 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[17] 55 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/PRDDATA[4] 573 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_3 819 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[10] 311 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[2] 474 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[13] 129 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1[1] 894 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[16] 383 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_4_RNI4IU79 432 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[30] 517 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[4] 241 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[17] 212 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[26] 680 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[2] 534 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[10] 849 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[15] 356 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Oili1 334 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0 793 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI78M4E[9] 512 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[29] 686 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[12] 380 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[7] 392 232
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO[7] 46 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0Oo_1 320 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[0] 329 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_RNO[0] 752 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[32] 643 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i_0 718 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_32 658 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[7] 298 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_2_1 55 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[8] 489 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[18] 275 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[2] 409 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1lto7 28 192
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_o2[0] 517 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[25] 452 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[13] 909 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[18] 540 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz_1[0] 659 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[2] 281 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_4 312 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OioOo_2 244 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_resumeack 827 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo[7] 213 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[1] 421 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_1[1] 818 126
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[4] 24 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[20] 895 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[17] 859 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[23] 913 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m17_2_0_1 119 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI6AA84[20] 924 192
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[1] 537 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[57] 962 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[24] 400 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m12_0 260 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m67 143 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[25] 394 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[2] 383 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[11] 558 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[24] 444 220
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sellto7_2_0 30 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un24_oIiOo_1.CO3 276 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[27] 897 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1139 753 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[30] 695 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[3] 315 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[9] 227 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[1] 193 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_12_0[0] 782 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[3] 852 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[56] 635 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un179_I1Oi1 71 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0_RNI1GLK5 611 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132_RNIPQTN7 663 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[5] 520 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_393 646 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[5] 344 238
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv[5] 602 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIARI09 781 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[8] 533 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[33] 471 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_OIiOo_5 288 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l1oo1 83 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[5] 215 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[18] 838 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1li1_0_a2 328 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2_0[3] 166 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[3] 863 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15_5 257 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_0[3] 290 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[0] 598 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_665 693 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_3_RNI09IF31 851 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_lOoi1_1 313 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_read_gpr_rs1_ex.gen_rs1_exu_stall.un7_gpr_rs1_stall_exu_NE_3 729 153
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[23].BUFD_BLK 631 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI7PFUI[2] 890 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4[1] 191 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[5] 230 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/wtrst_1 498 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_926 796 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[14] 250 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[9] 373 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[9] 263 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[12] 914 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIFP0P9[8] 80 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[11] 492 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[8] 321 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[6] 384 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[15] 314 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_0 787 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[7] 247 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[23] 552 177
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[8] 24 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un131_I1Oi1_1 70 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[2] 541 169
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[9] 466 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[15] 907 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[9] 298 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[20] 923 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[28] 389 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[1] 332 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m2_0_a2_7_0 791 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1185 719 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[21] 685 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[2] 149 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[5] 99 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[0] 205 201
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA28 572 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[10] 842 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_rd_op_ex 790 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[4] 417 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2[32] 398 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/un4_update_dout_1_0 503 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_0 712 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/m_env_call_retr 746 147
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[18].BUFD_BLK 635 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[5] 553 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[8] 238 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[22] 866 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[9] 443 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[1] 315 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[6] 426 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[4] 484 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OI1I1 394 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/IilI1 372 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[17] 444 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[4] 442 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[25] 667 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI586GO[10] 882 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[3] 249 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_680 670 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[24] 60 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[2] 262 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[21] 499 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[9] 715 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNILI1DG[0] 818 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01 592 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2125_0_0 671 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[15] 498 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[19] 905 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m3 611 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1282 646 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[1] 197 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1_RNIKGARAL1 792 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[8] 59 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][27] 884 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_488 622 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[12] 908 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/empty_out_RNO 571 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/illegal_instr_retr 747 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[14] 364 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[7] 430 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_5[13] 712 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[8] 337 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[21] 457 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[9] 359 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[13] 372 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[0] 40 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0[0] 146 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_1_sqmuxa_i 11 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[22] 918 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[12] 433 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_e_2 643 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[29] 947 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiO1 237 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[9] 600 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1170 742 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0[15] 345 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m37 167 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[11] 782 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[13] 335 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[24] 447 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[13] 414 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[13] 708 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[3] 728 150
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write_8.m5_2_0 513 159
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[25] 483 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_m2 722 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_8[5] 350 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[6] 196 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[0] 382 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[11] 441 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[0] 325 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.m4_1_0 98 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_3_3[0] 827 120
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[0] 544 169
set_location coma_mode_obuf_RNO 141 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_39_0_a2 671 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[25] 244 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1[0] 94 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liOOo 126 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[2] 201 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un37_lolIo 59 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[0].BUFD_BLK 609 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[57] 844 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_27[3] 573 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[3] 314 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5_2[2] 201 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[15] 831 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2[10] 766 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[17] 372 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[7] 694 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_7 833 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[11] 887 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[7] 853 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iolOo[0] 225 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOo01_i_a2_0_0_0 115 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNICGA84[26] 931 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[3] 327 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[2] 620 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[17] 702 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[9] 212 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m14 783 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[8] 295 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[7] 71 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[25] 544 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[9] 368 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_453 796 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O1lIo_1_0_.m11 120 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un60_OIoO1 96 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftIR_ne_0 653 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/abstractcs_cmderr_cmb_0_sqmuxa_i_RNILV1N9 850 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1[0] 74 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2[1] 468 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[12] 498 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4951_3 696 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto10 227 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[7] 371 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[27] 882 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[23] 672 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[7] 177 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[12] 537 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[15] 899 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_s[6] 568 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_611 741 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[7] 410 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[5] 478 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_0_sqmuxa_i_x4_RNI0KISI 179 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[20] 740 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[3] 537 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_495 737 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[4] 402 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[8] 928 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[28] 798 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IlOo1_0 334 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[28] 904 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_675 670 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_2 814 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oooo1_0 83 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[14] 925 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_2_0 775 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[19] 366 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[18] 453 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_3 839 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[1] 303 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv_0[7] 690 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[1] 947 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[22] 547 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1022 669 195
set_location fifo_to_tpsram_bridge_0/buffer_full6_6 481 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1_3 77 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv[1] 834 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1[1] 187 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIBE6GO[13] 866 153
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un2_we_i_1 494 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_826 790 207
set_location fifo_to_tpsram_bridge_0/state_RNO[0] 469 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/un1_iOI01_1_i_0 407 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[11] 123 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val_RNI7LT92[0] 634 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a2_0[2] 767 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1077 772 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[6] 573 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[36] 813 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_7_RNO_1 812 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_0[3] 138 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un71_I1Oi1_2 47 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[8] 983 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un7_Iiii1 143 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0[0] 683 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[27] 847 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[14] 163 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m48_i_o3 143 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOOOo_2 119 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNISUR5C[23] 714 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[27] 786 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[45] 591 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[1] 304 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1[4] 138 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6] 643 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_de_ex.de_ex_pipe_trigger_ex[0] 744 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[30] 234 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[12] 805 130
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10_0 593 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[4] 850 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[0] 629 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_c_c 803 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un10_buff_resp_head_compressed 731 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m8 107 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_ex_2_1 740 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_217 618 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[2] 498 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[2] 262 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[20] 716 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[3] 256 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNIJAVNRK3 775 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_3_RNI5HQPJO3 792 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[22] 268 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[29] 833 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[6] 737 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[13] 93 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[8] 840 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oloo1_RNO 84 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[7] 838 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/un1_iOI01_1_i_0 331 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_225 754 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[22] 313 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[13] 616 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[23] 336 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m212 355 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oliO1 324 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[30] 517 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[22] 158 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[0] 606 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1_1 320 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_4 458 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[8] 290 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[1] 506 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.debug_mode6 747 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/dealloc_resp_buff_10 813 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[0].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/gen_bit_no_reset.state_val[0] 783 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1_RNI913KJ1 809 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[5] 514 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[6] 58 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_2 610 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[24] 946 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_rd_ptr_0[0] 786 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_38 761 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_str_ex 710 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_o2_2 347 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[0] 603 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[9] 146 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[2] 719 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[14] 418 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_2 383 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[4] 406 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[1] 489 220
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO[4] 621 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[8] 882 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[14] 99 187
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[6] 497 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOli1_9 275 168
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[16].BUFD_BLK 575 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1[4] 419 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][22] 874 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOio1 98 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[3] 180 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m268 374 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[6] 438 184
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[3] 39 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[27] 900 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.IloIo 522 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O01i1_i_a3 314 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[1] 364 235
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/make_parity_err.parity_err15 514 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[43] 386 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_894 665 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[29] 69 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[9] 205 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_retr_0_0_0 801 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[5] 735 151
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_2 430 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[1] 284 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[6] 485 220
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_6 443 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[6] 333 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_812 787 186
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[20] 58 229
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_0_sqmuxa_2 45 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19 86 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[56] 600 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[0] 684 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[22] 845 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m10 23 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr4 836 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[8] 140 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_759 760 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lO1o1 104 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[6] 260 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[8] 175 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/gen_bit_reset.state_val_12_u[0] 848 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[8] 339 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[13] 167 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[12] 604 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_m2_2[1] 155 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2_0[0] 826 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[61] 979 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[4] 397 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_taken_a1_0_RNIG66O8 794 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ii1Oo 222 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[24] 310 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIoo1_RNO 85 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_2_i_a2_0_2[1] 820 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3[1] 23 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_i0oo1_tz_0 67 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[8] 383 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_resume_req 785 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i_1 826 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_1_a0 781 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[8] 895 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_263 693 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1[0] 503 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_160 645 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[22] 935 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[14] 281 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel[2] 600 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/cause_excpt_code_excpt[1] 783 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[10] 567 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846_RNI1MMDF 724 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[20] 526 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/un1_iOI01_1_i_0 347 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I0I01 321 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_2_i 768 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[4] 201 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[17] 359 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[8] 190 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2123_2_s4_1 668 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[3] 446 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_RNIT3VA9 189 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_ptr[0] 806 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[28] 732 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un10_l1ll1_8 439 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m14 259 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[5] 355 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2 849 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m26 166 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[6] 886 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[3] 190 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0[7] 123 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lOo11 301 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/un1_iOI01_1_i_0 267 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[15] 263 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1 266 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_resp_valid_rd_s 775 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_c_1 794 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_998 789 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[29] 663 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39[3] 369 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo[4] 277 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[0] 331 166
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[5] 15 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[6] 368 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lI1I1[0] 471 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJDVQ8[30] 785 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[0] 431 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iI1Oo[0] 204 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[4] 230 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[3] 281 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4917_3 683 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_10_0_o2 251 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[19] 731 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[34] 942 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[8] 345 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[4] 143 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_37 683 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[4] 413 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[19] 899 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[4] 650 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loOOo 129 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_3 385 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[20] 983 171
set_location CoreAPB3_0_0/CoreAPB3_0_0/iPSELS[1] 595 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[5] 667 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[15] 720 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O0iI1 510 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4[6] 158 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[5] 875 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[1] 262 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m10 79 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[24] 754 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[6] 350 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[2] 144 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNIOQ2K92 179 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[0] 272 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[9] 491 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_8[11] 299 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_10[11] 341 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/extract_os_i_loop_l1.un12_req_os_i_src[0] 786 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[16] 215 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIQF7VA[10] 664 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[0] 191 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtm_resp_ready 694 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[7] 265 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[6] 132 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[15] 923 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_1 47 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[15] 971 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0IIo 334 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_791 704 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[10] 414 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[26] 887 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[22] 917 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[33] 719 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[14] 493 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[1] 561 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[0] 680 130
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count[3] 525 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[29] 915 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[1] 215 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.fifo_reset 693 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[7] 710 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_u_1 781 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_14_RNO 875 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[13] 513 193
set_location SSDetect_0/rx_start[1] 16 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_16_RNO 880 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_459 717 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[10] 65 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[28] 922 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[24] 618 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[26] 830 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[1] 736 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_697 778 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[1] 947 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u[3] 952 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[9] 850 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_796 667 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_valid_0 803 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/un1_iOI01_1_i_0 330 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_de_ex.de_ex_pipe_trigger_ex[1] 752 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftBP_ne_0_3 649 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[16] 706 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_512 716 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[51] 236 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[14] 236 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr[1] 831 157
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples[1] 525 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5[1] 182 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12 646 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_951 760 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IiOo1_2 298 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].un1_lsu_flush 756 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[36] 937 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[16] 774 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_sn_m7 850 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001_RNO[1] 170 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12] 674 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[6] 380 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4] 695 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[25] 733 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1i11_2 348 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[5] 719 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[3] 401 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[6] 521 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[6] 222 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un20_emi_req_os_at_flush_RNO[1] 789 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_o17_2 705 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[5] 711 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[6] 311 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[31] 911 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_4 777 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[7] 818 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1OOo 134 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/wr_en_data_or 863 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un139_i11Io 508 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][8] 887 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[21] 610 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[34] 716 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[2] 267 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[1] 187 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1179 766 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un6_I1ii1_0_a2 142 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[20] 454 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[5] 494 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[16] 291 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[6] 328 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_7[0] 227 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIIo[0] 273 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2_RNO[22] 859 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_364 692 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[15] 712 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[16] 597 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[0] 331 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto3 244 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I11l1 480 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_273 736 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIRHRQ8[16] 775 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_0[17] 682 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[17] 935 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[26] 756 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[13] 596 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O11l1 481 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_337 706 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[29] 810 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_170 730 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[18] 684 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[1] 145 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[25] 939 189
set_location fifo_to_tpsram_bridge_0/next_state11_22 489 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[9] 179 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[6] 94 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[14] 995 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m30_2_1 47 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m_0_3_1[0] 815 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_1_140_a2 286 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1255 727 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1196 777 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo_RNO[1] 151 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite_5_0_0_127_i_a2_i_a2_1 684 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_1_N_5L8 735 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[15] 129 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[22] 736 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[9] 215 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_116 776 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/force_debug_nop_de 755 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_888 724 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1116 682 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[7] 338 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22[8] 406 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[12] 678 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I1io1 64 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[7] 188 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[6] 255 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z[1] 238 214
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[11] 62 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I01i1 312 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1_RNO[15] 502 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_1 681 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[6] 59 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[21] 987 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/iII01 367 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0_1_0[0] 267 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O0lI1 516 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_ready_reg_RNO 743 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m183 347 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_28_u[31] 970 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5[5] 126 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_15[9] 287 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[13] 274 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_23_RNO_0 947 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[23] 970 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[9] 853 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readonaddr_ff 761 118
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_7 766 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[13] 71 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4[0] 609 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Olio1 66 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/gen_bit_reset.state_val[0] 848 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_5 658 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[8] 741 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr[3] 801 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un11_oioOo 205 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[23] 940 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[11] 775 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_50 767 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un75_I1Oi1_0 46 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0 760 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_5 317 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[33] 714 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI93FGI[2] 510 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO_1[1] 824 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[49] 948 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a7_4_RNIF9BRG[0] 149 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[11] 720 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[40] 597 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[11] 621 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[33] 729 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ilii1 145 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[22] 913 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[17] 261 208
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[15] 487 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[6] 247 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1[19] 324 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[17] 736 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[2] 88 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_o2_1 114 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/genblk1.rst_synch_reg[1] 696 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[8] 209 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[8] 202 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/alu_op_sel_1_iv_0_RNO[1] 719 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[10] 923 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[12] 538 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[23] 886 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[31] 839 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[11] 393 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_7 85 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[7] 178 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[19] 733 132
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0_1 1742 5
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite 687 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[12] 255 199
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_1_sqmuxa_2 44 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[6] 194 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[3] 87 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[14] 289 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[0] 79 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.lloIo 507 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0_RNI6OE601 788 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[5] 192 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[27] 971 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_43[10] 357 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 304 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[4] 770 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[9] 427 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[22] 447 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[10] 482 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid46_1 718 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][12] 900 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[4] 436 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM[1] 172 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[25] 890 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[15] 93 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_4 777 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write8 507 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[8] 322 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[11] 298 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo51_RNI3DGUB5 54 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[15] 720 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_lliOo_1.CO1_1 278 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[2] 410 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_ex_2_1_RNIEDMV8U3 768 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[4] 85 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[15] 691 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[5] 419 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[30] 864 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_11_RNO 814 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[1] 515 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[15] 878 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[2] 714 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[9] 359 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[15] 837 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m3 804 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_11_RNO 464 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[28] 746 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd 737 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[3] 386 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[6] 930 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2[1] 729 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_299 765 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_281 682 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_441 813 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[57] 616 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[12] 258 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un3_IOIOo 136 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_742 777 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[11] 251 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[24] 444 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[14] 237 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/gen_bit_reset.state_val_RNO[0] 866 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[15] 756 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOoOo_0 232 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[14] 245 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_1_3 336 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/olli1 252 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[20] 414 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[23] 909 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2_1[8] 372 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[24] 923 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[11] 58 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[0] 344 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[3] 139 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[10] 212 169
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txready_at_ssel 591 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_374 775 213
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3_1[1] 34 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[13] 499 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[22] 925 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[6] 423 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[3] 878 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un83_I1Oi1_1 50 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[19] 738 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[12] 539 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[27] 712 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/clear_parity_en_1_sqmuxa 493 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_2_1 720 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_183 666 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_il0Oo 230 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo[5] 281 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_o1oOo_0 234 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2 210 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[2] 203 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/loIO1[8] 117 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[27] 865 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[8] 129 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIBTFUI[4] 871 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[11] 462 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[15] 67 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[25] 893 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[5] 133 193
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state137 611 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_29[2] 407 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[9] 131 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[0] 283 217
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_1[0] 623 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[14] 889 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_o2_2_1 95 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_48 887 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[5] 857 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[25] 394 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[6] 62 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[13] 459 193
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_16 513 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1146 676 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[17] 854 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_2_RNO 826 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[16] 890 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[35] 335 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OIi11 453 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[25] 614 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[9] 369 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[21] 848 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[16] 418 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[0] 431 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[30].BUFD_BLK 621 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1039 742 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m21_1 178 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[30] 983 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[13] 434 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[4] 554 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[6] 132 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_hword_high_only_u_i_m2_1_0 876 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[4] 949 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39[7] 370 231
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc2 23 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m5 33 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[6] 745 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31_1[16] 982 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[0] 525 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_10 723 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid38_1_1 759 144
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[1] 35 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i[1] 166 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un59_ool01 203 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[3] 214 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un18_lsu_op_str_ex_2 718 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_390 707 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[7] 356 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[12] 327 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[27] 853 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_307 736 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_1 274 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[1] 309 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[12] 728 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_5 319 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[6] 418 205
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[0] 47 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[2] 517 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[2] 590 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[16] 866 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[10] 287 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1287 741 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[21] 711 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[25] 745 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OOIOo_RNIKB7HO 138 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[28] 783 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_1 187 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo[1] 186 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m7 131 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oiil1 496 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3_1[5] 135 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[13] 899 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_626 778 192
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2[1] 480 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliO1 232 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[16] 618 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dpc_debugger_rd_sel 837 144
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo 606 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[11] 501 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns[5] 537 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[29] 958 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_4 559 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[7] 501 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un179_I1Oi1_1 69 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3[5] 553 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[14] 347 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846 660 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_6_RNO 24 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[3] 201 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u[8] 982 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_d_1_sqmuxa_2 555 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[18] 469 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.haltreq_debug_enter_pending6 782 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_34 646 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m271 382 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_4[15] 111 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[11] 848 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oIol1 435 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[8] 232 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[14] 220 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0[4] 156 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[9] 454 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[7] 71 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[18] 440 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a4[2] 682 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[4] 217 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_trx_os_d_wr_6_i_i_a2 745 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_a0 857 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[8] 371 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1iO1 295 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[11] 193 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[0] 399 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[6] 407 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[10] 345 196
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[11] 504 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[4] 458 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/tdo_0 656 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_910 652 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_129 759 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[2] 364 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[27] 445 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[17] 769 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un14_oO1Oo_5 239 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.CO1 20 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0_0_RNITU5E381_0 773 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[0] 210 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_3_0 771 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[0] 721 154
set_location fifo_to_tpsram_bridge_0/state[0] 469 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_axb_31_1 947 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_195 742 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO[3] 606 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[22] 811 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[31] 751 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[30] 689 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[7] 345 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[5] 426 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[2] 194 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un165_I1Oi1 59 210
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_7 6 164
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_0[6] 287 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[5] 343 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_m_0[4] 693 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[20] 590 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[20] 519 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[12] 851 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[0] 723 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[4] 326 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[0] 438 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111_2 264 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_45[5] 604 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3[0] 779 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[27] 362 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[7] 588 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[11] 494 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[13] 709 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lilIo54_1_0 137 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_1_RNO_0 810 150
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[31] 480 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[2] 772 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[0] 231 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[11] 557 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_414 725 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[13] 828 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIGMUT5 413 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[10] 447 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[2] 487 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[3] 555 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[6] 856 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[9] 431 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[27] 445 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[11] 390 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_0_sqmuxa 704 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[38] 238 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[1] 153 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0_a2_0 117 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[28] 872 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_O1Ii1_4 418 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op[0] 716 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[15] 735 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[5] 214 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[31] 491 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[5] 716 136
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples[0] 522 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_I00Oo_4 248 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[6] 887 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[7] 112 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_682 658 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[0] 62 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[9] 549 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[18] 911 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[7] 841 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[13] 259 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[0] 71 189
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[29] 468 243
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2[2] 487 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[5] 279 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/I0lo1 378 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[15] 545 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_2 771 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_2_i 603 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_587 825 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0_a2_0 178 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[8] 498 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_528 795 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_2[2] 179 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2[17] 190 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[15] 362 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[10] 466 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[21] 392 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[2] 422 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[31] 476 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[17].BUFD_BLK 634 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_ptr[0] 703 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[10] 536 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[13] 312 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[0] 823 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[11] 118 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[7] 496 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_31_RNI01RTHF 807 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[19] 262 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[3] 766 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[6] 221 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_sn_m2 882 141
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[8] 513 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[17] 836 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3 866 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_4 688 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_4[4] 152 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[22] 755 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[4] 209 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[9] 199 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un7_IoOOo_0 121 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[32] 235 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[17] 757 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[18] 959 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[3] 410 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_1_RNO_1 813 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[10] 320 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[29] 483 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_955 703 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[16] 732 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[8] 351 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_pktsel 596 211
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[4] 473 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[15] 733 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[20] 840 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO 333 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[13] 177 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[5] 250 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz_0_1[0] 658 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[8] 915 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[6] 461 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[28] 869 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[6] 277 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[6] 414 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mstatus_sw_rd_sel_1 838 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_550 692 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[6] 261 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[3] 155 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[5] 850 147
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[25] 63 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[3] 213 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI69S5C[28] 722 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[11] 605 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[21] 994 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[12] 461 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[21] 850 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[13] 590 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO[2] 419 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iIIi1_2_tz 317 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa_RNI98ALL 725 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[7] 125 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel 591 211
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1 500 159
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[8] 40 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[16] 896 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[0] 445 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv[0] 721 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[10] 550 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1_0 605 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_2[7] 383 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2[3] 182 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[27] 723 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m21 130 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14 521 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[9] 700 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[15] 551 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[40] 387 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state[2] 552 211
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[6] 22 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[4] 89 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[13] 550 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[24] 902 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[13] 177 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[11] 912 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_o2_1_0_o2[15] 273 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de_s_0_RNO 803 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[24] 838 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[26] 430 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[26] 738 136
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_dataerr 570 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_a0_1 804 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[1] 731 154
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc4 47 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[7] 862 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[8] 292 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[20] 755 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[0] 264 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[2] 195 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[19] 713 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[5] 556 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[13] 226 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[5] 310 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0li1_RNO 229 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_branch_cond_1[0] 740 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[12] 761 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[11] 733 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[3] 419 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff[0] 837 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[4] 346 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[20] 386 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_dbreak_ex 755 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[24] 472 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[10] 419 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_569 670 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Io0l1[0] 492 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_olio1_2 91 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[3] 302 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0_RNIF52NJ6 756 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[21] 935 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[12] 718 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_o3_3 695 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[14] 70 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_0_sqmuxa_4 575 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2123 669 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[0] 765 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[1] 510 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[10] 459 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[42] 566 175
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[16] 79 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[1] 409 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[15] 129 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[18] 716 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.step_debug_enter_pending6 762 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[14] 361 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[11] 726 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m14 129 213
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[2] 15 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[8] 888 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_exce[0] 758 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_0[5] 284 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0_0_RNIDR6AE 761 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1135 776 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[26] 995 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[4] 165 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[3] 718 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1 284 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOoI1 406 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[4] 102 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un55_Oo1Io 491 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[8] 185 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[11] 422 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[4] 77 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un25_ool01[8] 191 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_9_u_2[7] 498 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[1] 70 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m45 166 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[31] 679 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loI11_Z 350 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[0] 347 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[5] 867 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_26[4] 355 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1oO1_0_1 250 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[12] 536 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/IilI1 361 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[5] 369 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[28] 117 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_RNO_0 804 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIo01_i_x2 116 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_0 590 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[1] 294 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[5] 208 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[14] 994 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[17] 616 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un368_lIlo1 313 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un30_lIlo1lto5_0 248 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[7] 829 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[14] 902 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un5_UTDO 610 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un117_I1Oi1 41 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/un1_iOI01_1_i_0 265 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[28] 499 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_olio1 94 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2119_1_RNO 670 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[3] 118 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[14] 285 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1232 670 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0_1[31] 888 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[30] 807 127
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[9] 31 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_4 774 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[18] 754 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[18] 862 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[11] 59 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1220 790 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[2] 474 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOI11_0_a3_RNIFORSC 120 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[10] 115 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[5] 623 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2 779 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[33] 627 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_335 724 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op[2] 738 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[8] 390 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[7] 501 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[6] 47 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[10] 1004 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[31] 708 210
set_location fifo_to_tpsram_bridge_0/next_state11_17 512 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_datas2 765 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[7] 303 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[10] 278 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i1oo1 101 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[8] 859 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2[7] 287 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0oo1 93 202
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag 20 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[15] 262 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_valid_u 799 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oill1 466 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[21] 459 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2[1] 839 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_765 754 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[22] 158 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[2] 710 154
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int_0_sqmuxa_0_a2_2 520 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1 406 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[18] 216 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[12] 530 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/oo1Io_0 338 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO[3] 263 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[14] 407 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[23] 417 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_csr_complete_retr 813 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/soft_reset_taken_retr_RNIKQ2OL 813 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[8] 739 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[11] 699 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_2[2] 178 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[7] 603 187
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_s1_0_a2 24 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold_RNO 812 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_32[31] 935 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[7] 358 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[14] 827 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[0] 707 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[31] 500 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[6] 277 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_1 635 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_str_amo_addr_misalign 772 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[1] 835 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[0] 858 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[0] 334 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un9_OOoo1_3_i_o2 94 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[8] 648 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[24] 474 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[29] 730 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_ifu_expipe_resp_next_vaddr 808 153
set_location Core_reset_pf_0/Core_reset_pf_0/un1_D 847 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_halted 819 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[17] 287 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[16] 310 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[1] 514 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24[5] 333 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[30] 863 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[16] 69 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[8] 182 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_4_i 764 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_56[11] 293 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0 333 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0_RNID4LG01 760 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[0] 861 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4_RNO[1] 933 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[12] 414 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[32] 726 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[6] 206 187
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[4] 21 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[0] 334 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[9] 115 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m9x 719 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_u[2] 1007 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i_a2 838 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4[1] 187 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel 851 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01[1] 121 202
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc5 47 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI117O2[2] 273 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[5] 563 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[8] 775 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0_1_0[0] 284 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/dummy_target_i_resp_valid 734 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/ssel_rx_q2 599 211
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[26].BUFD_BLK 647 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0_1 815 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_668 735 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[8] 425 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[19] 927 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[7] 566 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oo0l1[0] 469 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4[3] 122 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_7 813 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_579 693 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[6] 338 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[52] 968 192
set_location d_m2_e_1_0 763 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_11 802 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_0 139 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_1 804 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[55] 841 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2_0[15] 731 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_0_tz[0] 766 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1108 682 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1[20] 773 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[12] 348 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[25] 959 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_621 754 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[47] 391 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[21] 840 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1123 657 210
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UTDI 592 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[8] 408 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[4] 857 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[10] 848 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOli1_1_i_0_o3 272 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[5] 423 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a3_1_2 261 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m69 142 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0[11] 803 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_complete_retr_x 804 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_RNIRTR73[0] 631 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[21] 893 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1052 718 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2[4] 500 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[8] 250 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[7] 360 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0[1] 626 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[6] 875 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[5] 399 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/N_545_i 228 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_2 429 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.m2 32 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[25] 704 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[13] 108 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[19] 676 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[19] 880 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[28] 876 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[4] 362 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[3] 359 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_d 811 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41[5] 347 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][7] 893 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_int_sn_m3 840 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][28] 869 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OloOo 216 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/UTDODriven[0] 568 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[1] 91 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_14_RNO_1 874 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[4] 183 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[9] 934 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1IIo 331 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un9_o1oOo 199 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[10] 438 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[5] 486 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un20_emi_req_os_at_flush[1] 785 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[10] 738 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[7] 59 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[8] 683 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[19] 849 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[10] 550 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1079 736 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[16] 268 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m6_2_1 676 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[13] 860 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[31] 838 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i_1_RNO_0 821 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_227 657 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[19] 736 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[24] 478 169
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns[2] 539 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[11] 186 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ilo01 115 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oooI1 450 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_gpr_ded_reset_reg/wr_en_data_or 624 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[3] 232 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001[0] 198 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.illi0 429 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[30] 689 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[31] 866 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un203_I1Oi1_2 47 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_misalign_error_retr 747 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO[0] 261 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_63 710 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[0] 880 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[10] 870 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_33[10] 288 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[16] 89 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[41] 232 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1[5] 652 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[12] 127 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[6].BUFD_BLK 573 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][6] 781 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[20] 538 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_0_i_o3[8] 108 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_data[1][5] 788 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[11] 324 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[8] 292 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_197 634 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[18] 376 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[3] 355 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[2] 449 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[5] 478 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[0] 860 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[25] 871 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_1 806 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto3 275 192
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[4] 24 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[10] 917 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[14] 878 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/un1_iOI01_1_i_0 273 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[29] 110 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[1] 292 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[28] 466 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[9] 321 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[3] 307 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[10] 344 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/genblk1.rst_synch_reg[1] 687 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[17] 654 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex 785 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_318 706 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[12] 617 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_775 705 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1061 703 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[52] 591 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[19] 875 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[27] 897 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4950_3 704 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[5] 223 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[2] 359 172
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[6] 470 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[22] 866 145
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[6] 487 160
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O01Io_RNO 62 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[18] 926 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[4] 472 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960_1 687 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_43[9] 359 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[4] 52 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNI8RFS461 781 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrx_async_reset_ok 595 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_sqmuxa_3_2 814 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m4 22 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_822 795 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/mdc_Z 216 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_0 250 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_811 639 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_131 756 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[23] 238 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[10] 419 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[19] 920 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_305 693 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI8LK9D_0 744 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[8] 844 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I11i1_0_a3 383 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[2] 810 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[31] 653 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[12] 722 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_794 682 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m22_3_1 659 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_3_RNO[0] 679 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1261 778 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[38] 238 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[11] 224 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[7] 493 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_OIiOo_6 295 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[5] 192 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2[0] 772 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[7] 401 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_678 789 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_332 633 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[4] 801 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[4] 98 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m6 610 117
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_cdr_ready_reg_2[0] 16 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1305 681 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb_RNO[1] 695 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[5] 364 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a5_0_4 166 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m4_2 670 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/I1lIo_2_0_.m11 104 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_3_f0_i_o2 765 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[45] 240 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_m6_0_a4_0_a0_2_1 777 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_a2_4 93 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_29_RNO 886 177
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[17].BUFD_BLK 634 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[12] 983 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[29] 622 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[3] 424 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data[0][2] 789 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[14] 839 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_1[3] 717 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_1_0_2 707 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[1] 189 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[8] 275 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[1] 840 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[30] 851 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_2[11] 395 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1_RNO 256 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNI99EPJ1 258 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_iIio1_1 93 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[10] 421 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0 110 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[5] 442 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_strobe 573 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[4] 732 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[0] 208 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1[2] 593 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_934 778 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_3[5] 191 177
set_location fifo_to_tpsram_bridge_0/ram_w_en_0_a2 490 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[5] 513 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[20] 958 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[38] 395 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto8 270 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1[2] 180 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_760 657 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_343 740 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[9] 683 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[2] 103 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd_1 729 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[9] 346 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[2] 38 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0li1_0 335 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[17] 812 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[53] 831 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[26] 391 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[7] 500 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_4_RNI5JU79 452 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_5 77 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[0] 423 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iloo1_RNO 90 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_parity_err_0_sqmuxa_1 512 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[17] 899 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[7] 858 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4951 699 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[1] 262 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[29] 905 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_0_sqmuxa_1_i_0_o3_0_o3 755 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[2] 244 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_44[8] 959 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIGTK9D_0 753 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[26] 379 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_2[0] 838 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[1] 288 184
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[31] 486 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[31] 874 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[3] 191 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[11] 845 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_20_RNO 887 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.llol1 300 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_o1Ii1.un17_o1Ii1_c2_RNI72A3C 431 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[22] 553 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0_o3_0 28 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0[19] 295 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[3] 219 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[0] 89 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_952 776 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[46] 610 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/dealloc_resp_buff_11_0 757 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[2] 30 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[9] 922 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1020 718 228
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[10] 511 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[25] 613 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[40] 588 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[12] 530 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[15] 68 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[2] 382 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[3] 211 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[21] 799 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o0ii1 119 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/un1_iOI01_1_i 257 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[9] 359 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[1] 367 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[2] 345 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/exu_csr_op_wr_data14 808 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[2] 346 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_45_RNIRI50I1 793 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a2_1 734 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_instr_decoded_3 729 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1_0_0 106 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel_2 803 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[13] 641 154
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt[2] 518 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[4] 382 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[2] 764 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5s2_0 854 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand0_mux_sel_1_iv_2_RNIIG5251[0] 722 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[17] 392 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m22_2_0 658 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de 745 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_clock 502 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/un1_Ioli0_1_0 366 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_693 753 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[32] 425 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_91_u[2] 1006 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[24] 809 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[2] 542 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[2] 475 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_522 681 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sba_resp_ready_int21_1 813 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO_1 695 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848_4 683 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un18_i0Oo1 284 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[16] 24 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[14] 901 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/OO001_3 203 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA[0] 559 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_22_RNI76SVEO3 808 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_alldone_2_sqmuxa 574 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[30] 924 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[33] 612 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_oIIi1_5 249 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[4] 399 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[34] 717 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[11] 261 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[39] 306 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/looo1 86 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[8] 838 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un19_oI0i1 227 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[20] 449 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[25] 897 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[1] 854 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPHTQ8[24] 732 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[15] 151 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_1[2] 773 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[0] 558 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][24] 877 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1226 680 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l112 401 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[3] 898 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5[0] 664 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1008 717 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[0] 233 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0[27] 170 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[0] 442 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[11] 714 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[37] 957 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[2] 151 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_0_1 46 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_enter 808 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_22 294 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[1] 446 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m3_0_a3_1 808 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0_1_0[0] 337 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[51] 837 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1269 657 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_RNO[1] 621 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[9] 387 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[6] 623 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiOIo 224 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_0_sqmuxa 632 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O00o1_N_3_mux_i 114 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1264 681 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI1B0P9[1] 72 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[0] 480 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oI0i1_i_0_a2 271 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[16] 891 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_13 798 123
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[13] 615 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[17] 309 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[6] 182 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[10] 320 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[17] 561 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol1Oo[0] 212 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un18_oii01 78 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[16] 518 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[24] 812 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1o01_RNII47I8 72 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.awe0 701 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[4] 456 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0_RNIICTDIS3 802 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl0112 249 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01[0] 126 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ii0Oo 239 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[5] 400 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_0_sqmuxa_0_a5_0 160 201
set_location SSDetect_0/rx_start_2[0] 13 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[6] 270 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[0] 357 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[17] 420 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1175 685 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] 232 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[17] 458 216
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[13] 620 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6] 644 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_6 703 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[18] 879 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_5 285 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_o2[7] 223 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o1ll1 468 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[2] 149 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[1] 573 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_14_122_a2 295 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[7] 948 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_4_194_a2 261 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_126 682 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[11] 674 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[0] 132 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[2] 340 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_rd_op 731 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[20] 855 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[28] 981 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[27] 633 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[21] 726 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[7] 252 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[12] 866 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_2 387 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m18 513 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[29] 252 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[20] 79 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[10] 712 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_a3_0_1 275 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_101 687 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[5] 918 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_770 706 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[9] 940 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[3] 649 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[1] 851 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_10_1[0] 641 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[9] 958 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_445 752 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_m6_0_a5_0_0 820 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[6] 303 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[18] 203 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_7 76 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[5] 475 243
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0_1 59 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIiO1 221 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u[2] 995 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_O1iIo 456 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[3] 506 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[4] 156 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[21] 985 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIJDFGI[7] 566 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[1] 840 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[2] 551 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[8] 355 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3[1] 129 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_534 621 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_302 669 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[20] 102 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1272 762 201
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[16] 51 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[12] 255 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m19 165 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_1[6] 642 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.awe0 699 132
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_s2_0_a2 527 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[1] 504 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[30] 725 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[23] 286 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[25] 553 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_10 644 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[7] 466 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12_cZ[13] 297 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1[4] 98 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[9] 93 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_0_RNI1TBI281 786 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m10 106 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_c4 609 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13[3] 778 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[2] 359 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[2] 758 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[1] 264 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_0[2] 151 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2[4] 973 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[29] 910 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[0] 408 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_o3[3] 853 120
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns[0] 536 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_103_i 345 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[38] 434 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[1] 131 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[17] 829 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1186 753 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_strobe 567 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[8] 396 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNI6098E[21] 679 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iOil1 389 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_904 717 207
set_location Core_reset_pf_0/Core_reset_pf_0/dff_15[0] 847 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[2] 69 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa_0 623 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_0 720 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_11[3] 513 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[3] 393 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_0[0] 372 213
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[1] 468 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[4] 268 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[18] 910 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[23] 710 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_70 622 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Ilii1 144 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oIIOo 142 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][20] 887 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[2] 947 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[31] 743 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41[8] 368 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[4] 882 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[9] 849 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[7] 335 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[28] 746 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_sig 793 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[14] 385 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[4] 364 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[6] 411 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1_3 105 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[10] 377 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_0[1] 681 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/gen_bit_reset.state_val[0] 844 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_481 775 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[4] 300 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[1] 722 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_2_RNII920TM 823 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_782 705 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OiIO1_Z 183 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[21] 464 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0[1] 142 204
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[2] 471 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[5] 662 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4[3] 877 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_rd_byte_en[0] 755 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_192 722 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[2] 30 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI1K99I 824 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[41] 565 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/stop_strobe 520 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[3] 969 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[10] 345 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[6] 340 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un45_OOOI1[10] 364 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1[4] 281 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[1] 541 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_3[2] 221 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[12] 456 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_0[11] 847 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[17] 910 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[0] 424 181
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m4_1_0 608 117
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[7] 34 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o0o11 423 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_9 784 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/un1_Ioli0_1_0 302 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[17] 862 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[4] 339 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un147_I1Oi1 70 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[3] 513 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[5] 86 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[0] 834 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0ii1 120 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_844 729 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_591 706 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_8[9] 346 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd_3 723 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[14] 869 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.init_wr_dcsr_step_en_RNIG2M9T2 780 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[6] 197 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[16] 721 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[13] 299 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1011_RNO_0 304 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[12] 215 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[11] 882 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[22] 933 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[11] 441 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[1] 611 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[9] 212 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata[6] 593 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv[4] 714 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0_1_0[0] 297 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[31] 891 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[11] 851 201
set_location pf_init_monitor_0_0/pf_init_monitor_0_0/I_INIT 508 2
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[10] 770 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[8] 711 132
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[5] 490 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[13] 946 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_1 837 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_694 634 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_i1oOo 240 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][0] 761 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.OOoIo[0] 471 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ioo11 361 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[2] 520 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIo01_i_0 115 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[8] 717 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_533 705 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO[3] 653 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[4] 368 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[15] 354 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[4] 408 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1[11] 114 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_fast[0] 858 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[14] 318 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2_0[6] 134 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[14] 407 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_wr_rd_state_Z[0] 783 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[7] 351 175
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/un1_tx_parity_1_sqmuxa_0_a2 534 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[12] 617 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_15 794 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[37] 616 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IOo11 305 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IoOl1 437 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mscratch_sw_wr_sel 802 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_2 738 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[29] 863 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i11Oo_0_a3_4[3] 205 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[0] 420 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[28] 941 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[6] 332 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg[3] 759 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmstatus_allany_havereset10_0_a3 816 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[16] 723 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_997 670 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc3 607 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op[0] 766 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1237 645 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_359 692 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[58] 633 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[6] 196 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[20] 102 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb 786 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_9_RNO_0 847 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[14] 613 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[19] 670 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv 813 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[4] 601 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_948 752 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Oooo1 95 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[3] 481 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_m1_e_0 814 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[10] 320 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ooo11 388 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2[8] 299 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[41] 956 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[2] 983 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[4] 322 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m7 21 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[8] 213 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_25_2 708 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[1] 308 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[11] 425 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[20] 922 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[2] 297 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/io0l1[0] 479 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[9] 197 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OIo01_0 115 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO[1] 239 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[4] 163 211
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[13] 499 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[2] 727 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23[5] 405 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_1[13] 341 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[1] 383 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[26] 469 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[14] 648 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[21] 450 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[23] 751 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[2] 321 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/liOo1 290 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0[3] 217 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[2] 472 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_addr_align[0][0] 759 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[8] 865 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[26] 748 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_APB_0_Read.prdata18_0_a3 611 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[21] 799 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[33] 286 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[3] 916 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un43_I1Oi1_1 57 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[6] 85 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[25] 547 178
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[18] 77 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[5] 184 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_6[15] 704 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol0l1[0] 469 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un21_i0O11_i 84 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_RNO_0[1] 33 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_dummy_target_sx 771 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7CB84[30] 908 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[3] 854 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/un1_irq_stall_lsu_req 784 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un23_trap_val 756 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[5] 171 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_s 819 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[9] 848 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_741 777 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[31] 677 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3[3] 165 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[0] 346 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[22] 804 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3] 718 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_504 736 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[0] 100 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[21] 874 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO1Oo 200 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7OKNF[0] 750 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[0] 241 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[24] 669 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OI0Oo 228 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_2 386 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_o2 345 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_758 656 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2[15] 305 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[5] 863 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[7] 923 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un95_lliOo_1.CO2 294 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_536 656 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0_RNIURTKGF1 768 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_647 743 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I0o01 111 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_746 705 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO_2 331 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_920 645 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[30] 748 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_i_iv 727 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_29_RNO_0 885 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[5] 291 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[8] 522 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[12] 948 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_492 658 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[17] 64 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[2] 887 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[10] 653 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m5 105 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[25] 660 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_413 658 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_IoOi1_0_a2_3 248 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[15] 683 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/IiIo1 229 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[15] 832 154
set_location fifo_to_tpsram_bridge_0/next_state11_21 505 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m46_2_0 263 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[9] 531 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ollOo 135 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1[12] 331 216
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_i_a2[3] 528 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[4] 571 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[14] 541 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[17] 287 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[7] 52 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960_7 704 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0[3] 823 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[7] 347 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[0] 447 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un10_l1ll1_7 466 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_1_0_N_3L3 800 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[14] 135 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_11_RNO_1 815 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[7] 568 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[3] 859 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_rd_ptr[0] 804 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[8] 319 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[13] 105 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[15] 598 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_3_RNIVSQ5B 311 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOi11 356 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_a2 107 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[9] 958 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2_1[6] 143 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[7] 502 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[5] 851 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[13] 723 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[2] 387 216
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc2 22 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un9_l1Oo1_4 291 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int21 812 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oioo1 100 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_424 715 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[3] 209 211
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4[0] 46 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_RNO[0] 118 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1[2] 740 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[26] 886 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[3] 718 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1_RNI8HDTF 822 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[8] 861 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_264 704 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_0_sqmuxa 774 129
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc2 30 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[19] 385 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sellto7 26 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[19] 447 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[29] 865 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_stall_csr_1 748 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[25] 929 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNI623QO6 796 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[8] 344 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_9 95 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_OOii1_0 153 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4950_1 695 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_18 754 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OoIOo 139 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un65_ool01 202 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[1] 590 190
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt[1] 20 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[8] 412 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[5] 736 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[0] 350 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2119_2 657 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[24] 889 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_15[22] 227 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[15] 621 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[6] 624 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_857 771 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioIi1 210 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[33] 628 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[7] 544 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1_sqmuxa_1[0] 43 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[2] 674 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un5_ool01 182 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[14] 844 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[9] 324 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[19] 793 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[2] 467 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[1] 184 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[2] 336 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[4] 854 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[11] 425 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pslverr_reg 777 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[0] 326 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_4 727 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[7] 466 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[2] 178 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/I0Il1 466 202
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[5] 494 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_1_0 670 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_1 396 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m3 711 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oioi1 144 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[2] 487 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un22_o1Oi1_1 80 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38_1_0 765 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8] 669 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[3] 239 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux_0 749 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_503 751 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[0] 860 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[17] 276 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un21_loOo1_i_o2 335 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[7] 493 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[14] 685 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l10Oo_0_a3_0 222 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_17[22] 226 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[15] 907 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m278 383 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0_2[2] 820 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[19] 793 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[1] 284 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1 706 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[3] 869 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[8] 344 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[12] 414 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[8] 415 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[0] 327 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_reg_ex 761 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[5] 357 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[0] 384 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[27] 971 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[1] 950 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[29] 849 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1_0[7] 154 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IlOo1 145 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1091 682 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[10] 309 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lOll1 458 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[7] 718 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[16] 453 217
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[17] 54 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1011 754 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[9] 196 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[5] 545 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[4] 200 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[7] 145 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_o6_1[1] 657 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[25] 904 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[25] 231 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1IOo 132 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_i_req_ready 779 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_391 742 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[26] 872 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_719 739 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_396 730 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[17] 599 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[8] 319 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5[4] 108 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_Z[1] 833 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I018 323 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mvendorid_sw_rd_sel_0 808 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[6] 880 133
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5[5] 492 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[7] 285 169
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[12] 493 160
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel[3] 571 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[5] 167 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[5] 70 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IoIO1 84 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[3] 427 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[11] 186 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[28] 620 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2[4] 33 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/un1_Ioli0_1_0 325 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo_2 243 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[3] 846 178
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[2] 44 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24[6] 367 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_4 248 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[7] 496 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3[2] 116 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0_0 863 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[28] 852 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_17_RNIQM1QJO3 802 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[11] 380 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1291 788 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_ss0_0 771 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1_i_m2[2] 898 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0iIo 438 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1[5] 134 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O0lI1 485 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q1 710 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[1] 783 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1211 751 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[45] 955 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[4] 888 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[26] 905 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iOo_RNI09I8B 226 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[4] 961 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[1] 852 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[4] 801 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_49[9] 947 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[14] 903 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[1] 404 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m4 31 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[14] 515 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m28 69 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[3] 895 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OoOl1 433 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state21_a1_0_a0 790 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[22] 451 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[7] 238 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[0] 260 205
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv_RNO[5] 609 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI9RFUI[3] 894 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNIG3V3L71 800 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[24] 898 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_249 753 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m13_2_1 128 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_20 654 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[24] 656 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[1] 170 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2[1] 674 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[44] 817 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[7] 269 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[24] 465 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[10] 857 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_274 633 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[12] 830 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1[5] 959 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0[2] 246 177
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0[3] 612 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[26] 473 196
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state136 609 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[31] 865 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_subsys_cfg_0_o2 776 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/un1_Ioli0_1_0 304 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_959 681 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_9 94 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr_s_s_RNIOH34R 817 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[16] 820 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[23] 395 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14] 695 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[6] 464 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m5 119 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[19] 768 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_gpr_addr_1_sqmuxa_0_268_a2_0_o2 863 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[1] 502 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_0 563 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_506 710 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[0] 487 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_pending_a3_0 827 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[25] 901 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[1] 851 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[23] 785 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[15] 922 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[4] 544 193
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_sqmuxa 622 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0[0] 416 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[16] 374 210
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[0] 481 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[3] 155 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[22] 873 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[11] 520 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[3] 699 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[7] 247 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[11] 843 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[51] 626 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIOMCV6[4] 227 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_9_RNO 863 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO1o1_RNI5IQ17 104 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[2] 262 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[8] 776 142
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[1] 592 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m[15] 710 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[0] 330 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[31] 396 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[27] 432 196
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[1] 458 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1250 774 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_ss0_0_a2cf0_1 754 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[5] 518 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2[2] 776 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[5] 238 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IOoO1_RNIL90CO 300 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_0 670 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[4] 382 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[2] 553 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[7] 876 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_10_f0 767 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[7] 204 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_m9_i_0 174 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[8] 535 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_639 718 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[25] 933 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[29] 900 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[14] 108 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1_0[13] 825 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[3] 213 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m5[1] 760 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[15] 895 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2[1] 730 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[1] 561 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr[0] 755 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[21] 543 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[10] 400 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_419 645 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[18] 723 120
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[7] 612 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/i0iI1 278 196
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_20 488 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[7] 420 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1[8] 136 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[30] 693 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[1] 896 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[2] 801 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_1[4] 257 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[30] 905 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[27] 869 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[7] 485 217
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[20] 501 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[17] 838 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_911 690 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[6] 203 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_340 699 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4 600 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[6].BUFD_BLK 608 123
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/full_out 574 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand1_mux_sel_0_1[0] 689 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0_1_RNO 805 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_31_RNO 853 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[8] 197 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex[0] 762 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[6] 352 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr[0] 696 127
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[1] 38 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[47] 623 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[10] 325 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[37] 816 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][5] 897 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[8] 366 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[16] 397 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1[0] 622 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[29] 527 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[6] 299 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_pending_a2_1 786 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.N_4_i 123 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[30] 649 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[2] 275 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un9_o1ll1_6 260 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/olOl1 430 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO_1[1] 671 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[14] 214 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[2] 739 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0 92 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[5] 344 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1041 750 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[21] 992 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_3 802 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0[0] 81 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[28] 961 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[19] 391 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[13] 969 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_67 669 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ilii1_2_0_0 145 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/OloIo 233 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[16] 384 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[16] 454 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_bcu_op_completing_ex_0 790 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNI3SN3NQ_0 787 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[11] 788 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_0[2] 754 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[3] 444 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_2[2] 725 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs1_rd_hzd_4 728 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[0] 830 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[9] 850 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_1[13] 164 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_s_RNIQ7RI2T3 801 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[1] 546 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1[9] 353 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[24] 870 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[6] 717 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[35] 610 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[9] 357 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[14] 883 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[24] 468 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1299 718 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[9] 258 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0[30] 945 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[3] 718 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_1 384 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1219 740 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[2] 338 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[25] 737 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[28] 708 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_3[3] 150 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[17] 934 150
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[24].BUFD_BLK 646 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1294 777 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[10] 304 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1_RNIHBJH62 299 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_5 310 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[22] 448 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[7] 451 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[12] 827 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1153 668 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846_0_0 650 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[31] 335 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_145 682 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1214 764 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[9] 537 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[6] 192 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1241 670 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state138 621 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[31] 907 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[7] 746 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_456 732 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[0] 153 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_5_c4 22 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[4] 548 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[19] 734 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_3 252 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv[15] 745 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_53 650 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_7_RNO_0 811 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[2] 247 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[7] 501 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[12] 358 168
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[24].BUFD_BLK 620 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[53] 966 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[0] 172 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/make_parity_err.parity_err5 511 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2[14] 207 213
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UDRUPD 441 6
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[21] 59 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[15] 213 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO_1[3] 692 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[8] 266 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO1o1 117 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2[0] 726 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_1[3] 226 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[11] 536 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[28] 898 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1[3] 734 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[16] 404 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[9] 884 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_i_req_ready_x 777 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[13] 223 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_0 59 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1277 645 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[33] 490 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[8] 240 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI3D0P9[2] 35 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[15] 348 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[1] 240 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_10_m_0[2] 861 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[13] 399 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[11] 366 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/mem_rdata34_0_0 803 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m4 30 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo52_RNIDMMEA 76 186
set_location fifo_to_tpsram_bridge_0/ram_w_addr[2] 471 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[9] 263 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[22] 849 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[11] 752 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[5] 54 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val_12_0[0] 823 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_iooo1 94 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_22 671 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[22] 854 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[17] 214 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[0] 811 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1li1[7] 355 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iOi11 452 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[9] 514 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[13] 833 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_29 749 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[0] 78 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[3] 661 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[15] 678 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[50] 624 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[0] 512 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[7] 412 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0 773 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_81 730 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[44] 242 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[0] 546 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[7] 475 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m9 29 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ilio1 90 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIO11[0] 91 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3[14] 803 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_complete_retr 815 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_1_RNO_1 70 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[10] 329 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[15] 326 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[3] 732 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[18] 295 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[6] 238 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[16] 692 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo[0] 296 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[9] 218 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[4] 93 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[21] 852 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[6] 401 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m15_0 647 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_iOIOo[0] 141 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[3] 343 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[29] 883 138
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[6] 615 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[12] 680 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/un1_iOI01_1_i_0 353 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_328 681 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0[6] 195 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[34] 717 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[6] 244 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_3 362 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_6 392 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4928_2 677 174
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_26_RNI3M8GT 38 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un34_loOo1[6] 339 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[14] 934 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[19] 959 153
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[25] 476 243
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/IilI1_RNO 334 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[10] 524 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[31] 932 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_10 116 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_30[0] 358 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI7HFK1R 816 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[25] 945 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0[5] 817 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[0] 144 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIP2CS7[5] 904 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[1] 215 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_pending_a3_0_RNO 823 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][15] 888 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[5] 860 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[12] 379 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[13] 506 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[6] 857 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.SUM[2] 941 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[1] 197 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex[1] 769 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2_3 813 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/wfi_waiting_reg6 783 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[6] 1003 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOo01 80 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[4] 217 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_821 730 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_168 774 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[3] 877 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIR4FO8 281 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[6] 141 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_609 759 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_5_RNI9LSPJO3 811 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[5] 155 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[23] 868 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_3 774 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[4] 737 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Ilol1 307 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[3] 437 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[19] 305 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_0 781 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1iIo 563 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14[14] 982 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[23] 897 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO1I1 524 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[13] 848 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[11] 532 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic1881 671 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[18] 907 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_RNO[1] 302 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_o1I018_1 309 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[11] 440 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[14] 836 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[10] 858 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1161 723 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[4] 297 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[17] 398 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_383 692 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[20] 402 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001[2] 200 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de_RNO 749 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNIRBKDT71 778 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[17] 856 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[5] 196 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[2] 323 208
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_RNO[3] 538 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[9] 258 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[4] 249 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[10] 344 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[16] 48 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1249 789 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[2] 217 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_3_0[5] 334 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[7] 223 171
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[14] 57 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/un1_iOI01_1_i_0 351 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[22] 293 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[27] 720 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/III11 133 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[8] 849 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1244 729 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[4] 556 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[18] 82 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[56] 965 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z[2] 418 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_i_x2_1[5] 156 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Il0l1[0] 474 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[7] 212 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[2] 386 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[7] 214 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[8] 474 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_13 632 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_0 106 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_1 792 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_misalign_error_i 754 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_4_RNO_0 874 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[21] 831 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 512 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state_0_sqmuxa_i_RNI4B2FB 854 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[2] 261 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[12] 350 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_65 691 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOIo1 326 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIII1 506 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[4] 204 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[4] 420 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[19] 391 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[1] 872 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[0] 190 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_1_0 143 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[10] 256 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un30_l1I01_4 368 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIIVK9D_0 748 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.N_8_i 103 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_39_0_o2_0 669 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[60] 849 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ll1i1_0_a2_0 387 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[7] 302 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[3] 409 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[10] 350 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olo01_RNO 111 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[11] 365 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OOOl1 426 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc3 36 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mie_sw_wr_sel_1_0 837 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2[34] 397 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un73_OOOI1[8] 415 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_11 457 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag[0] 33 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[29] 632 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1I11 309 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m3 130 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[0] 628 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto15_4_0_2 226 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[8] 866 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1050 740 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[27] 499 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[1] 656 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[7] 345 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[6] 153 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[5] 840 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_3[1] 356 213
set_location SSDetect_0/is_match_0.un3_is_match_4 12 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_1[5] 947 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[4] 854 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[24] 347 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Il1I1 401 175
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[1] 472 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[5] 235 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[2] 534 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv_i[6] 682 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m4 653 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[13] 358 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat14 651 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[4] 482 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[10] 746 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[14] 330 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO[2] 648 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_2[0] 235 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1o01 79 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb_RNO[3] 688 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNI0NE1B[18] 74 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_mtie/gen_bit_no_reset.state_val[0] 790 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1004 742 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_3_0 736 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5[0] 620 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q1_3 709 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m23_2_0 689 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI8B984[13] 911 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un18_oii01_1 77 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[3] 676 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO_0[1] 666 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[11] 337 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val[0] 823 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_16_iv[34] 489 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[2] 369 172
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[18] 470 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[26] 877 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_19 754 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[27] 728 133
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[10] 492 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m1_e_4_0 815 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[31] 860 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[0] 322 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_3 683 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1iO1 368 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[3] 536 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_9_RNO_1 870 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo 133 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[1] 775 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[4] 296 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[30] 406 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[19] 594 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[5] 318 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[2] 311 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[28] 376 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i[8] 699 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[8] 208 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[61] 640 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2[17] 173 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[27] 901 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_7 827 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a2[4] 167 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1256 812 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[31] 672 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lliO1_1_iv_1[1] 82 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_3 58 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[0] 124 184
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0] 15 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[31] 790 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[27] 500 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[7] 844 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[35] 735 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[3] 343 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[5] 213 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l000111 177 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_178 656 210
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_UDRUPD 610 111
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[9].BUFD_BLK 598 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[13] 315 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I1oo1 87 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[13] 864 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[0] 215 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[7] 335 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/IO001 283 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[4] 286 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i_a3 769 132
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[30].BUFD_BLK 643 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt_1_sqmuxa_0_a2 519 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO_0 219 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[1] 550 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_9[1] 189 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/empty_out 571 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_3 837 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2[15] 708 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo 142 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un15_OIoO1 126 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel[1] 566 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[27] 935 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[4] 207 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un7_ool01[8] 180 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i[29] 886 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[13] 253 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_strb[1] 778 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/un3_irq_stall_lsu_req 766 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_1[2] 105 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un2_i0Il1 456 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[43] 622 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[6] 533 196
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[13] 58 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[9] 344 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_5_RNI8CGEL[15] 678 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[9] 149 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_1[31] 753 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0i01_0_x2 78 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_86 730 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold_2_i_o2 878 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[7] 420 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[12] 610 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO[2] 260 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[18] 521 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1l11 342 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst 504 2
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_25_RNO 945 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO_0 662 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iio11 369 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_485 682 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_loOo1_0_o2_0 292 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[12] 713 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_empty 773 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[8] 233 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_0_1 105 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[3] 571 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[0] 853 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_bcu_op_sel_ex_2 772 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[25] 244 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNICTI09 783 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[19] 728 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_10 365 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[24] 472 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_RNO 109 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[10] 881 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[29] 833 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[23] 919 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[13] 836 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un183_I1Oi1 68 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un4_UTDODRV_4 428 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[1] 376 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1208 748 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[19] 522 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2[5] 359 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[4] 594 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iooo1 90 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[11] 323 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO[4] 228 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[2] 221 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[5] 719 144
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_1[5] 554 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m15 676 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[17] 957 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[0] 172 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[30] 799 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_1[3] 333 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_5_RNIQDDH9 670 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[6] 849 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[52] 836 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[2] 738 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[15] 642 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[3] 296 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un16_i00i1lto15 258 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[15] 659 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l1iIo 440 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[2] 120 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_5 575 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ioll1 486 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[5] 342 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[19] 81 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1136 655 225
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_SWITCH_LANE9[0] 10 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[10] 815 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIDCBP2_0[1] 226 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3_0_0[3] 819 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[28] 861 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0 610 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[18] 724 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[5] 439 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132_3 694 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[24] 867 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_915 694 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[24] 750 126
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[26] 474 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_50[11] 396 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_emi_req_os_at_flush[0] 787 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[26] 827 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[9] 329 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_a2[4] 848 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[3] 317 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de_RNIOCJGR 753 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[26] 358 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[10] 545 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[8] 954 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_3 397 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[0] 39 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[16] 926 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[12] 710 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[20] 748 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_1_1 57 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_256 665 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[6] 237 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a2[2] 149 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[0] 777 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2s2_0 768 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m[1] 434 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[10] 862 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[7] 405 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_510 740 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/loil1 514 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[6] 202 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_busy_1_sqmuxa 573 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ooIl1 495 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[21] 600 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[0] 351 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_a2_0 133 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[33] 452 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[18] 835 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[10] 530 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lOlo1 298 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_0 89 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE_10[10] 18 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI0o1[1] 64 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os 795 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[17] 405 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[44] 385 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[17] 418 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_error_sig_N_4L5 826 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/OlI01 332 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a2[1] 652 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][22] 870 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[17] 261 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_m2_e_2 791 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[3] 358 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[30] 825 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[51] 943 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[7] 308 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[3] 874 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5[1] 650 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_oi1o1_0_m2_i[0] 93 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_2 58 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[26] 927 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_2 833 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[12] 615 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[36] 234 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[28] 982 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[28] 696 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_147 680 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_51[7] 566 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iOo_RNO 220 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[2] 723 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_450 632 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2[13] 723 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[5] 317 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[6] 434 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_884 717 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[6] 193 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_oI0i1_1 211 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[2] 412 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_22 632 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[1] 313 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1[7] 265 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIPU8GO[29] 887 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readondata_ff 758 118
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_1 704 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_14 314 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3[8] 143 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[16] 722 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2 787 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[25] 931 156
set_location SSDetect_0/is_match_3 16 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr_1[1] 751 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNI8EFAU_0 118 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr[2] 837 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[5] 379 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[27] 787 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNI4KONQ4 117 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l00o1_1 47 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[3] 201 222
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO[0] 617 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[17] 857 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en 812 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_o2[1] 788 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0[9] 180 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[24] 981 174
set_location Core_reset_pf_0/Core_reset_pf_0/dff_14[0] 842 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOiI1 400 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[13] 144 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[14] 850 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[5] 262 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIO11[0] 91 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[1] 868 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[15] 103 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[2] 319 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo1 289 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[0] 475 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[32] 944 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[32] 635 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo[8] 208 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[30] 824 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_11[1] 287 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[2] 127 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[30] 682 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[32] 728 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[29] 709 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_RNII9FRC[2] 216 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[29] 732 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a2 260 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[9] 524 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_0[15] 133 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[1] 309 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_holdsel_RNO 572 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_660 667 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_Oill1 329 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[7] 535 208
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[0] 18 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[4] 363 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIiO1_RNO 310 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un213_I1Oi1_2 58 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_744 693 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[17] 298 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m39 117 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[0] 302 196
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[6] 45 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[6] 391 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[7] 451 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_1_sqmuxa_1 808 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[7] 345 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_a2_2[4] 696 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/next_buff_valid[0] 739 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1[0] 298 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[1] 841 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo[2] 241 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[15] 572 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[31] 911 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[7] 463 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_468 701 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[10] 521 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[36] 565 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[5] 862 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_rd_1 784 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ[13] 405 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I0ii1_2 147 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[7] 735 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_6[6] 103 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[9] 204 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO[1] 659 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[4] 206 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_cfg_enable 571 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[0] 377 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[3] 193 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[18] 908 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[5] 845 127
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit[1] 519 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iOIOo 139 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state136_1 608 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_27_RNO_0 841 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_0[5] 332 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_988 703 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[5] 813 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[43] 254 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[2] 381 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[9] 549 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_0_sqmuxa_0_a5_0 177 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_reset 692 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IOo_RNO 137 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[2] 347 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[11] 692 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0[1] 197 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[7] 566 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i_1_RNO 822 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iO0Oo 229 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[1] 123 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[15] 252 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_1[4] 923 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/N_17_0_i 173 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[1] 338 196
set_location COREFIFO_C0_0/COREFIFO_C0_0/re_set_RNO 468 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][26] 883 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m[0] 449 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[1] 264 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_1 277 192
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane_RNO 12 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[13] 620 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25_1[11] 365 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[19] 384 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/loIOo 135 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[0] 302 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[13] 223 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m5 119 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24[7] 359 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[4] 160 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[16] 520 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[11] 751 169
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[4] 533 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[9] 37 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[2] 213 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[6] 917 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[28] 805 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iiOI1 408 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[31] 559 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/lIlI1_RNO 148 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[8] 671 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[47] 599 172
set_location fifo_to_tpsram_bridge_0/buffer_full6_7 499 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_IlIi1_1_0 243 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_2[6] 645 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11[2] 82 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[13] 737 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[7] 439 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[0] 256 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[10] 740 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[2] 51 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[13] 944 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[13] 382 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_flush 826 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_781 688 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[11] 361 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex[0] 851 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[4] 247 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[6] 130 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_RNO_1 765 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[6] 362 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[15] 53 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_0_o2_0[3] 779 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[28] 656 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIRJTQ8[25] 733 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[0] 50 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[32] 458 202
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[29] 482 243
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_2 679 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_28[10] 356 222
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[2] 12 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1 258 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo_RNO 307 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[10] 716 142
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_2[1] 620 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[6] 87 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[14] 933 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_687 748 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_786 713 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[18] 726 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[29] 941 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ooIIo_RNO 305 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[4] 441 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[1] 484 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[25] 868 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[9] 448 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/IilI1 369 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[2] 1007 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[7] 405 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[21] 862 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_0_4 78 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[19] 387 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[13] 435 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[14] 858 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr[1] 633 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IOo 137 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[2] 105 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_rd_ptr[0] 735 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[0] 342 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0[3] 183 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0 428 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[29] 613 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc6 47 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[13] 458 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[13] 921 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex 787 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_643 716 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[6] 488 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_1_1[16] 958 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un114_OOOI1[11] 428 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[22] 920 186
set_location fifo_to_tpsram_bridge_0/next_state11_29 511 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[11] 366 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1 132 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[0] 144 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[6] 596 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_33[1] 311 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[1] 421 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Iloo1 90 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[31] 886 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[14] 361 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_134 738 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNIBKIM4D[5] 804 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[16] 32 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_423 644 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[12] 410 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[5] 79 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[19] 921 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[14] 901 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[0] 226 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_1[6] 779 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_1 56 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oIiOo_1.CO2 282 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/un1_Ioli0_1_0 291 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[8] 526 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_2[28] 980 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_a2 784 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[8] 257 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i[7] 717 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_1[2] 695 150
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0_DELAY 7 376
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[4] 854 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1IOo 132 171
set_location Core_reset_pf_0/Core_reset_pf_0/dff_3[0] 835 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[15] 382 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_21 646 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_oIIi1_0 308 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[0] 470 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[5] 316 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[3] 182 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_rd_en 860 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_5 696 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un7_cpu_d_resp_valid_rd_0 797 150
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext_1_1[2] 611 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_3[2] 753 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[2] 356 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_670 657 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[11] 452 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[9] 501 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[31] 725 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_IOio1 95 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[13] 359 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/IilI1 402 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[2] 779 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[3] 417 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[7] 726 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch[0] 703 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m40_1_0 163 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[1] 357 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0] 368 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[19] 732 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[16] 299 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[9] 517 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[7] 346 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[9] 59 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un20_emi_req_os_at_flush[0] 780 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_397 724 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_478 772 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[53] 606 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[2] 85 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a2_0_RNIQH3GK[1] 847 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[16] 297 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_8_RNO_0 855 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iIIl1[0] 470 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0iO1 318 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_di_mux 606 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_ac0_5 23 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[3] 609 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[12] 414 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_pending_2_0 791 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[22] 546 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1300 699 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[21] 798 127
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write29 510 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35[6] 347 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_34[2] 334 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo_3 268 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[33] 476 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3[15] 331 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0[2] 971 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtval_sw_rd_sel_1_0 839 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_MTIME.un1_T_l_En_0_a2 609 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_68[11] 357 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[29] 249 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[2] 174 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m22_1_0 671 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[2] 187 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_ready_reg_RNO 809 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[5] 344 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[28] 474 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_24_RNO_0 877 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[14] 330 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1_4_0 76 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[27] 891 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOiI1 428 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[2] 308 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_a0 818 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[9] 197 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_8 410 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/O0111 149 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un12_I1oo1_4_RNI9891A 85 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[7] 823 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[1] 89 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13[1] 779 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i10i1_RNO 277 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/io001 182 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31_0 605 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[5] 483 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1[6] 669 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[9] 476 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[8] 551 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[26] 797 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[16] 916 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[19] 188 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1 234 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[0] 484 175
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[3] 505 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[51] 837 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[30] 283 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[13] 96 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNICLOH11[2] 233 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0[1] 827 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[10] 109 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[0] 350 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[9] 409 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22[4] 376 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_0_sqmuxa_1_0 619 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[10] 427 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[3] 573 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold[2] 612 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_lsu_op_ex_pipe[3] 709 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[28] 982 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[7] 892 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ioOl1_3_0 407 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[7] 751 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a3_2[9] 132 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_1[9] 297 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_1[0] 415 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_6_0_a2_0[1] 843 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_2 53 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_28 741 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[5] 418 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[3] 87 169
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_cZ[4] 599 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[10] 840 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtvec_sw_rd_sel 796 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2[19] 181 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[20] 519 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/mem_rdata34_0_0_RNIKKCRJ 763 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[17] 945 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m53 131 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[10] 360 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[6] 302 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z[1] 419 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[12] 747 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0_1_0[0] 213 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo51 64 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[18] 725 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[5] 716 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy_RNIB2JKIO3[21] 796 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[7] 865 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIH9TQ8[20] 718 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[3] 743 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_729 698 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[7] 663 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[1] 323 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[29] 848 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state135 618 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[6] 274 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_8 651 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_l_En_0_a2_RNIC89L7 573 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[0] 214 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_exception 707 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[2] 464 187
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNILICS8[0] 13 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_655 705 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[4] 176 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m23 118 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[13] 90 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[15] 369 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[3] 891 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[1] 762 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo 268 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[0] 473 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[6] 484 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[28] 325 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[27] 910 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_289 634 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[9] 698 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_4_a0 782 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[12] 380 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m34_e 20 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0[5] 627 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[0] 264 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[13] 287 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oiOo1_2 277 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z[1] 139 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0[7] 190 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_142 657 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[12] 738 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI953IQE[5] 794 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_RNO 805 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto3_1 245 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel_7_f0 591 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_2 723 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[30] 731 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[8] 852 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[7] 369 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[6] 153 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/l1lIo.m5 62 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_61[0] 957 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3[16] 335 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[6] 254 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_6 405 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa 595 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[0] 68 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1[25] 934 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[5] 515 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[24] 979 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.mdc_0 216 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OI0o1[1] 77 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[9] 933 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a3_0[2] 136 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[2] 278 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[5] 860 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7[9] 58 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.IloIo 515 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[20] 785 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1191 679 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1081 737 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[0] 371 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[10] 860 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_541 644 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat13_RNI1RVGA 671 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtm_resp_ready_RNO 694 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a3[0] 618 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1111 693 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_Olii1 151 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_1[9] 46 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[15] 907 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[2] 262 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[20] 394 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[6] 424 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[10] 104 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[8] 859 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[6] 564 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[4] 544 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_ld_addr_misalign_0 769 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lI0Oo_i_a2_0 230 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[19] 519 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[1] 55 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u[9] 946 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[16] 811 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[15] 296 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m2 164 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oO0o1 132 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[20] 886 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_644 814 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[17] 744 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[16] 655 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[2] 405 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[34] 420 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[8] 335 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[0] 144 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_104 763 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_0_RNIE5PQ8U3 770 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[27] 729 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[10] 298 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_0_tz_RNIQSNOO[20] 278 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[31] 403 186
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA27 575 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[21] 913 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1265 676 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_sn_m4 850 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked 771 154
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[12] 468 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0[20] 157 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[20] 229 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n1 308 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_10 57 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_unit_places_0[1] 730 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1_RNO[6] 147 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv[11] 756 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1176 684 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[5] 294 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_912 691 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_25_RNIDCVVEO3 803 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1281 668 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loo11_1 441 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[22] 638 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[7] 316 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5[3] 188 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[3] 543 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[22] 74 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1[6] 346 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0[1] 752 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[30] 855 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][16] 876 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_o4[0] 118 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_14_3 691 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[13] 906 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a4_1[0] 69 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[15] 542 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m28_0 46 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m246 377 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[2] 951 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[1] 404 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_380 669 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[22] 713 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_62_RNIOR8F41 972 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un88_OilI1_0_a2_i 392 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_RNO_0[47] 955 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[8] 544 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[3] 440 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_737 657 198
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[3] 37 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_947 689 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1[5] 189 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[3] 230 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[11] 334 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[12] 95 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_429 680 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[18] 588 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2_1[3] 106 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[10] 384 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0[0] 631 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[10] 274 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOoOo 220 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_57 655 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[21] 292 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_39 702 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0 112 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[58] 631 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk2.un5_OIiIo_2 405 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_921 748 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[11] 849 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[16] 178 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[21] 986 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/un1_iOI01_1_i 324 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_4 308 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[0] 224 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0 274 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[23] 544 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[6] 873 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[28] 860 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_O1Ii1_1 313 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[4] 844 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4[1] 633 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_868 692 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_masked_cZ[1] 760 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[7] 338 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_3 401 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_2_i_o2 883 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2114_1 656 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[8] 729 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i[1] 876 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[5] 211 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_3_0 807 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[11] 390 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0[15] 682 180
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_19 510 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_839 656 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[3] 34 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m2[1] 777 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[13] 691 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m2_0_a2_2 880 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3_1[16] 963 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[6] 345 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[18] 399 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[8] 864 129
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[1] 26 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[2] 826 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Iili1[7] 349 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[5] 408 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1_RNO[6] 645 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[7] 188 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[21] 943 159
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[2] 47 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_8 637 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[15] 767 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111 268 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un29_ool01 187 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[9] 258 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[21] 465 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2 94 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[29] 742 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m19 693 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_ss0_0_a2_0_0 752 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[4] 439 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[22] 913 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[11] 430 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_185 717 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_a2_2[28] 279 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[6] 921 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[4] 511 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[39] 552 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[26] 921 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[1] 856 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/un1_iOI01_1_i_0 310 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1_RNIRNGTI[0] 102 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[29] 804 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[21] 395 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[6] 193 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1_0_RNI6BA8F 817 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_RNO[3] 249 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un85_i11Io 507 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[5] 872 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/abstractcs_cmderr_cmb_0_sqmuxa_i 846 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_u 793 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[4] 727 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[11] 364 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0_RNI8LD7F1 760 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[7] 341 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[29] 334 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I0111 110 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[11] 232 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[4] 183 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[7] 252 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 519 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_5_2 732 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_442 695 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_1_a2_0 839 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[1] 237 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi019_0_a2 72 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[9] 180 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[10] 884 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[27] 969 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[19] 739 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_o1Ii1_RNIM7MGF1[0] 321 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[22] 474 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un9_l1Oo1_3 327 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loi01[9] 93 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[22] 448 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_valid 498 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][1] 763 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[6] 321 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[25] 707 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[24] 603 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_a2_4[28] 287 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII1118 138 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[6] 597 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0[31] 944 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOo11[0] 199 181
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i[2] 613 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_13 657 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[12] 515 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1141 739 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo_RNI5SKTK 267 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[12] 488 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1776_0_0 61 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0[13] 222 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[5] 597 196
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[1] 497 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3[7] 194 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8] 668 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIMV0B71[0] 165 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[2] 449 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[16] 279 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[30] 467 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[30] 993 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[20] 841 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[8] 741 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[3] 452 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[26] 480 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[12] 825 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[4] 412 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].un1_lIII110 478 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_25_RNO_1 944 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0Ii1 323 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[26] 738 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iOo 251 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[15] 357 228
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_42[4] 597 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[12] 529 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[3] 570 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[26] 885 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[0] 611 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_ex 753 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[27] 348 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[19] 932 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[14] 541 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1289 681 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_6[2] 771 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[3] 873 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[24] 603 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[5] 403 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_261 753 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1284 716 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[9] 116 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oOIi1 322 181
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[9] 500 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int[0] 775 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[12] 502 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3[12] 334 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_73 736 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[17] 837 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[2] 308 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[11] 211 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_trigger_wr_hzd_de_RNI1D18B 750 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_0_sqmuxa_0_a5_0_0 157 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.misa_sw_rd_sel_8 836 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un230_lIlo1 318 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[28] 464 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[2] 190 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[13] 726 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[5] 214 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0_1[0] 968 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i1I11_2 358 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[14] 716 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[31] 797 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[28] 460 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[11] 542 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOO11 73 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[2] 236 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[24] 838 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid 809 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_8_RNO_1 871 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_1[0] 654 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIFK8GO[24] 876 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[20] 918 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_s_0_RNO_0[0] 812 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_16_110_a2 294 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[16] 929 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[2] 832 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oO111[2] 215 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_RNO 606 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[6] 791 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[9] 124 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_0 797 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_17 697 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[8] 864 130
set_location COREFIFO_C0_0/COREFIFO_C0_0/re_set 468 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[14] 251 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_163 745 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[0] 399 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[3] 213 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[16] 279 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[12] 146 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[33] 464 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_o2_1_0[28] 286 174
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[11] 42 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[3] 148 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[11] 116 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[20] 879 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[3] 318 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_878 643 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[17] 575 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor_RNO[47] 958 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[6] 32 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[21] 722 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_835 640 213
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_7 54 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv[6] 127 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/IilI1 392 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[8] 268 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[35] 314 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[7] 838 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI1UT441 862 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[2] 409 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[21] 848 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_253 669 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[11] 281 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_12_RNO 446 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[6] 918 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_150 755 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[1] 591 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_17_RNO_1 944 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[4] 798 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[9] 148 193
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel_RNO[3] 531 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[49] 936 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[6] 848 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[4] 793 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[4] 886 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[17] 374 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[15] 234 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[27] 945 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_707 811 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0_iv_1[0] 759 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[26] 470 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un141_I1Oi1_1 68 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[21] 296 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[30] 474 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[2] 423 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[31] 465 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_12 780 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_341 669 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[14] 113 177
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv[3] 610 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_346 694 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0[22] 225 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0_a2_1_0 102 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[17] 259 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_55 620 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[18] 1006 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[4] 544 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[18] 879 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5[2] 672 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[24] 742 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[31] 797 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/IilI1_RNO 405 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[14] 361 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24[8] 351 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l1ll1_1 472 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2_0[0] 167 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[9] 607 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_IlOI18_1 319 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ooOl1 449 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_O1Ii1_5 414 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[5] 381 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[6] 763 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIll1 534 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[8] 182 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[4] 490 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[5] 572 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[16] 329 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[5] 252 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_34[0] 286 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_809 655 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1 270 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_ft_1 427 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[30] 914 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[19] 472 241
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_13_RNI74QUEO3 807 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[0] 549 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01[2] 283 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[26] 826 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a1_0 782 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[0] 46 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[7] 75 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_0 99 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[16] 474 243
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_OOio1_2 107 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/un1_cpu_d_req_ready 691 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo[2] 142 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[2] 174 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_319 668 219
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0 0 377
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1023 698 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un26_sba_req_rd_byte_en_int_i_o3 734 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[21] 605 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[10] 313 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[22] 875 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_11_RNI30OUEO3 795 171
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[28] 480 243
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2124_1 667 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[5] 318 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_43[0] 360 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_2 284 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[2] 30 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[17] 262 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_0 872 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI5VEGI[0] 369 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[11] 823 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13[3] 790 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIFGDL9[11] 271 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[25] 308 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[18] 766 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un2_Oo001_2_1 195 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1[0] 470 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[29] 502 172
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[15] 485 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iloi1 330 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m15 116 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[22] 766 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i_RNIC365VM 823 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_I1Oi1 39 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O00o1_f0[2] 76 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[6] 176 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct 609 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loII1_cZ 266 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_271 644 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[24] 612 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[5] 196 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[29] 833 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_5 442 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[3] 373 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[10] 152 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[11] 97 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNISSBTF[5] 822 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_395 642 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[27] 690 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_3 57 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2[2] 722 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[8] 572 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[8] 856 160
set_location PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3 1153 162
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[3] 788 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[6] 457 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_d[0]_0_sqmuxa 614 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7A984[12] 909 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_19 942 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m71_1_0 141 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[28] 904 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_6 225 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[15] 848 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[30] 480 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[6] 177 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto3_0 209 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_7 307 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_fence_1_i[0] 754 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[8] 416 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.IloIo 322 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[2] 472 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[16] 649 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[24] 245 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3[0] 164 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_0[2] 717 156
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[5] 462 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_2_a3_1 790 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[0] 471 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[24] 958 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[14] 361 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_173 752 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01[2] 303 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[12] 540 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[4] 861 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[0] 184 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[0] 777 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_718 644 186
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[29] 468 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO_0[1] 823 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[3] 322 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_662 631 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_24 680 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[31] 364 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[9] 659 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[4] 281 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed[2] 726 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[10] 659 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_567 711 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0[1] 75 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[1] 145 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[20] 850 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[2] 382 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[5] 181 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[21].BUFD_BLK 633 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_354 739 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[31] 396 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_5_ac0_3 46 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[2] 785 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[22] 618 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state[2] 764 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[2] 186 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[17] 843 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IOoOo 219 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[17] 720 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[10] 370 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[31] 716 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[10] 429 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[0] 241 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo[0] 284 190
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m16_2 514 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places57 919 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[19] 461 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[3] 574 171
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5[6] 497 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3[1] 778 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[4] 255 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[3] 298 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_2_0 55 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un13_lolIo_1 58 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[7] 920 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[5] 342 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4] 708 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_437 706 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0_1_0[0] 386 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un11_csr_trigger_wr_hzd_de_5 743 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_c2 309 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[4] 719 133
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_parity 536 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0[3] 44 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[4] 419 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[13] 945 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[4] 85 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0o11 404 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_12[0] 286 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[1] 484 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[11] 468 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[30] 893 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[25] 943 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff 756 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OIoOo_1 231 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[0] 311 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[3] 208 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/IilI1 391 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[5] 412 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[12] 787 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_15 716 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2122_1 667 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[3] 334 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo[0] 383 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[6] 368 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[16] 295 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2] 662 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_2_sqmuxa_i 754 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv 722 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKX1[0] 734 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8[4] 860 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[0] 858 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_9 754 147
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[14] 57 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[15] 622 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[12] 894 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[23] 751 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_2_N_2L1 732 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[7] 556 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[1] 470 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[29] 753 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[11] 913 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_805 775 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3[1] 556 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_1_sqmuxa_i_0_m2 738 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0[0] 980 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNI8EFAU 110 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[1] 884 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un10_mul_mp 803 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[27] 626 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27[2] 417 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[26] 826 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[3] 487 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[6] 752 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[9] 896 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_817 695 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14[11] 983 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[2] 532 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_0_3_1 819 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[9] 432 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[5] 956 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr_s_s_RNIA0DB32 818 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OIOl1 427 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv[6] 712 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1_a3[27] 871 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[5] 782 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[8] 137 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22[5] 405 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x2[2] 193 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[3] 420 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35[5] 346 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[3] 253 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[1] 475 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_19_1_0 688 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_17_0_RNO 845 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIFLM4C[8] 698 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[4] 886 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[3] 156 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_925 824 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[7] 358 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_2_a2 831 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[4] 537 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1_RNIPTG3A1 785 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[2] 447 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[12] 101 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.l0li0 426 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[5] 286 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[2] 538 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[43] 818 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_26[1] 356 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[12] 547 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[4] 431 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[5] 233 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_RNIP78KK 630 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[32] 403 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[7] 204 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[26] 861 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_d_0 807 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5[1] 680 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0 829 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2_8_1 663 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_shifter_unit_op_sel_ex7_RNI2Q7JDU3 763 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[2] 372 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[7] 256 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[35] 352 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_520 728 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[9] 310 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[7] 417 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[0] 155 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a0 759 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_RNO[2] 82 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[19] 525 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][17] 881 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[21] 842 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loo11 456 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_187 691 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[28] 887 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[26] 806 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/gen_bit_reset.state_val_2196 822 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[2] 260 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr 817 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[12] 332 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[9] 814 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[4] 403 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[4] 199 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI1i1_i_o2[2] 382 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[22] 60 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/OloIo 515 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[31] 324 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOii1 146 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m14 140 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[21] 866 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1[15] 356 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[50] 949 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[11] 881 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[3] 97 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[1] 246 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[6] 772 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[7] 152 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un5_ool01 200 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2122 664 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto9 273 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lOo01 147 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13[0] 786 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[8] 957 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_672 687 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_14 68 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_sn_m4 824 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 482 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid38_0 760 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIAEA84[24] 858 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[13] 58 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[11] 336 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto4_1 264 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[4] 309 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[3] 338 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_577 760 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[21] 397 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1[5] 593 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[3] 708 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[52] 957 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOl11 345 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_7 738 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[6] 671 189
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[4] 76 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[7] 538 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result194_0_0_RNIOP1PQ 754 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[8] 569 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1 464 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/un1_Ioli0_1_0 412 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[9] 189 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m1_e_1 831 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] 511 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[23] 194 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_lOoi1 319 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_m_env_call_retr 753 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[9] 844 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[5] 332 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[21] 600 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[16] 904 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[26] 373 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_191 693 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[13] 383 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[6] 321 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[19] 522 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_784 794 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1 560 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0s2 500 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[2] 185 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m227 350 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_0[1] 225 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[30] 617 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_2_0_0_o2 273 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[13] 90 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[3] 446 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[16] 863 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[7] 803 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[0] 523 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[15] 571 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[7] 346 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38 762 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[2] 511 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[7] 204 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo52 82 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[3] 269 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[16] 446 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_2 392 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_392 814 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_1_N_3L3 694 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[11] 426 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[8] 333 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_4 218 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m29 117 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un99_I1Oi1_1 55 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_20_RNO_1 885 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[21] 876 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand0_mux_sel_ex[0] 836 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[28] 1005 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[33].BUFD_BLK 642 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_919 691 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[10] 920 145
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4[4] 40 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[38] 434 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[23] 898 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[1] 262 172
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[27] 469 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr[1] 836 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[7] 889 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_5 728 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a2_1[0] 668 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[13] 225 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[25] 130 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout_RNO 883 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_34[9] 285 213
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_6 427 3
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[6] 596 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNIKD30T93 799 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[0] 126 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[6] 513 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/i11l1 386 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1 494 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[9] 859 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3[6] 191 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol17 303 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[31] 674 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0[6] 635 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[3] 137 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[17] 453 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][19] 864 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_994 788 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m46 130 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNO[0] 764 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[11] 733 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[4] 236 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0iOo 238 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[3] 768 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[11] 380 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_OIiOo 296 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[8] 739 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_0 215 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[9] 746 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[21].BUFD_BLK 596 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[27] 269 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_sel_iv_0 777 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1062 667 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[1] 195 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oIlIo 265 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 506 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[4] 228 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[12] 956 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_407 677 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[14] 838 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1[15] 765 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_10 225 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_8[7] 825 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1295 823 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[33] 387 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val[2] 825 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[4] 370 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[1] 387 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[6] 814 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1215 689 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[15] 96 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[46] 592 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[2] 471 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_0_0[3] 146 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[5] 518 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNI5ILFJ1 776 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_2_RNI49B6991 784 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[20] 888 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[12] 349 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[1] 241 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[8] 767 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_5_u 592 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[19] 77 210
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[2] 558 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[12].BUFD_BLK 597 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[13] 775 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_shift_op_complete_ex 768 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_5_RNO_1 868 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01 382 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0li1 229 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[23] 550 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[3] 446 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un7_ool01[0] 186 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNIFA4LE[4] 785 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOIi1 231 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_branch_cond_2[0] 705 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[0] 860 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[4] 301 225
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[13] 499 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_o2 830 117
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_PADDR_3 389 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[8] 889 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[6] 198 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OlOOo_0_a3 111 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_reg4 787 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_683 704 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[2] 273 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIBIAGO[31] 895 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m1 34 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_28_RNIA1R0FO3 808 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_valid_sba_0_a3 802 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[7] 727 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo[9] 292 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[9] 569 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[8] 526 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[14] 503 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[12] 57 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[28] 692 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m4 682 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[25] 930 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIKVKJ31 847 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto4 224 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioi11 351 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_0 682 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.IOoIo[0] 366 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_fenci 838 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_RNO_0 207 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 508 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m17_1_1 661 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[3] 529 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_int_sn_m6_e 806 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[1] 319 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[14] 386 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_21[22] 224 225
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[0] 457 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[12] 692 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.un2_haltreq_debug_enter_taken 810 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/gen_bit_reset.state_val[0] 823 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_1 227 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/dcsr_rd_data[6] 831 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1_RNII91C63 791 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[2] 201 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[17] 853 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[10] 723 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.dcsr_debugger_wr_sel_1 861 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OO1i1 279 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNID63E9[10] 227 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0[9] 119 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_iv_0[10] 717 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/un1_iOI01_1_i_0 371 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2[4] 342 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[12] 537 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[7] 856 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0] 696 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[23] 884 138
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_cZ[2] 594 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2129 669 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[8] 411 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_a2_0 764 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_valid 810 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[19] 739 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 302 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_8_0_RNO 855 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[15] 906 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[22] 982 165
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/make_parity_err.parity_err_12_iv 517 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12[8] 345 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[10] 378 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_reg4_RNIL4ELG 713 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_416 813 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_3 204 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid34 826 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_14_0_RNO 866 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1 231 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q[3] 603 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1o11_1 360 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_1[0] 95 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[31] 923 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[4] 235 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001[3] 175 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[13] 399 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[3] 183 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_trig_pipe_reg_ex_retr.ex_retr_pipe_trigger_retr[0] 807 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[34] 489 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[10] 250 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[11] 970 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[19] 916 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[40] 707 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[23] 861 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[14] 394 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[17] 358 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[8] 199 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[3] 728 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[22] 730 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[23] 836 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[23] 834 126
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt_RNIBKVI3[0] 17 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO[4] 229 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un16_I1Oi1_1 45 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[32] 628 168
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv_RNO[4] 606 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNIDEGQM92 771 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[2] 466 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[3] 570 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_q_1.CO2 611 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[4] 695 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1_RNO[20] 276 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic851_2 644 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo[0] 315 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[1] 128 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_933 681 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_26[0] 349 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[19] 742 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[7] 429 202
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/un4_update_dout 496 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[11] 885 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[22] 919 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[22] 648 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os_RNI6C8RFN 819 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3[6] 994 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[17] 755 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][3] 759 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a3_2 655 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1i01_0_o2 111 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 293 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[28] 480 244
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[0] 481 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[1] 166 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[7] 117 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30_2[31] 924 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val[0] 632 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[3] 958 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[5] 494 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9] 675 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[6] 489 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[16] 768 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[0] 74 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[4] 73 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[2] 343 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[4] 480 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[1] 627 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2_RNO 648 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[28] 958 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[4] 295 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_594 676 198
set_location Core_reset_pf_0/Core_reset_pf_0/dff_1[0] 834 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0[0] 57 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[4] 372 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1oo1 69 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[29] 755 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_81[11] 276 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[8] 213 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[54] 964 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[7] 232 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2_0[8] 297 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1[6] 141 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[22] 658 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[4] 290 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_s_RNIQR5JU1 825 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[3] 285 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[27] 498 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[17] 379 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1245 733 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[1] 357 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI1RGO04[0] 144 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4[0] 185 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[23] 921 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_15_0_RNO 885 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[17] 668 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[12] 158 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[6] 78 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un21_gpr_rd_rs2_completing_ex 890 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[15] 282 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel7 594 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[25] 773 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[6] 379 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[17] 616 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[3] 872 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[22] 666 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[30] 968 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I0Ol1 410 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[16] 48 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0[0] 184 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[26] 722 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[5] 746 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[0] 163 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel[4] 573 208
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_ns_0_0[0] 21 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[13] 708 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[27] 969 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[11] 430 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo 307 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[26] 427 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt[1] 611 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[5] 280 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m80 140 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[4] 296 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[6] 289 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_559 704 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNICIUT5 392 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[19] 72 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iO0l1[0] 495 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_req_count_i 802 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write_8.m5_1_0 509 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[18] 820 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[1] 488 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_1_4 419 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_o5_0[0] 666 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[36] 396 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[20] 444 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][4] 866 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[12] 213 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[24] 272 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[13] 359 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[25] 840 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_182 715 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[54] 633 175
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/txrdy_int_1_sqmuxa_i 532 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_empty_0_a2 749 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[0] 720 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[8] 187 190
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_1_sqmuxa_i_o2 9 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1 792 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l00o1 46 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_rd_ptr[0] 780 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[1] 157 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIl11 265 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[9] 502 253
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[6] 264 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_9[0] 905 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un11_ool01 191 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[7] 505 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_2_sqmuxa 34 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[10] 429 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[1] 381 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[13] 848 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[9] 681 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[19] 670 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIiOo 212 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un36_l1I01_1 381 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m3_0_a3_2 807 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1031 722 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_4_a0_RNITCNU673 823 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[10] 729 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa 570 210
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[10] 42 229
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[5].BUFD_BLK 572 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[9] 439 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_581 693 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[7] 649 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[0] 628 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1l1_u 492 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[1] 824 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iOo_0_0 233 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[12] 789 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIL72R7[11] 80 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[4] 351 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1 472 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[28] 981 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[12] 287 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OioOo_11 227 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[15] 561 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[4] 635 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1 756 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/haltreq_debug_enter_taken 809 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[25] 613 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNI73I4J[10] 509 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[9] 339 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m54 297 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[29] 500 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[0] 314 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un22_o1Oi1_4 74 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[31] 900 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[18] 477 192
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_code_upd 14 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[16] 896 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv_i[0] 680 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv[33] 729 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[15] 837 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[12] 621 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_6 774 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[24] 680 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNIE6MPA 312 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[3] 226 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex[2] 859 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_684 727 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[1] 845 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[12] 345 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[13] 518 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[20] 846 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[24] 710 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.i4_mux_i 28 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_2_0_0_o2_0 247 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[6] 385 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i10l1[0] 523 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[14] 911 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[9] 705 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[8] 250 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[12] 980 177
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext_1_0[4] 604 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1231 687 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[30] 795 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[4] 315 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1l11 290 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i1oo1_RNO 101 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[3] 719 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_593 669 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[27] 684 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[28] 872 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/trigger_debug_enter_taken 804 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[21] 934 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un5_I0i01_0_a3 117 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[21] 729 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[16] 357 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[9] 292 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[23] 270 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[23] 823 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13[0] 775 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[4] 311 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[20] 708 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_13[22] 223 225
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b[1] 19 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[10] 278 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u_2[9] 957 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[26] 808 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[24] 953 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_2[3] 552 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[19] 683 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[13] 331 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[6] 67 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[30].BUFD_BLK 645 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[22] 392 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un22_OIoO1 106 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m10 117 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_exu_mux_result27_1 749 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_987 787 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[7] 134 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_922 705 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[1] 169 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[1] 185 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en_1[2] 716 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[24] 981 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_755 761 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIU7FO8 358 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1[0] 280 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_535 746 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0[8] 232 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[10] 842 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[27] 835 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_3_5 489 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[13] 484 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[19] 931 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[22] 447 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[10] 416 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[1] 786 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_1 847 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o11I1 365 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[4] 995 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_i0iIo 506 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i 751 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2124_1 653 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_4 679 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1[1] 958 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/N_822_i 258 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[28] 396 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_11 624 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[8] 203 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[6] 77 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[3] 292 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ilio1_1 92 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[5] 439 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un17_start_div 817 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[60] 645 166
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_2 591 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864 1152 162
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1181 709 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[1] 659 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[18] 908 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNIMDE88[10] 94 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO_1 244 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[8] 310 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[44] 600 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[29] 280 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[9] 469 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[41] 232 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_1_0[3] 705 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][24] 883 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[0] 796 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1[0] 214 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[20] 448 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m106 354 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[3] 955 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[16] 859 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0[6] 86 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0_0[1] 651 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNINS8GO[28] 897 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[2] 770 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[1] 507 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[11] 261 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[25] 847 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_2_0_tz[1] 91 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_903 771 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_17 704 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter6_3 897 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[13] 655 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_85[11] 347 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0[2] 91 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[19] 594 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[13] 590 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ol1i1_0_a2 378 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[26] 764 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[7] 410 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/i1111 395 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_658 646 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[7] 428 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/rd_data 789 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[0] 185 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[6] 245 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[20] 424 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[0] 168 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[0] 52 220
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa 606 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex 760 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[19] 460 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[3] 780 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[2] 882 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO[1] 604 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_q1 607 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[5] 774 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un4_cpu_i_req_is_apb 797 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_OIoO1 127 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[31] 804 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[3] 528 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[4] 155 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_13_2 664 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[3] 840 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[4] 340 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[9] 538 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un33_Oo1Io 490 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m10 127 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[3] 281 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1_RNO_1 255 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[14] 717 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[9] 128 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[30] 750 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[12] 847 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[2] 568 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_92 644 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_3_f0_i_a3_RNO 797 117
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_19 60 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_596 752 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un15_buff_resp_head_compressed_0_a2_1 707 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_4 104 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_0_a0_0 823 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[4] 205 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[12] 679 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOiOo_0_a2_0_1 224 177
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0_a4_4[0] 8 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_482 680 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i11Oo_0_o3[3] 211 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[28] 738 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[4] 140 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_77 726 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_5 345 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_o2 693 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[1] 729 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNILC68E[17] 727 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_47[11] 281 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_21 865 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[3] 294 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[8] 114 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_o2 269 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[3] 386 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[63] 839 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m19_1 707 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[0] 842 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[26] 806 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[10] 240 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int_0_sqmuxa_0_a2 524 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1_RNI1G1DG[15] 513 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[5] 220 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo[1] 271 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_1 407 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0_RNI1BODTC1 777 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[9] 312 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[15] 244 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[7] 198 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[13] 299 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[14] 642 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[10] 110 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2[0] 836 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][1] 756 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[0] 181 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[9] 368 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ooo01 92 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[9] 172 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m6_1 56 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNIS43M53 177 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[37] 721 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[14] 862 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[12] 983 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[19] 873 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[16] 263 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[23] 873 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][2] 778 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_places_1_.m9 715 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[0] 651 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/un1_iOI01_1_i_0 285 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21[12] 409 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_0[11] 398 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3[2] 321 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv_RNO[8] 693 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I01 337 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1239 679 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[2] 417 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[1] 266 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[4] 198 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[1] 196 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1[2] 343 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un7_ool01[5] 194 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[5] 417 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooOIo 236 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[1] 246 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1234 762 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[1] 510 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIOOo_1_i_o3 117 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[30] 406 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[22] 849 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[25] 846 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1l11 322 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_461 751 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[19] 814 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[0] 372 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_762 628 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[32] 635 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[9] 319 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[7] 370 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[21] 873 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[15] 356 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_347 646 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15 208 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3[2] 177 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff13_i_o3 766 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_RNO[11] 313 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[12] 424 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[28] 163 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[9] 322 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a2_0 253 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][12] 893 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_216 692 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25[2] 410 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[12] 260 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIGC0D6[2] 419 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[18] 861 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un9_Io001 193 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_1[2] 617 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[38] 819 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[9] 320 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[25] 750 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[9] 510 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[9] 885 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[9] 292 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3[12] 109 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_1_sqmuxa_1_0_a3_1 778 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[3] 243 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv[28] 722 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1 237 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[7] 349 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type[9] 813 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOl11 325 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo[6] 160 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_o2_1 692 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[5] 207 172
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[10] 19 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_2[5] 330 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[23] 450 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_6_0_a2_0[0] 858 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel[0] 34 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[3] 183 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[11] 527 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_6[8] 129 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[28] 806 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo[2] 67 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[4] 457 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[5] 817 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0[23] 173 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_25 762 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[26] 837 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[7] 223 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[14] 263 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIUSMI5[3] 225 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[7] 930 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[10] 115 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[12] 396 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[22] 555 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_o1il1 508 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[23] 783 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_accepted 715 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[8] 970 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[2] 299 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lOi01 72 178
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO_2 495 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_410 741 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[26] 906 198
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc4 13 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[18] 919 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[0] 311 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[37] 426 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_RNO[8] 186 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[33] 790 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[2] 250 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[1] 337 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[25] 734 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/IilI1 382 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[2] 504 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60[4] 979 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_61[11] 347 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_505 708 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[6] 307 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[12] 531 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[3] 241 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m155 374 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[63] 640 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_381 722 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_386 740 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[3] 253 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[5] 310 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold[1] 621 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_d 769 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[28] 750 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_9 633 198
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[23] 60 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[3] 301 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2[0] 678 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3[4] 188 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[9] 198 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.per_trigger_debug[0] 807 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[8] 66 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956 696 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[38] 627 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[0] 178 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[7] 285 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[14] 251 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv[12] 765 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[2] 861 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[9] 128 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[3] 499 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[2] 258 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m10 517 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[2] 310 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[17] 874 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[5] 893 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI44QTM1[0] 164 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[6] 333 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[7] 305 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[7] 182 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1[16] 320 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[6] 485 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[4] 209 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0[3] 722 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_7_RNO 810 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_750 668 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_IoOi1_0_a2 246 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO[0] 714 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[2] 371 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[16] 215 217
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[24] 487 243
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit_3_1 607 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI4LNGA_0 821 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_8_i 756 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0[3] 244 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[1] 371 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo_1_0 207 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[14] 236 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[3] 425 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m_0_3[0] 811 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[11] 968 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[31] 492 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001[0] 195 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[4] 672 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[7] 548 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[23] 459 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_15 789 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m0_i_a3_0[0] 733 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[2] 195 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[7] 772 120
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[11] 47 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[0] 210 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1] 780 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[4] 921 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/ssel_rx_q1 598 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[5] 310 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oll11 320 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[5] 471 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[3] 874 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_7 267 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[24] 658 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[4] 485 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[4] 367 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/data_rx_q2 607 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[28] 477 168
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[5] 507 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[0] 183 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[22] 1004 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[28] 477 169
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[2] 16 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv[1] 730 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[17] 594 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[28] 923 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[14] 515 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[14] 601 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[7] 381 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[7] 111 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[8] 661 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[1] 271 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[5] 427 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op[1] 736 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[19] 764 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[4] 373 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un8_l00o1_1 41 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_6[13] 114 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[9] 842 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[51] 594 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize 600 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_329 712 225
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit[3] 525 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[12] 548 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[6] 192 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][7] 885 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[23] 899 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[5] 864 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1053 767 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[2] 861 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb 799 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oloi1 254 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[25] 835 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/N_308_i 781 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_471 665 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[14] 717 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_75 680 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_772 786 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[4] 198 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO_0[0] 155 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[9] 102 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[1] 429 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto15_1_0 243 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[3] 745 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[7] 367 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m6 668 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[9] 600 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[26] 481 244
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[0] 605 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_5 680 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[26] 763 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[17] 561 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[28] 718 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[11] 271 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_strobetx 573 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[25] 398 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[10] 234 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[6] 408 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3[5] 98 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[24] 807 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[3] 301 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1092 656 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[11] 560 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[16] 894 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_RNO_3 224 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_7 223 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[10] 378 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1012 729 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_10 711 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[30] 447 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0_a5_0_1 179 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][3] 768 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[30] 652 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[10] 212 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[25] 897 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_ss0_0_a2_0 773 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_2_3 801 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_RNIV073C[1] 697 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/un1_Ioli0_1_0 293 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_17 54 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[20] 545 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[14] 1002 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_699 705 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[29] 835 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[4] 792 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_u[0] 933 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk2.un5_iOiIo 457 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[17] 857 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_0 380 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ[12] 400 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/wr_en_data_or 816 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_str_req_buff_addr_misalign_u 706 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[1] 465 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[14] 117 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[14] 205 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_8 249 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[5] 377 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_3 322 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_80 724 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[4] 229 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[4] 315 222
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[9] 622 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[4] 828 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[4] 421 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1 785 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[22] 486 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un528_lIlo1_2 231 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_728 696 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[3] 631 154
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa 560 207
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[10] 65 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I01_2 337 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[7] 486 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[18] 873 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_98 641 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m28 746 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[10] 559 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_3[13] 96 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[15] 380 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[11] 270 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[14] 721 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[13] 606 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid33 816 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m7 46 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[59] 630 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_rxfifo 602 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_1398_i 811 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[4] 225 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_1 588 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[7] 406 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_autoincrement_ff_3_i_m2 764 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un26_Oo1Io_0 489 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_is_subsys_hart_soft_reg 789 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_16[20] 202 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_2[0] 97 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_35[9] 310 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO 238 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c_RNI9BM3B4 789 135
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[0] 474 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/dpc_rd_data[1] 872 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[7] 568 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.gen_per_trig_tdata1[0].machine_sw_wr_tdata1_mcontrol_execute_wr_en_0 860 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[16] 863 151
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[27] 469 243
set_location fifo_to_tpsram_bridge_0/state_ns_i_0_a2_1_RNO[0] 475 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[25] 732 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[17] 298 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_RNI62P334 788 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[23] 811 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/IilI1 404 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM[1] 21 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1071 681 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[3] 360 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[3] 43 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[12] 338 187
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[2] 17 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_65[11] 375 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[21] 874 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Io111 267 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[14] 365 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[9] 205 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[21] 799 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[23] 835 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[9] 818 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[3] 442 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[3] 88 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[7] 80 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[11] 775 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/havereset_skip_pwrup 818 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[12] 276 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[0] 295 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13[2] 770 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iiO11 148 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2 783 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[26] 675 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[9] 228 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[7] 367 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[15] 212 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[21] 543 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/il1i1_0_a3_1 390 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[3] 154 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4[2] 881 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[8] 909 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1[2] 341 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[8] 542 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[3] 181 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[7] 338 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[18] 761 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[5] 185 186
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[14] 495 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/OOlo1 290 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[15] 954 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[2] 922 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[24] 838 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[4] 261 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[9] 202 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oooI1_1_1 453 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_0_sqmuxa_0 165 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[7] 983 153
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error 496 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[17] 865 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[9] 261 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_a3_1 272 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_ioIO1_1 154 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1[6] 1001 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_first 604 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_RNI0LOMD[1] 698 126
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[0] 626 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1271 746 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[6] 546 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[12] 503 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[17] 334 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_2_2 344 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[2] 458 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[26] 744 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[11] 792 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[14] 718 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNO[1] 765 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[9] 549 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[13] 67 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state[3] 758 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_827 715 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[22] 393 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[4] 340 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[3] 513 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex6 779 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[8] 668 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[29] 871 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[6] 476 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[7] 691 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM[3] 175 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[11] 526 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[10].BUFD_BLK 632 126
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_3 630 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[14] 331 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[36] 403 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[30] 731 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_O1Ii1 315 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[6] 869 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_2[8] 137 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[7] 45 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_7[10] 294 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv_1[7] 692 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_22_RNO_0 873 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[2] 332 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOol1 404 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[5] 800 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[14] 285 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_o2_1_0_o2_0[15] 271 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IiI11 321 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0]_3[3] 743 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3[7] 860 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[6] 872 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNINIKV4[0] 238 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[12] 349 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[31] 734 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[27] 390 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O1lIo_1_0_.m6 133 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[2] 483 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[8] 363 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[15] 496 211
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata[0] 597 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[8] 970 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[5] 423 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[15] 125 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[11] 235 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[5] 557 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[45] 559 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/IilI1_RNO 397 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1042 735 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[29] 632 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[28] 471 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[6] 450 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand0_mux_sel[0] 667 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[1] 695 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_0_RNI63HIUN 779 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr_s_s_RNIEE3QL 819 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[18] 760 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[2] 67 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_inhibit_ex_RNINO19L 738 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[3] 874 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_2_4 107 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_8 776 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1260 725 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[3] 955 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[2] 824 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[6] 653 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[2] 716 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_78[11] 285 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[5] 876 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[8] 520 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[9].BUFD_BLK 607 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[4] 329 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olOOo 141 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un9_cpu_d_resp_valid_sig_1_0 792 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un13_OIoO1[4] 115 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[13] 830 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[13] 713 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[5] 161 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[18] 294 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1[7] 383 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[9] 458 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[9] 469 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m26 678 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_fault[0][0] 770 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1[31] 412 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[15] 349 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[8] 412 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[2] 708 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[1] 568 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2114_1_2 655 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[10] 650 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_615 777 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_clock_int 496 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4[6] 196 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[7] 272 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[22] 846 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[4] 751 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[15] 252 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[6] 345 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a2_0[2] 681 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[10] 295 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI1i1_i_a3[0] 381 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21[8] 354 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.I0li0 425 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[42] 395 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un1_oOo01 82 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[12] 102 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[15] 125 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[2] 310 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1[0] 83 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[23] 333 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[9] 698 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[5] 342 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3 835 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[24] 906 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val[0] 820 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[2] 511 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[13] 314 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result194_0_0_RNI4TU1TD 821 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places[3] 920 165
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state[1] 513 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[2] 329 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[1] 562 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[8] 416 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2[4] 717 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_0_0[0] 717 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[3] 230 196
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9_4_1 609 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI45Q5C[18] 721 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[13] 522 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[30] 802 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[11] 419 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[1] 98 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m67_0 293 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_3_RNO 939 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_17 796 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_13_RNO_0 843 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[18] 727 138
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_parity_err_0_sqmuxa_2 516 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[7] 542 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un6_OoI01 306 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[3] 370 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un31_next_quotient_0_a2_0 887 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_sig_0 801 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[1] 728 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[11] 820 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_retr_d_d_0_RNIMQNPK 826 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNILF98E[26] 672 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_929 722 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[3] 481 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[0] 735 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[9] 343 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/IilI1_RNO 382 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_2[1] 662 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_8[11] 823 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0[2] 193 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_28_0_RNO 883 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/clk_en_dm_cmb_i_0_a3 846 123
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[13] 49 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[8] 377 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[3] 385 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[5] 234 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[0] 708 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[0] 336 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[13] 950 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[63] 640 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[5] 521 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[6] 518 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[5] 527 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[1] 372 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_IloI1_1 481 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo[3] 181 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[3] 357 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m13 33 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_c 770 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/ebreak_debug_enter_taken 813 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_data[1][0] 786 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[12] 683 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1279 738 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[2] 455 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2[27] 982 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[26] 850 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1163 692 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[25] 817 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_0 678 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1274 691 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o2[3] 188 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_9[0] 303 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[14] 81 195
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc6 23 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[8] 189 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_3[31] 728 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[15] 911 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[22] 799 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[4] 875 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[5] 819 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_3 237 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[13] 284 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[18] 91 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[5] 211 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[27] 895 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[28] 909 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[32] 398 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[4] 719 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_14 721 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[10] 508 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[10] 56 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_6_RNO 854 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[10] 854 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_1[3] 619 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[27] 767 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[29] 842 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0_1_0[0] 308 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_12[9] 308 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[14] 387 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21[7] 360 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[23] 940 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[9] 200 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[5] 434 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[27] 899 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39[4] 368 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0[12] 221 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[7] 309 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[7] 260 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[2] 413 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[15] 594 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[10] 227 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_2_0 45 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[31] 494 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l1ll1_0 486 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[12] 26 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[14] 882 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_Ooo11_1 400 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO[8] 932 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[27] 499 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_20 864 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2 684 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un129_i11Io 512 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[6] 533 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ili11 428 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[20] 729 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[8] 803 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_m1_e_1 815 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI1UT441_0 861 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[0] 333 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0 178 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[16] 763 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[0] 272 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un159_I1Oi1 65 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[8] 869 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[18] 722 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_2[4] 679 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[4] 441 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[16] 772 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[8] 182 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[13] 257 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_4 701 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[37] 433 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1005 690 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[2] 312 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un9_next_exu_result_reg_int 826 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_12[10] 280 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[1] 482 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[19] 981 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un13_instr_is_lsu_ldstr_ex 711 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[7] 54 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[15] 128 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[3] 204 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[2] 212 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO 73 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_345 703 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[8] 236 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[0] 407 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_addr_align[0]_3[1] 763 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4] 698 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_implicit_pseudo_instr_ex_2 743 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel_RNO[1] 533 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4950_0 687 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[9] 548 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_26[3] 357 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[12] 246 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[27] 932 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0Ii1 294 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[16] 618 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[10] 267 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_1_N_2L1 678 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_2[22] 222 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[3] 378 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1285 706 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[5] 198 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[1] 197 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNI0AFO8 419 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[9] 54 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[5] 185 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2121_2 666 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[43] 254 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[26] 981 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[9] 711 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[5] 449 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[6] 516 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a3_0 691 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[6] 342 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[2] 192 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_254 666 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[1] 72 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastbit 569 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[41] 402 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3] 719 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0IO1 107 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[8] 659 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_40[8] 967 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[8] 892 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[1] 278 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m8_a1_0 788 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[4] 185 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[2] 455 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[7] 179 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1309 735 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1203 702 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILBRQ8[13] 736 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_uncompressed_full 711 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[7] 234 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_1 806 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[25] 899 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_c_0 793 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[1] 656 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_0_1 764 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mepc_rd_data[7] 851 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[4] 818 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[22] 393 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[23] 620 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_complete_ex 770 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[27] 894 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[12] 491 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[0] 321 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un18_Oo1Io 488 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_426 681 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_0_sqmuxa 925 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[5] 510 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_operand_sel_ex[0] 729 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oIl01[0] 96 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[0] 168 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2[8] 886 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[35] 527 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[14] 900 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[3] 170 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[12] 764 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[30] 767 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[4] 112 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[24] 388 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[6] 120 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata2_sw_rd_sel_7 850 138
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_bitsel_1.CO1 570 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[5] 504 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[30] 457 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[0] 301 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_0[1] 108 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_m13 596 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIo01_i_o2 112 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[12] 247 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[2] 352 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0[4] 54 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[7] 210 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[4] 603 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[18] 709 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[9] 225 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[16] 78 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[0] 734 132
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_par_calc.tx_parity_5 536 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[17] 407 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[9] 401 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[2] 273 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[21] 686 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_8_RNO 461 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2[8] 125 204
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_23_RNI27LRM 67 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO_0[3] 160 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_rd_ptr_0[0] 767 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[1] 872 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/IilI1 358 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[5] 250 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_1_sqmuxa 725 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[5] 211 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[26] 942 196
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_URSTB 571 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[1] 187 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[27] 460 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[10] 431 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[5] 514 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001_RNO_0 198 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[23] 752 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[23] 455 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lii11 358 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[9] 181 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[4] 573 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[6] 323 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_10 346 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oOIOo 139 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1[0] 229 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto8_1 236 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_14_RNI96RUEO3 796 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[29] 885 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[3] 755 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[26] 478 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[32].BUFD_BLK 619 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4[3] 652 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNI5HTC1T1 845 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[28] 619 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[8] 277 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[10] 294 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_o4[5] 297 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[28] 745 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1[29] 334 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1 407 168
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[3] 496 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_tz_tz 831 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[23] 734 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.N_2_i_i 32 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[0] 97 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[6] 344 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[11] 119 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[29] 887 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[18] 944 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[1] 210 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[1] 184 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1 761 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[6] 415 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI1o1_i_0 105 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q0 754 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[4] 994 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[12] 828 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.step_debug_enter_pending 767 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[20] 423 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[5] 837 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_363 705 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[24] 310 166
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[7] 33 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_1_RNISHFFMD_0 931 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[8] 801 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_0_sqmuxa_0 177 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state93_2 606 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIV8FO8 369 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_c_RNI21GQO6 751 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1060 685 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_RNO_0 767 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[6] 654 166
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2[1] 475 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_7 144 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[23] 860 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[5] 187 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_RNO[1] 14 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_5 707 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12 747 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[8] 800 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_213 668 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[18] 721 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[19] 756 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_hword_high_only_u_i_m2 887 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftIR_0_sqmuxa_i 658 132
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[19] 472 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[17] 270 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIi01[3] 99 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[6] 202 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_110 656 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[19] 720 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[8] 785 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[4] 308 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un9_cpu_d_resp_valid_sig 793 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[3] 810 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[22] 555 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[5] 187 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_I1o11_2 332 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_iv_tz[0] 726 171
set_location fifo_to_tpsram_bridge_0/next_state11_28 487 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[55] 970 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[4] 168 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_94 747 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 230 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[3] 373 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[23] 892 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[3] 66 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel 826 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.SUM[3] 199 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand0_mux_sel_u[0] 735 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_20_RNO_0 884 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[31] 716 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1 317 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[5] 859 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIK1L9D 790 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[14] 66 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un3_cpu_i_req_ready 784 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3[11] 846 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OlO11 84 177
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE17_2 7 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_1 286 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[24] 475 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[34] 419 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1[29] 860 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[29] 354 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_set_wfi_waiting 781 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1266 716 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7[8] 60 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un38_OIoO1 130 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[31] 496 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr[1] 884 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/un1_iOI01_1_i_0 318 231
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc2 605 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/O0lo1 374 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1 378 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OioOo 225 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[10] 212 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[4] 533 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[5] 432 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0[14] 129 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_3 307 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[4] 885 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[30] 875 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto9 240 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[31] 297 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[11] 460 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[15] 778 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[0] 325 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_36 870 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_141 690 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[0] 82 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[5] 220 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_2[18] 189 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_28_RNO_0 942 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2_0 777 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[3] 343 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[8] 417 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_I1oo1_3 124 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_1[4] 762 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/reg_write.tx_hold_reg4 511 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[13] 860 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_o2_0[2] 751 132
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[0] 47 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[1] 203 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[9] 205 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_lIII110_4 476 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[7] 412 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0[12] 131 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u[8] 956 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr[1] 830 118
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_req_count_i_RNIU964N 822 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNIQUT5C[31] 678 192
set_location Core_reset_pf_0/Core_reset_pf_0/dff_6[0] 833 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate[2] 657 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_342 654 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/io1Io_RNO 342 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite_5_0_0_127_i_a2_i_a2_2 690 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[3] 543 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[6] 175 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0iIo 572 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un93_I1Oi1_1 53 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m56 154 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[1] 306 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[32] 484 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_RNO 215 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[0] 400 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2131 666 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[1] 802 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_232 765 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[25] 476 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[13] 763 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNIE5T6F[1] 784 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[23] 834 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un47_ool01_1 188 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[26] 874 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[1] 889 133
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO 502 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[20] 933 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0ll1 312 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0[5] 291 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[1] 883 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[4] 114 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1131 706 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[4] 847 195
set_location Core_reset_pf_0/Core_reset_pf_0/dff_7[0] 832 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[18] 505 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[2] 573 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[28] 871 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[9] 761 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[1] 857 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[25] 872 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto4 207 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[11] 568 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[27] 420 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[3] 169 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[11] 115 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIS5FO8 372 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2[0] 478 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[62] 646 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[19] 50 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_944 715 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[7] 750 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_tz[5] 743 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[3] 357 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_39[2] 366 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[3] 899 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[5] 367 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[0] 334 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[5] 259 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[21] 389 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0[0] 694 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[22] 615 172
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0_a4_0_1[0] 42 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[11] 845 141
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[4] 594 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[14] 260 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[27] 456 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIDJUT5 355 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO[4] 228 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23[12] 401 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI101[0] 99 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[17] 657 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[14] 590 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[23] 445 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[10] 439 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0_0_RNICTBGR72_0 791 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[8] 668 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[21] 610 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_373 751 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[26] 384 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[7] 160 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[29] 695 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_c 818 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[1] 882 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[2] 434 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_465 788 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_0[0] 554 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6_1_RNO[0] 782 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[12] 850 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mie_rd_data[22] 800 138
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1[3] 510 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[20] 549 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3[17] 350 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[16] 426 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[2] 392 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m13 172 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[30] 855 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_2 720 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[6] 634 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[6] 279 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[12] 739 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[1] 130 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1[0] 955 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_314 759 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/IilI1 402 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m116 348 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0[4] 715 153
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[10] 81 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[10] 544 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[0] 55 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IOio1 86 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[11] 379 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_Ol0Oo 317 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[9] 249 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv[3] 717 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[8] 932 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[6] 568 193
set_location fifo_to_tpsram_bridge_0/buffer_full_0_sqmuxa 483 255
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[24] 618 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_14_RNIVJOOA 693 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[21] 846 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[2] 318 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[21] 919 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel_RNO[2] 532 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[15] 889 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[5] 771 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[0] 742 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[9] 394 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m21 151 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state62 569 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOii1_0 135 213
set_location fifo_to_tpsram_bridge_0/next_state11 486 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[2] 309 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[7] 298 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001_RNO[0] 178 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[3] 211 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[13] 113 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[15] 741 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_6 319 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo263 176 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[3] 853 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[45] 553 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_194 704 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[10] 860 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[25] 514 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[6] 308 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u_2[3] 956 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[9] 887 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/IilI1 292 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[8] 491 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_9 809 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[11] 282 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O0Ol1 431 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[10] 558 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[9] 449 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[11] 380 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.N_20_i 45 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[37] 728 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[17] 197 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[20] 776 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[14] 382 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[24] 388 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[8] 522 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_d_1_sqmuxa 603 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[39] 732 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[2] 195 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[49] 632 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[8] 336 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[29] 462 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKY1[0] 738 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[18] 723 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[0] 347 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[32] 468 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[7] 732 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[0] 795 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[25] 740 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_2 285 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[2] 868 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[1] 213 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[18] 716 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[0] 339 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO[5] 236 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns_i[0] 475 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un75_I1Oi1 42 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/IilI1 297 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOiI1 405 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1128 723 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[12] 742 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[7] 335 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[6] 797 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_387 639 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_addr_align[1] 766 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/l01l1_RNO 484 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_places_1_.m8_e 709 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[13] 891 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[26] 657 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[24] 946 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_0 44 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_at_flush_0_sqmuxa 790 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[57] 615 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_lsu_stall_sw 783 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_4[26] 478 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[7] 486 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lli01_i_a2 105 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[20] 885 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[16] 428 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[12] 892 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_5[0] 617 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[8] 423 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_4_0 744 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[0] 778 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO[7] 232 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_864 737 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[8] 954 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[15] 649 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_2 415 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[21] 872 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][16] 873 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7[16] 71 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[11] 497 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[6] 199 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[21] 838 126
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/stop_strobe_1_sqmuxa_0_a2 520 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO[1] 418 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[3] 415 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[11] 320 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un145_lIlo1 322 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/llo11_1 391 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_226 666 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[8] 189 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[16] 762 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[1] 487 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[12] 851 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_rd_valid 836 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un77_ool01 201 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[2] 529 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[8] 268 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIF9FGI[5] 521 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m23 31 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[1] 517 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Il111 83 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1o11_1 396 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_4 114 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[27] 968 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[5] 364 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto8_2 272 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_0_0 731 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mcause_sw_wr_sel_3 838 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[11] 313 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[8] 492 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_4_0 92 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[15].BUFD_BLK 572 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIJO8GO[26] 889 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[13] 824 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m16 680 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[24] 956 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[10] 109 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_3 701 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1 828 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[35] 396 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[4] 746 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[15] 895 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_158 737 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff[1] 828 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[2] 60 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[6] 231 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzerott_m2_0_a2 604 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_544 667 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I0ii1 147 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff15_0 772 135
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel[1] 604 214
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_cnt_5_1.CO1 12 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[12] 222 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[8] 413 196
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_8 56 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_2[9] 163 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[26] 626 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_475 701 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_420 669 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1290 703 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[11] 334 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[6] 484 187
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_11 7 164
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_202 721 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNI7NNAIO3 783 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[26] 926 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[15] 860 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1210 652 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[21] 968 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[12] 692 193
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_11_fast[6] 494 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[4] 240 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/o0IIo 329 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2[1] 706 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilOOo[0] 124 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[3] 301 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[6] 390 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[2] 817 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[8] 870 139
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_7 561 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_0_sqmuxa_0_a2 156 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_22_RNO 872 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_968 712 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un77_lIlo1lto15_4 255 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_o9 607 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[24] 835 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[21] 493 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_o1i11_0_a2 340 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_en_retr 802 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un14_oO1Oo_6 236 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[8] 305 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[31] 875 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto3 271 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_1397_i 805 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[11] 312 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiI11_i_o2 153 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[21] 463 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2_1[12] 824 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[14] 772 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[29] 796 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[28] 612 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[27] 850 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo0o1_0_o2 93 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[8] 130 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[5] 724 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oiol1 302 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[18] 677 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[15] 369 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/ioIO1 153 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[26] 944 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[6] 339 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_sw_enable_2 785 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Oll01 151 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[29] 848 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[6] 864 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[12] 381 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[25] 359 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[5] 76 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[7] 277 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[11] 517 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4[8] 112 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[30] 953 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[2] 1005 159
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_15_RNI63LRM 28 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_761 788 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[16] 588 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[12] 308 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/un1_iOI01_1_0_a3_i 265 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOoo1 93 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[3] 332 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO_0[1] 686 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_667 680 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[21] 700 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_766 655 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[30] 721 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[1] 370 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNIRS9V26 768 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[4] 205 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1006 758 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[14] 685 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m[14] 674 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q[1] 601 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/m_env_call 752 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[14] 82 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[3] 859 147
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[7] 613 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo_RNIR06IC 306 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_halt_ack 825 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[17] 59 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[31] 808 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[0] 765 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[8] 954 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[6] 391 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_874 655 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[1] 953 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un31_I1Oi1_2 44 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1193 655 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[1] 544 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[0] 786 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1113 679 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[29] 763 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[1] 218 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[5] 602 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2_RNICVMQQ[0] 687 153
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc4 35 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_543 690 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[7] 635 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIVNTQ8[27] 805 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[0] 849 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un71_ool01 200 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_1_0_a2_0 762 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[15] 65 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[8] 600 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_0_3_i[0] 673 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[10] 255 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[7] 380 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[1] 509 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[34] 937 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[17] 398 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first_RNO_0 568 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/wr_en_data 831 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_RNO[1] 306 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[7] 160 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[8] 417 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[5] 417 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[3] 779 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0IIo_i_m3 271 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oiOi1 292 174
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_3_RNIQG4NV 37 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[29] 398 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[2] 810 129
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[2] 624 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[14] 920 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[22] 621 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[21] 176 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[6] 556 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_OOoi1_0_a3 343 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[16] 234 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[1] 696 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO[6] 261 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[1] 203 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_1_0 736 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_797 668 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/un1_Ioli0_1_0 330 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[1] 246 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[7] 132 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO 317 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[21] 888 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[19] 821 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[6] 314 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[7] 94 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastframe 565 202
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_22 60 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[20] 847 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_8[10] 298 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[13] 248 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[25] 854 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1[27] 949 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oIiO1 300 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIIi1_2 236 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[32] 235 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[29] 874 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[7] 720 145
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_RNI5PDQ7[2] 538 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[5] 494 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1 92 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001[2] 202 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[14] 686 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1_RNO_0 94 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IiII1 366 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[4] 422 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0[4] 154 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[7] 321 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un137_OOOI1_cZ[19] 448 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[26] 662 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m16_0 262 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[17] 354 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[4] 158 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII110 487 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[0] 338 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_978 808 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1240 692 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[1] 195 214
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[29].BUFD_BLK 641 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_22_0_RNO 886 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_899 643 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1082 681 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo_RNO 142 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[2] 157 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_2 744 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_2_sqmuxa_i_a3_0 747 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un32_o1Oi1 75 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[29] 498 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter6_4 898 132
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO[2] 34 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[0] 326 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01_0_sqmuxa_i_x4 176 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOOl1 418 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[0] 770 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1028 695 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[8] 221 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_or[0] 859 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/IilI1_RNO 391 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1_RNO[3] 231 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[9] 896 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[2] 343 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[6] 499 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[23] 672 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[7] 228 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI7H0P9[4] 72 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m5s2 759 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[28] 979 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[14] 716 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[22] 763 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[15] 769 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1[3] 285 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[19] 414 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l0Ol1 424 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oioOo 232 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_i_m3[1] 305 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[27] 944 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[28] 859 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_3 666 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3[7] 944 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto15 251 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[28] 267 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_546 691 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[15] 314 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[20] 716 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[10] 528 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[3] 436 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1_x4[10] 188 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[3] 356 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[8] 227 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[3] 304 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0_iv[10] 716 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[0] 865 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[20] 901 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[2] 481 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4[24] 167 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[1] 453 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_771 654 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_30_0_RNO 881 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[23] 834 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/un17_full_wr_0 707 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[8] 102 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_0[4] 151 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[20] 689 133
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re 604 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_ba_err_1 758 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[10] 111 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[12] 97 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_d_1_RNI0H7VEQ3 774 156
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_i_a2_0[3] 535 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_28[11] 355 222
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[14] 506 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[9] 394 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[5] 176 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1_1_0 804 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[10] 567 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[5] 126 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[27] 902 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[15] 722 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_677 775 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_6 151 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[14] 785 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[5] 714 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_776 812 210
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[20] 487 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2[30] 1005 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3[12] 823 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[4] 841 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[24].BUFD_BLK 630 129
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE_0_sqmuxa 23 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[30] 325 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1O11 114 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[8] 461 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[10] 994 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[12] 124 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[1] 84 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[1] 485 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[10] 858 132
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3[1] 21 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_2[2] 851 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[23] 395 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_2_N_3L3 739 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[7] 380 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[16] 383 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[11] 501 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1171 738 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[16] 670 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[13] 329 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[14] 54 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[9] 845 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[2] 193 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IoIOo 135 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un15_buff_resp_head_compressed_0_0 705 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_par_calc.rx_parity_calc5 521 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O01Io 59 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM[0] 194 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[6] 361 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[19] 281 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[0] 512 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick 629 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_6_0 837 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[30] 923 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[14] 501 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[4] 138 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[16] 692 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_s[2] 561 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[10] 295 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[11] 393 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un47_ool01 199 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[27] 899 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_733 748 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1143 811 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[12] 845 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_269 675 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[4] 69 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[4] 128 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_u 623 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[27] 909 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1i11 348 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[2] 223 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[8] 406 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[16] 263 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[12] 415 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[15] 851 124
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[19] 63 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[38] 933 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[0] 427 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[9] 569 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_ac0_7_a0 12 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[4] 737 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[8] 188 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][11] 885 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[21] 753 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_2_sqmuxa_i_a3_0_RNIF7HK8 785 135
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE17 6 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[14] 431 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[26] 680 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1_0_a3_1[15] 380 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O0I01 331 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[34] 392 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[23] 712 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff[2] 762 118
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[13].BUFD_BLK 596 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_3[4] 257 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_3_1 835 117
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_pulse 530 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/UCLKMUX1/clkout 607 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iliO1 326 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[28] 871 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[12] 848 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[24] 732 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv[0] 785 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_519 657 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[11] 390 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[11] 672 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[35] 335 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_1 374 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[1] 188 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[0] 272 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[26] 614 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[8] 382 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[16] 730 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_4_0_RNO 859 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_0[0] 309 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[2] 893 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][27] 882 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1090 633 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[8] 305 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO_0 334 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[9] 709 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[4] 154 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[1] 210 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1010 766 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[6] 214 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[30] 607 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[2] 297 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_625 654 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[6] 134 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state[3] 558 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[4] 241 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[39] 821 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[24] 750 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_8 345 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oloo1 84 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO019_1 432 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_650 752 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_wr_en 852 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IiIO1_Z 296 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/un1_iOI01_1_i_0 394 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[22] 451 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[16] 524 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[11] 714 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[41] 568 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_trigger_wr_hzd_de_RNI41LM3 745 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[13] 92 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_0_sqmuxa_1 609 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[0] 737 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_895 753 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_0_sqmuxa_1_i_0_o3_0 750 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un18_Oo1Io_0 487 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[5] 562 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[7] 392 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_il0Oo_0 214 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[31] 767 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a2[24] 731 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0[0] 295 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un11_i0lo1[3] 358 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[18] 325 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5_0_1_0 804 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_RNO 755 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[1] 343 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/IilI1_RNO 404 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_458 727 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2[9] 293 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state_1_sqmuxa 609 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_0[18] 730 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIDG6GO[14] 882 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOi11 461 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[10] 442 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[9] 752 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[2] 214 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_wfi_retr 778 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2_0[15] 279 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_0_a4_RNO[3] 921 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[7] 92 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[24] 774 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_360 689 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1296 736 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111 282 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[1] 322 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a3_0[0] 649 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[16] 262 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[16] 178 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[1] 741 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[14] 557 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[3] 547 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[8] 307 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1216 654 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[0] 850 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[27] 853 141
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_10_RNIT2V2H 55 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[8] 168 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[19] 874 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I01Oo[0] 205 181
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE_9[10] 19 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3[13] 171 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[4] 669 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_2_1 153 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[8] 531 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[3] 631 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_RNI1DOPJO3 812 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[13] 251 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[3] 393 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[14] 483 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[10] 524 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1011 273 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[2] 767 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[10] 198 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_emi_req_os_at_flush[1] 784 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[27] 655 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/clear_parity_en_1_sqmuxa_i_0 525 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[10] 311 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4[7] 199 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[2] 51 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/IilI1 394 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa 627 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[6] 268 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[6] 204 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[13] 136 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[8] 307 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[6] 177 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIBFA84[25] 936 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[30] 864 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[9] 387 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/II0Oo_2 226 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[8] 536 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[13] 462 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[27] 497 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_ready 807 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_84[11] 334 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[9] 225 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/l0IO1 237 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_6 703 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_715 650 222
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[22] 486 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[6] 119 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2 413 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[0] 867 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[18] 388 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_3_0 829 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[50] 953 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[5] 322 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[2] 279 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa 557 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[27] 710 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[7] 784 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/un1_Ioli0_1_0 429 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[32] 325 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_8_1[0] 811 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[8] 488 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[24] 900 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[2] 781 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[14] 844 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[27] 771 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_datas2_1 763 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[13] 790 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[4] 700 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un41_ool01 198 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_165 807 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/fence_i_hold 822 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_279 674 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[1] 84 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[29] 664 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0i01 78 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[20] 727 126
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[3] 575 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[19] 875 150
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag_RNI1NUK5[0] 34 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[8] 933 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINFFFD[5] 715 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[27] 689 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_385 638 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[12] 733 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_trap_ret_ex 794 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_0[1] 288 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x2_1[2] 203 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[6] 270 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[4] 263 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlOI1_RNO 320 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_4 737 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[9] 319 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_26[32] 484 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[28] 464 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[20] 592 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[0] 81 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[3] 833 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1[0] 163 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1235 657 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNI65U5Q 759 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/un1_iOI01_1_i_0 395 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_3 728 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_29 745 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[6] 237 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[7] 493 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[18] 930 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_618 664 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un331_lIlo1_1 323 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[0] 427 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[32] 722 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[6] 138 192
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[8] 40 222
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive_0_sqmuxa 557 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_1 247 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[9] 953 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[10] 426 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_649 673 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[26] 195 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1I11_RNIL0RR8 313 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[9] 551 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[27] 815 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[34] 467 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[18] 1004 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[20] 936 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[6] 516 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[3] 778 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[16] 463 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[4] 396 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[7] 80 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_op_sel_ex 772 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_6 691 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[25] 200 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_IoIi1_i_a2 248 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[6] 197 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxp_dataerr 567 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[28] 465 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_strb[0] 780 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[6] 927 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[7] 696 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_l_En_0_a2 575 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[9] 932 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.IloIo 480 214
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q[2] 602 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[24] 848 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3[0] 662 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[1] 283 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[1] 212 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1040 653 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_703 663 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIB7I4J[12] 530 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[16] 470 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[0] 855 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNIEP2E54 256 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[9] 320 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[20] 526 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[16] 479 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/dbreakpoint_iv 744 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo_1 216 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[5] 865 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_2_sqmuxa_i_0 745 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un8_req_addr_mux[1] 739 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc6 20 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_11 813 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[15] 261 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re_q1 605 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_2 967 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[24] 906 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26[1] 361 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_497 770 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_370 678 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[4] 635 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[20] 300 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un1_I1Oi1_6 76 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol117 302 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2_0 85 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[1] 351 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[6] 957 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int35_0 791 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[28] 876 165
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write14 508 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de 803 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[5] 813 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram3__RNO[0] 627 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0[0] 705 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_misalign_error_i_o2 881 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_2[15] 637 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[15] 852 147
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[22] 49 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2_0[8] 429 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[5] 481 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1306 652 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid47_2 753 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[1] 65 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_4 77 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1246 664 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[46] 609 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_2 567 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[10] 853 192
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1[2] 499 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[3] 99 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[29] 882 138
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[4] 500 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[7] 412 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ill11 444 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m30_2_1_1_0 44 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[4] 461 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_1_242_a2 417 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un6_loOo1[1] 339 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[7] 192 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[19] 739 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[7] 483 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_12 881 138
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_7 501 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11[9] 192 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[28] 479 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_21 705 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[3] 706 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[7] 228 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[11] 224 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[27] 926 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[1] 893 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[12] 537 187
set_location SSDetect_0/is_match_0.un3_is_match_2 18 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[22] 806 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[3] 182 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state_valid[1] 768 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[29] 772 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/IilI1 405 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_3 271 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[0] 567 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_m_env_call_ex 745 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNI75KT83 804 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[4] 232 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iooi1 334 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.N_5_i 98 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0_RNO[5] 67 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_valid_de_2 754 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[28] 463 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/next_buff_valid[1] 742 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Io1Io 416 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[4] 93 192
set_location CoreAPB3_0_0/CoreAPB3_0_0/iPSELS[2] 590 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req[2] 878 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[15] 427 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oool1 483 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[46] 950 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_175 715 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_3_0 830 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m66 295 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_269_i 346 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_4 252 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un43_I1Oi1 50 201
set_location fifo_to_tpsram_bridge_0/buffer_full6_5 480 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[12] 509 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[4] 319 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[18] 91 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto8 234 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_RNO[3] 603 117
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[3].BUFD_BLK 570 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_oIiO1 302 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_2_N_3L3_1 752 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo53_0_0 81 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[23] 982 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_19_RNO_0 871 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II0l1[0] 501 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4[2] 601 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[16] 326 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m1 116 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IOIi1 263 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m[5] 844 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[23] 838 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[6] 174 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iiOi1 292 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[0] 469 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/un1_iOI01_1_i_0 313 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[9] 375 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[7] 309 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[3] 396 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt[2] 825 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[30] 740 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[2] 182 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[2] 886 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_223 787 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[33] 936 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[6] 30 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[15] 398 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m16_1 71 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold[0] 616 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_120 765 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001[2] 171 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[6] 210 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un7_cpu_d_resp_error_rd_4 825 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][17] 870 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[15] 546 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OIIOo 133 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un1_Oo1Io 486 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[15] 691 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[31] 673 133
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_RNO 529 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[6] 333 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[2] 451 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIJM6GO[17] 874 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[25] 846 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readonaddr_ff_RNO 761 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[24] 466 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[19] 943 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1107 806 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[1] 286 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[2] 512 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo51_RNIP1IIG6 52 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oIio1 91 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[6] 210 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[7] 181 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[15] 100 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[8] 392 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[15] 270 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_3 849 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0iOo 148 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[5] 754 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[5] 763 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[6] 560 187
set_location fifo_to_tpsram_bridge_0/ram_w_addr[1] 470 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIDVFUI[5] 877 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[16] 871 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_710 678 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[0] 193 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[10] 104 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_181 631 210
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_ns_0_0_m2[0] 12 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_1[3] 974 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[0] 328 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[14] 829 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[8] 114 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[9] 880 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OOll1 508 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[20] 872 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[1] 774 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[6] 374 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data_1_3[7] 837 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[13] 558 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[9] 274 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr[0] 814 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIIIo 230 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow_1_sqmuxa_i 515 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[6] 394 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[21] 681 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[16] 834 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[0] 377 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_mux_sel_ex[0] 724 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[7] 232 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[13] 776 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_s[5] 562 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[3] 862 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[22] 445 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_2[0] 394 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[1] 481 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_382 680 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/li1o1 89 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[25] 741 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[27] 885 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[7] 554 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[23] 801 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[35] 387 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_at_flush[1] 785 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIM3L9D 787 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[1] 294 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m[8] 859 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_71[11] 284 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[30] 992 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[17] 262 225
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM[3] 15 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[11] 362 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[9] 858 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2[4] 701 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_27[10] 370 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Oi0i1 313 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[2] 736 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2_4 93 189
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[3] 477 244
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0 118 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[23] 762 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2[0] 834 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m76 129 207
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2[0] 474 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0_18[22] 221 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[13] 725 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[6] 192 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1 74 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_alu_op_sel_ex7 766 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo_RNO[0] 152 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_early[0] 760 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1[0] 186 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_984 653 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNILFFGI[8] 533 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7[6] 850 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un203_I1Oi1_2_0 45 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0[0] 162 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[14] 481 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[36] 813 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[27] 871 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[1] 293 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3[8] 795 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex_1[0] 773 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0[4] 715 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[0] 861 133
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun 592 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[25] 740 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/IilI1 289 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m4 66 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4926 673 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_o2_1 92 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_83 711 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un41_i0lo1[4] 354 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[11] 307 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[15] 888 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[30] 795 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIUJ7VA[12] 673 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_858 734 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ol111 107 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftBP_ne_0 649 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[23] 755 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1_2[42] 256 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_RNO_1[0] 836 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[19] 80 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[8] 892 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted[0] 777 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_3[5] 177 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[14] 152 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[26] 509 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12 742 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[9] 298 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[0] 830 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_64[11] 350 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_a5_0_1[3] 176 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4915_3_0_RNIHA5E01 688 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[2] 516 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_req_ready_0_o2 755 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_230 698 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_looo1 91 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[3] 566 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[16] 266 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[14] 263 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[0] 363 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[17] 79 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[6] 321 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[26] 901 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3] 692 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[39] 390 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[16] 649 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[10] 65 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[30] 469 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[36] 948 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_Z[0] 417 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[4] 355 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m7_0_a4_0_3 820 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[25] 901 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_324 732 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[5] 514 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_datareg_3_sqmuxa 601 210
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_1_sqmuxa_i_o2_0 30 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[17] 702 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[21] 854 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[18] 869 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo18 293 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[5] 367 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[20] 276 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[22] 634 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_5[28] 458 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[28] 910 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_inhibit_ex_RNIMBF6F4 766 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_26 714 207
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[18] 56 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[7] 370 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m18 261 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[30] 773 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid 796 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[13] 560 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[7] 319 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[11] 379 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[3] 386 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0[7] 126 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m2 163 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[29] 759 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[12] 55 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[7] 538 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[31] 405 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[13] 225 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_meie/gen_bit_no_reset.state_val[0] 780 142
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17_1 602 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_s_31_RNO 890 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[3] 196 214
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[3] 570 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[1] 123 193
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_11_fast[8] 492 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO[1] 146 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[13] 944 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/OIiIo 546 177
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[8] 72 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[6] 58 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[12] 640 154
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane 16 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_1_sqmuxa_i_o3 785 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[31] 775 129
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1 577 260
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_RNO[0] 703 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[4] 949 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/un1_iOI01_1_i_0 336 240
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[7] 571 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[29] 730 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[26] 362 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[7] 78 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[13] 229 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_2_4 418 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[1] 51 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[29] 781 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_4 266 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[19] 525 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[19] 468 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11_cZ[16] 330 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_6[35] 490 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[42] 356 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1II1 371 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[9].BUFD_BLK 571 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[14] 275 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959 702 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_167 638 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[4] 138 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[22] 730 127
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[3] 484 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1158 680 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR21 670 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[7] 895 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o25_0_a3 121 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[0] 574 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[10] 492 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[28] 722 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Olll1 521 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[9] 328 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[9] 532 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[19] 88 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_alldone 568 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[20] 319 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[4] 174 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[4] 411 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_251 622 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[31] 726 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_1[9] 393 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[15] 259 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_hword_high_only_req[1] 876 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m19_3 689 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[2] 392 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNICJS9T 318 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/un1_PADDR 516 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[22].BUFD_BLK 644 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[17] 859 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_75[11] 355 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][10] 799 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1[11] 672 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_1[0] 657 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_pktsel 596 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_993 701 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[15] 592 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[27] 496 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[5] 419 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[27] 870 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff14_i_o3_0 780 132
set_location fifo_to_tpsram_bridge_0/state_ns_i_0_a2_0[0] 472 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[17] 333 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_sel_1_iv_0[0] 714 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[12] 313 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[15] 804 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[17] 214 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[10] 62 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[0] 301 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[1] 769 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/II1Oo 228 175
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/fifo_valid 493 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_153 707 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_764 643 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNIQ7C8H 256 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[0] 186 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[4] 57 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_584 751 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[4] 819 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid_2 721 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[13] 891 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[0] 239 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI67Q5C[19] 728 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un87_I1Oi1_1 58 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[22] 644 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[40] 424 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel[3] 606 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[3] 742 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[8] 49 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[42] 819 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[2] 306 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/rx_fifo_read_1 493 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[3] 869 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[28] 739 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[6] 25 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[3] 246 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[13] 331 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[4] 416 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_10 459 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[7] 885 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_833 645 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[26] 626 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[4] 781 154
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[8] 489 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[31] 678 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60[3] 967 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[30] 403 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_s_RNIK5Q6HF2 779 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIDHA84[27] 924 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[9] 202 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[13] 953 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IOOo1 425 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[6] 448 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1275 680 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[8] 190 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[20] 885 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_3_0_RNO 853 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0_1_0[0] 388 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat[1] 684 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[11] 417 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2_RNIGDF031[24] 837 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNINDHSD[11] 243 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[3] 365 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_24_1 666 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_RNO[2] 825 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[6] 739 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m19_1 730 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz[0] 654 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[22] 676 133
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count[0] 522 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[5] 755 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[21] 547 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_238 810 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[27] 810 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[13] 377 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_gpr_rs2_rd_data_valid_3 726 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_1_i_m4[1] 862 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIiO1_RNIAB63H 301 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/parity_err_1_sqmuxa_i 521 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[11] 301 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[5] 341 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[5] 430 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_31[1] 369 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_2_4 813 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.haltreq_debug_enter_pending 790 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[3] 331 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un112_OOOI1[20] 387 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[5] 545 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_2 136 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[10] 128 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0[12] 120 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[4] 373 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[5] 296 231
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[27] 472 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI7A6GO[11] 879 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[2] 883 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[17] 458 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1__RNI0980D[6] 643 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[4] 356 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[13] 298 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[16] 327 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[0] 636 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m7 690 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2121.rv32c_dec_mnemonic2121_1 662 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[10] 551 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[3] 608 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mcause_sw_rd_sel 844 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[1] 567 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24[0] 422 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[19] 526 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[3] 872 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[1] 504 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[21] 828 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[2] 248 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_instr_inhibit_ex_0 765 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[40] 836 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_1 809 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_oIIi1_4 244 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[9] 955 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[23] 730 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[11] 253 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[0] 485 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[4] 451 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[11] 311 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_valid_ex9 790 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[14] 734 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1 122 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[11] 259 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0OIo 222 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[5] 97 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[8] 571 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[37] 552 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[15] 832 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[21] 955 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[23] 450 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a2_1[2] 678 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[9] 854 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_o2[4] 823 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_d_1_RNIV8VJL41 773 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_16 957 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[14] 353 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[26] 932 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_2 656 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_200 656 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[2] 121 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[22] 680 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/set_wfi_waiting 778 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIT6CS7[9] 866 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_O1Oo1 288 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[3] 539 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[11] 54 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[5] 149 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][11] 891 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/li0I1 519 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0[5] 129 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1280 643 192
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane_RNO 16 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[14] 991 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m11_2_0 680 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[12] 275 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[16] 876 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_0_i_m2[1] 649 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[0] 498 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[18] 78 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_5 797 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[3] 369 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[0] 269 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo_RNI8G024 133 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_177 737 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[10] 845 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[8] 801 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[27] 859 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[4] 851 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[12] 261 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[5] 404 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_ioIl18_1 457 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[22] 931 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_663 724 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_2_a2_1 801 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[8] 293 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[27] 723 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_0_sqmuxa_0_a2 526 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[12] 738 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[5] 859 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_583 689 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de_s_0 747 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_4[24] 421 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[15] 487 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1i01 107 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[30] 328 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[19] 863 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[8] 61 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[10] 513 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1[0] 98 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI7BA84[21] 920 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[0] 213 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60[5] 950 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[31] 118 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[19] 756 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_26_0_RNO 884 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un3_OilI1_i_m3 406 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[2] 546 196
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_9 50 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un46_mtvec_warl_wr_enlto2 906 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[18] 617 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[30] 521 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooO11 116 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[31] 905 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_3_2_RNO_0 761 135
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[10] 623 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[6] 444 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[25] 845 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_o3[4] 311 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/un1_m9_0_1 175 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo[5] 266 180
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_15 9 164
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[23] 789 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[26] 658 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_0 734 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/un4_exu_res_req_retr 744 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[29] 492 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[14] 94 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_6[1] 292 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[30] 517 171
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[19] 482 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[18] 856 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[12] 691 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA[7] 570 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un13_i0oi1 212 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_28 296 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[7] 853 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_6[10] 295 213
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_1[3] 32 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_18[20] 184 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[11] 926 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/i0111 104 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[26] 415 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[16] 873 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iOIo1 343 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[20] 808 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[14] 363 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_774 653 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_595 644 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[31] 405 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/I0iI1 494 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IolOo[0] 251 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[1] 747 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[1] 169 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[23] 714 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_o2_1_0[15] 227 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_652 679 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[4] 356 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[23] 873 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_2_236_a2 416 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[17] 333 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[38] 382 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1308 769 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa_0_0 621 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[11] 675 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_14_0_i 391 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[4] 346 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_13_128_a2 283 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_557 774 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m[9] 714 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0_1_0[0] 341 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO[5] 235 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[4] 494 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_4 667 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[30] 304 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n1 315 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[16] 948 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_1[3] 341 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[4] 993 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_lIIIo_0_o3_1 217 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[0] 260 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_il0Oo 238 186
set_location SSDetect_0/is_match_0.un6_is_match_4 17 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[14] 905 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[5] 364 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[16] 589 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex[3] 734 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0_0_RNITU5E381 784 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[7] 483 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1032 666 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[13] 241 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o1111 83 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIT6FO8 349 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oO0Io_1_0_.m2 141 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[9] 107 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNITJRQ8[17] 714 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO[7] 211 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[29] 943 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[31] 867 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[12] 395 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[15] 342 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001[7] 210 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1024 716 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_read_gpr_rs1_ex.gen_rs1_lsu_stall.un14_gpr_rs1_stall_lsu 755 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[10] 313 232
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[5] 475 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[8] 845 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_penable_0_sqmuxa_0_0_o2 737 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Iio01_RNIU8EJP1 73 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1183 750 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[13] 929 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o1iO1 325 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2[26] 295 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[8] 106 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[23] 800 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[5] 841 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[12] 381 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[18] 770 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1[1] 133 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[16] 767 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[6] 493 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_2_RNO_1 871 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[26] 797 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[5] 332 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[4] 194 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_214 751 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[9] 550 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_wr_rd_state_Z[1] 781 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_axb_0_i_0 511 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[13] 311 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[14] 949 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_11[0] 875 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[18] 902 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lOIOo 142 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_7_176_a2 278 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[1] 463 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[20] 846 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4914_1 668 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[3] 413 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_586 643 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1058 628 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv[2] 605 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioIi1_0 247 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[19] 305 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/branch_cond_0_iv[1] 770 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[4] 288 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid46 744 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_803 749 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_liOI1_4 477 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[27] 752 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[8] 368 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[1] 154 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[11] 109 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[23] 454 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/l01l1 484 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0[14] 108 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO_0 497 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OoO11_0_a2 98 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[7] 383 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4955 693 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[17] 708 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[14] 426 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[8] 129 198
set_location PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL_RNO 90 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[4] 711 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_830 674 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_0_sqmuxa_0_a3 798 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_5 379 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[8] 668 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[9] 269 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr[0] 707 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[15] 252 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[7] 103 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_208 787 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[27] 674 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[21] 667 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[15] 736 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[13] 287 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[3] 709 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_7_RNIDPUPJO3 805 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[5] 321 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_144 678 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[10] 240 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[11] 540 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNIPLN4VG 771 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1[0] 161 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[17] 943 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iO1Oo 219 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[3] 488 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[1] 494 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[16] 730 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[25] 837 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[14] 745 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[12] 609 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[10] 199 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[7] 860 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[3] 666 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_673 667 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[25] 845 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/IilI1 317 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid 792 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[0] 266 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[11] 562 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0 731 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2_0[2] 694 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_3 283 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ilOo1 327 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2[3] 357 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/write_subsys_hart_gpr_ded_reset 789 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[5] 823 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1228 751 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[14] 868 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[15] 261 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][19] 867 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_14[1] 283 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_162 786 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0[4] 187 177
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[23] 61 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[8] 317 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[11] 833 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_0_sqmuxa_0_a2 159 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[1] 180 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[15] 417 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_2[5] 780 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1[2] 469 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[1] 404 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_ff_4 752 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[9] 57 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1[4] 347 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001[1] 172 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][31] 891 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[27] 933 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[3] 508 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[18] 836 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[13] 86 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDMI_ne_0 651 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_x2 103 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_561 776 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout_4 882 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[6] 359 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mcause_sw_rd_sel_1_0 835 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[25] 945 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_1[14] 672 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI23Q5C[17] 720 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[24] 753 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[20] 463 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[5] 748 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[18] 286 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][5] 883 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[2] 790 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0[9] 148 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_12 315 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1_0[3] 842 141
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[6] 618 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_29_RNO_1 884 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m8_0 764 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[3] 418 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[22] 457 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_664 621 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1ol1[1] 304 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNIJE4LE[6] 768 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_529 666 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/IilI1 353 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[4] 414 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[48] 270 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[5] 343 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[3] 379 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[3] 273 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[24] 733 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[25] 679 132
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_1[4] 634 114
set_location COREFIFO_C0_0/COREFIFO_C0_0/RE_d1 479 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNINNJ0L 774 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1[15] 286 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[2] 188 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I0Ii1_RNI73OH4 298 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m21_1 687 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[3] 628 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[4] 235 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[7] 188 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i 860 126
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[5] 594 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m1_e_0 803 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/genblk1.rst_synch_reg[0] 692 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_5_1 45 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[26] 969 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[30] 731 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[6] 568 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[6] 92 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[16] 24 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[17] 759 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2 797 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[16] 702 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/clr_wfi_waiting_0_RNI059SR2 787 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o1ol1 307 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_SWITCH_LANE_0_sqmuxa_2_0_0 5 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[10] 53 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[15] 125 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[2] 413 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[0] 525 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[5] 810 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIF1GUI[6] 891 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result194_0_0 753 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_967 703 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[12] 263 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO[12] 242 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[12] 739 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[18] 45 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IiOOo 122 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[21] 692 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6[0] 752 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IOoO1 301 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[14] 756 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_6[1] 220 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[3] 514 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_7[29] 671 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO[6] 209 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[41] 924 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[1] 501 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[26] 774 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[34] 613 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[11] 235 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[16] 929 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[16] 811 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0_RNI9QTR21 821 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[19] 397 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_4 321 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[8] 446 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3[5] 139 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI7DM4C[4] 696 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[5] 211 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_valid_ex 788 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[18] 404 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[18] 521 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[21] 263 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_5[29] 478 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[4] 592 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_RNO[8] 187 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[9] 184 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[8] 242 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[8] 348 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1 774 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[16] 297 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[6] 470 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[9] 861 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[4] 230 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[10] 120 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un7_trap_val 762 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_psel_0_a2 608 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO[3] 415 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[3] 506 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[53] 966 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ilIo1 336 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[19] 522 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[4] 319 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[4] 214 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[9] 795 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[29] 743 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[8] 364 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1080 699 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[7] 954 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[3] 873 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_42[10] 368 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[5] 56 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_27 682 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[2] 566 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[11] 129 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_u_2[0] 978 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_936 642 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[17] 413 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_22[20] 176 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[27] 227 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m16_1_0 679 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_0_1[2] 139 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0[3] 180 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[5] 186 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[24] 931 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[22] 669 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIQ3CS7[6] 889 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[20] 719 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[2] 206 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3[0] 320 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_40[9] 955 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_725 656 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/li1Oo 222 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[14] 503 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_1 655 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_1_sqmuxa_1_0_a3 795 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[54] 614 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_d_1_sqmuxa 559 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIEKUT5 237 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[1] 348 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1_RNO[3] 208 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO_0[0] 713 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[16] 599 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[7] 860 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[25] 541 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[11] 395 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[18] 905 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[20] 727 127
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_RNO[2] 17 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1[1] 103 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ool11 355 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_172 668 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[2] 851 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[7] 316 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO 644 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[1] 279 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[21] 388 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ol1I1 387 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[28].BUFD_BLK 643 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_31 697 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_800 692 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[5] 717 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[13] 739 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[31] 944 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_462 691 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1286 723 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_9 463 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[14] 277 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_1[28] 978 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[7] 207 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[16] 401 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un6_T_h_En_0_a2 607 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_ack 836 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[1] 777 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[4] 488 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[7] 134 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[9] 44 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[15] 889 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4_0[1] 632 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[10] 427 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[12] 732 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[1] 295 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_lIIIo_0_a3 223 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4_1[1] 595 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[4] 819 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_31[11] 354 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[51] 236 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNITLFFD[8] 710 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0[11] 766 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[31] 902 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[9] 354 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_571 687 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[9] 306 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_masked_0_0[1] 778 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[22] 855 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_689 701 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[33].BUFD_BLK 618 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[6] 196 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[11] 129 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_m3[2] 562 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_0_o2[3] 743 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_1[0] 299 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[7] 436 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[7] 420 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand1_mux_sel_1_0_iv[0] 837 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IiOo1 298 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_olio1_0 90 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[4] 208 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un16_i00i1lto4 268 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto10 287 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_628 704 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[11] 792 120
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow_int 511 169
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag[1] 23 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[13] 848 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[4] 362 223
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31 639 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_read_gpr_rs1_ex.gen_rs1_exu_stall.un7_gpr_rs1_stall_exu_NE 752 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[13] 945 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m58_0 298 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[1] 747 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_674 652 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1[3] 893 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[12] 390 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[6] 782 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[25] 733 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[4] 649 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[22] 253 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[4] 564 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oloi1_RNO 254 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[2] 721 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[4] 205 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ioIl18_i 464 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oo1o1 92 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oioOo 211 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[12] 650 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m16 19 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[0] 729 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0[3] 160 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[3] 859 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[19] 719 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1_m2_e 226 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[16] 897 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_3 786 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_747 660 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_a2_0_0 134 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un111_I1Oi1_2 64 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_valid 862 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI91JD4P3[0] 879 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[20] 884 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[1] 894 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_9[9] 282 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2[1] 654 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[5] 714 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/un1_Ioli0_1_0 277 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO[2] 323 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.CO0 198 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[19] 874 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex[0] 822 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe_RNO 564 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1__RNIOKV7D[2] 729 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[19] 958 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[4] 249 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIEIA84[28] 911 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[13] 794 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1 586 122
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_10 836 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[5] 236 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[13] 380 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_0_2 565 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI7C8GO[20] 885 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[27] 717 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[14] 966 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6_0 53 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[19] 740 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[1] 249 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[15] 359 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIOo1 334 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[2] 301 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_977 697 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[10] 922 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[24] 718 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[7] 511 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[9] 392 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_2[26] 201 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[2] 368 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[4] 157 211
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int_0_sqmuxa_0_a2_0 523 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[1] 331 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[11] 742 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m[6] 852 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[3] 539 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[23] 876 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[5] 708 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[1] 481 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[5] 388 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un219_I1Oi1_2 56 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed[14] 685 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[16] 728 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[9] 840 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[23] 570 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_849 700 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_17_RNO_0 954 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[14] 692 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[7] 341 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[8] 233 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[6] 233 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[1] 196 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftBP_1_sqmuxa_i 669 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[30] 404 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[0] 473 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[4] 716 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[18] 886 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i 703 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[7] 438 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[27] 967 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0] 698 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[31] 503 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_2[2] 20 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[5] 486 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[0] 481 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[62] 845 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iIIi1 310 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1102 702 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[35] 394 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_11 222 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[7] 368 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][13] 866 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNIRFHITD 828 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[26] 884 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[0] 409 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[27] 655 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_0[5] 293 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[14] 718 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[6] 560 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[7] 335 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[7] 467 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][30] 899 154
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[4] 473 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[6] 489 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[14] 96 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_1_0 753 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff14_i_o3 774 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[8] 439 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[9] 293 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un42_o1Oi1 83 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[10] 842 147
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_1_sqmuxa_2_0_a2 4 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[15] 928 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[0] 746 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO_0 766 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[6] 736 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state134_2 633 114
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt[0] 522 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[21] 858 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_capture_reg 781 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_836 651 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[11] 915 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo17_0_a3 431 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[8] 551 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[23] 815 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oOoi1 335 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[29] 502 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[2] 855 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m9 165 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[7] 481 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[12] 487 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[0] 932 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv[2] 109 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[4] 494 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[12] 53 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[22] 850 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i01Oo[0] 196 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[9] 123 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[27] 728 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_361 787 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[18] 854 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_366 666 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr[3] 777 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m322 371 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel[2] 532 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[8] 369 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1 49 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11_cZ[14] 352 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[23] 704 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[20] 977 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[28] 893 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs2_rd_hzd_4 712 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[0] 323 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m25_e 115 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iool1 308 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[0] 723 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[11] 293 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_1 267 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[16] 969 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[17] 903 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count[1] 519 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNI2EN6Q[0] 771 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[13] 248 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[4] 457 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[13] 737 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[1] 878 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_472 703 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1063 632 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[7] 232 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiIOo_RNO 140 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[25] 337 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[30] 767 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[17] 918 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[5] 450 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid 812 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_118 655 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[7] 460 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[11] 67 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[8] 755 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_235 776 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op[1] 715 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9] 681 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[2] 662 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[17] 549 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[7] 233 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0i1_0 201 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[0] 435 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shift_op_complete_ex_a0 801 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[26] 468 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913 666 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_42 713 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_906 655 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[5] 250 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_penable_0_sqmuxa_0_0 772 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[0] 206 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[30] 897 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[4] 704 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[2] 258 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[9] 889 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[10] 421 196
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_29 485 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1072 747 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[11] 761 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0Oo 235 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[1] 400 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[16] 104 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[15] 74 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OIl11 332 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[20] 448 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[14] 555 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI4TN4A[0] 162 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0[25] 285 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_35[11] 277 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[11] 391 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[8] 530 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[3] 48 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[15] 965 159
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[23] 55 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[41] 263 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0_a3_1_1[1] 409 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_6[24] 421 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone 574 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[18] 905 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1_3 404 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_1 68 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2[6] 337 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2[14] 881 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[4] 236 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[3] 791 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[10] 141 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[29] 895 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_I1iIo 464 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOii1_2 143 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1[13] 847 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[4] 212 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[2] 236 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[4] 422 222
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_0 426 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_0[3] 693 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oO0Io_1_0_.m5 140 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[18] 797 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNI54164[2] 224 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[16] 714 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_87 725 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[18] 710 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_0[4] 255 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[2] 200 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[18] 776 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[3] 512 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1104 654 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[6] 85 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[15] 400 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_720 733 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_0[1] 404 213
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[7] 491 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.trigger_debug_enter_pending6 752 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[7] 558 166
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[18] 56 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I0o01_RNO 111 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[28] 942 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[10] 218 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[5] 361 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_5 725 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_ooo11_2 365 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[4] 481 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[0] 697 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_36 678 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[8] 52 204
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_4_c5 23 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[4] 792 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[19] 966 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[23] 252 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[18] 716 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_c_RNIQ642L 780 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo 220 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[26] 476 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[35] 726 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0_tz[0] 830 126
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[23] 481 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/step_debug_enter_taken_RNIRN07L 827 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_845 785 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0[15] 128 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_d_decode.un8_cpu_d_req_is_tcm0lto18_8 770 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_ackhavereset 825 124
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_busy 561 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo[6] 280 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[36] 557 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_2 392 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[0] 456 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI101_1_ns_1_0_.m7_1_0 102 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_I0OIo[0] 221 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[19] 447 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[24] 930 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiO1 226 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_3_tz 93 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[30] 525 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[7] 260 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[31] 719 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIERK9D 755 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[0] 776 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[3] 281 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_14_RNO_0 870 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[21] 604 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ii1i1_2_0_0_a2 393 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[8] 302 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_Olii1_1 147 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_1 394 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[21] 984 159
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_3_0 608 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[39] 306 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[11] 211 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_o1Ii1_cry_4_RNO 418 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_i0lo1[12] 283 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13] 686 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[13] 296 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_a2 834 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[29] 781 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[29] 329 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[2] 525 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNI6UE88[14] 95 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[3] 342 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0[6] 195 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2117_2 680 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[2] 890 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[31] 909 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[63] 642 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[23] 902 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[3] 336 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un23_I1Oi1_2 48 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_0[0] 632 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/un1_iOI01_1_i_0 230 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[9] 370 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[22] 650 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[20] 464 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O01i1_i_o2 317 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_ooli1[0] 326 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_0[4] 652 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[11] 693 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[1] 82 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[39] 553 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[20] 93 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol1o1 113 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[19] 402 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_strb[1] 790 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_RNO[1] 786 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_371 760 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[0] 421 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_376 637 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[19] 598 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[23] 922 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][10] 790 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[12] 304 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[18] 666 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[7] 264 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[13] 490 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q[5] 569 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_1[1] 782 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[31] 610 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[0] 459 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[5] 424 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[27] 726 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_11[9] 284 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[52] 968 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[5] 406 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[9] 863 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[17] 549 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[2] 736 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_1[1] 704 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_4[9] 102 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[2] 30 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[1] 462 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[27] 616 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo_3 273 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[3] 302 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[7] 190 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[3] 378 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0[4] 828 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[3] 839 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[1] 843 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[12] 314 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[3] 162 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2[2] 113 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[3] 593 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_0[2] 848 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI07I0QD[5] 836 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[21] 918 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 517 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[1] 249 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_3[4] 743 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_0_RNO 727 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[13] 817 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_5_0_RNO 857 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/un1_read_rx_byte_1 515 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_xx[19] 830 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1[3] 159 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[0] 190 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[0] 313 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex 833 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[5] 799 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[6] 284 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_0[7] 292 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[29] 330 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[23] 552 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo 129 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[0] 589 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[17] 870 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[5] 190 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[23] 746 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O0i01_0 76 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[1] 432 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/IilI1 367 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[7] 318 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_oIIi1 296 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl15 522 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_806 663 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_20[22] 223 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_RNI9T465[1] 75 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[8] 806 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[23] 980 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[19] 420 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[30] 880 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[23] 463 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[24] 893 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_OOoo1_0_a3 91 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un95_i11Io 511 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[6] 494 184
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[1] 503 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[37] 728 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[0] 55 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[4] 980 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_2 210 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_13_0_RNO 879 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1[5] 374 192
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO[4] 22 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[17] 291 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_3[0] 669 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[11] 274 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[2] 289 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[7] 171 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI83P6N1[0] 161 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27[8] 356 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0i11 427 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[0] 480 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[7] 305 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][7] 877 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_32[0] 309 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[9] 408 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[0] 709 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[22] 737 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001_RNO[9] 184 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_curr_fetch_ptr[1] 883 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[1] 429 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[21] 753 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[13] 381 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[29] 965 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25[11] 361 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_lIIIo_0_0 229 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1 445 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un11_oIoOolto3 243 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[25] 200 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[19] 728 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[26] 724 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[13] 122 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[7] 243 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[29] 873 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[11] 53 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[17] 963 159
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m14 525 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr_2_f0[1] 726 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv[3] 716 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[10] 341 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[16] 848 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[12] 407 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIoo1 85 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_rd 799 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_205 703 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[3] 618 115
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[4] 367 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0_RNI82T691 756 150
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[2] 588 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_28[4] 398 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[12] 919 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[11] 853 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_9 359 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[22] 479 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[24] 867 151
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_0_sqmuxa 496 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[13] 872 153
set_location fifo_to_tpsram_bridge_0/ram_w_addr[8] 477 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/count_en_0_sqmuxa_1_0_a3 807 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/un12_q0_0 734 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m5 126 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiIOo_RNO 143 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2 732 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[1] 715 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[17] 831 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_0_0 138 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[19] 864 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_451 703 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2[0] 138 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_752 654 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[6] 595 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[18] 708 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[0] 412 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[6] 338 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0[0] 821 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_ns_i_a2_0[2] 665 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[4] 590 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_enter_req 827 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[0] 224 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[48] 951 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[37] 927 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[15] 64 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_addr_align[0][1] 767 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[11] 552 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_exit 791 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[5] 276 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0OIo_0 227 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[5] 369 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[13] 416 208
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[2] 74 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_21_0_RNO 901 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[39] 389 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[10] 227 190
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_a3[1] 537 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr[0] 698 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[1] 813 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[15] 234 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[5] 308 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_447 678 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_ss0_0_a2 789 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_10_RNIJJE6D 458 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic847 645 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[7] 41 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_alloc 790 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_llOo1 327 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][17] 874 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_85 691 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[5] 495 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[1] 856 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv[16] 759 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_0_s 751 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[24] 656 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[5] 520 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2_0_3 79 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[8] 191 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[6] 214 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ooI11 339 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIH3GUI[7] 893 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i00o1_0_a2 105 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[31] 802 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[8] 259 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I019_RNIBEMUF1 303 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_10[1] 309 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii101_RNO 86 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[3] 294 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[4] 138 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_iooo1_0 84 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoOo 220 178
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[1] 19 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[1] 714 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_11[10] 297 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_0_sqmuxa 766 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[6] 737 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[12] 296 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OOIOo 133 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNIP7VU3A1 775 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[25] 340 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[17] 409 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[23] 908 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[14] 903 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIHD0D6[3] 420 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[25] 931 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[23] 543 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo_RNIKP865 142 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[5] 143 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][28] 884 151
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO[2] 614 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_48 759 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[9] 886 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[8] 302 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un83_ool01 197 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[7] 494 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[5] 186 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/un1_Ioli0_1_0 349 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[25] 871 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[13] 841 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[1] 262 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retrce[0] 772 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[8] 717 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[58] 851 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1[1] 104 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[5] 84 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[2] 549 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[5] 28 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid 798 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOoO1 230 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[7] 48 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mcause_sw_rd_sel_1 834 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[8] 275 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[2] 836 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[11] 711 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[13] 299 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I0101 128 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[4] 340 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[1] 482 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[53] 941 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[2] 195 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[16] 776 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[0] 187 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[4] 407 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[3] 385 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[9] 347 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic849 647 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[2] 800 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[29] 865 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_lsu_req_valid 835 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNIRK2V1 791 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_iili1[0] 337 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[13] 440 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_4[0] 126 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_48[6] 597 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[34] 261 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[15] 502 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO 284 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[4] 473 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg_RNI6EB8H 793 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[9] 88 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[7] 303 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[36] 234 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OiOo1 294 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_mux_sel_ex[1] 727 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[24] 294 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[12] 533 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[4] 424 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_610 679 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[4] 706 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[9] 387 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[0] 163 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_ns_i_a2[4] 667 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[14] 347 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_99 653 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_0[0] 93 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_stall_csr_2 719 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[20] 957 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[12] 44 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[17] 807 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[4] 713 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[6] 354 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[9] 759 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_a2 142 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[6] 546 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_PADDR_2 563 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[26] 842 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[5] 268 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[13] 548 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[4] 591 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_0[2] 1003 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_taken 764 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_26[7] 360 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[19] 524 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_418 678 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[4] 228 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[24] 475 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[30] 990 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[8] 886 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_RNO[10] 152 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[63] 839 193
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[3] 503 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[26] 827 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_busy_cmb_mux.un1_debug_csr_rd_en_1 853 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[28] 919 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[44] 817 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u 811 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_13[0] 283 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3[1] 822 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[14] 332 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[11] 881 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1230 701 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[22] 737 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[6] 321 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_accepted_0_o2_0 768 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3[29] 775 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[27] 654 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i_1 862 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[3] 291 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2[0] 727 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[0] 334 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[19] 870 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_valid 715 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1307 641 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[24] 305 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/genblk1.RXRDY5 512 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un14_i00i1_i_0 225 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m26 43 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_misalign_error_i_o2_0 877 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[13] 840 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[5] 954 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[14] 735 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_32[10] 296 219
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_18 509 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[17] 297 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_ready_reg 743 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_s_29_RNI7ST9PO3 805 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[20] 735 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[6] 174 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un47_I1Oi1_1 48 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[15] 888 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_59[11] 347 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[3] 900 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[18] 908 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m16_1_1 166 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr[2] 799 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ[11] 361 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[16] 453 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_15_RNO_1 883 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_RNI42K8A 104 183
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO[2] 518 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[8] 233 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0[7] 165 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[29] 739 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[0] 571 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[1] 743 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m24 62 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[28] 163 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i01i1 320 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[9] 842 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIi1_1 223 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Io1o1 132 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a2 748 171
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/o01Io_1 66 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_1 614 117
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m16_1_1 526 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[5] 471 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[34] 473 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/rtex_1 188 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[10] 980 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0[1] 706 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[12] 287 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[0] 834 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_1[0] 686 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2122_i 940 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[1] 200 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[5] 781 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[23] 616 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_1[1] 616 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_active_retr 815 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[15] 771 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[7] 340 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[6] 193 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDODRV 568 115
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[8] 513 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[4] 860 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[6] 482 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[10] 320 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[6] 540 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_292 709 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[3] 333 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IoI11_RNO 414 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[25] 901 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[18] 665 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1_0_RNIO1BB7S1 815 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.dpc_debugger_wr_sel 835 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[18] 382 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un12_lolIo 57 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[23] 445 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[7] 875 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[15] 385 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[28] 873 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIBG8GO[22] 874 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[19] 388 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olIOo 140 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[6] 595 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[0] 14 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[8] 955 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[14] 361 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[24] 933 150
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE9_0 3 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[8] 539 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[6] 270 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[7] 369 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[3] 526 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[9] 551 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[5] 351 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1ce[0] 136 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1_1_0_RNO 805 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[13] 31 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[2] 140 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[4] 781 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[58] 631 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[25] 816 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_i_m3[1] 836 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[24] 752 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[10] 508 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[23] 393 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[4] 369 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[61] 837 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[2] 309 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1133 805 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_3 211 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_10_sx 803 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[5] 772 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[10] 811 121
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/endofshift 589 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_IOiOo 216 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[9] 303 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[55] 943 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[2] 478 172
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_3_sqmuxa 27 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2_0_m2[3] 711 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[31] 404 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[7] 497 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_636 646 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[5] 411 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[18] 745 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[10] 843 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[17] 711 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[22] 290 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[1] 507 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[0] 490 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[16] 479 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[8] 253 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I0001[1] 177 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_8 96 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[10] 558 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[18] 453 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_oioo1_0 99 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1054 747 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[5] 377 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOOl1 399 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[2] 951 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[26] 868 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un12_o1oOo 210 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[3] 183 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_2 738 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[4] 778 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[6] 249 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[12] 295 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[9] 213 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_7[0] 307 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_a2_0[24] 720 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[31] 876 133
set_location PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD 1 163
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1_0[0] 348 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_0[1] 200 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[16] 320 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_tz 66 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0[12] 127 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_224 647 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[7] 194 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_bitsel_1.CO3 567 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[9] 383 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[14] 259 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/IilI1 268 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[7] 408 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[22] 727 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[4] 412 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[3] 389 210
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[28].BUFD_BLK 640 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[19] 911 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[0] 774 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_139 822 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[26] 748 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[11] 551 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[5] 598 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13] 695 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[0] 595 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[20] 595 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oii01[1] 76 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1 505 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_1_2 454 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_1_1_0 795 144
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/PRDDATA[2] 569 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[50] 953 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[27] 922 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[28] 284 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[15] 410 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op_ex[0] 758 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[25] 945 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIFB0D6[1] 417 165
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[21] 493 246
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_o9_RNIUDLNB 606 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[10] 353 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i10i1 277 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel[0] 609 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKX0[0] 750 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[26] 449 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_184 690 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[0] 523 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0[2] 412 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[18] 895 159
set_location CoreAPB3_0_0/CoreAPB3_0_0/iPSELS_raw_2_adflt 628 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0OIo_0 226 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[9] 377 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[2] 79 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a3[2] 751 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[1] 540 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[4] 540 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[28] 978 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[6] 247 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg[1] 756 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv[4] 712 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_autoincrement_ff 766 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[1] 493 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[2] 630 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[28] 715 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/next_buff_valid[0] 782 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[16] 742 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/un1_interrupt_taken_timer_2 795 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un291_rv32i_dec_sw_csr_wr_op 721 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[1] 304 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[53] 831 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[13] 690 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[6] 275 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[10] 212 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[23] 452 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un31_I1Oi1_2_0 43 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_2[10] 407 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[26] 880 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_bcu_op_completing_ex_0_RNIGTKL51 774 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[6] 853 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[0] 846 141
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit 605 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[9] 922 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[5] 990 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[8] 572 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[20] 706 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[17] 854 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_538 701 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[0] 631 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un21_i0O11_i_a2 97 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0] 371 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[0] 123 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1_RNIS235T 90 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[5] 328 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioOo1 294 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6[0] 791 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[8] 364 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[25] 396 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_9 134 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[0] 377 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1258 739 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[22] 855 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[10] 309 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[24] 924 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[6] 546 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[12] 847 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[2] 494 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tbi_tx_1 96 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[6] 957 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z[37] 395 193
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code_5_f0_i_a2 17 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_6 834 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a3_1[2] 845 120
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4[2] 44 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11] 712 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[29] 871 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[5] 862 148
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/Ol1Io_3[0] 52 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un32_o1Oi1_0 73 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[31] 923 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[3] 136 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[21] 931 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[30] 921 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][18] 887 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[4] 863 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[0] 592 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_2 615 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_0[29] 878 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_s_0_RNO[0] 810 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_943 773 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0_1_0[0] 343 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[4] 270 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[8] 210 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_dummy_target_RNO 789 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[17] 930 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1093 702 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[0] 64 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[9] 272 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[17] 595 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llO11[3] 83 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[2] 44 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[27] 460 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[8] 260 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1013 694 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[12] 440 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[7] 175 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte_1_sqmuxa 510 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[8] 371 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_1 116 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[11] 396 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_83[11] 359 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[23] 913 157
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag[1] 30 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[12] 457 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[41] 568 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[16] 70 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[7] 981 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1 603 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0[2] 714 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[15] 710 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[3] 61 199
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st[0] 22 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/iliI1 424 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[17] 942 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[22] 556 180
set_location PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL 11 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[2] 881 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[0] 726 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[4] 453 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[5] 717 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[10] 880 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[22] 619 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11[0] 81 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o1oo1_i_0_tz_1 107 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[20] 754 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[31] 934 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[11] 825 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[27] 498 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l01015_0_a3 130 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.IloIo 516 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[4] 713 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[1] 413 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.OOoIo[0] 468 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[2] 65 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_5 694 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[30] 452 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m46 160 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNIA0FQD[6] 80 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[9] 931 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[11] 94 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[5] 180 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[28] 746 126
set_location Core_reset_pf_0/Core_reset_pf_0/dff_11[0] 848 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] 517 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[5] 98 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[44] 602 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[4] 421 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[24] 898 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[19] 967 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[0] 594 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[5] 754 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[14] 724 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iI0Oo 267 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_a4[2] 61 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[2] 884 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_5[9] 358 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[17] 478 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112 665 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int[2] 770 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk2.un5_OIiIo_1 419 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[24] 475 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o1i01_0 112 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[10] 747 198
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_ac0_5 45 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[25] 383 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un107_I1Oi1_2 43 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UDRSH 607 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[9] 515 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[1] 355 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0_1_0[0] 332 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[45] 825 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_ba_err_ff_0_sqmuxa 761 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1030 643 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lO0Io.m3 61 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[40] 930 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[7] 488 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[23] 979 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[28] 828 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[4] 798 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[0] 232 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_0[4] 850 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[23] 921 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_14[0] 864 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[20] 564 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[20] 550 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[8] 483 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[9] 441 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n1 611 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_606 642 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m13 115 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[15] 334 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIio1 66 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_pktsel_0_sqmuxa 607 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[20] 471 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[6] 451 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[10] 857 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[20] 814 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][27] 876 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[5] 821 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[6] 344 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_9 651 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[3] 874 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[42] 935 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[3] 393 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[2] 505 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[9] 490 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[6] 857 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo[7] 234 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OIoOo_1_0 235 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[17] 293 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[3] 826 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[0] 362 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[24] 828 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oOo11 300 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m12 80 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[7] 258 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[2] 90 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_o2 800 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[11] 834 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[26] 688 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_ptr_RNO[0] 699 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[9] 518 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[44] 623 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[0] 575 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_0 803 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[30] 877 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1236 714 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv_RNO[1] 789 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_109 810 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[19] 139 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[5] 180 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[12] 110 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted[6] 776 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[5] 437 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[2] 648 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OIoI1 440 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2[22] 778 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[20] 159 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[19] 928 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff[1] 749 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_0_sqmuxa_0 787 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[27] 459 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O0lI1 520 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_out 567 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[12] 222 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_10_RNI1UMUEO3 797 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_exu_alu_result212_1_d_2 796 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns_a3[5] 531 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[27] 227 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0[0] 677 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_85_u[9] 942 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_818 665 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[27] 709 144
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_2[4] 33 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22[7] 401 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[14] 481 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[9] 447 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[19] 83 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[5] 271 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1011 309 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[14] 909 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 484 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1II1 373 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[12] 141 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[1] 368 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a2_0[1] 820 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0[4] 816 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[9] 447 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[11] 856 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[12] 261 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[15] 280 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1[2] 229 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[33] 714 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI9K8U6[10] 260 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_23 285 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_2 406 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_ioIO1 150 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_44 652 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[1] 295 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[0] 187 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[25] 941 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[11] 269 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[30] 943 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state21_1_0 788 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/timeout 882 130
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[5] 43 223
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[5] 565 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[3] 393 202
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un6_countnext 605 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0_1_0[0] 349 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[1] 366 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OOI11 111 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[19] 833 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_787 656 195
set_location fifo_to_tpsram_bridge_0/ram_w_addr[9] 478 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2_0[1] 646 171
set_location Core_reset_pf_0/Core_reset_pf_0/dff_10[0] 843 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[12] 51 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[25] 274 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[5] 412 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[1] 79 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[4] 480 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0_0 716 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_545 793 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[8] 411 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_508 762 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13[1] 783 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo[3] 240 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1043 684 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_1 375 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_RNO 686 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[4] 799 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[19] 299 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_il0Oo_4_0_3 222 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_367 724 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[24] 710 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[25] 231 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[11] 116 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[15] 151 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_2[4] 259 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un12_lolIo_1 128 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[5] 822 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_0 122 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[27] 488 244
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[4] 565 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0[0] 615 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[24] 465 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_5_1 736 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[37] 561 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][29] 878 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[10] 355 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O0lI1 509 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31_0 623 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_ptr[0] 782 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[17] 197 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m4 114 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1_m2_e_0_0 223 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[3] 538 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid46 738 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[28] 255 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[20] 699 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[34] 479 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[16] 857 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_0_3 270 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[21] 312 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[14] 363 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[4] 274 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[3] 285 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[7] 543 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/hipri_req_ptr[0] 768 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1_1[7] 74 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[15] 757 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[31] 651 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_889 678 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[8] 383 223
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[5] 20 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2_0 803 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_10_RNO_1 867 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lOl01_2_iv_i 145 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[19] 718 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[1] 322 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[25] 937 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oIoo1 92 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[23] 733 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1270 684 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_strobe 566 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_74[11] 364 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[19] 920 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[3] 232 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[0] 713 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[0] 372 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[7] 823 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[4] 356 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/instr_inhibit_ex_0 757 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0[19] 166 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[0] 701 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[3] 697 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m293 367 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[16] 334 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/un1_Ioli0_1_0 229 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[2] 437 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[9] 740 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/genblk1.rst_synch_reg[0] 705 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[12] 495 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[31] 233 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[7] 726 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[11] 245 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[2] 35 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_631 785 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[7] 727 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[0] 713 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_i_1_m2[1] 773 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oI1I18 462 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_211 620 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[1] 81 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_1[1] 175 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[0] 192 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwrite_5_0_0_127_i_a2_i 687 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[0] 487 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_1 440 6
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/looi1 326 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0_1_0[0] 326 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[14] 929 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i[11] 363 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6[4] 681 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[31] 934 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[23] 617 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un1_oOo11_1_i 305 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state_valid_3[0] 773 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_6[0] 297 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[5] 664 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[22] 974 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[27] 298 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[5] 328 166
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1lto7_2 25 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_0_a3_2[7] 297 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[12] 354 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/IilI1 290 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[28] 884 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_illegal_instr_retr 749 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[1] 200 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[3] 477 243
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I1lIo_2_0_.m3 60 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[7] 332 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[21] 863 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[3] 318 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2_7 665 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[7] 195 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic847_2 644 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_ack_RNIAS9O01 935 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z[3] 188 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r4_i_o2 493 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[13] 918 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3[1] 318 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][9] 787 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[23] 385 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_113 700 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_353 640 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[17] 55 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Io0o1 90 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[6] 914 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[23] 727 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2[1] 930 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[6] 510 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_237 722 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4_RNO[2] 186 186
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[31] 67 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_10_1 941 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[14] 366 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[31] 466 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[21] 798 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[22] 737 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_128 665 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[11] 766 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[8] 511 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i[0] 360 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m20_0 253 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[1] 278 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lOlIo 272 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_read 752 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[9] 788 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[12] 382 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_793 664 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[1] 567 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_liol17_1 320 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[12] 325 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[1] 541 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_3 788 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1173 809 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ioIIo_RNO 308 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a2_1[1] 804 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[20] 906 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_82[11] 345 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 527 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[5] 179 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1 101 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[6] 33 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_2[3] 714 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[31] 876 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[0] 123 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state_valid_9[1] 777 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[15] 955 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_1[0] 837 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_o2_1_0 787 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILDTQ8[22] 769 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[5] 209 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[23] 980 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[13] 546 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_52[8] 1002 171
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[11] 504 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1[0] 416 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[24] 776 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_6_i 759 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_19_RNO 869 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[1] 323 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[29] 710 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid36 825 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_377 699 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_clk_en_dm_1_i_o3 855 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[5] 499 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un16_I1Oi1 42 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[21] 799 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un149_OOOI1[29] 466 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[9] 354 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNI0E7JA[0] 782 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[8] 402 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_832 677 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n4 305 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[3] 152 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/ll1i1_0_a2 379 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[9] 535 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1[8] 869 189
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[24] 67 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[2] 739 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[3] 339 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[2] 149 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01_1_sqmuxa_i 621 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_885 630 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[17] 929 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[20] 712 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/IilI1 332 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un52_oIiOo_1.CO3 285 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[8] 147 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[12] 851 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[21] 844 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_63[11] 348 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[9] 257 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol15 435 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[3] 993 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[14] 525 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m[13] 669 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1[4] 185 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_0[0] 668 153
set_location fifo_to_tpsram_bridge_0/ram_w_addr[4] 473 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22[12] 352 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr[1] 706 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count_0[2] 625 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5[14] 116 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.psel 752 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_x2 175 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[13] 393 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_10_RNO 868 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic851 642 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[4] 285 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/IilI1_RNO 289 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_fr_1 423 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_15_2 689 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OIIl1 533 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.un1_dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset 668 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/l0iI1 500 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI44QTM1_0[0] 159 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un10_ioOOo_2 125 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].un1_lsu_flush 759 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[18] 525 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[14] 375 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oOil1 385 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[2] 630 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[27].BUFD_BLK 642 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0]_3[1] 739 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.gen_per_trig_tdata1[0].machine_sw_wr_tdata2_match_data_wr_en_0 858 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[12] 843 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[2] 188 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[8] 336 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[2] 188 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliOo 211 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_alu_op_complete_ex_0 799 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_57[11] 354 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[4] 482 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[9] 482 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i1I11_cZ 354 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIoO1 289 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[8] 534 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[5] 236 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_o2_RNILR2O6[3] 860 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[60] 645 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[8] 838 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[11] 499 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_3_iv_i[0] 304 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[26] 109 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo 235 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[10] 353 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_1_0 726 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[7] 204 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un195_I1Oi1 55 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[33] 358 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[4] 530 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_m17 701 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[9] 908 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[12] 402 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIHNM4C[9] 706 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[15] 831 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[30] 452 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][15] 889 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[6] 408 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[9] 187 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_ex_2_1_RNISIFQHS3 769 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/IilI1 413 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNIMI94D[0] 158 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23[8] 414 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[34] 399 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[24] 742 132
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[9] 500 246
set_location PF_IOD_CDR_C0_0/PF_IOD_CDR_LANECTRL_OVERLAY_0/I_IOD_0 0 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[38] 427 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_olli1lto15_0_0 246 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[5] 55 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[10] 36 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[7] 172 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[2] 759 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001[5] 234 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[9] 56 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2] 729 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iOlOo 165 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_612 758 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[8] 503 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_20 643 216
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_int 504 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_455 690 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_4 848 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_4[1] 225 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[28] 604 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[23] 270 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_517 640 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_a2_0[31] 802 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_instr_is_lsu_op_retr_0 796 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate[12] 665 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_0_RNI1H6UT81 785 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[5] 499 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[6] 193 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_601 750 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[7] 408 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[17] 896 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOIIo_0_a3_0 239 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[4] 251 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[16] 714 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ilOl1 434 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[2] 195 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3[5] 827 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[8] 683 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a4_1[1] 631 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[17] 892 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[9] 854 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[9] 448 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m234 356 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[6] 753 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv 670 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[30] 740 135
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO[1] 563 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[12] 728 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[16] 446 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2[0] 194 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oIoo1_RNO 92 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[9] 857 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[2] 59 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[9] 740 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op_ex[1] 748 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[4] 863 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[10] 381 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[4] 124 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/liol1_RNO 318 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[7] 854 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[7] 370 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[28] 383 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[36] 727 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[8] 120 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[6] 624 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un4_llii1lto4 146 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[26] 905 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[41] 620 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3[0] 297 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_532 660 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[5] 26 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int[3] 778 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[1] 370 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[4] 529 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[27] 761 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0[5] 83 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/io1Io_RNO_0 441 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[19] 914 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[0] 796 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[6] 397 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[4] 711 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[18] 79 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[10] 848 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[4] 438 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4[0] 880 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_IoOOo[0] 129 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[20] 865 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[0] 118 190
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO[0] 31 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[5] 332 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match[0] 755 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_207 746 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[54] 614 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[1] 72 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0] 702 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[0] 601 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mscratch_sw_rd_sel_1 821 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[4] 343 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_29 284 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[8] 575 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m2_0_a2_7_2 818 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[45] 559 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[2] 29 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo 625 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[14] 405 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[2] 477 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i1lOo 166 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[31] 459 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOOIo[0] 164 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1070 737 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/un1_iOI01_1_i_0 306 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ii0i1 297 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[10] 367 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op[0] 735 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[2] 308 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_il0Oo_4_0_4 218 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[31] 675 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_6 706 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[8] 74 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[2] 737 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[9] 306 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI3LFUI[0] 877 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[25] 738 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[2] 519 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[7] 511 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_a2_0_1[0] 524 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_i00i1lto15_3_0_0_o2_0_i_o2 246 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[29] 503 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex[0] 742 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[29] 737 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_12_i_1 858 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[26] 469 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][20] 885 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[33] 936 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_487 679 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m256 381 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_854 744 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIF998E[24] 673 192
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[17] 54 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[2] 384 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_2 256 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[17] 591 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[14] 906 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_synch[0] 703 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[2] 877 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1[2] 137 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[6] 68 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/loI01 344 178
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM[4] 21 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[1] 338 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel 834 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[6] 276 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0_1[30] 946 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_136 744 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[25] 725 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[2] 330 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[7] 323 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4[0] 651 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[8] 293 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_1_2 206 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[3] 649 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[4] 729 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[0] 205 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_802 785 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[5] 349 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[6] 509 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1[30] 979 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2[1] 198 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_res_pos_neg_3 932 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[31] 889 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[1] 211 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_20_0_RNO 872 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1276 784 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[17] 242 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[2] 426 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[9] 600 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_15_116_a2 299 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[17] 481 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9] 672 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[14] 260 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[27] 431 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[15] 882 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[5] 858 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[11] 318 234
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[5] 25 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[1] 408 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0IOo 141 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[8] 866 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[15] 738 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[2] 347 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[1] 239 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNIHC4LE[5] 798 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.req_complete_reg 776 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lilIo55_1 136 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0[9] 101 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNI945FTD[5] 816 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2_1_sqmuxa 620 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0[5] 557 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oIiOo_0[8] 290 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0_1_0[0] 333 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_1[5] 174 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[10] 248 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[8] 548 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1 87 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[3] 902 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[0] 233 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[2] 320 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[24] 630 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lO0o1 138 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[0] 126 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_14[22] 220 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[30] 912 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[16] 864 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_wr_op_ex[0] 766 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[15] 382 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[17] 658 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/un1_Ioli0_1_0 475 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_0_0 680 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[20] 748 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[30] 741 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[30] 870 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[20] 958 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[18] 907 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oooI1_1 455 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_4 574 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[5] 336 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[5] 447 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state[4] 555 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[26] 472 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[11] 792 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[1] 63 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[17] 493 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/un1_iOI01_1_i_0 374 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[13] 381 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[27] 459 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_958 677 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[3] 121 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[16] 355 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[6] 299 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0[6] 159 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_25 698 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[0] 849 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIIVK9D 754 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[19] 461 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_1_1 701 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[13] 912 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[25] 878 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[18] 795 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[4] 210 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO[1] 684 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[4] 373 213
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[18] 490 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[2] 131 178
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[5] 475 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[4] 306 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[27] 776 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_h_En_0_a2 568 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[9] 125 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[2] 52 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m2_0_a2_5 811 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_620 654 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[3] 94 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[24] 200 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[6] 881 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ioOl1_3_0_1 404 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.N_53_i_i 183 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m1 679 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_o4_0 881 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[5] 508 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[1] 313 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0[1] 419 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[15] 494 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[18] 410 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[25] 871 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[15] 259 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[1] 852 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[2] 365 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[33] 780 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_1_RNO_0 809 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_0_RNO_1 724 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[26] 993 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_5 183 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_428 784 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNI0GF1D81 790 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[5] 121 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[5] 120 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[29] 886 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[5] 405 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_1_1 654 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[4] 339 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[0] 269 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[24] 473 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_0[0] 833 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[18] 363 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[10] 868 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[8] 884 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[17] 947 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_62[11] 338 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[34] 472 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[17] 76 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_751 665 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_io1l1_axb_0_i_0 510 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[1] 180 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[19] 841 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[5] 399 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[17] 930 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[7] 304 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[5] 508 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[4] 456 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[13] 63 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][18] 875 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[1] 376 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_657 639 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_6_212_a2 414 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[24] 851 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[23] 794 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_756 751 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_22 800 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[6] 323 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[18] 45 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i[9] 338 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s 760 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[13] 538 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[4] 41 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[11] 311 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[17] 834 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[11] 118 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_0_a2[2] 753 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[18] 924 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[22] 814 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack 830 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_365 764 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_RNO[12] 314 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_502 642 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[2] 389 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4[6] 116 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[30] 688 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[3] 648 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[30] 480 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_2[3] 378 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[26] 891 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un5_mul_mc 765 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un5_o1Oi1 77 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[11] 497 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[11] 562 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit_RNO[0] 523 159
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_10_iv 625 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[7] 883 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[9] 398 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[4] 52 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_hword_high_only_req[0] 898 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O11Oo[0] 193 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[7] 465 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/IOlo1 296 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[1] 510 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_o2_0[0] 165 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[4] 371 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m19 110 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[10] 735 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[30] 832 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[20] 159 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/io101 98 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state[5] 557 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[8] 883 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_2_0_0_a2_0[1] 819 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv_RNO[33] 782 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[10] 910 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv[3] 830 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[30] 234 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[17] 90 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[2] 194 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[5] 342 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[19] 957 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/wr_data 804 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[7] 802 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[11] 515 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_17 884 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[6] 409 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[15] 612 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_0_1[31] 929 171
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[0] 23 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][6] 897 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[2] 352 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_N_10_mux_i_0_0 763 147
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_8 494 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[9] 70 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m6 127 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_illegal_instr_ex 732 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtval_sw_rd_sel 835 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[13] 253 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[17] 710 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/debug_reset_pending_2 781 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_1_i_o2 118 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_28_RNO 941 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_27_RNO 862 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[10] 823 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[26] 384 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un123_I1Oi1 38 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[18] 733 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[7] 172 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_0_RNIHPCED 785 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2[2] 200 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1[15] 121 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[11] 531 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[6] 796 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO_2 245 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o10Oo 219 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IOoOo_0 223 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[26] 735 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[7] 310 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[1] 569 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0_RNI16EFQ 800 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[0] 360 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_106 649 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[3] 216 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1 787 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un6_IOII1 404 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iO0i1 300 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OlIOo 137 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo[0] 250 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[5] 539 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[3] 535 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[10] 523 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[20] 876 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[3] 435 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[26] 898 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[3] 294 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[0] 654 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_fence_1_0_a2[1] 736 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[5] 235 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[2] 791 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOiI1 431 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_RNO 725 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m63 152 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/wr_en_data_or_0 865 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_44[9] 337 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[5] 300 225
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/dll_inst_0 2 377
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI9E8GO[21] 894 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_RNO[11] 255 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[17] 212 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[6] 543 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[3] 339 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_290 652 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[2] 759 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[3] 145 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[15].BUFD_BLK 631 126
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[7] 483 247
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg2Seq.controlReg25 505 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[12] 295 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un43_I1Oi1_0 55 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_c2 316 168
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[9] 509 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[6] 316 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1[3] 143 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[8] 130 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[4] 588 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_1[4] 192 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[30] 375 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIOl1 435 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[14] 901 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[31] 499 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNIEO6RBD1 826 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[10] 732 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[17] 709 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m4_0_a2_0 809 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un1_lO1O1 525 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un83_rv32i_dec_gpr_wr_valid 695 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_0[1] 915 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_5[0] 307 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lliOo_0[6] 291 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20[10] 424 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_valid38_1 756 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[25] 392 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[1] 217 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_930 772 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[22] 804 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[0] 187 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOi01 119 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_4[4] 224 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[62] 845 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_10[9] 281 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[18] 919 147
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_0_sqmuxa_0_a2 25 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_m2_0 728 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[7] 132 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/write_en_1 704 132
set_location fifo_to_tpsram_bridge_0/ram_w_addr[5] 474 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[30] 912 151
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[4] 485 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[6] 398 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[20] 531 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0 768 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[23] 845 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[13] 257 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[2] 297 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[10] 264 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[11] 551 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0[2] 80 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[18] 411 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[30] 874 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/wfi_waiting_reg 787 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[14] 791 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1[7] 342 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I15 480 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[29] 956 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0[3] 416 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[1] 754 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[20] 364 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_0_sqmuxa 588 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[26] 625 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[2] 345 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNILQ8GO[27] 882 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmcontrol_ndmreset13_4_0_o2_0 844 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/I0OI1 341 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI10U4D 788 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[0] 329 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[31] 842 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNI96C8E[31] 676 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_14 758 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5[2] 202 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_375 763 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_434 804 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[19] 965 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3_0_0[0] 671 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[2] 377 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[3] 302 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/alu_op_sel_1_iv_0_cZ[0] 761 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_0_sqmuxa_i_a2 703 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[23] 468 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[25] 815 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[32] 477 214
set_location AND2_2 18 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[3] 87 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[6] 203 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2_1[0] 164 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OI0l1[0] 493 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[29] 401 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[8] 263 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[6] 54 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un29_loOo1_i_o4 331 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[5] 199 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[4] 175 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_259 715 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OIOl1_1_1472 460 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_0_iv[4] 607 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[9] 377 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[8] 824 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[28] 977 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12[5] 343 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[16] 834 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[1] 338 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[7] 822 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[22] 1010 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_3_0_a2_0[30] 280 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_firstrx 594 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[5] 231 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00017 175 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[23] 824 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_3 382 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[27] 807 133
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[8] 622 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_34[11] 295 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[11] 503 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_0_1 676 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[29] 943 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un4_rs2_rd_hzd_5 722 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[14] 569 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[19] 915 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_983 792 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[28] 871 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[13] 690 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[3] 100 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z[38] 451 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/un9_req_wr_byte_en_mux[0] 765 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m1_e 814 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[24] 843 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[21] 913 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[2] 244 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1[4] 653 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[1] 829 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[5] 306 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[0] 331 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un5_lsu_emi_req_rd_byte_en 705 150
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[21].BUFD_BLK 629 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_RNO[1] 822 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_161 713 216
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[17] 470 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[27] 757 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[16] 262 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[0] 210 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[10] 523 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[7] 51 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[22] 732 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto15 233 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[18] 761 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[7] 369 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[31] 833 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[29] 608 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oil11 325 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[10] 741 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[14] 258 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[19] 858 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[62] 941 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[13] 222 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[23] 828 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[3] 735 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv[0] 120 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[23] 615 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[2] 186 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[11] 301 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_7 256 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1 316 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_ssel_mux 595 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_362 772 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_28_u_2[31] 964 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[10] 407 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958 716 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[2] 486 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_26[10] 366 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[0] 268 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_msie/gen_bit_no_reset.state_val[0] 784 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oO0Io_1_0_.m4 134 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[3] 418 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a2_0_0 342 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[4] 228 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_893 654 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[12] 488 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2124_2 664 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_9 755 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[6] 656 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[1] 516 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[13] 834 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[14] 766 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[16] 259 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[7] 291 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_o2_0[1] 92 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stx_async_reset_ok 588 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[0] 488 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[3] 649 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_error_sig_N_2L1 822 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[2] 567 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[4] 779 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/un1_Ioli0_1_0 289 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[2] 173 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_instr_decoded_1 730 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[20] 808 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15_7 246 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[15] 254 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[3] 70 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[13] 108 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[9] 205 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0_1_0[0] 351 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_298 699 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_350 736 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[4] 257 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/un1_iOI01_1_0_a3_i 351 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[3] 322 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[2] 943 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_2 799 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_964 665 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[18] 723 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[5] 251 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNILO6GO[18] 892 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_3 305 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[11] 230 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_29[1] 357 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_3[9] 378 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[59] 838 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[14] 686 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[17] 316 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[18] 477 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI0o1[0] 82 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2[0] 756 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[9] 448 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_8[13] 710 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_div 814 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[11] 211 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[16] 722 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[5] 891 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_10[10] 343 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[26] 473 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel_3 843 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o12_2 740 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_10 814 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[13] 273 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[27] 269 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIiO1 310 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[24] 968 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/sw_csr_wr_valid_qual 806 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[2] 153 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_RNO 810 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[4] 715 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1083 763 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1IO1 229 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1 217 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.gen_per_trig_tdata1[0].machine_sw_wr_tdata1_mcontrol_execute_wr_en 857 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[1] 319 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[1] 418 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iII11 146 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[21] 920 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[6] 470 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[7] 835 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[1] 853 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[9] 709 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i_o2_0 700 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un23_ool01 196 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[16] 890 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[13] 254 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_32[9] 336 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[26] 791 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_30_f0[0] 574 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_o2[1] 92 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[34] 419 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z[2] 144 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[25] 383 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tbi_rx_1 102 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[14] 927 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[2] 736 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3[4] 301 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[4] 468 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_4_1_0[5] 862 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[11] 332 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[26] 737 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[37] 233 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[10] 525 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un114_OOOI1[31] 480 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_7 389 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[18] 856 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[4] 319 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_45_RNI7JIH72 797 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_12_RNO_0 808 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[28] 763 166
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_lastframe_1_sqmuxa_1 562 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[16] 474 244
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_q3 602 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[14] 80 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count[0] 783 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[2] 318 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un35_ool01 195 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_155 689 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_7[5] 331 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO[1] 623 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[34] 826 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[1] 765 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IloOo 207 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[30] 978 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[2] 801 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_900 631 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[11] 253 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[7] 818 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[30] 385 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[4].BUFD_BLK 569 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[28] 690 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[1] 69 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[35] 951 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0_1_0[0] 316 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[3] 254 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[10] 50 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[14] 92 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o01i1_0_a3 316 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[11] 605 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O1o11 402 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1[10] 284 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[4] 720 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1168 702 222
set_location fifo_to_tpsram_bridge_0/state_ns_0_0[1] 471 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[2] 858 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[24] 656 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[6] 700 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[6] 237 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0_o2 110 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_828 749 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[3] 357 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[26] 903 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI0o1 106 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNIFR1EB 291 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_1_2 341 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[5] 74 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[22] 852 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_24[11] 392 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IOi01 79 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_valid 856 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_171 629 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[2] 173 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1[1] 173 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un2_Oil01 153 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_585 809 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[1] 415 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_404 687 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[17] 81 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[5] 508 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_242 774 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[4] 856 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_clock8 502 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[11] 123 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[3] 363 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[4] 917 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_resp_access_parity_error_0_sqmuxa 847 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_24_RNIBAUVEO3 798 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[15] 772 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9_5 613 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2_RNIFCF031[24] 838 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[14] 850 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[6] 191 205
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0 1154 162
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[10].BUFD_BLK 570 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un170_i11Io 515 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_372 728 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[4] 368 234
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxp_lastframe 575 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_0 340 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo[2] 282 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0[8] 187 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un7_ioOOo_2_0 120 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[25] 541 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[6] 446 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1_RNO[0] 501 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[61] 956 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[13] 709 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[4] 194 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OiO01 516 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[10] 489 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[6] 75 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m17 162 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/un2_is_locked_1 745 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1[0] 249 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[1] 274 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un10_Oo1Io 493 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O0oo1 82 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[5] 215 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[6] 362 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[5] 514 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/OO001 203 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_reg[1] 775 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[12] 605 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1025 714 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_m3_i_a3_0 808 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un150_i11Io 537 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[8] 364 216
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_0 400 198
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state13_i_o4_0_o2 14 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[5] 372 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[2] 332 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[12] 718 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[25] 696 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[35] 610 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_c2 600 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_valid_int 731 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[28] 693 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoiO1 294 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_0_RNO_0 720 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_974 762 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[4] 209 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[29] 758 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[5] 562 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3[13] 328 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[33] 719 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo0Oo 219 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[3] 850 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[7] 179 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[31] 726 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[3] 131 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO_2 643 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m6_0 52 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[5] 597 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2_3_RNIQ8SLJ 807 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[11] 843 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex[1] 828 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[25] 734 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[2] 267 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_0[9] 380 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[6] 574 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un13_lolIo_1_0 56 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr_RNINOH7A[0] 805 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo263_2_1 174 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[30] 403 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[3] 303 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[7] 429 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[24] 841 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[16] 895 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[27] 497 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[4] 331 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_2208 798 141
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[7] 594 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[25] 865 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[28] 655 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[10] 243 214
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[24] 491 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[19] 833 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_liOI1_4_RNIG18PA 482 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[4] 468 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[4] 926 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_411 821 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_fault[1][0] 771 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_564 702 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[10] 202 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[14] 800 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_712 668 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[13] 531 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[7] 159 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_5[29] 725 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_29_0_RNO 877 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_ff 752 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1223 698 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[9] 847 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2133_1 677 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[3] 484 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_pending_2 820 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[30] 743 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/li0i1_RNO_0 314 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[3] 36 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_890 642 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlI01 323 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_valid_2 744 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_0_248_a2 413 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[27] 759 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_221 700 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[19] 863 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNI9398E[22] 638 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0IO1[0] 217 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[6] 375 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[31] 751 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_3_230_a2 412 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[3] 127 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[23] 380 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_15[0] 905 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[3] 833 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[13] 251 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[3] 148 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[3] 211 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[7] 406 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[11] 560 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[20] 916 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[22] 853 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_4_1 787 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[14] 783 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[10] 992 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[7] 94 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[7] 198 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OIO11_3 90 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv[0] 667 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[4] 326 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1[0] 930 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30_1_1 978 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_3 810 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[23] 497 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_en_retr10 773 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[15] 768 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z[2] 202 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[6] 598 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[15] 766 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIH7RQ8[11] 711 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[2] 735 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiO1 219 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/empty_r_fwft 514 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[10] 552 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_123 628 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[29] 645 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[4] 542 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[3] 282 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo[9] 156 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1011_RNO 309 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[6] 344 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[5] 250 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[25] 753 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[2] 286 207
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag[1] 29 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[59] 973 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[3] 506 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[19] 463 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_1_RNO 65 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1100 777 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig[24] 752 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[14] 727 142
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[20] 53 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[17] 833 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[3] 232 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un107_i11Io 536 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I01i1_3_0_a2 332 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[16] 397 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2[26] 977 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m24_2_0 159 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[8] 365 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[3] 512 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[9] 530 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[25] 868 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_6 366 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2_3_0_RNITQ0FE2 767 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O00Oo 215 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[3] 454 202
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_18 79 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2[14] 161 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[7] 753 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_17_0_i 390 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[0] 366 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Iii11 359 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_30 663 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[28] 472 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m19 752 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i0o11 370 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f1_0 770 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m319 370 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[4] 387 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_1 316 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_4 84 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_28_RNO_1 940 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[20] 369 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[14] 919 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[27] 805 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[0] 571 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[1] 330 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIFLUT5 268 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[15] 831 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f0_RNO_0 775 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3_1[14] 99 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m7 115 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_a2_0_RNO 750 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[37] 404 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[6] 201 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[1] 468 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic852 637 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0Oo_RNO 228 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I10i1 233 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_338 722 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[2] 187 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_5 388 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[22] 80 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[20] 916 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_1[29] 721 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[11] 903 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_2_i_a2_0 770 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[9] 160 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i1101 138 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[6] 479 247
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[1] 612 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO[1] 780 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[40] 715 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[60] 978 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO_0 691 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_1_RNO_1 807 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_ptr_RNIIHIB7[0] 702 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[9] 226 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_2_i_a2_1[1] 820 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[2] 405 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_26_RNIFE00FO3 815 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[2] 257 213
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[1] 475 241
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_563 783 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[11] 248 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_4_0 222 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_34[9] 967 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[18] 542 184
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_17 508 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[3] 699 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[25] 741 129
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[15] 489 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[4] 79 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[36] 727 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[0] 400 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2128 653 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_831 651 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[0] 839 183
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[7] 489 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[11] 656 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[13] 144 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[3] 402 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OO1Oo 239 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[1] 488 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[12] 929 204
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[3] 499 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[30] 939 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[28] 805 127
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[0] 29 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[2] 341 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[3] 423 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/io1I1 292 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[10] 363 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[1] 321 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_1[28] 462 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[11] 875 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[23] 194 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIi11 444 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[8] 130 190
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_indicator.fifo_write8_1 506 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[7] 512 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[0] 83 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[3] 245 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1007 808 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel[2] 568 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_574 688 213
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc3 35 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[4] 754 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[8] 775 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[25] 677 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m18_1_0 681 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[16] 862 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[3] 170 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2_RNIF8II0R2 803 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[31] 461 214
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[22].BUFD_BLK 628 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/abs_busy_cmb_mux.abstractcs_busy_cmb7_0_a3_RNIHOBJ9 843 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[11] 274 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2128_2 663 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[2] 145 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[22] 853 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1068 773 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[34] 376 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[2] 317 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[0] 340 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ioo11 397 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[11] 463 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_2[0] 369 174
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane_4_f0_i_o2_RNI4OQGP 22 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIF5RQ8[10] 812 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O11i1_2_0_a2 346 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[0] 368 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0[11] 127 204
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[9] 27 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff_2_sqmuxa_i 750 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoo1_i_o2 95 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[11] 456 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[15] 953 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIIi1 247 186
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/load_lane_3_f0 18 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un16_valid_sba_0_a3 793 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[9] 559 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[1] 540 208
set_location fifo_to_tpsram_bridge_0/next_state11_19 507 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[2] 231 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_gpr_wr_valid_1 644 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_midbit_2 606 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_9_2 783 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv[3] 724 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_63[31] 928 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[4] 469 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_1[3] 782 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_996 768 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[27] 848 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_uar_err_ff_0_sqmuxa 763 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[9] 212 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[4] 127 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[4] 436 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/N_20_0_i 171 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_7 316 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_23[3] 368 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0[2] 608 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[9] 51 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[26] 898 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[26] 374 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1_0_a3_0[23] 319 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid 763 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[30] 386 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[16] 427 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_5 753 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[7] 881 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg4 812 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[13] 596 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv[4] 832 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[0] 322 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[28] 904 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[2] 251 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_622 750 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un12_OOOI1[4] 432 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[56] 840 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1[1] 199 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO[1] 816 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_iloOo_c3 260 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[0] 81 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[22] 863 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un295_lIlo1lto8_2 264 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_527 665 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[13] 690 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_566 761 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[7] 106 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[7] 90 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[14].BUFD_BLK 595 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[31] 802 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex[0] 773 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001_RNO[9] 182 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[9] 775 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[2] 242 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[0] 260 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[12] 511 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[24] 755 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[9] 344 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[10] 381 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[4] 177 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNID0CK42[0] 157 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un6_Tc0_h_En_0_a2_0 627 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[0] 461 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_1[2] 699 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[5] 88 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[16] 534 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un117_I1Oi1_2 40 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[5].BUFD_BLK 606 123
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/cdr_start 14 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.I1li0 99 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[17] 106 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[27] 848 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOo11_RNO[0] 195 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m13_2_1 18 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[20] 294 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[25] 688 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[9] 410 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[23] 617 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2[29] 283 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic849_2 638 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[14] 284 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[19] 447 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[7] 159 193
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE 16 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[5] 458 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_10_RNO_0 867 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[4] 743 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_2 44 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[16] 445 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_o2_1 730 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[13] 378 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[4] 290 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_m[4] 822 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[20] 842 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[7] 400 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[11] 549 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[8] 327 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_15_RNO 881 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iooi1 134 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.lloIo 488 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_9[7] 820 138
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[6] 493 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[3] 231 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/resp_dest[1] 784 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_3[1] 292 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_4 812 138
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_2_0_RNO 594 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[14] 766 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[0] 832 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[4] 319 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[7] 318 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_573 677 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioli1 342 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[17] 547 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lOil1 391 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOo01_i_a2_0_3 114 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[1] 851 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[11] 681 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_15_RNIB8SUEO3 810 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[29] 252 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[24] 894 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[49] 632 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[10] 36 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_a3_1 844 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[6] 234 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[27] 426 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m30_2_1_1_1 42 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[28] 655 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[5] 263 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[1] 437 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_Ilio1_0 113 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2_RNIDAF031[24] 826 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[15] 254 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[5] 495 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[49] 830 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_18_RNO_0 868 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[4] 127 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[21] 966 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIS5CS7[8] 899 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[8] 49 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[24] 832 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_157 619 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m10 139 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[37] 721 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[3] 372 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[19] 875 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/wr_en_data_or 863 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[14] 802 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[9] 218 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u[9] 956 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os_RNIE15QF 791 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[19] 928 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[13] 327 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[25] 909 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/INVBLKY0[0] 730 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[23] 832 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0OOo_i_a2 238 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oI1I1_1 470 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI0o1_1 103 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un12_O0001 190 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[28] 806 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_3_2 773 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0] 231 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l00Oo 237 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_308 712 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff 749 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_m9_i_1 173 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/o0IO1 213 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_5[15] 700 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[13] 355 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[23] 913 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIR9T5J 844 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[54] 959 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[11] 301 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_0_3[4] 149 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[7] 53 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo 327 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[22] 859 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[3] 852 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[5] 956 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[6] 668 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[5] 415 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[28] 405 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_rd_op_retr_2_iv 792 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_0[3] 826 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[2] 302 213
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_5 441 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_86[11] 356 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_lsu_op_retr9 802 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M_0 498 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[30] 918 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2126 652 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_754 704 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_801 674 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[10] 742 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto5 265 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[17] 380 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[26] 673 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_6[0] 222 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[7] 525 202
set_location SSDetect_0/rx_start[0] 13 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1[0] 140 196
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O11Io 68 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[10] 430 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[8] 421 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[3] 48 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel_RNO[1] 31 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[12] 710 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[4] 314 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[4] 339 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_7 55 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_896 663 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_1[1] 103 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[1] 835 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINFTQ8[23] 784 123
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[4] 32 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[10] 679 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[25] 732 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[19] 728 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo_1 246 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[31] 898 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m224 353 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[47] 812 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un4_gpr_wr_valid_int_3 724 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/un1_iOI01_1_i_0 387 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_2[1] 692 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[2] 104 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[10] 844 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[11] 408 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[20] 883 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[20] 730 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iIoo1_RNO 87 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/reg_write.tx_hold_reg4_i_0 507 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[22] 846 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_synch[1] 702 133
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnextzero_m4_2_0 602 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_autoincrement_ff_RNO 766 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f1_0_RNO 774 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[11] 97 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[18] 613 168
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[3].BUFD_BLK 588 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR19_1_0 667 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_576 639 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiI11_i_o2_5 150 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[20] 229 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO[3] 145 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[15] 236 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[13] 953 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/count_en_0 790 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoOi1 237 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0[7] 798 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un22_il0Oo_0_a2_1 234 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_7[1] 306 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[4] 225 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[2] 434 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[33].BUFD_BLK 641 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_haltreq 824 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l10i1 233 172
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane_4_f0_i_o2 19 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[2] 68 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[31] 646 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IOll1 457 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr[1] 795 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[3] 145 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_Ilio1 89 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[6] 426 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[15] 88 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[6] 761 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[6] 871 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[3] 832 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[15] 792 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[56] 963 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4[1] 656 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_295 750 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_5[2] 223 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_m2_0_a2_7 816 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilIOo 140 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[43] 554 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[3] 713 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[31] 869 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[22] 863 166
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[5] 492 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0_1_0[0] 315 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_ii0Oo_2 235 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01_0_sqmuxa_0 162 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux_0_RNO 753 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o1oo1_i 97 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m16 164 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_1_1[3] 219 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[0] 474 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_743 786 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1109 627 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38_RNI1R9MH 760 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNI3SN3NQ 788 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2124 663 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[2] 423 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_o2[1] 163 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[18] 903 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[9] 860 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01_0_sqmuxa_0 174 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un27_ili01_i_o2 118 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[0] 420 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_0_tz_0[0] 651 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[25] 553 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[12] 842 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[31] 845 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[21] 694 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/ioOl1 464 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[0] 176 207
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[5] 32 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[6] 233 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[7] 548 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31_0_1 977 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[9] 329 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/llIOo 141 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[21] 169 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIi01[4] 98 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0[13] 303 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[29] 329 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[9] 563 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[0] 200 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][26] 886 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[0] 702 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[1] 485 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[23] 733 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[33] 320 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[12] 502 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[4] 270 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[14] 256 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[13] 371 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/I1lIo_2_0_.m3 102 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNI0FNBG 783 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_3 439 6
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_stall_csr 767 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[59] 638 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[9] 55 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_ready_sig_1_RNIJFC2E2 806 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[16] 893 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[1] 514 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNI2G7JA[1] 791 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[4] 276 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[13] 311 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/csr_trigger_wr_hzd_de 749 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[18] 910 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un1_rs1_rd_hzd_4_3 729 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[14] 591 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[8] 133 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1ll1 299 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3_RNIA6V5D 255 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol19 391 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[6] 724 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_653 664 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[18] 260 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_o7[0] 145 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[24] 721 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_implicit_pseudo_instr_ex 751 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_2[13] 749 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[22] 230 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_1_RNIC4GH72[4] 156 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[0] 261 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0[10] 112 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OlIi1 251 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIoOo 232 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt[3] 526 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_2_a4 848 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mvendorid_sw_rd_sel 811 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[14] 281 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[6] 859 177
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_7 632 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[50] 634 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[13] 340 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[1] 795 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[6] 758 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0_o4[0] 29 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[7] 816 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[38] 740 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[16] 862 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_669 679 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9 87 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[19] 768 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIo01_0_0_tz 112 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_23[1] 401 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[28] 727 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[18] 504 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][24] 876 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2[7] 964 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_1[3] 77 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_RNO[1] 701 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][13] 878 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[10] 877 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[15] 494 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[0] 774 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[22] 901 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[3] 559 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_RNO[0] 313 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/O1111 83 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[9] 274 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[2] 487 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[23] 845 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[5] 52 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[2] 566 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_0_1 598 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I01i1_1_0 322 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[27] 471 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] 486 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_6 700 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_RNO[0] 306 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4[5] 202 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[0] 654 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/Oi001 181 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[13] 693 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[20] 861 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[10] 380 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_OIio1_1 105 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[4] 351 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOI11_0_a2 132 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[12] 242 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[14] 739 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[4] 342 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[13] 368 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1[2] 132 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[14] 732 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_1[3] 39 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1026 619 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftBP 657 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[39] 552 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[9] 128 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[16] 713 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m12_1_0 103 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI_2_sqmuxa 666 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[5] 233 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3_1[3] 150 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01_0_sqmuxa_i_RNO 522 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1198 666 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] 237 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_0_sqmuxa_2 554 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/IilI1 397 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[3] 719 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[1] 416 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1118 699 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_21 775 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_RNI580NA 619 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol15 483 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[1] 511 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[9] 283 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llO11_i_0_tz[0] 108 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[9] 149 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[10] 723 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[22] 1007 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[16] 968 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[10] 873 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[13] 510 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un135_I1Oi1 63 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[5] 341 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z[2] 277 193
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[27].BUFD_BLK 617 129
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[8].BUFD_BLK 605 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[10] 735 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[7] 502 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[1] 866 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[27] 633 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[22] 901 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lolOo[0] 246 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[15] 612 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 236 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[0] 725 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[0] 725 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a4_0[1] 640 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/N_834_i 296 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[14] 846 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[5] 862 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[26] 829 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[23] 918 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2 102 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[6] 235 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate[31] 763 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io6_10_RNIEPCN26 53 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_oI0i1_3 206 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_10 95 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[5] 664 133
set_location Core_reset_pf_0/Core_reset_pf_0/dff_0[0] 831 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO[4] 331 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[2] 376 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o1I01 289 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOoo1_1 101 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[5] 113 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1_RNI6B1NA 618 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_2 698 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[4] 308 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_3_0[64] 833 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy[22] 880 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[9] 263 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_5 810 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_rd_byte_en[1] 712 150
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_midbit_3 596 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_i[1] 738 150
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[2] 613 115
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv_2_RNO 688 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/llll1 477 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a2[1] 145 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo[4] 286 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[30] 939 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[13] 251 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[14] 885 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_11 429 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[14] 704 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[17] 906 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[15] 68 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_RNO[0] 81 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[1] 343 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iO0o1 139 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_30_RNO 930 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[7] 369 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[29] 908 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[5] 250 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[8] 419 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/io1Io 342 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_0 388 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_30_RNO_1 929 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[26] 470 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[3] 303 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[8] 50 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_433 650 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O01I1 470 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[1] 242 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_5 378 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[2] 678 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I00o1[0] 77 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iiOl1_RNI2H6B6 468 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OOii1 154 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_6_0_RNO 853 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[27] 757 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[27] 471 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[2] 605 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[33] 830 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[11] 884 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[24] 837 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[8] 361 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 523 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[23] 704 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[1] 374 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[2] 317 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[12] 495 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[10] 265 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_29[9] 354 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex9 744 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[9] 76 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27[4] 381 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_4_224_a2 411 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_7 377 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_valid_de_2_RNINIJB6 758 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_en_retr 802 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_679 749 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[1] 728 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oiIl1 475 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places[4] 922 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[54] 964 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_152 703 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[28] 704 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_1_0 801 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[6] 782 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[19] 734 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[11] 487 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f0 773 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[28] 647 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[28] 728 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[10] 921 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[11] 734 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_1[29] 479 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m13 781 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[17] 260 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[26] 922 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[12] 407 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[8] 934 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[8] 288 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[10] 547 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_2[7] 940 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[2] 258 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[3] 872 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[6] 386 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[16] 378 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[3] 568 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[21] 898 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[21] 891 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_551 758 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_313 667 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un4_I1Oi1_1 49 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[31] 932 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[3] 363 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[13] 532 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/rx_fifo_read_0 293 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_29[0] 355 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIoO1_RNO 306 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[15] 498 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m9 713 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[7] 388 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[1] 330 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[9] 191 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_fault[0][2] 769 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[13] 834 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[2] 184 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel 799 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[24] 909 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_654 728 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_1 372 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[15] 163 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[8] 337 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[10] 482 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m13_2 125 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[17] 285 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex[1] 729 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_a3_0[6] 139 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[43] 950 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[3] 697 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic853_2 638 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_66[11] 280 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[6] 546 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_0_0 124 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[7] 499 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand1_mux_sel_0[0] 700 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[2] 274 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_iooo1 90 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[9] 932 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[3] 352 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utimeh_sw_rd_sel_2 836 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1148 641 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_0_a3[25] 392 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1[1] 133 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[22] 951 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[28] 884 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[20] 53 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[6] 856 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_3_0_0 767 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[20] 718 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[11] 223 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iiii1_3 133 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[14] 846 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[7] 425 223
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/clear_parity_en_0_sqmuxa 501 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un12_i1oOo 241 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_33[1] 591 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[12] 343 186
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[13] 71 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2_0[6] 353 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI47S5C[27] 687 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0[3] 298 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[14] 690 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4[4] 201 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[26] 980 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1I11_RNO 228 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m41_2_1 114 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[3] 488 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_957 659 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_63_RNIH51Q7 819 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[27] 752 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[27] 928 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[8] 453 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_0_sqmuxa_RNIBM8F94 756 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/genblk1.RXRDY 515 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[4] 765 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[20] 689 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[13] 538 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1[3] 141 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_o2[28] 285 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[6] 278 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[7] 367 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[4] 102 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1033 663 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_6 604 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_ptr_0[0] 806 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[12] 355 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[27] 929 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[21] 296 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[27] 685 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[15] 364 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[7] 547 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_739 666 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[6] 303 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[8] 411 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[9] 247 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[2] 145 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[9] 915 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1[5] 415 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[0] 241 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_4 251 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[5] 308 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IOiO1 274 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1[26] 976 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0_a2_4 332 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0[4] 615 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0_RNO[4] 71 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[17] 715 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_2_0 834 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[13] 740 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[28] 735 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[11] 362 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[1] 855 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNI4KM1RR 818 192
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_int 524 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_6[6] 123 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_O0io1_1 99 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[7] 90 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[5] 953 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[17] 333 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[25] 799 135
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[0] 13 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[15] 904 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_lsu_op_complete_ex 737 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[5] 403 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_26 641 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_i_m3_RNI3639C1[1] 828 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[2] 193 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l0li1_0_a3_0_0 237 171
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.rx_byte_2[7] 495 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[11] 561 184
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel[1] 533 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I0001[2] 169 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[13] 277 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[29] 959 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[0] 846 157
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[0] 536 169
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[1] 629 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid48 735 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[9] 359 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[30] 858 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[2] 243 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_a3 829 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[5] 88 187
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[6] 483 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[1] 404 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][21] 885 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[21] 838 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[14] 738 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[10] 341 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[15] 792 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[8] 535 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[8] 719 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_o4[0] 616 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[51] 626 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/active_1 555 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_21_RNI54RVEO3 812 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[27] 966 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_iI0Oo 322 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIKVKJ31_0 842 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1101 107 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[25] 908 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[2] 206 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[3] 566 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][14] 878 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[28] 749 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[12] 829 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[10] 273 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1098 686 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[5] 155 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1018 738 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[4] 715 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][0] 879 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[30] 952 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_452 735 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[1] 762 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_23 762 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_73[11] 382 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[14] 379 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_q_1.CO2 641 183
set_location fifo_to_tpsram_bridge_0/next_state11_23 484 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[7] 824 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[31] 652 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIANK9D_0 776 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_9_RNIO9Q5HO3 807 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_2_1_0[3] 148 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m3 17 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[6] 86 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shift_op_complete_ex_0_1 771 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[19] 321 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[6] 264 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[10] 544 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[19] 847 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[5] 192 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[7] 560 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[5] 480 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lII11 143 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[11] 526 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[1] 156 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_0[3] 175 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_403 769 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[5] 354 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_415 701 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[30] 747 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[22] 906 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[4] 436 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_2[1] 783 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_a2_0_RNO_1 749 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[29] 249 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[11] 618 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4[4] 185 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_282 662 213
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[3] 482 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2[0] 294 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2_3_0_RNIVUKUCE 806 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1 409 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[5] 724 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[24] 468 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_2[0] 107 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[46] 950 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[17] 563 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_9 645 153
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_tune_st_4_i_a2 2 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a4[0] 64 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[6] 330 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olo01 111 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[0] 611 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[3] 88 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex[0] 764 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IlIi1 216 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[20] 445 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_RNO[2] 600 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.IliOo_0 180 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[13].BUFD_BLK 630 126
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[5] 486 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_0 751 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[29] 774 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv[14] 756 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0_a3[1] 750 141
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[1] 589 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[5] 332 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[31] 812 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[11] 307 166
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_checkorun_1_sqmuxa 589 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1[3] 201 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_439 653 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_IoI017_1 304 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/abs_busy_cmb_mux.abstractcs_busy_cmb7_0_a3 832 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[9] 454 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[6] 509 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UDRCAP 440 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[13] 800 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[5] 341 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[29] 875 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[25] 890 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un18_Oo001_3 202 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0_5 768 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_931 653 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[60] 936 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l0iIo_2 397 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[1] 489 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UDRSH 606 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[39] 732 123
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[3] 469 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[10] 959 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[3] 699 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lo1Oo_2[3] 195 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_696 638 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12_cZ[14] 255 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_31[10] 353 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1[7] 963 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_2[5] 182 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[5] 524 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1055 689 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[3] 342 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[3] 242 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[8] 122 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[9] 842 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[2] 854 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_x2[2] 411 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[29] 678 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IIiO1_RNO 266 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1I11 239 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[7] 367 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[4] 697 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[7] 267 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_irq_reg/gen_bit_reset.state_val[0] 626 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[0] 348 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[17] 656 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/IilI1 318 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1[3] 83 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_RNO[8] 189 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[2] 320 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[10] 921 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[48] 820 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[11] 391 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_240 651 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[22] 554 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[6] 87 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[2] 711 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[6] 393 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[0] 899 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_1 809 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[22] 871 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_199 698 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[4] 332 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[37] 433 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1 879 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[8] 544 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[2] 217 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[15] 776 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[12] 739 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[62] 643 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_3_RNO_0 942 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_421 649 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[9] 735 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_814 774 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_722 640 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m21 695 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[5] 327 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[17] 835 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[3] 219 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[22] 979 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[9] 672 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[6] 142 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[2] 856 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[0] 339 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1253 614 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[2] 463 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_o0I01_2 369 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1_0_a2[22] 303 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[24] 768 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un4_lolIo 128 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[25] 612 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[8] 709 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[9] 208 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[11] 369 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[9] 436 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[6] 331 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2[2] 720 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[4] 158 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[14] 363 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_351 738 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0 797 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/un1_Ioli0_1_0 321 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_lsu_op_ex_pipe[1] 712 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_356 774 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[4] 648 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.SUM[0] 197 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[3] 292 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[3] 71 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[13] 69 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_lastbit_3 605 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[29] 847 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1159 759 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[0] 314 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo[1] 248 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2[3] 222 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56 80 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOOOo_4_0_a2 112 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_bcu_op_completing_ex_0_RNINFCC8F1 822 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un52_o1Oi1 72 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_I1Ii1 419 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[3] 250 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_709 719 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[23] 615 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2115_2 653 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0_1_0[0] 209 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1[18] 298 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[14] 117 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0101 109 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2[3] 679 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[28] 763 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[16] 355 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/io0i1_0_a3_0_2 322 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[9] 403 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[26] 896 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel[3] 531 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_iOii1lto2 134 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_2_0_RNO 861 168
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[26].BUFD_BLK 639 129
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane9_0_a2 18 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_gpr_rs1_rd_sel_19_m_1[3] 702 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_taken_a1_0_RNISFEIG 792 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1048 677 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[16] 62 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_OOio1_2_1 112 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un8_gpr_rd_rs2_completing_ex_0 777 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_598 714 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iOiO1 389 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0[1] 186 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4915_1_0 680 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[19] 713 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIVNFFD[9] 740 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[12] 213 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un29_loOo1_i_a2_0 322 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ii0I1_RNO 528 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[5] 664 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_2_1_0 151 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[5] 701 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[5] 259 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_24[0] 368 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un2_next_stage_state_de 746 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[28] 906 204
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[25] 64 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12[6] 342 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[3] 460 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[4] 628 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[10] 920 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[8] 767 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[31] 166 171
set_location SSDetect_0/is_match_0.un6_is_match_2 14 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ll001[1] 199 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd_2 739 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[13] 413 210
set_location Core_reset_pf_0/Core_reset_pf_0/dff_13[0] 840 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_2 338 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[9] 786 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[13] 914 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[4] 93 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[9] 931 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0_a3_0_RNO 858 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[11] 411 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[0] 362 216
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[7].BUFD_BLK 594 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_918 702 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_10 796 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/li0i1 316 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_at_flush[0] 780 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/wr_data_1 768 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[11] 965 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[0] 86 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIOI98E[27] 684 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_23_RNO 941 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[6] 531 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un137_OOOI1_cZ[20] 447 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[6] 882 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo[1] 248 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[0] 399 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data[9] 790 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[2] 747 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1[1] 474 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1][6] 792 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[2] 354 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[15] 125 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_IOoi1_6 393 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_a9_5 623 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[16] 834 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[20] 883 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[1] 376 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dpc_debugger_rd_sel_1 809 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i0IOo 136 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_a17_3_1_0 652 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_44 659 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m4_e_3 642 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_m2 112 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[22] 851 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_debug_enter_req_ex 755 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11_cZ[13] 326 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[20] 741 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[29] 737 129
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_1[4] 31 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_o1Ii1_c3_RNIRCS1B 431 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_2 126 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[25] 296 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[11] 361 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[5] 282 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[2] 599 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[16] 765 123
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[2] 499 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/un1_Ioli0_1_0 328 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[2] 770 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[4] 460 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1[7] 117 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[14] 525 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[13] 212 219
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[0] 28 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[19] 44 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24[8] 364 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[4] 885 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_3_1 833 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l0111 96 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_12_2 664 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[32] 478 214
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_7 439 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI6J8HN2[0] 157 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[9] 883 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[30] 749 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[2] 477 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_711 662 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[13].BUFD_BLK 569 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_2_1 753 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_843 677 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[1] 91 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_readonaddr_ff7_5_2 772 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[4] 401 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.CoreAPB3_0_0_APBmslave0_PWRITE_s0 631 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2124_1_RNI69MLV 660 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l0IOo 141 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[28] 787 123
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[9] 619 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[8] 130 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[28] 907 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[8] 409 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1064 630 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[4] 271 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[1] 847 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_617 665 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[25] 802 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[21] 919 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[2] 644 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_716 712 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPHFFD[6] 774 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[3] 186 211
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[28].BUFD_BLK 616 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[3] 559 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m32 167 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[2] 199 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1127 669 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_27_RNIHG10FO3 806 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO019_4 544 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.lloIo 522 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_0[4] 154 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_248 703 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[12] 847 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Ii111 288 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_409 785 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_5 395 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][26] 878 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel_3 832 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[11] 775 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[8] 480 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[26] 446 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[11] 345 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIK7BNS[14] 259 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[19] 298 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[0] 89 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv[2] 831 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_RNO_2 208 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[0] 471 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[6] 340 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_901 692 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I15 485 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[1] 206 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[9] 743 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1011 303 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m290 362 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[42] 954 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[39] 929 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_l1ll1 479 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1009 676 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[2] 73 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_a0_sx 821 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[13] 299 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_6_0_a2_0[15] 116 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_trx_os 783 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[18] 863 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[7] 913 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oo111 265 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[2] 72 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0[3] 708 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[28] 881 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[13] 254 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIAGUT5 402 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[0] 465 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[12] 741 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12_cZ[17] 254 222
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_wmux_0_RNIUMTG1[4] 30 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[18] 522 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un9_IOIOo 134 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[4] 391 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_72[11] 357 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[14] 609 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[7] 254 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex 821 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[14] 258 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_lo0i1_2 254 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo14_0_a2 438 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[27] 687 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[14] 758 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNIFBI4J[14] 519 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/next_buff_valid[0] 812 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[1] 267 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un19_cpu_d_resp_rd_data_sig[3] 817 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[28] 976 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIF83E9[7] 225 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/liOi1 283 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[3] 390 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[10] 959 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[7] 769 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[14] 411 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1[3] 416 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_3[0] 367 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 518 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[9] 487 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[0] 133 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo54 79 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[11] 872 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[18] 864 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll15 524 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2[3] 697 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[6] 168 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[9] 845 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[11] 912 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[4] 207 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[13] 802 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[51] 967 193
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[4] 572 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[5] 307 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Illl1 479 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] 521 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[0] 706 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_o3[3] 144 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[9] 272 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_49 639 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01[21] 295 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[5] 454 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[13] 768 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[36] 556 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un74_i11Io 535 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_23 794 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[9] 739 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[22] 942 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[14] 515 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m12 161 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1268 701 192
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[2] 12 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[12] 847 171
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_samples6_1_0 504 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i[0] 136 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[24] 954 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_164 680 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m15 641 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[15] 380 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un1_Oo1Io_2 485 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[15] 390 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[14] 379 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[17] 452 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[5] 291 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[28] 866 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[3] 436 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[17] 75 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[2] 376 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mcause_rd_data[31] 842 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[15] 733 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[2] 194 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[23] 751 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_3 269 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5[2] 127 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a7[0] 151 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI8BS5C[29] 755 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iil11 324 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[6] 1006 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[1] 187 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[8] 859 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[6] 414 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[2] 121 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[8] 219 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[15] 283 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[5] 546 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0[0] 720 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[27] 850 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_48[11] 279 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/havereset_skip_pwrup_4_u_0 818 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_28[1] 342 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[27] 674 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[1] 483 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_reg[0] 756 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[5] 451 214
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[9] 611 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNI1QTQ8[28] 738 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[14] 694 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1073 699 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oOll1 461 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[4] 412 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1_26[33] 490 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I15 534 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[26] 450 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llo01_0 79 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[5] 404 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2[24] 355 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iii01[0] 74 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[26] 625 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2[8] 824 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[29] 678 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_0_0[1] 713 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lliO1_1_iv_0[6] 80 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIO11[1] 87 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[11] 257 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27[5] 353 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0_2[0] 685 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[7] 406 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[27] 858 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[1] 182 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[15] 857 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[9] 846 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[0] 471 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0[0] 629 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[5] 76 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[24] 800 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[7] 269 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O1li0 106 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[21] 488 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[2] 681 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[3] 892 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[25] 696 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un195_I1Oi1_0 54 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[9] 844 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lOIi1 311 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[24] 892 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[10] 397 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[30] 738 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[12] 914 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[1] 570 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9_3 90 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0[3] 826 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[56] 605 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[37] 552 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[1] 181 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[15] 736 159
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2[7] 37 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.un1_shiftDR20 665 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[11] 312 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[2] 187 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed_RNIEIJ0C[14] 679 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[13] 514 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m6 695 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_34[1] 280 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iii01[1] 80 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_691 689 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_219 642 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDR_ne_0 655 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[21] 729 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IO011 356 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_62 748 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2_0[15] 713 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_9_0_RNO 849 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[5] 512 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[20] 869 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[6] 230 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[42] 572 169
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_17 72 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[1] 208 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_0 76 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_m10 593 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[0] 294 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_valid_mux_1 766 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[10] 530 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[52] 836 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[13] 89 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[8] 190 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[22] 349 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_ioIO1_NE_1 183 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_840 676 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi0o1 97 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un107_I1Oi1_0_0 58 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[0] 409 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2[7] 721 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[7] 209 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[38] 740 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oO111[0] 205 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[24] 630 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[1] 190 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[20] 894 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12_0 698 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[4] 945 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_ack_RNO 837 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[13] 737 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_RNIRF1VG1 666 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[7] 547 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_fence_reg 886 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_s_RNICNKKE3 762 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0[0] 118 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_935 676 207
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[0] 73 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooOi1 236 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[0] 791 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[12] 650 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[24] 959 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_3[28] 396 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_15 697 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[4] 352 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[29] 237 220
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[7] 593 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[24] 789 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_297 773 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4[3] 526 159
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[13] 48 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01_0_sqmuxa_0 166 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_530 713 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[10] 353 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[10] 89 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[6] 519 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_2[6] 702 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_o2[3] 706 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[0] 771 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_174 771 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[6] 590 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[0] 543 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[14] 648 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_783 678 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOiOo_NE_0 272 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01[20] 291 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IIO11 89 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[3] 375 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5_2[3] 196 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_0[0] 839 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[28] 463 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[0] 317 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m15_1 678 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_3_RNO_1 941 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM_0[2] 190 198
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2[5] 29 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_i_access_misalign_error_ex 754 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ioIIo 308 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1 485 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1_0[5] 190 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNIBMA4P 787 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[0] 850 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[7] 330 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[6] 422 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[21] 921 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel 856 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_a4[3] 173 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un442_lIlo1 242 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[9] 248 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[29] 753 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/un1_iOI01_1_i_0 214 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2_RNI580NA_0 617 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_15 331 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[29] 870 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0_a2_3 103 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[5] 199 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[10] 112 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_310 771 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[11] 575 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNIP1M9E 791 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed[6] 641 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_coarse_sel_0_sqmuxa_0 32 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_ptr_0[0] 782 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[6] 447 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo[2] 283 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_0[0] 721 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[11] 409 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_8[28] 393 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[62] 950 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[26] 412 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[17] 430 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_sn_N_8_mux_i_i_o2 566 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[8] 498 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OloI1 413 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_fenci_proceed 814 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[14] 61 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m11_i 29 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_2 373 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1105 701 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_s0_0_a2 516 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[17] 333 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[12] 812 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[2] 140 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O0o01 110 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[10] 812 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[3] 292 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_892 627 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[14] 593 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_oi1o1_0_m2[0] 84 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[14] 160 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOOo1 352 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_5_2 303 171
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[15] 489 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Oo1Io_4 484 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o[0] 112 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoo1_i_a2_0_0 91 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_resetn_tx 599 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo 224 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_addr_align[1][0] 758 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[13] 735 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_RNI3CI9AB1 811 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949 699 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I0ll1 458 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_1[6] 193 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[8] 386 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_iII01_5 363 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[30] 910 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/un1_NxtPrdata23_0_RNI6GCHA 506 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[28] 292 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_holdsel 556 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_4[8] 189 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[27] 506 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[13] 740 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un4_Oio11_1 363 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/N_123_i 812 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[6] 168 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[2] 742 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_0_RNIC3CB5C1 777 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff_10_f1_0 760 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[4] 257 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[5] 352 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un45_oIiOo_1.CO3 279 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[12] 466 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/empty_out_RNO 608 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[22] 917 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1202 715 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[8] 654 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m5 661 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[34] 406 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[2] 385 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[12] 78 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mscratch_sw_rd_sel 798 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_767 773 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_115 655 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_0_sqmuxa_1 614 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[27] 770 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oo0l1[0] 497 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[2] 505 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4928 675 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m27 665 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[15] 903 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0[1] 628 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[8] 732 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[32] 458 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[24] 458 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[7] 955 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[28] 714 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/un1_Ioli0_1_0 298 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[5] 228 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[2] 154 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[5] 208 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[0] 820 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg[2] 761 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[1] 234 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[4] 847 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[17] 911 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[3] 121 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match[1] 789 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[8] 710 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[12] 858 147
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK 634 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2[2] 677 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[31] 905 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[6] 394 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un165_I1Oi1_2 53 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo[3] 283 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI4LNGA_1 746 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[2] 342 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1 312 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1056 721 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[1] 623 115
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1l1_u_1_1 523 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001[0] 178 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[11] 966 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1301 713 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[8] 320 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII1118_0 136 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[3] 493 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[39] 953 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_869 673 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_20[20] 172 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_0_3_1_1 826 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[17] 946 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[3] 415 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un19_sba_req_rd_byte_en_int_0_a3_0_a3 784 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[17] 260 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[0] 301 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[3] 667 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[19] 924 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[7] 856 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[26] 908 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[15] 619 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10] 688 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[51] 629 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_946 711 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO[0] 817 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_i[1] 764 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[57] 962 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[21] 862 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[14] 543 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[16] 716 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIC53E9[11] 258 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[13] 406 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m1_0_a2_2 885 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[30] 404 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[9] 306 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m190 341 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[13] 211 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[2] 849 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_0_sqmuxa 760 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_valid_reg 730 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[7] 344 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[29] 844 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12_cZ[16] 294 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[17] 939 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[0] 166 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO_0[15] 176 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO_1[0] 147 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.implicit_wr_dcsr_cause_wr_data_1_m2s2 823 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[12] 769 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/O00o1_f0[2] 115 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[29] 736 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_OlIi1 208 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_33[11] 298 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_ptr_0[0] 792 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un11_csr_trigger_wr_hzd_de_6 751 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2[15] 712 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[3] 653 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oooi146 137 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_0_1 735 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[14] 121 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_1[13] 747 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[9] 101 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m40 254 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIGTK9D 751 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_0_0_RNI889TQ 314 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[36] 462 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[34] 397 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m18 82 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[16] 833 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo[5] 214 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[28] 878 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[8] 132 193
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[25].BUFD_BLK 615 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_28 913 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q[1] 565 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_7 771 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[13] 774 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[6] 460 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][6] 898 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_592 654 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[25] 385 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un41_Oo1Io 483 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_RNO 820 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[14] 882 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IO0Oo7 270 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[2] 865 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[6] 56 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[4] 716 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_905 714 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[11] 540 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/dealloc_resp_buff_0 788 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_2_0 822 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[4] 367 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1188 630 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/llIIo[0] 275 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[27] 175 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[5] 417 213
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[28] 471 241
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_m1_e 766 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr[2] 833 118
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_s1_0_a2 507 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[6] 541 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un18_lsu_op_str_ex 719 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[10] 436 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[27].BUFD_BLK 638 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_RNO[1] 706 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[0] 125 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_10_158_a2 252 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un17_iIlo1lto3_fc 269 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[9] 370 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_500 688 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[9] 480 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[0] 742 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[4] 492 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m15_1 642 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[12] 349 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[30] 822 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[26] 942 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0_6 588 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[5] 159 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1_0[8] 151 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[13] 348 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[25] 808 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[3] 216 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01_0_sqmuxa_0 174 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[31] 752 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[28] 910 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNIOST5C[30] 652 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_68 750 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO_2 242 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[27] 872 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_RNO_0[4] 409 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[7] 785 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[23] 962 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[15] 892 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0iOo_7 149 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[18] 979 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_2[1] 108 183
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[21] 59 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un35_ool01 189 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_41[0] 364 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2_RNIVCD062[2] 718 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_2_0_0_a2[1] 827 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[11] 879 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_loli1[0] 324 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_777 747 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[40] 228 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[5] 415 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[8] 840 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[23] 749 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[4] 51 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr5 831 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a4[2] 677 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[4] 367 190
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/clr_flag_9_0_a2 26 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[5] 367 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[7] 145 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m3 36 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[19] 847 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_196 626 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[22] 720 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_5 272 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR20 664 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[4] 155 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[28] 890 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_323 653 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[2] 408 193
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[2] 485 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1 333 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[8] 353 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[8] 186 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1_1_RNO_0 314 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[4] 492 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_3_1[0] 823 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[5] 104 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[6] 740 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[6] 419 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m167 377 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[9] 742 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNID7FGI[4] 573 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[26].BUFD_BLK 614 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[10] 234 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/olo11 395 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[11] 312 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/alu_op_sel_1_iv_0_cZ[1] 709 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_1[2] 558 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.CO0 496 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_1_sqmuxa 616 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_33 757 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[5] 134 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[13] 130 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[6] 193 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1[6] 200 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[12] 85 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[5] 121 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_879 640 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_865 627 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[17] 704 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[3] 306 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1o11 398 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[16] 463 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[19] 598 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[14] 257 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo[2] 185 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[10] 341 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[20] 992 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[29] 860 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[7] 360 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[11] 94 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_URSTB 568 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_846 725 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[1] 228 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_wr_ptr[0] 784 160
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[13] 512 249
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[4] 593 202
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[11].BUFD_BLK 593 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err_ff 764 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[8] 317 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_8[0] 805 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/olOo1 328 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_msrxp_strobe 570 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15_4 249 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OO011 298 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNID9I4J[13] 531 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiOIo_RNO 231 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[29] 905 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_5 286 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1302 721 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[9] 182 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_1_0 838 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_lIoO1 312 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[10] 508 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_5[0] 703 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mie_sw_rd_sel_2_0 814 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0[0] 830 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0Ii1 216 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m17 677 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_27 678 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[18] 820 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo[3] 284 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I11i1_0_a2 377 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[29] 623 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[8] 369 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[6] 340 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un18_OilI1_0_a2 352 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[24] 325 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[1] 324 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l1l11 315 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][2] 888 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[13] 726 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[26] 758 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[10] 360 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1iOo 219 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_0_1_0 816 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNICPK9D_0 822 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O0oI1 472 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[24] 893 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.overflow_int_4 511 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un160_i11Io 534 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o[1] 116 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[25] 898 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[0] 176 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_80[11] 353 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_RNO[2] 668 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[0] 709 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_245 687 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[2] 340 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[29] 705 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[8] 534 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[17] 846 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[17] 239 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[30] 871 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[18] 46 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[10] 508 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int_RNO[64] 835 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[10] 245 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_fence 749 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15] 637 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[30] 870 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[12] 534 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_2[1] 402 213
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[1] 30 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[17] 945 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[17] 794 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[19] 402 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[0] 620 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/lIIl1 518 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_8 221 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[0] 125 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[23] 818 171
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg1Seq.controlReg15_1 512 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[2] 416 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[0] 346 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[8] 879 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[6] 524 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[7] 857 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[15] 971 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1094 713 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0[4] 300 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[4] 339 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo_RNISIVKC 265 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][0] 877 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1 391 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_I1oo1_4 121 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0 771 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1014 776 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[6] 456 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/wr_en_data_or 855 138
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[14] 613 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_gpr_addr_1_sqmuxa_0_268_a2_0_a2_0_0_0 841 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_olli1lto15_0_0_1 245 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_3[0] 360 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[14] 275 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[5] 443 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[4] 770 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[19] 671 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lIIo1_0_o2[0] 355 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[21] 235 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[7] 207 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_access_mem_error 816 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[8] 96 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand0_mux_sel_1_iv[0] 862 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a0_2 763 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[6] 134 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m25 137 204
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync[1] 21 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un13_OIoO1[6] 74 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[10] 729 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_0[1] 957 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO 708 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1OIo 227 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[2] 701 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[6] 727 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_2[4] 245 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[3] 795 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[25] 363 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[31] 964 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_1_0 782 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[4] 277 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[10] 490 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[20] 912 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_9[2] 799 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[9] 185 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[5] 64 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3[4] 992 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[10] 151 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001[0] 214 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[24] 814 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[0] 191 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[4] 176 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_int[0] 790 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo56 73 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_1[4] 756 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_26_RNO_1 946 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[34] 472 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[4] 340 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oiiI1 422 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[12] 30 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[3] 825 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_11_1 939 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/i10I1 486 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[20] 936 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[27] 807 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oOOo1 354 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[24] 721 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[15] 254 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/iI001[0] 212 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_425 652 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[16] 266 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_10_i 758 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[2] 773 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[1] 353 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_19_RNO_1 867 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[17] 106 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[2] 260 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_uncompressed_half_i_o2 723 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utime_rd_data[29] 732 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[5] 989 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[14] 901 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_932 618 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_10_s_0[0] 805 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[3] 150 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_1_0_0 808 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[12] 290 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[0] 167 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[8] 228 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[7] 505 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI2BDEP[5] 264 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[3] 484 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_875 794 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[13] 372 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_239_i 348 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[42] 248 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[31] 511 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[24] 732 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m24 160 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i[10] 365 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_OoI01_1 302 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[17] 102 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.penable 733 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[21] 315 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_357 677 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[7] 204 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[7] 884 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo[9] 205 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[9] 406 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[2] 794 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[17] 412 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/resetn_rx_s 590 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_1_1[1] 693 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[30] 911 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1298 702 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[14] 207 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1088 683 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_1 244 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un118_i11Io 533 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[16] 279 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNITOG631[20] 79 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_4_c3 21 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1218 775 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[10] 394 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_32[11] 294 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_467 750 201
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[3] 52 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un9_o1ll1_5 266 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m71_2_0 137 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_1[2] 978 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_4[31] 721 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[12] 215 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_3[4] 684 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[13] 114 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[1] 707 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1_3_0 438 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_39[3] 569 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[20] 487 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[58] 960 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_6 786 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4915_1_5 731 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m1 677 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_2 785 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_30_RNO_0 946 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[0] 329 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m80 386 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[5] 330 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_3[29] 398 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[4] 502 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[4] 477 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Ii111_2 288 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[30] 856 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[13] 63 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_2[0] 698 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_280 772 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[17] 474 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Oi0I1 532 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[2] 737 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24[4] 330 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[4] 108 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[27] 894 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Olol1 438 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[6] 287 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[1] 246 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[0] 702 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[22] 776 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[5] 733 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_117 772 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[30] 618 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[0] 822 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oOoI1 422 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001[2] 207 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex[1] 758 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[3] 207 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_o1Ii1_axbxc5 430 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m19 635 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[17] 478 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[29] 625 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24[1] 376 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[30] 467 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[32] 944 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[3] 699 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[9] 700 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_6[15] 127 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIIi1_1_RNO 323 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[2] 60 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[13] 778 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_2[3] 145 192
set_location PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_DELAY 2467 4
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[3] 478 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_990 662 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[8] 44 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1[30] 304 174
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0[3] 603 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[18] 383 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_10_RNO 439 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[26] 836 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_1_0_N_2L1 745 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_ex_1[1] 769 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_824 760 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3[0] 124 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[5] 194 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[18] 392 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[1] 370 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m275 380 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/IilI1_RNO 292 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[5] 67 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[2] 627 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_7 631 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[6] 316 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_25 722 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[1] 749 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_1_1 63 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1044 629 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[24] 236 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[2] 62 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_read_mux 761 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[14] 559 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[3] 372 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_30[1] 341 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_1[8] 771 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[3] 338 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1_RNO[0] 153 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u 620 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_714 676 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[39] 444 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_2 811 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[12] 343 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_Ilio1_2 88 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[0] 241 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[6] 868 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oiol1_1 319 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[12] 688 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_494 676 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch[1] 704 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOOl1 429 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_2[3] 326 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[15] 123 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un8_req_addr_mux[0] 740 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1122 733 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[15] 771 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m315 366 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[0] 131 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un13_OlIi1 316 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[4] 409 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[30] 830 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_15[10] 286 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2114_3 650 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un11_trap_val 760 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIV779G 843 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1[0] 336 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[33] 464 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[1] 782 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[3] 178 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_1 89 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[2] 315 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[8] 423 181
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[1] 14 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0o01 112 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[7] 161 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[4] 403 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[2] 198 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_exu_alu_result212_1_d_2_RNI9RSEJ91 805 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l1i11 350 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_1 404 171
set_location pf_init_monitor_0_0/pf_init_monitor_0_0/I_BEN_6 1750 1
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2 772 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_r[31] 559 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid_10 774 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0_3 51 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[17] 742 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[6] 329 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m54 41 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[27] 910 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[6] 772 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2_3_0 756 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[6] 400 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[31] 924 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_3[15] 104 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[4] 698 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2_RNO 796 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[20] 564 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIIi1 236 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[14] 114 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1011_RNO 273 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[25] 928 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[17] 703 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_928 672 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_28[2] 346 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un8_I1Oi1_2 58 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un483_lIlo1 286 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control113 632 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[6] 455 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state140 603 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[2] 252 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM[0] 191 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[10] 375 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[1] 266 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_d_decode.un8_cpu_d_req_is_tcm0lto3 778 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_i_m2[2] 756 117
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[1] 13 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[8] 132 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1[27] 928 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.misa_sw_rd_sel_1 833 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_91 772 201
set_location PF_CCC_0_0/PF_CCC_0_0/pll_inst_0 2460 5
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m8 159 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[1] 244 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[10] 350 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc4 32 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/gen_bit_reset.state_val_12_u[0] 844 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[2] 201 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[11] 365 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_ssel_pos_RNO 597 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[18] 829 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a7_4[0] 155 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1o01 113 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 294 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_477 748 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_3_f0_i_a3 757 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_5[1] 296 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[14] 260 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNI0JLVBG3 777 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_IIiO1_1_0 321 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_33[0] 305 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[13] 82 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo267 172 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_883 749 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[5] 286 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[3] 507 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[0] 190 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[22] 446 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/li0i1_RNO 316 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[1] 545 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx_5_iv 597 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1248 677 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_2 141 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[20] 848 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[2] 91 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[4] 506 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_error 736 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[0] 348 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[15] 598 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[3] 507 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[4] 340 184
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[30] 469 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo[1] 151 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_902 750 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_i0iOo_0 217 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[4] 855 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_288 656 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_721 651 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI8UM8I 822 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[7] 388 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[5] 481 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m25 150 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[13] 797 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[1] 569 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[3] 76 166
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitcnt_1 609 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI91JD4P3_0[0] 867 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_23_RNO_1 940 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[2] 300 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_I1ii1_0_2_1[0] 132 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20[16] 377 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[10] 265 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[0] 794 147
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[0] 478 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_627 630 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_613 626 192
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[12] 52 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[16] 107 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[18] 975 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_726 712 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[29] 178 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15] 636 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_16 293 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[31] 907 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiIOo 140 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_21 282 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[5] 189 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[6] 654 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_0[6] 135 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1157 647 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[14] 854 133
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_RNIBS411[0] 46 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places58 917 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Oil01 152 207
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[16] 489 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[1] 80 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1124 675 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_a2_2[1] 70 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[18] 904 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m28_2_1 162 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_28[9] 352 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_31[9] 349 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[19] 463 216
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[3] 13 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.OOoIo[0] 323 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[13] 821 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_60[11] 278 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff9 810 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[13] 69 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IOil1 393 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[15] 778 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[5] 139 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[9] 738 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1207 679 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[13] 794 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[22] 849 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_6_1[0] 790 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_64 722 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[7] 803 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[26] 844 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOIIo 224 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[20] 590 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[16] 211 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[33] 262 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[2] 180 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[4] 206 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[45] 825 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[1] 853 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[10] 880 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4957_1_0_2 701 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[1] 138 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[31] 955 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[30] 465 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[30] 874 166
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[19] 57 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy[19] 793 156
set_location PF_IOD_CDR_C0_0/RCLKINT_0 580 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIMVBS7[2] 888 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[3] 841 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[1] 79 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1 339 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[1] 847 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[0] 435 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_fiforead_2_sqmuxa 553 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[28] 784 145
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count[2] 518 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_339 668 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ill11 384 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[9] 184 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[6] 249 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_cnt.xmit_bit_sel_3_i_o2[1] 530 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oioo1 91 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[1] 185 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[4] 147 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1[3] 83 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/un1_Ioli0_1_0 357 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1[9] 233 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/clr_wfi_waiting_0 789 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[30] 721 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[11] 734 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[27] 508 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un12_I1oo1_4 123 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[27] 964 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[8] 519 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2130 658 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[27] 963 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_resetn_rx 589 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[3] 736 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[5] 296 232
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_1 608 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_1_sqmuxa_1_0_a3 772 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[6] 305 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv[2] 719 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[2] 435 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[3] 424 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[12] 260 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_ns_i_a2[11] 652 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I0Oo1 356 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[1] 368 216
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[10] 618 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[39] 432 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_6[0] 627 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[5] 317 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_4[9] 128 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a2_6 755 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex[0] 709 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[4] 574 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un147_I1Oi1_0 67 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write[0] 707 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[4] 328 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[15] 571 177
set_location fifo_to_tpsram_bridge_0/next_state11_16 483 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2] 725 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii0o1 89 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[5] 210 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[4] 258 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[13] 440 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_3[14] 351 228
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel17_0_a2_0 1 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_dummy_target 772 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l10Oo_0 227 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[6] 195 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un159_I1Oi1_1 62 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[0] 842 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.CO4 939 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[15] 125 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1310 808 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[1] 433 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO[2] 149 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OlIi1 323 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[30] 489 243
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un1_l0o01_0[0] 118 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[4] 885 133
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_7 438 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[11] 842 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m11 26 177
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3] 22 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_14[10] 283 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[2] 329 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1 720 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_31_RNO 921 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[17] 904 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_5 391 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[7] 175 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[1] 841 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m6_0 135 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[26] 939 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_738 719 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[2] 349 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_1[0] 784 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[3] 448 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_8 691 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[15] 959 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[29] 842 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un29_csr_trigger_wr_hzd_de_3 815 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[14] 364 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[12] 956 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[10] 534 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI9GAGO[30] 895 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_6_RNO_0 815 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[0] 740 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/N_826_i 259 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_synch[0] 697 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un5_o1Oi1_3_0 79 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[12] 846 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[7] 87 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1[1] 515 168
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/pause_lane 17 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[7] 211 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[2] 442 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[12] 761 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[33] 262 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[0] 424 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[9] 321 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[18] 294 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un39_OOOI1[3] 445 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[12] 542 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[24] 953 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13] 692 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[0] 774 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_646 650 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[3] 598 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_963 711 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[26] 809 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_4[0] 832 120
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_28 506 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[4] 888 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[6] 736 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[2] 275 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[11] 712 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_a2 88 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_52 694 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[12] 52 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l1Ol1 429 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/frrst_1 504 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[1] 318 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1_RNO[24] 345 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[4] 816 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[12] 120 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_RNO[0] 626 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][4] 875 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[12] 537 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[7] 189 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[24] 458 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[24] 991 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[19] 892 144
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code_1_sqmuxa_i_i_a2 23 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[28] 675 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[10] 486 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[29] 762 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un128_OOOI1[24] 469 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_112 721 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[1] 471 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_a2_0_9_5 94 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l0iO1 329 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_96 717 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[12] 840 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[2] 399 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINDRQ8[14] 734 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[29] 478 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_149 711 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_880 770 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[26] 763 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[4] 198 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_req_resp_state_1 765 144
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/empty 499 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1[1] 261 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un155_I1Oi1_2 41 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_229 813 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[1] 245 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/soft_reset_taken_retr 821 159
set_location fifo_to_tpsram_bridge_0/next_state11_18 515 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.m5 27 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_4 676 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un11_lsu_resp_ready_c_1_RNIN2I2L 799 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[14] 838 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[8] 126 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_511 702 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_5[2] 184 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[1] 853 154
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[2] 491 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_3 472 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[8] 754 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[27] 498 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ii1o1 87 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_5 834 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][14] 882 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[26] 470 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[2] 644 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[26] 322 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un114_OOOI1[10] 482 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[3] 209 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_30[10] 352 222
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE_RNO_0 0 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[22] 769 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[14] 608 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[16] 286 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[1] 171 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[18] 589 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_837 639 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[11] 552 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[6] 214 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[6] 63 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[11] 366 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[10] 861 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_0[5] 171 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[13] 241 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0_a2_0[16] 92 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[13] 742 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_I1iOo_1 218 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[10] 768 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[0] 819 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[11] 104 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_614 675 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_2 334 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv[0] 709 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[40] 836 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.misa_sw_rd_sel 832 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_18 282 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo[1] 289 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01 377 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_a3_0[13] 125 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m8_e_0 710 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[16] 890 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrmc_1 281 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_14_i 761 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[28] 959 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[43] 818 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0[31] 348 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[20].BUFD_BLK 629 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/un1_Ioli0_1_0 386 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2[40] 289 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_1[6] 141 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[14] 66 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_3[3] 122 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[2] 569 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[5] 392 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[29] 237 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[2] 802 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[3] 951 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[2] 125 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_3_sqmuxa_1 731 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[17] 573 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/branch_cond_iv_0[0] 745 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[28] 619 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[9] 293 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_5_1[2] 188 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ilio1_RNICD455 120 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/next_buff_valid[1] 787 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_548 676 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[28] 755 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_18_RNI8TNVEO3 798 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_2_1_0 750 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[6] 235 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[8] 402 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[10] 90 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[21] 918 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[10] 533 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_1_sqmuxa 556 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNI3M2R7[18] 106 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[28] 772 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un147_I1Oi1_2 66 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un3_buff_resp_head_uncompressed_full 714 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_917 721 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0_1_0[0] 278 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[5] 312 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IIIOo_RNI4555G 137 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[54] 832 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[3] 328 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ilOOo[1] 127 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[32] 445 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[24] 883 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112_1 678 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[1] 730 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][29] 880 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2124.rv32c_dec_mnemonic2124_1_0 655 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_3_RNO_0[0] 650 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[40] 708 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[16] 357 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[1] 424 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[13] 418 208
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/un1_diff_sync 15 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.trigger_debug_enter_pending 777 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[17] 907 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_RNO[5] 657 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNII968E[16] 722 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_309 759 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[4] 291 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[11] 339 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un200_lIlo1_fc_1_1 268 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OIll1 539 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850_3 641 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_320 664 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_398 648 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m8_3_sx 808 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[6] 280 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.un1_shiftDR20_RNIJ92RC 663 129
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_21 482 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_20 292 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[11] 148 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[18] 1001 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[24] 894 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_trap_ret_retr 769 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_5 209 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[25] 679 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[18] 425 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_4 243 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[29].BUFD_BLK 613 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_2 788 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_2_RNIPUBB9 323 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[6] 374 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_2[0] 258 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[3] 761 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_wfi_ex 759 169
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[6] 508 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_2[1] 702 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_76[11] 342 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_6_0_a2[15] 118 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1OIo 226 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[35] 384 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_355 749 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Il1O1_3_1 483 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[37] 404 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[9] 482 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_41[6] 371 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[24] 809 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[4] 263 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[16] 914 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un6_Tc0_h_En_0_a2 569 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[2] 137 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[43] 933 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/txrdy_int 507 166
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_19_RNIR5LRM 69 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_973 749 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/un5_Ii001 190 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_891 681 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_sw_csr_rd_op_cnst 721 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNIJBP0PD 824 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[20] 718 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[0] 776 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_1[2] 789 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_o1Ii1_c3 429 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO[3] 335 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[10] 861 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[25] 938 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_12 702 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[3] 402 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[3] 251 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[18] 856 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[22] 1005 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[15] 545 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iil01 153 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[20] 735 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_4_a0_RNIFMJOM 780 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_565 711 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[3] 726 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0Oo 274 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIDI8GO[23] 890 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[41] 822 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[13] 775 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[30] 467 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[0] 864 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiOIo 229 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864_1 576 5
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc5 601 120
set_location Core_reset_pf_0/Core_reset_pf_0/dff_5[0] 830 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[20] 867 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_708 706 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_939 712 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg 789 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_412 688 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_125 700 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_1 92 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_URSTB 567 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[4] 552 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[27] 366 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[4] 859 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[8] 49 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_0_sqmuxa_i_o5_RNI86JQL 172 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_RNIF8OSC3_0 795 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iliO1 330 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[17] 389 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[27] 873 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[27] 804 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[13] 355 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[5] 804 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[4] 339 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[29] 313 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[19] 397 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[32] 275 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[0] 534 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_1_0 55 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_986 770 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[4] 640 184
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[24] 476 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1 332 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un18_oii01_1_0 75 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[1] 698 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[12] 332 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[28] 857 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[4] 363 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_7_f1_0 759 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_valid_0 804 150
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[2] 476 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[4] 535 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[1] 707 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1[13] 128 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[9] 877 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_1 697 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[18] 835 124
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_RNO_0 601 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtvec_sw_rd_sel_1 831 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I16 534 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_u_1_0 794 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4_1[21] 453 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[7] 238 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[11] 435 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[24] 902 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[7] 244 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[2] 106 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[8] 467 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[5] 845 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[3] 491 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state142 605 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO[1] 321 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o0Il1 459 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[0] 279 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1_a2[27] 866 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[2] 852 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[14] 608 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[11] 266 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_1[31] 352 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[7] 758 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[22] 1004 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[22] 634 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[8] 401 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_5 636 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[29] 799 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20[6] 396 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_RNO[0] 620 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[5] 660 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[2] 341 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[5] 754 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1138 650 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[8] 337 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[14] 904 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0[1] 185 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[13] 122 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[14] 355 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[3] 384 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[7] 224 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0] 477 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_807 708 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][3] 769 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00Oo_0_a2_1 229 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[23] 468 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[30] 283 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[2] 468 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ii1Oo 202 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m44 127 207
set_location COREFIFO_C0_0/COREFIFO_C0_0/REN_d1 479 241
set_location fifo_to_tpsram_bridge_0/ram_w_addr[0] 469 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un1_instruction_2 639 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[19] 853 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[2] 533 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_32_1[0] 929 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_2_1[1] 694 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_58 793 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m64_0 171 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[5] 191 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[14] 64 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_37 722 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_OoiOo[5] 282 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_3 842 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[19] 952 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_tx_1 422 211
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_pktend8 608 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[12] 715 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un12_gpr_rd_rs3_completing_ex_0 903 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[5] 228 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[3] 549 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un42_o1Oi1_1 75 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[13] 378 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_reset_pending 781 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[14] 349 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_0_a4[3] 916 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[31] 730 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[17] 379 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state[1] 762 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[6] 143 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[19] 741 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[22] 542 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[6] 504 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[21] 677 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[11] 725 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[45] 926 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_i_0_o2_RNIK9BH2[4] 825 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_42[1] 339 222
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_0_sqmuxa_1 40 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[11] 440 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[2] 144 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_a0_3 745 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utime_sw_rd_sel_3 847 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_2_i_o3[15] 115 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[1] 284 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIIIo 217 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_lO1i1lto8_1 250 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IoO11 98 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_1_RNO 863 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/un1_Ioli0_1_0 338 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[10] 669 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_inhibit_ex 750 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1 315 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[14] 500 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0_d 798 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0[1] 729 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[13] 761 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[26] 754 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[8] 353 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Olii1 144 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[0] 210 178
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[31] 486 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_states2_i_a3 852 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[19] 875 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_575 760 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_311 688 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[10] 328 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_316 771 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[0] 364 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_1_RNO 813 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_436 748 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[13] 410 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/trigger_op_addr_valid_de 748 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[29] 710 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[8] 351 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[4] 342 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[14] 117 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2[11] 121 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/IilI1_RNO 397 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[13] 87 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[13] 841 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[6] 346 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[4] 328 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[24] 892 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[12] 742 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IO0Io_2_0_0_.m3 26 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_o3 799 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[61] 644 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[8] 290 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[5] 405 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[7] 493 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un459_lIlo1 267 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[12] 911 150
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_1lto1 24 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[28] 722 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[1] 944 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[1] 237 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_RNO[2] 762 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[10] 866 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m14_2_0 158 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i1oi1 328 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[29] 743 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[6] 385 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel_1_0 833 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001[0] 191 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_151 677 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[5] 238 226
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_4 425 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[2] 561 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/misaligned_sbaddr_i_o2 746 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0o01 110 175
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[12] 507 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90 179 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[5] 662 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_3[1] 190 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[3] 280 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_accepted_de_s_0_RNO_0 825 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[27] 631 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/step_debug_enter_taken 815 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.IOoIo[0] 461 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/OloIo 322 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[6] 203 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[14] 214 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_886 651 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_641 712 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[6] 192 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4_i_m2[8] 492 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[7] 677 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[10] 811 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/o1101 138 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[5] 482 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_352 664 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_7_1 386 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[15] 608 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0[0] 757 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[28] 465 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[21] 527 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[23] 326 199
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[4] 491 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_O0io1 97 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01[1] 286 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[12] 830 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_1_RNI4ESAH1 795 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_RNITONSM 751 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[20] 413 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2_1[1] 878 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[25] 544 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[12] 247 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_o2[1] 676 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00Oo_0_a2_0_1 235 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0[2] 660 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_48[9] 952 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[11] 520 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1775_0_0 60 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[9] 248 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[16] 731 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_909 713 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first 590 211
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[11] 494 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[13] 351 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_0[1] 728 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OOio1_2 98 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[20] 760 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[5] 343 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12[2] 362 231
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[2] 552 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[4] 792 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int 746 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[27] 657 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[19] 916 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_20 807 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_iv_0[2] 714 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_2_0 815 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[9] 110 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_954 710 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_ready_reg_RNO 789 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[9] 899 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state_0_sqmuxa_i 855 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[30] 856 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[26] 862 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.implicit_wr_dcsr_cause_wr_data_1_ss0 824 147
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[8].BUFD_BLK 568 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[12] 511 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_285 652 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_0 816 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIAD984[15] 889 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[0] 283 216
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO[5] 28 204
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[7] 549 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_1[0] 626 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[7] 979 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[6] 434 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[1] 832 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_4[0] 623 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[55] 841 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_247 687 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[25] 965 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][19] 877 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[28] 766 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_readonaddr_ff7_5 771 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/IilI1_RNO 350 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/liol1 318 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_24 877 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_1[4] 990 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OlIi1 243 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[0] 272 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[10] 416 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOo01_Z[0] 81 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_10[0] 920 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[11] 366 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[14] 385 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loOi1_RNO 234 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[3] 17 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_rd_byte_en[3] 752 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[14] 884 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[0] 773 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001[6] 206 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI6H8MP[12] 256 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[43] 259 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_5 555 201
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[8] 29 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[22] 915 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4[5] 183 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[9] 561 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[31] 444 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_0[0] 837 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[1] 416 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0[3] 838 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[23] 612 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[23] 724 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[30] 640 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[20] 916 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_18 773 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m121 350 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un111_I1Oi1 56 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1[0] 803 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1_RNO[25] 343 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[10] 114 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25[0] 343 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[28] 477 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_i_o3[31] 765 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[7] 207 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[4] 309 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[4] 207 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[20] 914 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[9] 215 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[2] 104 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[15] 67 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[21] 857 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[1] 403 193
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[9] 39 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[1] 564 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[13] 406 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[11] 99 181
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[4] 53 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O11i1 376 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[5] 357 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[14] 398 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_o1Ii1.un17_o1Ii1_c2 430 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utimeh_sw_rd_sel_5 816 144
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt[0] 608 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_6 838 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[2] 516 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[21] 700 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[2] 759 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[28] 829 184
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_parity_err_0_sqmuxa 505 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[0] 213 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[15] 56 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[0] 483 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[28] 470 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0[1] 829 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_ready_1 693 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[2] 889 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[1] 471 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO[0] 155 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[24] 891 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[53] 606 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_842 745 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[21] 948 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[0] 861 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[42] 253 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[9] 123 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[2] 835 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[4] 871 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[6] 700 130
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1[6] 599 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[16] 483 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_0[0] 365 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m249 378 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un207_I1Oi1_2 42 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[24] 602 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[2] 410 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[19] 956 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[3] 441 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[31] 889 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[18] 754 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/wr_en_data_or 883 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[19] 742 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un4_IOoi1_3 385 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[14] 493 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un53_ool01 194 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[4] 846 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIFJA84[29] 947 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_35 716 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_i00i1lto15_3_0_0_o2_i_o2 259 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_N_9_mux_i_0_a0_0 822 150
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_stxp_strobetx 564 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a7_0_RNO[0] 164 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q[5] 605 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oio11 366 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[10] 917 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[20] 730 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioOIo 236 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_3 237 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[0] 344 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un51_i11Io 514 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[8] 365 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/wr_en_data 832 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1_m2_e_3 221 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_2[1] 232 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[11] 751 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/mnemonic536 875 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv[0] 728 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR19_1 655 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[3] 484 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[23] 904 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OO0Io_2_0_0_.m9 25 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_alu_op_sel_ex7_RNIGHJJAU3 767 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[30] 648 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[20] 278 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[15] 236 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[4] 857 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un80_OilI1_0_a2_0 386 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[5] 875 138
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2[2] 476 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1[2] 856 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[3] 758 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[15] 641 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[54] 832 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[14] 318 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oo101 108 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[20] 978 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[0] 505 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[29] 772 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[15] 282 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[2] 251 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1084 670 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[12] 304 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_37[9] 963 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[11] 431 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1038 783 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_2_iv[13] 760 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_ff 767 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4957_2 692 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[24] 838 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14[13] 938 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[8] 183 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[7] 49 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[0] 418 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un91_i0lo1[2] 385 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001[7] 212 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_406 703 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[15] 262 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[19] 832 126
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[31].BUFD_BLK 612 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[20] 733 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[4] 669 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[12] 887 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0] 721 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIVLRQ8[18] 709 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Iioi1 148 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[21] 707 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[5] 86 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_1 602 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[28] 750 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[25] 865 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_addr[5] 748 142
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_dataerr 595 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[10] 738 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.debug_resume_req_3_1 821 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[4] 247 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[14] 205 214
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n3 607 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_2 208 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11[1] 77 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_31 748 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[10] 259 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[21] 858 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m16 69 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n2 601 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_1[1] 656 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[5] 223 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[6] 507 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[5] 781 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[22] 796 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_0 253 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[3] 136 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[10] 273 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig[25] 740 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[28] 946 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[30] 607 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[8] 861 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_op[3] 741 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lO0Io.m4 68 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_3[7] 374 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0Oo 265 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un80_OilI1_0_a2 393 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un23_I1Oi1_1 56 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[1] 126 205
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_1_sqmuxa_1 39 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[20] 916 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[30] 518 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[3] 205 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_stxp_dataerr 571 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[30] 792 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[3] 242 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic851_4 641 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[12] 885 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_cmderr[0] 832 118
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_11_1 690 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1li1[5] 336 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_d_1_a3 765 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_554 673 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[8] 866 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_13_0_i 389 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_127 663 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[26] 940 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_1_RNO_0 794 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[9] 545 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_lsu_op_ex_pipe[2] 708 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[0] 93 181
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4_i_m2[6] 470 246
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_4_1_0 800 147
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[22] 478 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs2_complete_ex_s_RNIE9L3621 822 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[13] 795 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[0] 453 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[60] 849 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2122_4 677 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_0 726 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex5 769 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[31] 595 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20[12] 396 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[22] 639 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_5 381 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2[10] 110 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[19] 687 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[16] 454 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oIIl1 521 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[8] 206 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_542 686 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[10] 316 213
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state[0] 23 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_0[1] 726 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[12] 741 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[18] 287 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1288 723 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[14] 540 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[13] 383 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNIESQP1S 770 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[21] 712 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_oioOo 242 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[16] 742 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[3] 637 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_493 754 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_read 573 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[1] 352 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[4] 195 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1[3] 472 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/IilI1 350 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1_2 442 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo_RNI8T7D[1] 251 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[16] 732 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv[3] 122 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mstatus_sw_rd_sel 830 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_i_a2[2] 413 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx 597 208
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2[0] 29 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[4] 555 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[7] 729 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[2] 706 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_3_2[0] 296 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OI111 332 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[12] 55 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1106 641 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[14] 331 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_243_i 349 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_724 661 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[14] 347 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[10] 541 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0_RNO_1 875 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/IilI1_RNO 290 213
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[7] 43 220
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state142_RNIR1FRF 604 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[15] 212 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_7[12] 54 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_6 424 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[27] 909 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[2] 738 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[17] 716 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_lm_0_fast[0] 899 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001[0] 194 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa 572 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[6] 861 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_4[2] 189 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1152 640 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_operand1_mux_sel_1_iv_i_a3_3[0] 664 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[6] 770 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_25_RNO_0 938 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/mem_rdata34_0_a2 794 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[4] 882 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[3] 688 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_req_op_4 748 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr_2_iv[0] 814 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[26] 387 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[15] 66 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_1 217 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[28] 611 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[12] 128 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI4LNGA 798 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[17] 95 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[3] 683 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[11] 375 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI25S5C[26] 675 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[6] 797 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[9] 480 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[6] 520 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[11] 883 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3 812 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[20] 881 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_10_1[3] 810 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[16] 410 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m1_0_a2 840 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[16] 298 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[6] 416 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1l1_u 474 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[6] 144 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m28 113 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[3] 317 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[10] 273 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_34[8] 964 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un12_IioOo 222 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1oO1[2] 262 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_236 674 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_12_RNO 807 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[5] 874 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_146 760 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_1[13] 138 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[1] 513 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOoOo 232 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_28 867 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_2_0 806 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[13] 269 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[18] 617 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oo1Oo[1] 205 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[5] 266 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[2] 607 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[10] 852 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[10] 313 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[12] 276 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_1_3 737 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[21] 778 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m12 786 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[7] 272 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[1] 245 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3[31] 770 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[7] 319 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_21_RNO_0 823 183
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.i01Io 69 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[6] 50 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0_1_0[0] 340 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[27] 122 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[31] 652 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[30] 127 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_excpt_i_access_fault 759 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_553 784 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[12] 350 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[12] 743 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[5] 558 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[30] 606 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[1] 153 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[1] 320 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_3[2] 249 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[15] 314 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[8] 351 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[11] 686 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un115_lIlo1_1 234 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[3] 28 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[3] 676 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_2[11] 834 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[5] 720 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[3] 232 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_debug_enter_req_retr 809 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[15] 910 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1178 620 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[0] 473 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o2_0 742 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state93 601 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[30] 906 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3[2] 769 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[8] 129 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[0] 251 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0[15] 125 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIV80P9[0] 71 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_430 727 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[11] 66 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_11 806 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[2] 217 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1[7] 141 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2_1[8] 796 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[22] 839 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lI0l1[0] 499 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/IilI1_RNO 332 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_4 399 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][2] 890 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[2] 770 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[16] 839 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/un2_li001_1 184 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[18] 275 166
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[6] 470 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[25] 927 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[0] 747 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state21_1 784 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[27] 736 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/un1_iOI01_1_i_0 282 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1o11 358 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[18] 907 150
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[8].BUFD_BLK 592 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[7] 881 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_54 774 210
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[1] 38 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[11] 115 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[15] 255 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Io101 99 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_623 747 222
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[5] 43 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/il001_3_1.SUM[2] 171 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_799 720 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_synch[1] 699 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[19] 593 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_4[15] 99 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul_ack_RNIT73PPE 839 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[0] 65 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m19 71 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[21] 462 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[6] 61 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[7] 174 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_csr_rd_data_ready_3_0 857 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[5] 717 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[31] 296 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[0] 783 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[3] 343 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[1] 197 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[22] 389 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1154 734 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[3] 256 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_valid_sba_0_o2_2 821 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abstractcs_busy 863 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[6] 231 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_3[6] 176 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[42] 428 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[2] 717 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[5] 196 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[39] 567 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[4] 650 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[8] 242 211
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[2] 588 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv_1_RNO[0] 651 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[34] 317 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_req_valid40 747 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[1] 831 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI58984[10] 855 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m57 294 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[8] 776 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[0] 512 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[16] 368 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_2[1] 116 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[6] 523 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[10] 408 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_5 379 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Iil01[0] 279 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_3 690 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_1[3] 763 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[3] 872 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[14] 246 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[22] 782 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_16 806 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[8] 340 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[17] 860 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[4] 740 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_556 650 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/un1_iOI01_1_i 299 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m20 116 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a5_4 165 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[8] 775 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[6] 352 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[25] 799 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[13] 833 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 519 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[29] 903 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_o2 87 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiiOo_2[2] 170 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[24] 943 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[14] 564 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4[0] 183 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/CLR_FLAGS_N 18 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[1] 282 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[11] 223 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI5LHS6[2] 270 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_5 437 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_9[8] 239 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[7] 205 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_OoiOo[1] 284 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[23] 824 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[16] 107 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[9] 73 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q[4] 568 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mie_sw_wr_sel 797 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0[2] 184 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[42] 564 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[3] 976 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[1] 625 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_Oo1Oo_i_m3[0] 210 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[0] 556 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[1] 589 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[4] 934 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O1ll1 462 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ii101 86 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].un1_buff_req_wr_ptr_1_0_a2 833 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[30] 746 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2125_i 938 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[13] 888 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[18] 758 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[0] 273 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2[2] 730 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[6] 63 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[26] 878 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo_1[7] 278 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[5] 856 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[18] 91 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[30] 792 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[19] 756 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ioO11 103 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[7] 930 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_2_0_o3[15] 833 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[5] 773 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[12] 437 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[4] 616 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[30] 527 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[26] 878 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[15] 353 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[2] 386 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iooo1 91 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2121_1 660 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff_RNO 760 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[60] 639 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2_8 671 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[5] 171 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[24] 952 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[4] 489 181
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_29 67 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[10] 879 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[6] 238 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[13] 906 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state_4_fast[5] 859 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a1_0_RNIMAFE4 789 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2[15] 966 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_o0il1 411 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[18] 451 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[1] 433 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[15] 965 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[9] 373 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[2] 213 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[11] 885 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_499 661 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/clk_en_dm 844 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[14] 163 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[6] 887 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oIOo1 325 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/extract_os_i_loop_l1.un12_req_os_i_src[5] 788 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[28] 794 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[22] 720 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[16] 758 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI01Q5C[16] 730 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[7] 367 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m24 146 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0]2_0 881 153
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/empty_r_fwft_RNO 514 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[12] 282 229
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg_1_sqmuxa_i 592 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[29] 873 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_991 711 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_686 736 207
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto9_i_a2_5 485 255
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_rd_strb[1] 781 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/N_641_i 711 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_dataerr_5_u 595 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[2] 368 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_i1Il1_RNO_0 499 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_9[11] 293 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_2[3] 950 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[1] 398 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[23] 385 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2[2] 27 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[9] 621 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[12] 263 216
set_location PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1 579 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[6] 274 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[15] 244 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[15] 256 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_206 662 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[2] 349 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][25] 878 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[10] 435 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[22] 856 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_0[0] 674 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_a2_0_RNO_0 751 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOIo1_2_0 324 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[5] 330 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[10] 448 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utime_sw_rd_sel 845 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[12] 410 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_2[7] 184 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_0[3] 145 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lIoOo 388 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat15 662 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.rx_state18_NE_i_1 524 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[34] 479 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m27 150 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_14 806 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_2_0 258 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[21] 781 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[38] 449 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state93_RNI606C01 628 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[7] 509 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_fe 602 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_6 702 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff_RNO 749 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[15] 476 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_12 807 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_189 699 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[8] 147 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m57 40 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[16] 723 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_13[9] 304 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[2] 861 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[5] 259 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[0] 602 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_a2_0[3] 523 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[19] 882 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[11] 398 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[4] 413 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[11] 259 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26[3] 382 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[9] 741 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[8] 76 190
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[2] 26 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[21] 921 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_122 662 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[21] 729 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[13] 315 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter_4[1] 876 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[2] 436 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[9] 315 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][3] 758 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_RNIDCBP2[1] 221 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_RNIBTPAB 823 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNIT4M05E[5] 805 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_400 686 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1[1] 278 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/IilI1 331 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/un1_Ioli0_1_0_a2 408 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Oi1Oo_1_0_tz 218 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un10_i0Oo1 290 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[26] 675 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_940 739 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[3] 706 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[12] 97 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_0 769 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[4] 841 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_data_out_dx_31_1 643 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[32] 833 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11] 710 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[55] 623 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/IilI1 329 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[2] 417 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_521 675 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_ex_s_s 762 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[30] 989 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O0lI1 229 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[12] 467 187
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_4_u 539 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[10] 367 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lOOo1 422 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_72 638 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[8] 928 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[8] 854 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd_4 738 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m17_3_1 700 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[5] 898 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_5 740 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[1] 487 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[28] 607 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[7] 459 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[30] 892 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[1] 303 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[3] 844 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/fifo_reset_3 693 129
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[12] 48 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_o1Oi1_4 74 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_2_3_1[7] 109 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[6] 100 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[9] 818 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[7] 832 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[4] 458 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.un3_ex_retr_pipe_sw_csr_wr_op_retr 852 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[8] 237 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_i[1] 187 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_5 272 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O11i1_1 375 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1[4] 194 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[21] 520 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_624 746 222
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_1 438 6
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[25] 852 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_588 765 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[7] 718 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[9] 172 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oo1o1_i_o2 100 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[13] 243 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a0_2 825 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_26[11] 364 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_444 735 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e 679 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[7] 962 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[25] 740 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[3] 739 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0_o3 101 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[10] 321 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[33] 498 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[3] 181 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[23] 952 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un141_I1Oi1 65 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4953 706 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1078 681 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[17] 943 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[22] 727 123
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_2[3] 482 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[33] 471 213
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state133_RNIINL0C 603 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_sel_reg[2] 743 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[13] 435 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[31].BUFD_BLK 637 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0_1_0[0] 268 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[8] 232 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[6] 917 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[22] 676 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[2] 625 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un17_iIlo1lto10_fc_0 267 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un40_i11Io 506 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[11] 852 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[30] 862 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2_0[7] 722 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/llI01[22] 292 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_sn_m3 835 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/i_access_mem_error_retr 744 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_2 688 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[8] 268 231
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/rst_b[0] 12 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[18] 879 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[10] 230 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[13] 211 216
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[20].BUFD_BLK 595 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[28] 798 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[1] 219 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_927 759 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_4[2] 182 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_6[13] 705 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[26] 1000 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[11] 245 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z[0] 183 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[1] 711 150
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[4] 621 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[8] 184 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_4_iv_i 827 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[3] 795 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un55_I1Oi1_1 51 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_alu_op_sel_ex7_1 764 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[44] 600 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[11] 281 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJ9RQ8[12] 742 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2[0] 221 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_32 878 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[24] 718 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un12_lolIo_1 54 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_4 846 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[14] 245 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[5] 229 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[8] 457 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i0IOo_RNIV2N4M 150 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4_1[7] 202 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un13_ool01[0] 202 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_N_9_mux_i_1_0 800 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_5 115 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_0[2] 692 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_1 603 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[28] 479 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo 101 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dpc_debugger_rd_sel_2_0 830 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m4 101 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a2 666 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_635 700 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_1[4] 148 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2[1] 879 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un11_start_div_3_RNIQEVCD 928 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[17] 807 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[21] 799 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_659 758 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[5] 86 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_2_0 220 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[9] 276 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[25] 676 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/i1111_2 354 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[1] 315 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ii0I1 528 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OoIOo_RNO 139 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[9] 168 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_262 758 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[0] 465 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1065 734 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[31] 769 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_1_4 747 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[9] 347 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2[1] 774 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[3] 208 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_resp_rd_data_sig[7] 752 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[3] 249 183
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[16] 51 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[1] 872 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[20] 300 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[2] 173 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[1] 150 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[17] 657 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_7[9] 409 216
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_16 73 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_inhibit_ex_0 755 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[39] 731 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3[3] 823 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[11] 192 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[5] 374 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[31] 437 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[0] 484 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[18] 709 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[5] 401 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[45] 955 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[15] 417 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[4] 487 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex_2_0 788 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[6] 322 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[8] 135 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[18] 325 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[14] 903 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[27] 809 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_i_access_mem_error_retr 744 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1[17] 319 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR[4] 650 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[0] 735 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][23] 892 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[32] 728 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[21] 794 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_bcu_op_sel_ex7 778 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[31] 466 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[23] 741 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[6] 319 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_422 755 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[21] 472 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[14] 272 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[29] 942 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[16] 543 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[23] 711 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[5] 709 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[38] 722 127
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[6] 590 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooli1 333 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[6] 203 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[5] 946 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[3] 831 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_3_0 224 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[3] 652 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[12] 379 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[25] 343 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i1IIo_RNO_0 324 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[7] 889 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mie_sw_wr_sel_1 829 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[32] 722 120
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[4] 36 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_liOI1_6_2 291 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[22] 457 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1263 771 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[23] 752 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[29] 941 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo[7] 279 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[4] 509 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[3] 760 126
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[1].BUFD_BLK 566 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[17] 839 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[25] 65 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[11] 124 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2] 730 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIQ3FO8 361 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[33] 628 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[14] 247 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[18] 1003 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001 250 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[14] 375 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q[0] 564 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[28] 611 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[17] 885 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1[0] 78 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[20] 977 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1 269 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[2] 462 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[8] 268 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[32] 401 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_317 735 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[2] 426 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[42] 819 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[0] 208 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[22] 557 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_23_RNI98TVEO3 813 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_251_i 356 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m1 113 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[31] 494 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/llo11 384 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[16] 38 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[14] 152 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[20] 891 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[8] 620 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[10] 849 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[2] 382 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[32] 741 120
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[7] 65 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iil11 294 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001[2] 190 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2123_1_0_RNID8RV21 664 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_30[9] 351 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_dbreak_retr 751 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_10 687 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[5] 873 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OilOo[0] 220 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ilio1 87 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[0] 201 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_iv_8_0[0] 808 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[8] 655 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[7] 323 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_0 423 3
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync[0] 15 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_2_1 989 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[11] 365 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE 589 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[5] 341 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[7] 172 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un7_next_res_pos_neg_0 929 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[17] 470 241
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un2_req_resp_str_req_buff_addr_misalign[0] 770 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0] 708 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[3] 532 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I1lIo_2_0_.m5 69 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[7] 33 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtval_sw_rd_sel_1 831 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[14] 791 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un28_il0Oo 225 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[4] 105 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[14] 967 159
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[19].BUFD_BLK 628 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[1] 123 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[3] 154 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[3] 211 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[9] 196 174
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[0] 45 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[4] 866 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[2] 870 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[18] 973 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[16] 518 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m3 53 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[7] 204 202
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_10 564 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[52] 598 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[21] 855 207
set_location PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL 11 63
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lll11 447 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[9] 206 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[16] 910 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[21] 729 127
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[0] 574 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[51] 967 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOo11[0] 195 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[2] 768 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mcause_excpt_code_wr_data_0_cZ[3] 824 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001[1] 212 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_ss0_0_a2 787 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[11] 726 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4914 675 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_I1Oi1_2_0 40 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_18 623 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un1_I1Oi1_4 82 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[6] 386 192
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[26] 66 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io[3] 512 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[7] 705 124
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[12] 616 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI5RR0F2[6] 255 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oi1o1 89 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_or[0] 828 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2[3] 746 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_5[12] 120 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_RNITOT59[0] 134 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un4_bcu_op_completing_ex_0 758 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int35 776 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llOo1 328 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[3] 196 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[6] 245 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[11] 151 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[6] 249 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][8] 880 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_3[6] 201 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[4] 196 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[15] 560 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.awe1 629 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_272 747 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0_a3_2[5] 558 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[2] 573 168
set_location PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0 24 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_1[4] 952 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[8] 168 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[21] 765 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[25] 308 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[18] 467 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[9] 844 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[19] 881 198
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[30] 68 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o[0] 244 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][1] 884 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/req_os_d_src[7] 784 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[5] 154 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[3] 282 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l01Oo_1[2] 192 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_o2_1_0 99 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[24] 892 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[0] 200 202
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_first_2 593 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[28] 879 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_321 761 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_326 676 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[16] 839 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un11_lOO11 85 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4[12] 186 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mip_sw_rd_sel_2_0 825 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[48] 620 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[14] 500 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[16] 863 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[4] 358 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[11] 481 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_78 658 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[35] 384 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[19] 932 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_OOio1_1 86 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[6] 458 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset_3 690 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[20] 874 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[10] 400 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[8] 221 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[20] 595 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[4] 270 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3_1[4] 846 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[4] 977 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[27] 915 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[3] 409 169
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un4_UTDODRV_3 437 6
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[1] 357 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[1] 246 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_681 650 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[8] 599 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[6] 142 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[24] 735 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[22] 1003 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0 776 153
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[1] 502 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111_2 289 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_605 675 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[40] 715 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0[4] 410 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext 617 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_i[4] 894 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_2_1 125 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[31] 906 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[15] 759 120
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[1] 497 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4[2] 658 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/wfi 759 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[4] 825 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[6] 210 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_7[11] 293 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[5] 412 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11 291 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111 289 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_exu_res_accept_retr_3_RNI02H86R 788 168
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_RNIQBLDF[0] 467 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[3] 360 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[8] 922 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[5] 861 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[0] 855 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_l1i11 352 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.OOoIo[0] 369 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[5] 548 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[0] 553 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_5 75 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[5] 591 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][3] 894 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIRL98E[28] 727 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[4] 469 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_timer_enable_0 780 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[7] 841 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/un1_Ioli0_1_0_0 266 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][2] 782 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_RNO[1] 700 120
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/overflow 511 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[31] 383 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[3] 761 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un25_l1I01_1 384 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_8[0] 301 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[15] 743 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[46] 243 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[12] 927 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_995 675 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[27] 841 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[5] 80 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_16_RNIDATUEO3 811 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_287 676 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_0[2] 136 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[8] 209 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[7] 485 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[24] 681 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[12] 192 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[3] 355 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_lOiOo_i_o3 216 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2[0] 951 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_1[0] 785 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[17] 909 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[13] 369 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[21] 955 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[3] 734 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[16] 833 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1[21] 430 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m44 257 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_590 639 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[14] 261 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[5] 397 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[8] 528 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[18] 65 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[19] 916 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[3] 171 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[0] 333 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un2_exception_taken 795 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[6] 250 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_wr_en 859 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[2] 355 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1[1] 795 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[7] 111 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[3] 214 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[2] 779 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata1_sw_rd_sel_7 844 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[31] 714 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy[21] 857 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr_s_s_0 806 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[10] 230 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val_RNO[0] 820 147
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[1] 612 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[6] 734 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[6] 877 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[5] 401 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_10 796 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[14] 927 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[12] 718 126
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_consecutive 557 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[13] 907 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[7] 224 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/liIOo_RNIHMIO6 148 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_233 616 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[2] 840 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[38] 630 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_130 783 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[29] 843 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[20] 389 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_OlIi1 221 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l0I01 319 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_Z[0] 835 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[25] 828 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[18] 903 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_0 268 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[10] 716 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJBTQ8[21] 711 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[3] 132 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[4] 554 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[1] 861 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[14] 590 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[20] 387 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[16] 859 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un10_oioOo_1 274 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[2] 528 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[20] 861 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_348 820 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_2 734 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[10] 770 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[9] 256 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_882 640 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m23 42 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/pauselow 624 118
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[9] 637 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[2] 418 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/un3_empty_rd_1 702 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[20] 701 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[35] 396 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[2] 477 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[9] 928 153
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[3] 37 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[32] 325 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[10] 553 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[17] 405 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[4] 244 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[27] 944 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1304 675 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIERK9D_0 745 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[6] 444 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs1_rd_hzd_3 741 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[21] 954 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[15] 274 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[32].BUFD_BLK 636 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[26] 727 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[20] 939 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_841 721 225
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[5] 486 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[8] 717 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un155_I1Oi1 41 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[6] 389 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21[6] 333 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[11] 568 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_15 730 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[7] 345 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][13] 881 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[13] 800 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[22] 446 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[22] 705 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[1].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/gen_bit_no_reset.state_val[0] 782 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1034 642 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un103_OOOI1[8] 355 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2124_i 937 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[12] 726 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m8_2_0 41 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[11] 924 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/un1_Ioli0_1_0 289 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[15] 370 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ooli1_0 334 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[22] 947 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[8] 121 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[55] 970 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[30] 917 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[5] 873 147
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_n4 602 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO[4] 757 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5] 685 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4952_1 706 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_s_13_RNO_0 443 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2[29] 169 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[23] 452 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] 303 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[4] 413 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[1] 914 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_0_sqmuxa_1_2 762 132
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[0] 552 186
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA_0_sqmuxa 595 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[17] 622 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[15] 743 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gnt_0[0] 757 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[9] 248 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/IilI1 405 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[7] 483 246
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q[4] 604 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[15] 643 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[2] 966 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OIii1[3] 182 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[13] 902 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[31] 271 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[12] 851 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[1] 831 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[10] 381 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un34_fifo_mem_d_31_2 558 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[23] 675 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[2] 148 184
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[4] 17 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_cnst_9_6_.m14 157 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[7] 323 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_70[11] 287 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_5[4] 218 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[27] 466 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[13] 712 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[6] 543 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oo001[3] 181 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[28] 490 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1[14] 771 123
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[1] 573 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00016 179 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[2] 461 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_1_0 647 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948 699 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lI0i1_0_0_o2 267 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a4_RNILR4FC[3] 707 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[41] 378 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_2[29] 954 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[2] 805 145
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[0] 575 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_0[0] 135 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_RNIQFEQD[2] 81 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[11] 522 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[26] 880 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un13_IOIOo 137 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[23] 780 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[4] 548 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[59] 973 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2[24] 976 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto10 247 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m10 68 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[44] 952 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_0_sqmuxa_1 757 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo_5 153 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a4_1_0[0] 64 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[0] 325 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[7] 488 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[36] 557 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l1I01_1 376 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr[0] 834 157
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_2_sqmuxa 566 210
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo12_0_0 612 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[1] 714 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iOo_RNO_0 218 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[20] 429 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m78_1_0 337 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01_0_sqmuxa_0_a5_0_0 173 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[1] 766 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[25] 412 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[27] 940 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[12] 912 177
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9 616 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[28] 708 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[6] 271 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_10 428 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_RNIL72R7_0[11] 78 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][30] 896 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[1] 488 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_2[14] 772 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_fetch_ptr_yy_RNID5KKIO3[22] 804 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[30] 870 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[15] 833 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIH9FFD[2] 712 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[8] 322 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[25] 567 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[6] 510 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_334 737 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[21] 448 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[0] 486 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_3 745 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[16] 331 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/IiO01 485 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[1] 897 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[8] 348 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[2] 849 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[5] 703 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_582 700 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1238 638 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_o3 801 117
set_location PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3_1 13 164
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_0[2] 724 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_1[0] 154 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[2] 207 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[23] 920 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[11] 711 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[25] 725 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0_o2 632 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[7] 475 210
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_ac0_11 44 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_6 241 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[0] 302 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[33] 413 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01 185 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[27] 782 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_Olii1_5 147 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[24] 837 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv[1] 729 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[24] 866 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[10] 855 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[7] 659 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/un1_iOI01_1_i_0 307 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[20] 378 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[7] 863 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[21] 473 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i[0] 63 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_0[4] 690 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_19[20] 191 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[9] 760 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[20] 464 202
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st[1] 14 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[23] 367 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_4 305 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[2] 337 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state134 631 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[18] 68 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[9] 321 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[3] 314 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[28] 902 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_13[4] 475 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[19] 468 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[17] 874 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[21] 854 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[23] 880 150
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_5_c2 20 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_readonaddr_ff7_4 770 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv 786 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[18] 505 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_0 776 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a5_0_5 164 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[5] 134 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01[1] 307 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0[1] 187 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[0] 206 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[4] 471 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOol1 400 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[5] 859 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[8] 188 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[31] 845 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_763 782 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[9] 491 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[1] 212 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[16] 404 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[30] 159 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[2] 471 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[27] 711 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un310_lIlo1 321 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_203 695 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[5] 617 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_28[20] 183 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[31] 907 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter[1] 876 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[13] 712 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_100 710 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/gen_bit_reset.state_val[0] 861 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21[9] 375 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[2] 888 147
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[25] 63 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_5 661 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0] 703 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[23] 978 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_44[11] 292 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[3] 379 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un51_I1Oi1 51 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[26] 991 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[0] 363 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_tz[1] 721 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0_1_0[0] 336 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14] 694 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[25] 874 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_2_N_4L5 741 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un3_i11Io 505 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en[0] 758 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_186 700 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_1[15] 114 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[6] 893 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR_2_sqmuxa 661 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[23] 463 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[6] 129 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI3B5AH 825 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[4] 830 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[30] 731 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[2] 492 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[1] 293 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO[15] 222 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[2] 507 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[11] 301 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[6] 820 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_3_1.CO1 608 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[1] 847 127
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_slave 600 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[8] 208 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_c_0_RNI6PJI7 802 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_0 96 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[14] 1009 165
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[0] 478 241
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[4] 829 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un35_I1Oi1 36 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2_d_1_0 650 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[27] 953 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_3 676 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[4] 556 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_8[0] 220 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1]_RNICLNUF[2] 770 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[4] 772 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr[1] 697 121
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_1 615 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_O0li1[0] 225 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_q2 609 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_d_decode.un8_cpu_d_req_is_tcm0lto18_7 830 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_33[6] 960 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[26] 680 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/resp_dest[0] 738 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_valid_i_o2_1_0 824 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1066 770 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[4] 714 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4911_2 699 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1120 653 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex_1[1] 758 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1_RNO[0] 329 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.oIiOo_RNO[3] 283 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[7] 195 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid40 763 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[9] 346 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[9] 300 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_36[9] 963 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[1] 545 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_strobetx17 600 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[4] 235 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un17_oIiOo_1.CO3 293 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_6[8] 96 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv[7] 713 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[13] 230 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[27] 938 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc3 17 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_valid[0] 812 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[58] 637 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[25] 358 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[15] 777 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_27_0_RNO 885 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m7_0_a4_0_1 822 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_rd_op_retr 792 142
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[6] 596 192
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc1 27 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un423_lIlo1 249 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_req_valid_1_1 757 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2[1] 723 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[10] 881 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0_o2_0 266 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[19] 914 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[13] 539 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat[0] 691 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[16] 870 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_a2 728 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[3] 61 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[7] 123 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_315 665 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_16[1] 400 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[6] 890 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[4] 592 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[28] 819 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[20] 729 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_19 281 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[11] 562 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0_o3[1] 83 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[26] 872 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[8] 304 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[11] 880 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[1] 508 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un17_ool01 193 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[17] 748 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[22] 620 171
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[5] 70 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOo11[0] 201 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_13 663 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[30] 787 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[4] 543 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[12] 829 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[48] 617 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[10] 798 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1iOo_1 225 186
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[5] 41 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_6[29] 723 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[16] 709 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_14 812 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1_RNIEA0D6[0] 416 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_rd_pointer_q_1.CO1 609 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_3 304 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[1] 942 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_5_RNO_0 871 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[17] 758 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[31] 596 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_tick_4 598 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[46] 609 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_10_0[22] 220 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[4] 397 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[28] 836 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1095 753 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_2 622 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2118 676 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[30] 902 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1[1] 347 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[25] 378 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1015 637 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_1_sqmuxa 771 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[26] 826 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[4] 375 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lo001[1] 197 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[30] 523 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_set_wfi_waiting_1 782 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[17] 542 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[14] 836 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_5[0] 65 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6_5_3 743 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un8_cpu_d_resp_valid_sig_0_0 801 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_valid_iv_1_RNO 814 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IoOl1_1_1475 437 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iI1i1_0_a2 374 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[7] 279 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_RNII9A0H[1] 111 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2]2_0 876 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_773 663 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1027 618 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[8] 480 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_3 75 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[1] 58 202
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[11] 492 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_304 718 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2[2] 219 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[38] 392 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_44[10] 291 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[30] 733 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[7] 406 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[1] 411 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[20] 549 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r_RNO_1 500 255
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[12] 880 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_74 771 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[29] 758 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[17] 757 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[10] 319 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[15] 403 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[15] 831 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2114_1_RNI5AAK5 673 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Oooi1 327 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux 752 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/OlIl1[0] 469 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[3] 150 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[21] 545 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[4] 113 184
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_wmux_0_RNITLTG1[3] 28 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_ff_7_f0 756 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/un1_Ioli0_1_0 322 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[4] 863 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[13] 692 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/un1_iOI01_1_i_0 206 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[20] 849 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_154 781 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retr[1] 748 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[20] 860 129
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[2].BUFD_BLK 565 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1293 650 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[7] 254 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un5_IlIOo_0 135 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[29] 936 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[49] 597 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2[0] 725 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[31] 767 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2125.rv32c_dec_mnemonic2125_2_1 651 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_iv 615 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[13] 865 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNIURBE01 786 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1213 629 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0[2] 805 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_18_RNO_1 866 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_stall_csr_2_2 717 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_il0Oo 250 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii1o1 88 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_sqmuxa_2_a0_2 835 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[9] 128 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O00i1 239 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[4] 323 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_2[3] 152 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m24 639 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_0 723 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1_RNILOR4J 821 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1 370 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIIo1_RNO[4] 408 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[0] 354 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto8_2 231 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[0] 415 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_1[6] 638 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[16] 857 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_992 769 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[8] 275 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[10] 843 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01_0_sqmuxa_0_a5_0 172 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int_1_sqmuxa_1 786 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[28] 612 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[5] 268 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_2_a2[2] 121 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[4] 165 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[1] 166 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[11] 289 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto15 234 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[1] 302 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[6] 1008 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[1] 718 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O0lI1 290 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2[24] 202 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[40] 949 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[1] 780 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_12_cZ[15] 253 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[4] 309 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[1] 278 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un541_lIlo1lto8_3 237 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[1] 193 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/N_10_0_i 176 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[27] 727 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[8] 428 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[59] 838 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_9 787 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un3_o1ll1[11] 312 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11[14] 92 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_I00Oo 249 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[8] 41 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0[30] 797 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[30] 810 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[6] 770 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[3] 349 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un351_lIlo1 315 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_Oooo1_tz_tz_1 61 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_90 734 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/gen_mtime.un3_apb_int_sel_0_a2_1_8 735 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[4] 226 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[17] 710 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[28] 231 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/lO001[3] 204 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_gpr_addr_1_sqmuxa_0_268_a2_0_a2_1 851 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[8] 101 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[14] 724 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[5] 857 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[3] 784 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2[4] 219 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_1_0[1] 651 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[27] 742 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_o3 697 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[25] 866 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][20] 879 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[15] 757 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[0] 720 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo[3] 269 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[4] 374 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[19] 461 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a7_0[0] 147 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_8 254 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[6] 595 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[18] 856 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[7].BUFD_BLK 574 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[24] 937 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un11_ool01 195 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[15] 831 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[8] 366 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[7] 404 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_0[0] 950 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[23] 381 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[1] 862 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.lliOo[5] 286 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[11] 499 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_type_1s2 776 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m37_1 161 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[6] 390 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[7] 333 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[12] 551 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/un1_iOI01_1_i_0 307 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_2 233 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[4] 482 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/OloIo 516 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/instr_inhibit_ex 744 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oii01[0] 74 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[3] 621 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1[3] 801 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un27_lolIo 124 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[19] 955 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[24] 801 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[19] 894 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_req_complete_reg11_3_0_0_a3_0 605 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m47_1_0 43 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[42] 253 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_1[1] 762 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOIo1_1 296 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[7] 916 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[0] 165 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[10] 130 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[11] 930 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_980 686 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[31] 404 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[30] 904 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[26] 613 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[15] 307 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[25] 911 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA[5] 567 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[19] 896 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[3] 954 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[33] 399 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[15] 961 153
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[5] 471 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg 820 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[0] 469 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIlIo 267 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig18 600 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1_0[1] 54 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[0] 178 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[9] 521 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_valid_u_RNI46SCU 800 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un13_loOo1_0_o4 349 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[36] 407 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1[0] 132 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[3] 169 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[31] 947 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Olo11 390 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3[5] 938 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[6] 434 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1045 736 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[59] 635 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[0] 317 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_111 770 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_0 569 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[5] 700 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[2] 657 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[11] 75 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa_RNILBV7N1 725 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1074 688 198
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_axbxc5 47 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_mux_sel_retrc 745 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_443 638 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[27] 356 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[9] 116 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3[8] 880 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[2] 711 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[17] 701 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[0] 439 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_484 702 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[10] 321 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_2 74 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI7HN97[14] 248 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un1_IoI11 444 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_9_164_a2 253 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[18] 516 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[5] 718 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[13] 870 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[6] 930 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_valid_ex_2_u 783 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[12] 808 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[1] 739 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n3 317 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1[4] 235 222
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1.SUM[2] 22 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_312 701 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[5] 326 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[3] 157 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[2] 297 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[14] 207 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I0001[0] 174 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_24_0_RNO 887 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_6 254 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[9] 54 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1_RNIQHFRC[1] 206 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[10] 130 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[24] 687 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[4] 490 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[0] 952 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[31] 733 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[2] 498 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[7] 363 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[1] 240 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2116 675 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[1] 331 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[5] 851 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[21] 722 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[8] 40 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[6] 682 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un31_l1I01_1 398 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_23 617 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ol0Oo 274 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[12] 358 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[8] 326 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[44] 946 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_4 73 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[1] 355 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[20] 991 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[10] 858 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m50 126 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1243 682 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_7_0 219 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1_m2_e_5 223 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[29] 900 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[30] 902 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[1] 233 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_empty_0_a2_RNIA2LUU 796 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0OIo_0_a3_1 218 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[27] 175 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lOl01 145 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[34] 826 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[15] 719 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[18] 727 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_914 748 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[12] 318 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1] 699 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIAFL4C[1] 696 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_11[11] 290 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[19] 522 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[0] 421 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[22] 474 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m67_1_0 113 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[2] 505 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[8] 199 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_0 238 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[7] 194 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un263_lIlo1 326 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_16[0] 391 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/res_pos_neg 932 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[34] 937 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[14] 113 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OlOo1 330 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[26] 720 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112_1_RNI03J3J 683 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val[0] 793 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOii1 154 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[20] 596 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14_2 420 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_539 770 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[0] 738 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i[1] 367 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1001 652 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un9_o1ll1_7 274 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[0] 267 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[1] 267 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[9] 554 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2_0 75 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_exu_result_mux_sel_ex[2] 724 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1[16] 428 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_reg4_RNILISNE 789 147
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SWITCH_LANE_RNO 16 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv[9] 712 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[13] 926 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11_ns_0_a2_0_12[22] 218 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_i_access_mem_error_ex 753 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01_3_1.SUM_0[3] 189 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_sn_m5 845 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_5_RNO 870 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[17] 963 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[8] 420 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[7] 361 231
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state[0] 559 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1278 773 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[22] 230 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[61] 979 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[6] 411 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[22] 999 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[28] 946 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1129 652 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[29] 859 153
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_RNO[1] 13 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[31] 406 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_25_0_RNO 888 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l0iIo_1 439 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[23] 734 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[1] 505 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oooo1 90 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/pauselow_RNO 624 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoOi1_RNO 248 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[18] 473 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4915_3_0 687 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[46] 950 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[24] 691 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[1] 343 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[20] 815 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[0] 208 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_757 724 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un3_ooOOo 132 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[0] 15 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_strobetx8 591 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_43[8] 993 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un19_OIiOo 193 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[23] 842 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[7] 370 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[36] 403 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0[1] 691 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1201 710 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[19] 188 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[19] 517 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIJBFFD[3] 734 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/l11I1 299 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo[0] 285 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_11 808 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[4] 935 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3[6] 179 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[22] 553 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[3] 246 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[11] 492 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/un4_IIo11_17 290 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o0ll1 456 190
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[4] 503 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_69 755 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mip_rd_data_1[3] 809 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[12] 350 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[2] 554 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[3] 148 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[7].BUFD_BLK 604 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_749 759 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[20] 830 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[0] 477 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[9] 180 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[10] 264 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[5] 372 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0_a3_1_0[1] 826 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[1] 941 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo55 78 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[6] 519 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[5] 133 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[2] 657 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_859 782 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2[18] 193 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[8] 168 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l000110 176 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01 378 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[11] 415 198
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state7_0_a2 22 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[2] 88 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0_a3 119 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[21] 411 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex[2] 740 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[17] 424 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25[1] 350 216
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[24] 63 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_bit_reset.state_val_12_u[0] 786 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[28] 231 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[12] 805 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[4] 415 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[10] 665 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_260 685 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[7] 810 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[26] 219 217
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_11_fast[7] 500 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_2_i_o2[2] 784 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.dpc_debugger_wr_sel_1 805 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[3] 953 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848 673 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[4] 240 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_735 664 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_24_RNO 880 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[14] 901 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[29] 775 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_26_RNO 937 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[0] 841 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[1] 186 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[16] 403 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[9] 283 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_399 697 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[12] 350 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI0l1[0] 472 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[1].BUFD_BLK 603 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_327 792 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[13] 702 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[2] 291 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m253 379 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[29] 507 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_6 718 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[3] 409 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state134 602 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[27] 938 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[2] 315 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo_RNIBMSF3[0] 285 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[5] 548 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[0] 535 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[35] 405 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[3] 139 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[2] 62 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_d_1_sqmuxa_1 645 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_shifter_unit_op_sel_ex[1] 778 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_42[9] 354 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[9] 208 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[29] 860 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1_0_1 779 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2_1[14] 794 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[10] 715 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[11] 508 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[8] 305 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_lO001[4] 230 177
set_location fifo_to_tpsram_bridge_0/buffer_full 473 250
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_2_sqmuxa_1_RNI3SFHG 630 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_wr_rd_state_ns_0_a3_0_0[0] 790 147
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code 20 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_35[10] 282 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[0] 704 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[30] 988 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_5_RNO 435 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff 762 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv[1] 786 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[25] 846 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[10] 290 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_10[1] 566 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[16] 870 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[2] 414 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/i0Oi1 149 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][23] 894 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[27] 463 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_2[0] 67 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[4] 497 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_638 677 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_6[31] 699 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[11] 783 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2[0] 112 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_31_RNIV6I1U 792 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_514 673 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[23] 801 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0[2] 155 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_a2_0 775 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_13 759 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[5] 281 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_15[11] 278 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[6] 528 208
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[2] 33 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[15] 776 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[5] 556 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[22] 542 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa_0 606 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/gen_bit_reset.state_val_12_u[0] 861 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_N_5L9 729 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[16] 331 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[20] 850 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI_2_sqmuxa_RNIQU23F 673 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un47_I1Oi1 54 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_30[11] 351 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[8] 386 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_798 651 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[24] 724 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[8] 892 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[9] 741 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_capture_reg4 806 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_8 348 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/full_out 610 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_4 674 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_449 779 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][10] 882 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid 758 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_m4_0_a2_1 764 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[10] 381 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[2] 476 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[23] 962 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un8_loOo1_0_a2 354 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_RNI8PSHR[0] 816 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[1] 257 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3[11] 109 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[18] 525 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_1_sqmuxa_2 769 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_941 664 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[7] 403 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/PWRITE_m 622 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[31] 437 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[21] 844 189
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state[0] 514 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0Oo 267 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[8] 704 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[3] 246 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_0_146_a2 280 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132_RNI2O4OH 736 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1[24] 975 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[4] 529 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[39] 450 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[1] 840 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1209 686 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[6] 374 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[1] 74 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[9] 746 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[0] 329 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l1OIo 221 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m5 163 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[3] 470 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i 740 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[1] 699 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/l1oi1 324 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un28_i11Io 531 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15_7 224 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[11] 441 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1204 760 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01[1] 164 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[24] 838 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[7] 317 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[1] 138 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[1] 170 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[14] 831 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[11] 675 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOi11_4 403 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_509 663 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oo111_2 265 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1[7] 597 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[2] 526 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[6] 247 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[26] 849 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[9] 248 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[6] 308 196
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_RNO[3] 21 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_0_a2_0 809 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1167 746 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[6] 897 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[13] 129 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[11] 362 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_3 770 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_855 641 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_o5 158 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[2] 591 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[4] 239 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_48[8] 976 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_863 710 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[20] 719 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr_4_0[1] 828 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPJVQ8[33] 780 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a3_1[28] 743 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[4] 396 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_1 811 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[8] 535 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/IilI1_RNO 331 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[22] 917 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[22] 699 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m31 160 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1[0] 140 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[4] 72 196
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[4] 607 121
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out 623 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places57_RNIJO7A 914 165
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo12 612 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[8] 711 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[7] 244 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO 231 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_12_RNI52PUEO3 809 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_270 716 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m[16] 655 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[24] 899 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[10] 619 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[23] 977 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_1[4] 854 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2[15] 231 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[9] 502 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNI3T88E[20] 727 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[9] 205 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_268 701 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0[5] 755 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_897 638 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[6] 428 193
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[6] 45 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_1[0] 758 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[17] 799 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[5] 251 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_OioOo_2 207 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[10] 245 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_3_sqmuxa 731 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[31] 868 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[25] 615 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[15] 354 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IliO1_RNO_1 326 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_513 782 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m13_2_0 16 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[0] 188 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[1] 315 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[15] 334 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[0] 476 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[14] 949 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[3] 214 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[6] 362 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[2] 353 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[15] 50 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2s2_0_a3 780 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/oo111 285 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[35] 828 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[1].BUFD_BLK 595 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0[11] 97 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[2] 858 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_21_RNO 832 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[29] 875 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[23] 976 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[6] 270 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[6] 727 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_l1Oo1[0] 328 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lolIo_RNISGOVC 119 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_1_1_RNISFCQ8 824 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[24] 837 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m10_2_0 100 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[10] 771 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[7] 110 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[6] 725 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[11] 532 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[4] 207 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1096 715 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/data_rx_q1 604 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_17 795 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/OOII1 407 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ol1I1 465 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m17 122 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1016 811 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[27] 805 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[21] 273 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[13] 867 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[27] 352 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[9] 854 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIHK6GO[16] 865 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[3] 191 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0_0[12] 926 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[11] 118 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_0 205 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[24] 120 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][2] 880 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][6] 891 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/illo1 382 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_705 709 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[1] 725 139
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_RNO 608 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_388 784 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_RNI1SM77[1] 116 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_strb[0] 781 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[17] 928 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[6] 181 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[11] 180 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_2 830 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[30] 516 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2125 660 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[28] 865 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[28] 703 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[33] 406 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Il0i1[15] 213 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[4] 589 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooIi1_0_a2_0_o2 266 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[15] 407 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[28] 757 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_iIIi1 246 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[3] 317 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01_0_sqmuxa_0 171 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[13] 736 129
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[27] 66 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.awe2 624 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_fence_i_retr 757 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s 767 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mepc_sw_rd_sel_1 830 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[3] 847 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1iO1 212 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[2] 721 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[7] 152 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[7] 916 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_2132_fast 597 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_0_sqmuxa_0_1_0 780 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[5] 743 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_730 683 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[16] 814 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[14] 829 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_881 695 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_5_218_a2 410 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[25] 901 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI1I18 458 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[23] 363 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[24] 753 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[4] 469 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_34[10] 289 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[23] 962 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_valid[1] 785 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_mux_1555_tz_tz 755 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un8_OOOI1[26] 428 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[28] 784 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[3] 495 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1_5 233 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[20] 990 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15_6 226 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_exce[0] 762 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_608 739 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[19] 727 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[14] 81 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[22] 923 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_6_4_a0_RNIQV8S9R 789 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1_sx 793 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_27[9] 353 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2[16] 230 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.i0li0 107 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[2] 154 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[0] 372 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[2] 231 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[9] 292 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[0] 353 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25[6] 395 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_516 709 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7] 711 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ooO01 520 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_1[3] 857 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_9 408 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[5] 272 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[2] 523 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_1 618 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[25] 854 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_999 696 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[31] 736 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[8] 500 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[10] 927 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_2_0 638 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[17] 736 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_873 628 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_ac0_3 38 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1[4] 135 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un28_lolIo 123 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_41 683 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un4_exception_taken_5 776 144
set_location COREFIFO_C0_0/COREFIFO_C0_0/REN_d1_RNI2T40D 479 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[29] 740 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[25] 465 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2_8 95 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/un1_iOI01_1_i 391 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_4_1 661 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[7] 456 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_emi_req_accepted_0_a2 778 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[6] 879 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[17] 297 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[16] 869 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_0_i_m2[0] 651 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[12] 926 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[3] 216 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_I1Ii1 408 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.utime_sw_rd_sel_4 843 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_278 649 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[5] 941 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[8] 305 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m53_1_0 125 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_1_N_5L8_1_0 741 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_18 725 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i0oi1 203 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_457 707 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[5] 281 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI9HB2R1[10] 222 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[11] 549 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[21] 900 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_8_RNO 867 189
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[31] 484 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[7] 677 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un22_next_quotient_0_a2_0 878 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[11] 430 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[10] 524 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[26] 195 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns_i_i[0] 470 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk1.i1Il1 482 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo[4] 268 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[13] 715 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[11] 878 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[27] 495 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[0] 297 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[2] 338 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[10] 817 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[21] 681 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[30] 834 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_4 206 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoo1_i_a2 90 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ioil1 497 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[3] 183 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[7] 856 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[1] 364 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[18] 394 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un135_I1Oi1_1 61 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[10] 755 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_bcu_operand1_mux_sel_ex[1] 828 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[26] 239 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid32 820 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[6] 304 214
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[14] 615 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[26] 990 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[3] 788 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[58] 851 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lIio1_0_o2_0 88 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[26] 882 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[6] 230 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDMI_1_sqmuxa_1 687 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[6] 352 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1[13] 290 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un1_I1Oi1_5 81 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[14] 130 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames[2] 601 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[0] 226 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[5] 367 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI111 327 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI116 354 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[1] 206 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[31] 905 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] 299 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_860 650 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_0_0[4] 844 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io1o1_i_m2 98 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[2] 705 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_mux_sel_iv[1] 727 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[3] 271 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[1] 267 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un22_o1Oi1 78 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[3] 250 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[26] 832 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1046 648 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[9] 681 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[26] 622 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OloOo_RNIE4GMA 216 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[3] 732 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[31] 465 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m[12] 650 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[12] 539 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un10_cpu_d_resp_rd_data_sig[16] 667 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[17] 874 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/OOiI1 396 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[5] 279 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oi1I1 418 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[22] 1002 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[13] 91 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[6] 618 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count[1] 786 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[4] 700 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_1 283 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[20] 350 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[20] 445 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_8_RNIM7P5HO3 810 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[39] 432 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[2] 461 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[0].BUFD_BLK 591 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_OoIi1_7 240 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[31] 947 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/apb_penable_0_a2 604 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[25] 962 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un39_OOOI1[11] 409 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m10 52 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[6] 21 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[25] 878 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[0] 238 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I1ol1[0] 310 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo55_0 77 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[27] 871 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr[0] 758 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[2] 434 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0[4] 147 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1[13] 283 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[11] 516 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/gen_bit_reset.state_val[0] 787 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[0] 400 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[11] 422 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_pending_a0_1 792 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[9] 705 129
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[1] 37 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[46] 824 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[28] 477 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[28] 865 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0o11 425 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[8] 81 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[19] 378 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[10] 843 147
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r 501 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type[10] 771 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[5] 847 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_1_1 988 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_1 257 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[2] 430 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_csr_rd_data_ready_3_0_RNIAAFA7 856 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[1] 626 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[1] 342 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_4[12] 185 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[2] 463 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[10] 423 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0ll1 300 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[14] 611 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[3] 363 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_m1_e_0_1 809 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[1] 411 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_15 85 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_496 700 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[34] 502 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1[7] 340 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[5] 25 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[7] 448 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_de 746 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[6] 822 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[6] 570 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[23] 918 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/un1_gen_apb_byte_shim.apb_st_0_o4_0_0 747 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNI4I7JA[2] 785 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[11] 399 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[5] 129 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_first_RNO 590 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0[30] 281 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_22_RNO_1 865 195
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt[1] 520 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a1_RNIHIIL7O3 812 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[9] 517 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oioi1_tz[0] 155 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_2_RNI3FPPJO3 802 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2[1] 848 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[21] 913 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I10l1_1[3] 485 184
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_code_upd_3_iv_i 14 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIRI68E[19] 720 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1[20] 328 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_9 369 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iOoo1_i_o2 111 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[27] 908 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_700 662 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[9] 356 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[21] 280 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[5] 203 202
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_23 481 252
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[5] 565 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un33_i_a2_2[1] 217 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[5] 84 169
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_0_sqmuxa 605 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNO[2] 716 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[21] 523 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[3] 122 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busy_ff15_0_a3_0 748 132
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc2 42 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo 208 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_4[13] 112 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[18] 428 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_0_a3_0[7] 296 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q[2] 566 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNILUBS7[1] 873 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[4] 255 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid48_RNI3O089 703 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IIl11[6] 379 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[28] 909 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[8] 440 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4_0[0] 630 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[28] 866 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[10] 311 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[7] 588 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0_1_0[0] 288 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[9] 189 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1150 640 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[7] 311 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O0115 592 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[27] 756 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[14] 798 133
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_q[3] 567 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_2[7] 115 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m49 138 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2[12] 229 216
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_3 436 6
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[55] 621 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[2] 399 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[10] 663 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[1] 228 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01 623 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[14] 793 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[6] 87 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29 639 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[7] 425 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[13] 541 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[23] 842 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/IilI1 324 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_0[4] 198 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[4] 93 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_945 700 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[21] 988 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m8_0_1 51 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_0[6] 126 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[3] 452 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_870 671 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_30 746 219
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto9_i_a2_6 482 255
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[31] 947 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[14] 261 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[4] 212 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oill1 466 189
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[7] 488 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[6] 238 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIC698E[23] 719 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0[1] 757 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[23] 975 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un171_I1Oi1 52 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un174_shifter_result_1_1.N_2123_i 935 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_325 721 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[8] 866 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_619 782 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_540 781 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[11] 853 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[11] 710 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_46 671 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_1 561 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[30] 856 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[23] 724 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[4] 413 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[25] 926 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/liI01 191 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_966 652 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[6] 194 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].un1_lIII110 471 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[9] 774 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[4] 331 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_1_sqmuxa_i_o2 771 117
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[1] 19 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo14_0_a3 416 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[6] 144 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[30] 682 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[1] 719 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/i0IOo_RNO 136 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[21] 921 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[47] 241 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.lliOo[1] 295 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_0_0 690 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[0] 326 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[10] 229 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[11] 845 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4954_0_0 698 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo 184 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[19] 63 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[3] 512 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[3] 27 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[34] 723 126
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state6 598 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv[2] 715 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_cdr_ready_reg_1_0 14 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[11] 289 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[4] 719 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_state[1][2] 757 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0[20] 765 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_58[11] 385 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[11] 847 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[11] 484 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_0[4] 153 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[25] 842 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iI0i1_0_0 265 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi14 84 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[9] 300 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i0oi1_5 202 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_RNIIPO2AD 795 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[50] 593 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_8_170_a2 263 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_12_134_a2 279 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[0] 269 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[0] 331 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooi11 351 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24[3] 362 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[2] 850 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/lIlI1 148 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[10] 844 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[24] 681 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[21] 392 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[10] 298 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1057 720 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[29] 280 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[9] 318 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[10] 515 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[5] 242 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[29] 940 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[25] 817 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[9] 261 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un2_IIil1[0] 389 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[1] 842 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_1 731 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[30] 518 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[29] 669 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[3] 308 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4919_0 658 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[27] 382 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_27[1] 338 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[21] 457 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[15] 68 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/OO0015 226 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_26_RNO_0 936 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[21] 927 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[31] 271 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i0O11_0[8] 103 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1_RNO 807 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[16].BUFD_BLK 627 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[12] 355 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1029 700 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_RNO_0[0] 725 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[24] 301 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_0_1[1] 134 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_fetch_ptr_sel_0_a2_0_a1 815 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo52_0 76 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lo0I1_Z[6] 433 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m13_e 637 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_o2_1[28] 284 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ol111 77 175
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc3 17 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/IilI1 419 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1_RNO[3] 327 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[8] 712 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[10] 508 250
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[2] 592 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[0] 591 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l0Il1 456 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un13_l1I01_4 390 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[3] 838 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_0_s_RNIP356V 749 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[17] 868 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[6] 519 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[3] 592 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6[1] 694 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[16] 262 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1085 662 219
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[7] 495 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[4] 869 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[8] 199 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[31] 860 141
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_2[5] 596 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[23] 454 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[24] 724 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26[4] 340 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/IooIo_1_0_.m7 159 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[3] 317 169
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[18] 480 250
set_location fifo_to_tpsram_bridge_0/ram_w_addr[3] 472 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[29] 501 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_gpr_ded_reset_reg/gen_bit_reset.state_val[0] 624 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[4] 885 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un6_o1ll1 475 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un3_ili01_0_a3_1 108 171
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/load_lane 18 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]2_0 880 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[6] 119 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[16] 541 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un10_ioOOo 131 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/dut_tms_int 594 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[2] 844 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/olI01 339 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv[1] 665 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[2] 405 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[12] 506 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[0] 420 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0[5] 837 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[2] 297 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[26] 931 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[1] 244 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[0] 550 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_953 733 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i0oi1_6 209 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[3] 219 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[34] 716 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[15] 222 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_lsu_op_ex7 733 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_19 689 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[5] 306 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_28[0] 352 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UIREG_2 422 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7[29] 798 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1[22] 759 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1283 772 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO[0] 522 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOiOo_NE_1 292 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[11] 975 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2_1[2] 781 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[1] 353 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[0] 95 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[22] 1001 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0[6] 695 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[3] 856 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[4] 89 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[7] 328 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[11] 954 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0_1_0[0] 301 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un215_lIlo1 329 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[13] 497 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[6] 222 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[0] 125 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_27 627 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iO1 271 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[8] 433 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[18] 459 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0_RNO 781 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[3] 205 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_i_i_a2_2[1] 739 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[31] 916 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_234 769 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_976 651 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO_0[0] 689 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIALS4H[5] 254 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[17] 261 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[6] 555 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[14] 868 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_1[0] 101 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[11] 842 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_866 734 216
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa_1_1 435 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un15_buff_resp_head_compressed_0 696 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[30] 674 189
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_coarse_sel_0_sqmuxa 38 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un3_IOoi1_3 400 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][18] 886 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[20] 741 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[11] 271 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un4_UTDODRV 436 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un15_il0Oo_4_0 225 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[37] 957 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_rd_ptr[0] 767 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[25] 894 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[23] 712 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[27] 974 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0 325 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i1iO1_RNO 295 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[6] 423 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[31] 491 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[6] 660 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_dummy_target_RNO_0 793 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_483 710 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[39] 230 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[2] 215 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_i_resp_valid 770 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[8] 327 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/mnemonic538 710 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00i1_RNO_1 221 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/IilI1 355 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[19] 226 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[1] 448 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i1001_RNO[9] 181 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[8] 538 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNIAJT66B2 818 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/gen_bit_reset.state_val_12_iv_i[0] 873 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[31] 314 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[0] 83 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un5_o1Oi1_2 72 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_places_sel_ex[1] 771 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un31_ool01[2] 185 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[13] 35 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[9] 377 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[16] 310 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOiOo_0 226 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[15] 915 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[7] 291 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_121 667 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[4] 305 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIR4CS7[7] 842 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[14] 240 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[0] 484 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_265 686 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_readondata_ff_RNO 758 117
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[4] 495 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_1_RNO_2 797 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO0l1_2[3] 480 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[18] 794 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1197 663 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/un1_iOI01_1_i_0 335 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i01i1_4_0_o2 315 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[4] 102 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_bit_reset.state_val[1] 822 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1117 712 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[4] 352 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IO0o1 143 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[20] 872 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_i1Il1 494 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[35] 951 192
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[11] 43 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[18] 1002 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[26] 692 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/read_subsys_hart_soft_reg 819 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[19] 62 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11] 729 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3[2] 878 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_322 687 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILDFFD[4] 713 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNILFVQ8[31] 715 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_0[2] 277 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iIii1ce_0[0] 139 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/IilI1 316 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_o4[0] 674 150
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_0[2] 629 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO_3[1] 784 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[4] 229 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[0] 192 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op[1] 727 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[3] 510 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[0] 86 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un5_div_result_3 863 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/IilI1 337 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o[1] 280 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[23] 779 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[0] 247 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[5] 512 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[13] 798 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][5] 877 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[61] 644 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[5] 291 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0 114 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[16] 286 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[37] 390 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_RNIHP2B7 185 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i[0] 158 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[17] 836 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un5_iili1 339 171
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[12] 75 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[7] 54 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2_0_m2[2] 727 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[5] 379 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[12] 52 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2 603 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/ilI01 338 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[13] 901 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_3_RNO 437 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0_0 111 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[22] 917 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_fence_reg_2_0 886 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_296 711 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_oen_0_sqmuxa 568 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[22] 686 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[17] 409 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIi01[3] 97 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q_3[2] 620 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_924 700 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[52] 598 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[10] 649 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m47 42 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.un4_ex_retr_pipe_sw_csr_rd_op_retr 856 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[5] 510 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sba_req_valid_int35_1 782 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[15] 403 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[8] 52 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un12_I1ii1_i_o3 148 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[8] 539 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_11 105 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_22_N_2L1 809 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[8] 934 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_3_1 436 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/IIl01[1] 105 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[1] 205 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[6] 386 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0 777 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[25] 945 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[15] 890 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[6] 360 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[26] 469 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][31] 895 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i10Oo 227 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[18] 723 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo[0] 268 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m8 162 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[17] 703 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[4] 490 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m26 112 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[9] 329 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_i_1_m2[0] 768 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[14] 727 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/IilI1 392 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[15] 359 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[13] 597 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[22] 365 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[3] 245 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un1_OOii1 150 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0[10] 90 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_11 698 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[10] 606 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[3] 855 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/O1011_RNO 303 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[2] 306 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[9] 128 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[6] 739 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/is_locked_RNINLBGM 789 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[20] 864 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_I1Oi1_1 39 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[6] 264 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_7 741 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_59 810 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_490 686 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[12] 914 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[11] 193 214
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt_RNO[1] 20 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_555 753 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[17] 453 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[43] 383 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[5] 294 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[2] 915 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un48_Oo1Io 482 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q[4] 565 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNIR3S4[1] 265 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IOoo1_i_a2_0 89 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[0] 202 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1159 616 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n2 301 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[8] 309 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/stage_state_retr 751 145
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_1[3] 596 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[15] 894 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[1] 267 231
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[6] 487 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[4] 328 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[15] 832 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[1] 415 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[10] 848 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un7_ioOOo 127 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_7 464 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z[1] 182 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_876 709 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[26] 829 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_7 253 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/i1oOo_0[9] 248 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_RNO[20] 989 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[31] 744 126
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_27[2] 560 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_789 754 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[2] 155 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/fifo_valid_RNI196FC 498 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[17] 466 217
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_parity_calc 518 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_4[2] 106 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1125 770 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[11] 487 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[0] 407 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[2] 706 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[7] 530 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[4] 128 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_1_0 795 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_o1Ii1[0] 319 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[5] 73 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[8] 140 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[29] 939 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_3 590 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[5] 313 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNI9AKVB3 170 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m25 614 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_1[0] 686 150
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m8 527 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[10] 540 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_0[1] 749 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_0[13] 756 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/un1_iOI01_1_i_0 344 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[6] 288 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[0] 420 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[11] 270 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[5] 246 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1101 689 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[5] 617 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_2[2] 358 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[35] 392 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_3_2[6] 987 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m7 99 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_valid_2_a3 800 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/un1_Ioli0_1_0 415 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[4] 732 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto8_1 220 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][9] 898 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OOOIo[0] 201 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_275 734 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un7_ool01[4] 198 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[13] 513 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[12] 509 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIGP7L31 855 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[11] 465 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa 668 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0[9] 163 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[25] 753 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_d_1_sqmuxa 646 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_ptr[0] 699 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_25 699 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1[13] 777 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_204 700 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_s_5_RNO 570 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01[0] 320 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[0] 400 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1222 673 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_4[5] 504 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_ioOOo 123 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oIiOo[8] 298 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5[1] 595 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_halt_req 812 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[3] 179 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr[1] 769 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[29] 883 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[6] 328 210
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_pauselow8 633 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[6] 898 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[2] 541 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[3] 290 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[16] 915 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un189_I1Oi1_1 60 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0] 487 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[32] 942 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0[10] 796 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[23] 398 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[28] 843 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[25] 925 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1147 660 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0_a3_1_0 109 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[12] 252 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m41_2_0 112 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/iiOl1 504 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[58] 961 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[1] 714 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[3] 266 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[2] 1001 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1101 111 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[7] 207 210
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[9] 510 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[23] 831 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_1[25] 286 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[7] 787 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1162 639 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIII1[35] 491 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r[2] 483 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_a4_0_a2[5] 735 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_RNO[4] 650 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oiIo1 297 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[4].BUFD_BLK 591 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lI0i1 205 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[7] 525 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un24_Oi1O1[8] 544 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIOl1 434 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_2 808 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ioIi1_1 204 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[10] 259 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[29] 623 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re_4_4 552 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1_0_RNO[1] 485 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[17] 835 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/IilI1 424 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[8] 175 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[1] 939 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[24] 289 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[16] 56 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_2 149 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[26] 908 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand0_mux_sel_ex[0] 862 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[0] 854 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[10] 679 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[9] 213 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IlOI1 320 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[1] 220 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_fence_reg_2_0_o2 882 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNI68VTE 849 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_OlOI1_1 344 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[4] 206 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[1] 333 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_update_result_reg 831 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_1[1] 788 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[13] 348 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[7] 523 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_d_1_sqmuxa_1 601 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Oo001_0 192 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un16_gpr_rd_rs1_completing_ex_1 770 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/xmit_cntr[0] 495 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[22] 663 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0OIo_0_a3_0_1 220 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_iII01_1 367 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[42] 954 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[4] 412 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[1] 548 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data[3] 717 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_942 649 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[4] 229 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[21] 517 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[1] 381 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[6] 729 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_489 757 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un99_I1Oi1 50 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[8] 537 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[26] 724 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_11[0] 279 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_524 696 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[5] 743 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_midbit 603 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[2] 277 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[29] 461 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_85_u_2[9] 937 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[16] 859 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[7] 718 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[2] 652 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[2] 323 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[10] 618 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0[0] 158 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[12] 122 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[7] 555 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2133 689 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_981 756 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[5] 842 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[9] 518 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[9] 753 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_1[1] 705 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[17] 957 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_1 753 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[3] 266 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_19 728 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l000112 173 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[9] 743 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[29] 797 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[5] 78 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lli11 443 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[5] 397 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[31] 830 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_o1oOo 239 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[10] 414 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0[2] 730 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_dhold_dec_2 572 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[4] 347 193
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[3] 28 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[6] 236 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_22[6] 374 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ifu_expipe_req_branch_excpt_req_valid_1_0 764 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[3] 538 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_4 744 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[3] 530 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_0[1] 788 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDMI_ne_0_3 651 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un105_OOOI1[24] 463 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[3] 103 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[6] 398 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[6] 279 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[5] 510 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1[13] 485 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[8] 867 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[4] 327 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1[8] 133 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_3_sqmuxa_2 614 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[10] 223 198
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.ol1Io 46 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[8] 327 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[15] 373 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_0_0_a2[15] 126 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_1 74 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[3] 938 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_3[3] 183 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lo1o1_i_0_a2_3 88 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[29] 952 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[2] 423 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[2] 442 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[15] 830 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[21] 672 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[25] 837 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[28] 726 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un78_OilI1[17] 391 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNI8EUT5 318 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[4] 82 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[1] 773 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[12] 228 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[2] 435 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[10] 712 126
set_location fifo_to_tpsram_bridge_0/next_state11_20 504 252
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[2] 487 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_2[24] 289 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_2[0] 111 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2_0[7] 168 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[12] 122 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[0] 191 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[17] 545 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[13] 869 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[7] 254 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[15] 712 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[14] 798 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[5] 313 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[0] 867 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[9] 173 193
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2_RNO[6] 20 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIio1_0 86 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[38] 958 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[4] 201 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[6] 608 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en[3] 757 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1164 732 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[21] 917 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNIADN2U 169 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1[1] 88 202
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_byte[0] 498 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_data_valid_6 754 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[15] 828 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[4] 142 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[2] 418 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_RNO[0] 783 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un45_OOOI1[13] 349 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[0] 172 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_o4_0[3] 170 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_1[5] 820 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo[2] 248 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8[5] 872 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m300 366 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/olOI1 365 187
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[5] 562 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.m6 98 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[3] 233 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[2] 185 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[13] 496 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[24] 850 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lIll1 465 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/slow_mul.un5_mul_mc_sx 764 159
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[31] 480 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_6_RNO_1 868 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[0] 260 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[0] 296 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[1] 514 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIBE984[16] 959 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IoI11_Z 414 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OIlOo 165 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_8_RNIOI22J 711 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[6] 824 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute/gen_bit_reset.state_val[0] 858 145
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[6] 19 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[23] 795 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[9] 514 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OolIo_2_0_.m10 122 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNI4UQJGH3 774 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[11] 290 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_6[9] 355 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_523 675 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_9[10] 288 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[3] 208 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[1] 410 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[4] 698 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_RNIA72AVC 806 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[29] 499 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Oo101 101 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_RNIRMORJ1 620 114
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[16] 489 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[7] 243 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_138 626 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1_0[5] 287 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[1] 557 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_ns_0[0] 742 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[6] 327 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I11Oo[0] 161 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[11] 886 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[22] 268 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_0_RNIIUHQL[3] 144 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2[10] 195 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I1IO1_i_m2_i_m2[1] 156 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[12] 796 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m78 324 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOI11_Z[0] 134 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[22] 951 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[11] 337 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNI63C8E[30] 693 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_drop[1] 756 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_valid 738 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[27] 895 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un3_loi01 79 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[30] 485 244
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[10] 358 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[11] 224 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_16_0_i 386 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[8] 232 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[1] 916 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[5] 306 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[39] 230 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.N_23_mux_m 717 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_o4 807 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_accepted_1 747 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[3] 442 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[5] 306 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[9] 562 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIGCTP4[11] 220 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o11Oo[0] 245 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[11] 265 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_to_err_0_sqmuxa 756 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[3] 308 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[9] 365 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[10] 316 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.debug_resume_req_3 785 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[27] 614 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[7] 365 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][21] 894 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[7] 356 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[19] 920 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[21] 387 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[28] 901 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20[7] 402 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[12] 907 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/illOo 135 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[12] 879 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[5] 616 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[16] 976 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[3] 368 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[7] 377 184
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/update_dout_i_0 499 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[5] 273 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_1_RNIBAC46[4] 158 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a3_0[2] 294 189
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[12] 505 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/ol101 91 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[2] 566 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_695 688 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO_0[5] 174 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[17] 575 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un52_OilI1_0_a2_0_a2 358 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[31] 492 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ooo11 362 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_38[4] 326 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[20] 319 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[1] 213 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_3_1 602 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[38] 374 196
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[23] 482 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[4] 286 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0l11_Z[0] 344 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/liO0110_1 407 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[12] 608 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[8] 949 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[1] 333 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate[4] 686 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[4] 352 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_24[5] 340 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[5] 554 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_rd_pointer_q_1.CO0 647 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[13] 912 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[29] 664 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_2[2] 540 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[14] 738 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_rd_ptr_0_0[0] 780 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1oO1 294 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O0Oo1 330 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[6] 75 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_29 933 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1086 673 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[19] 593 181
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[3] 460 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[9] 93 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[6] 793 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_1_2_1_0 807 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[5] 366 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[14] 250 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[7] 494 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[18] 682 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[7] 303 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[10] 858 133
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[1] 23 202
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UDRCAP 435 3
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[1] 215 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[6] 777 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI9C984[14] 910 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[30] 458 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_526 637 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O00Oo_RNIAR34C 232 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[22] 615 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[27] 898 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_9 661 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[9] 53 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[13] 723 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oil11 293 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_29[10] 350 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_synch[0] 701 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I0o11 401 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[11] 548 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[29] 483 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/io0i1_0 313 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_a4_0_1[2] 62 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[11] 323 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/li0I1_RNO 541 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitsel_6_f0[0] 609 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_wr_sel.mepc_sw_wr_sel_3 853 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[2] 235 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_114 661 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0_1_0[0] 271 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[7] 744 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_3 254 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNIMOR5C[20] 723 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[3] 171 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[26] 879 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_666 637 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[5] 715 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[24] 747 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[4] 854 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[2] 868 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[33] 413 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[8] 122 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_2[16] 689 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[20] 888 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[0] 720 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[1] 802 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Iili1[4] 350 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[10] 480 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2_0[12] 183 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[0] 399 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[24] 474 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[6] 526 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[12] 110 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[17] 319 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[7] 310 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[4] 266 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/lio01 75 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[5] 555 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850_2 637 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[1] 27 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_0 421 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][25] 886 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I00Oo_0 237 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[2] 250 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/loo01 112 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Oo1Io_3 481 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_5_0_a2[15] 109 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_9 746 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[5] 342 228
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[6] 494 169
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_nextd4_NE_0 594 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m60 70 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_93 721 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_0[9] 150 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write[0] 700 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_169 674 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[11] 380 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_43[11] 349 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[15] 649 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/req_m2_e 799 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNI58O7J[2] 676 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[31] 727 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Oo1Io 467 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_349 732 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/N_112_i 827 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[32] 319 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_0[26] 757 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[30] 854 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[7] 648 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[11] 53 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[10] 781 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_27[0] 351 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.o0li0 421 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/o1011 326 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3_0_0 339 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[15] 428 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_a3_3[3] 559 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[1] 374 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[9] 549 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_54_u_2[2] 986 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[26] 450 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[11] 339 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[4] 730 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/gen_bit_reset.state_val_1[0] 632 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[3] 869 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_8 827 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0_1[1] 66 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[7] 407 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[14] 356 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[18] 408 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv[1] 674 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[33] 475 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0o01_RNO 100 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[24] 200 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[30] 618 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[5] 715 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0i1_0_o3 198 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un165_I1Oi1_3 51 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l1l01[7] 177 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[12] 246 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[0] 523 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[38] 722 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_reset 705 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIFI6GO[15] 890 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iloI1[3] 420 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[4] 228 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[14] 418 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_iv_RNO_1 705 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[4] 173 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848_0_0 661 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oio11 371 183
set_location PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_3 10 164
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[21] 66 220
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[5] 475 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_l0ll1_3 462 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[22] 913 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[28] 284 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[31] 843 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[4] 847 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[16] 902 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_1 782 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[17] 829 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk1.un4_i1Il1 497 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[4] 119 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un5_shifter_unit_op_sel_ex[0] 776 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_2[4] 200 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_568 629 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[20] 706 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_43[1] 351 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[12] 846 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oO0Io_0 65 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[15] 175 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un155_I1Oi1_0 55 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_RNIRC024I1_0 769 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[4] 571 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_108 678 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[7] 881 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI0O9V9[7] 229 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[12] 536 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][8] 886 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[24] 831 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1 385 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/full_out_RNO 574 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[25] 355 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[5] 402 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[2] 853 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[3] 162 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[24] 905 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_RNIJ50KKD[5] 830 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_43[9] 948 159
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un5_endofshift 601 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mtvec_sw_rd_sel_1_1 828 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_8[1] 302 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[7] 351 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[27] 500 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_748 673 201
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx 539 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_1[10] 405 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[13] 108 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[3] 27 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[11] 75 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[19] 281 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[18] 392 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_RNO[8] 188 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[11] 426 181
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[21] 488 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[4] 325 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_16_RNO_1 879 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[14] 896 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13[2] 791 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[18] 959 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[0] 855 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_5[24] 424 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_mode_retire_mask 817 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[16] 589 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[7] 574 175
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[0] 484 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3[7] 110 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_41[9] 949 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_3[4] 217 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[2] 864 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[22] 468 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[31] 324 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[7] 445 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un10_Oo1Io_0 480 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/resetn_rx_d1 593 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_OlIi1 251 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[7] 528 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[14] 316 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/resetn_rx_d2 590 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIEJL4C[3] 714 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr[1] 765 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[2] 286 208
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[25].BUFD_BLK 627 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state28 806 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_18_0_RNO 876 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_RNO 815 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[15] 799 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIL7GUI[9] 896 150
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxp_strobetx 597 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ioOi1[6] 209 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[11] 656 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_1[28] 162 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0Ii1 310 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic853 636 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_stall_csr_2_1 718 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][25] 884 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2137_1_2_a3 688 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_read_RNIIHG39 745 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_div_RNIPIHTR 836 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[26] 622 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_676 711 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1[4] 410 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_addr_align[0]_3[0] 758 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[1] 976 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_i_o2[4] 414 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2[17] 280 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[15] 356 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[0] 358 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_wr_strb[1] 788 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[29] 940 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result194 829 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_25[1] 350 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[5] 202 193
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[10] 65 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_0_0[0] 111 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[9] 727 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[11] 515 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[10] 404 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_0_2[1] 87 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_tz[0] 110 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2123_1_0 650 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[3] 442 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l1001[9] 182 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[24] 487 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[6] 681 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[0] 427 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/ftrst_1 420 211
set_location Core_reset_pf_0/Core_reset_pf_0/dff_4[0] 829 70
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[1] 84 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[10] 367 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_1_0[1] 86 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[0] 336 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_40 690 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[0] 821 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftBP_ldmx 657 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[8] 934 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[25] 448 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_IO0Oo7 273 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[10] 455 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[10] 428 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/prescale_counter6 896 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[62] 641 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[2] 868 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[24] 866 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iOli1_10 218 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1lOo 164 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[15] 816 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[28] 909 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[27] 626 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[20] 545 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/un7_full_wr_NE 700 132
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[0] 501 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[3] 532 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[4] 697 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un39_OOOI1[2] 460 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[60] 978 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[22] 964 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/I1i11 353 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_985 754 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1[2] 512 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a2_5 750 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[25] 513 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_0_RNIRG8LR 786 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_1_RNO_3 805 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[2] 710 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_847 768 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/i1O01_1_sqmuxa_i_RNO 434 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_179 689 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[9] 60 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][31] 892 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[10] 848 166
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[3] 568 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[10] 851 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[13] 698 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[8] 951 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[8] 428 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoo1 93 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un14_oO1Oo_0 231 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_req_os_count_at_flush20 788 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[4] 432 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[6] 143 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_580 710 225
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/rx_fifo_read 509 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[9] 684 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[10] 486 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[5] 434 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/OloIo 480 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[12] 498 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[1] 564 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[0] 934 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[27] 613 181
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_28_RNIBQ235 476 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_25[0] 347 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[0] 913 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.init_wr_dcsr_step_en 786 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[25] 813 120
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_shift_9_u_1[7] 499 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_lm_0[2] 839 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un314_lIlo1lto15_3_0 274 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[2] 339 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOii1_0_a3_0_2 148 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_stall_csr_2_0 713 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[9] 919 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O1lIo_1_0_.m6 40 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[30] 898 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[4] 522 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[17] 830 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I01O1.un1_Ii0O1 594 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_630 636 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[3] 487 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_629 672 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[0] 470 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_q[3] 637 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky[1] 571 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][11] 879 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[10] 63 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[0] 194 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13_3_2_RNO 769 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m6_1_0 675 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[1] 729 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[8] 96 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_293 686 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_0 303 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[16] 541 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_717 634 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Io1Oo_0[1] 197 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[0] 870 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_438 649 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_190 749 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7_1[4] 166 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/IilI1 237 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[6] 398 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[11] 891 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_578 677 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[4] 312 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ[10] 507 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11_cZ[17] 349 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m10 15 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][9] 868 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[6] 416 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[0] 952 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv_2 687 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[16] 862 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[2] 560 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[1] 333 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[13] 739 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[1] 829 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[30] 909 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_11[4] 342 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IloOo_2 213 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Il0O1 486 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[4] 709 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[20] 467 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oi0I1_Z[4] 541 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o0l11 297 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[29] 869 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[4] 632 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un123_I1Oi1_3 45 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[16] 975 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[10] 780 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[7] 855 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_RNO_0 817 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/un1_Ioli0_1_0 373 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0_o4 326 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1iO1 296 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[5] 233 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[7] 615 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1I1_RNO 456 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1[19] 393 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[22] 500 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][1] 882 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2115_3 688 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_0[7] 545 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[1] 183 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNIVKPOI1 789 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[9] 427 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_819 764 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[0] 452 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[3] 363 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_cZ[14] 369 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_wr_op_retr18 779 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[11] 532 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_8[0] 390 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[31] 495 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01[0] 215 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[17] 239 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un2_Oo001_4 203 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_12 617 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[11] 954 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_0_1[0] 133 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNIQSR5C[22] 639 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_18_RNO 864 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[3] 357 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_17_RNO 952 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un2_IOIl1 314 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[2] 258 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3[6] 877 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_82 786 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[24] 422 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/un1_iOI01_1_i_0 329 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[15] 103 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m35_0 749 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_0[2] 182 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[6] 260 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_4_1 733 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1035 756 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[0] 826 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1059 768 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1227 666 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmihardreset 690 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[0] 772 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[31] 790 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01_0_sqmuxa_0 171 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[22] 923 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/II0o1[1] 82 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[30] 795 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iIoI1[3] 410 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[5] 437 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[26] 446 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_operand0_mux_sel_0_.m3 682 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[32] 485 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[13] 418 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_5[0] 100 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[0] 362 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[4] 925 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[1] 200 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0o01 100 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[3] 335 169
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[14].BUFD_BLK 626 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_14[11] 284 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[8] 313 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[10] 502 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0_RNIRNTO 573 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[9] 431 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[22] 387 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32i_dec_mnemonic4960_1_i_3_tz 653 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[16] 875 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[31] 399 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[29] 910 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0 856 120
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames[0] 602 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1205 626 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_949 765 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[23] 860 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[10] 335 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[6] 362 234
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig14_1 519 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[26] 476 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[6] 450 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_5[8] 224 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m24 41 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[0] 743 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_2[0] 696 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[7] 699 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1192 710 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[26] 755 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[25] 550 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel7_0_0 570 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[39] 821 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI32EI4G1 819 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[11] 119 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_42[11] 362 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1112 688 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi1o1_i_o2 97 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_RNO[5] 415 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI0M7VA[13] 707 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA[6] 554 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1233 760 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_i_x4[10] 170 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[4] 460 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.lloIo 526 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ool11 350 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un1_OOOI1[16] 409 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_7_3 733 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[25] 884 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[27] 939 183
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[8] 492 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_3[14] 165 174
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[19] 50 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2_0[31] 750 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ioli1 342 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_6_152_a2 296 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[30] 857 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[1] 542 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIlIo 269 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE_4 207 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_13_RNO_1 874 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[29] 915 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[2] 468 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[13] 128 202
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[27] 488 243
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_valid_code_RNO 20 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[9] 554 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[2] 333 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_1[3] 719 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[6] 789 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[5] 847 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[18] 462 216
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[3] 631 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[10] 385 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_a2_0_0[3] 325 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[22] 734 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[0] 147 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr[0] 696 121
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt_RNO[0] 608 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[9] 721 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[9] 675 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_661 676 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_MTIME.un1_T_l_En_0_o2 602 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv[2] 722 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_m2[1] 406 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_ex_retr_pipe_lsu_op_retr 800 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iol11[6] 370 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_valid 767 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[26] 759 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[19] 754 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/o0Oo1 324 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[1] 481 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[9] 521 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oi1o1_i_o2_1 96 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[10] 375 223
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[25].BUFD_BLK 640 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_1_sqmuxa_1_0 834 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[4] 391 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[17] 719 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un10_iIIi1 311 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].un1_lIII110 473 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[4] 948 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/ooIIo 305 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0[3] 219 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a2_0_RNID49ST4 763 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_394 675 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[24] 877 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[13] 351 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[21] 473 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[11] 269 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Iili1[5] 338 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[8] 183 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[23] 703 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[8] 355 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[13] 425 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[0] 186 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[2] 763 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[14] 493 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[1] 851 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1_RNO_1 217 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr_1[2] 799 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_trig_de.un11_csr_trigger_wr_hzd_de_8 747 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[27] 962 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI69984[11] 888 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[7] 823 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u_2[8] 985 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[9] 316 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_7_RNO 442 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iIll1 522 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[2] 228 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_1_i_m4[0] 861 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[26] 878 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[7] 299 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_5[1] 218 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0ii1 149 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_1_RNIT9DEA 622 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[5] 857 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1 287 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[14] 87 166
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[30] 489 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[26] 862 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[10] 414 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[9] 316 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[4] 312 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[26] 830 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_4_RNO 875 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_i_req_ready_x 775 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[6] 852 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[0] 124 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[2] 180 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[27] 230 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/iI0o1 106 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[28] 853 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_next_state_0_sqmuxa_3_0_a3_0 854 123
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel[1] 31 202
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_alldone_0_sqmuxa 566 201
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[10] 491 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un2_I0io1_1 110 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[6] 287 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/liII1 362 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_267 698 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[2] 88 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[24] 677 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[50] 839 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][2] 764 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_3[1] 131 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[12] 688 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/io0o1_0_a2_0_4 72 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div.un11_start_div_3 862 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[7] 858 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_m1_e 801 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_i_ex 779 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[24] 721 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_815 675 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[28] 675 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2_i_m3[31] 558 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[23] 490 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_1[15] 843 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OiIl1 498 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[2] 120 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[13] 896 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_600 649 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[10] 57 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3_RNO[2] 876 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[12] 517 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[30] 752 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[6] 419 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[21] 729 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[0] 867 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[31] 929 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[18] 56 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_36[8] 937 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[14] 405 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I00i1 239 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/iOiIo 554 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[1] 590 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[3] 235 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[4] 477 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[1] 220 201
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4[1] 520 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[13] 709 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1194 730 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_408 674 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_RNO[2] 418 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_is_hword_high_only_u_RNO_0 845 156
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5[7] 488 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2[1] 729 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[8] 620 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1114 723 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[15] 259 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][15] 890 154
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[3] 538 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_446 638 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un28_lolIo 51 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[1] 123 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_d_1_sqmuxa 616 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[2] 309 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_o0il1_i 414 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_3 265 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.mimpid_sw_rd_sel_1_0 842 138
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_20 68 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_24[9] 389 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1li1[4] 356 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[8] 589 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[19] 796 127
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[7] 609 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lIoI1 403 187
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un10_fine_sel_axbxc1 45 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_0[5] 287 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[11] 136 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.penable_RNO 723 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[6] 413 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[0] 426 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[2] 411 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int_13_m2s2_0_a2 749 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[30] 325 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[3] 338 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[3] 425 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_862 691 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[2] 173 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[0] 232 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[10] 287 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[20] 988 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oI1i1[2] 323 166
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[1] 35 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5[0] 186 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[11] 369 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1[3] 298 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un1_ioOOo_2 128 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[2] 788 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_2[6] 771 138
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[3] 469 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[19] 293 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[12] 348 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[9] 919 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[49] 625 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[10] 325 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo_0[1] 242 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[7] 335 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m59 146 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_9_RNO 432 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state_valid 768 144
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2[2] 477 240
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[21] 647 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m3 684 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[25] 832 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1187 687 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1142 759 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[19] 734 181
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[26] 61 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[29] 504 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_synch[1] 706 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat12 657 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/un1_Ioli0_1_0 291 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO[5] 139 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[4] 892 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[15] 213 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[15] 953 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[3] 182 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[8] 453 214
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_ns_0[0] 22 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_instr_is_lsu_op_retr 797 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un7_I10i1_1 204 168
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UTDI 596 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[19] 915 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[16] 832 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[10] 774 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[9] 403 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[30] 518 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0[2] 289 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_252 615 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[29] 941 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_div_RNIKS93LE 838 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[2] 371 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[10] 273 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[11] 359 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_671 805 207
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/dll_delay_code[1] 19 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][10] 881 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[0] 855 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1_0 557 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[7] 770 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[18] 903 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[1] 950 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[21] 838 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat_RNO[0] 691 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[9] 269 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[5] 198 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[8] 181 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1[4] 495 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[0] 156 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_19[10] 417 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/iOOl1 421 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[39] 393 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_1_RNIRG5AQ 416 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[4] 411 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[5] 306 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/un1_iOI01_1_i_0 330 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_28[3] 411 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_19 675 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[4] 397 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[9] 436 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[10] 62 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[28] 478 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[16] 667 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[3] 473 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[12] 831 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/clr_txfifo_5 606 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[18] 975 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[4] 235 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1iIo 465 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[25] 604 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OoiO1[2] 297 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[3] 63 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un4_I1Oi1_2_0 56 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01[0] 313 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[5] 246 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[20] 912 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1[5] 276 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[17] 719 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Oll11_Z[1] 380 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[14] 854 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_n3 307 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01_3_0_a2[1] 248 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[8] 183 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1155 769 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_lliOo_1.CO3 299 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/llO11[13] 82 180
set_location PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_98_0 0 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a2_2 750 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a3_0 861 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0[4] 750 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[3] 415 223
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_ssel_pos 597 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[16] 524 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[28] 974 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l1ll1 474 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIIo[0] 264 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_88 733 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_wr_op_ex[1] 734 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_12 766 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_sba_req_rd_byte_en_int_0_a3_0_a3 769 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[7] 262 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[28] 471 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[24] 880 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[10] 533 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_277 699 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[9] 844 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0_o3_1 104 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[2] 198 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2125.rv32c_dec_mnemonic2125_3_3 660 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI9DA84[23] 923 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[0] 250 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OiI11 319 184
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt_9_iv[0] 15 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_79 672 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0_RNIAC4V15 757 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[3] 220 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iO1I1 507 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m15_e 97 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[24] 907 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_sn_m3_i_o3 819 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[11] 825 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[20] 849 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_busy_cmb_mux.un1_debug_csr_rd_en 859 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m205 357 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IoI01_RNO 289 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[3] 853 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_resp_valid_0_0 758 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0[4] 300 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmireset_RNO 688 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[12] 416 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[25] 841 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIoO1 290 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_2_sqmuxa_1 626 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_curr_fetch_ptr_1_0[1] 882 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[0] 521 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[5] 432 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1 73 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[6] 361 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_RNI846IM3[0] 156 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_23 65 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/i0oi1_i_o2[0] 324 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1252 731 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[3] 937 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_7[1] 511 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oliO1 339 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[4] 702 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_4 394 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[4] 481 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_417 780 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[2] 231 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[45] 403 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2__RNI07RO5[15] 636 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[27] 743 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_8 302 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_1[4] 344 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IIOo1 333 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/oool1 303 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[12] 113 186
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_statece[1] 506 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[7] 380 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_562 819 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[15] 261 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_l00o1_1 53 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[10] 482 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[6] 416 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/excpt_ebreak 758 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[0] 486 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oI1I1 470 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[6] 79 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[21] 611 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[21] 421 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[7] 182 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo_RNO[3] 283 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[4] 274 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1144 697 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1_m2_e_4 219 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[38] 741 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[25] 475 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_iO1Oo[0] 228 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[5] 504 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel 607 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[3] 506 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[4] 50 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state_ns_1_0_.m13_1_0 787 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_838 676 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOi11_1 375 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_davailable 610 208
set_location fifo_to_tpsram_bridge_0/state_ns_i_0_a2_1[0] 474 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m11_2_1 682 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[14] 295 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[16] 721 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_12[1] 278 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_2 393 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[27] 811 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_51[11] 277 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[10] 360 223
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q[1] 637 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/soft_reset_pending 812 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_872 708 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_982 662 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[5] 819 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[13] 93 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[50] 624 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[13] 31 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oi101 118 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[6] 736 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[11] 266 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[4] 140 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/l0l11_Z[2] 299 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[14] 564 178
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[19].BUFD_BLK 626 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[7] 386 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[7] 367 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[15] 278 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a3_0[5] 142 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_2[6] 46 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[24] 623 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/dpc_rd_data[29] 829 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[5] 489 184
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/iPRDATA_0_sqmuxa_RNI3FK6K 624 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[3] 254 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[21] 455 195
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[22] 49 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[3] 284 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m23_1_0 685 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m0s2 761 138
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[19] 482 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[6] 856 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[6] 337 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[12] 925 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[12] 296 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[18] 107 199
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[3] 572 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[6] 790 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[24] 375 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un4_rs2_rd_hzd_1 733 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_first 600 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[19] 918 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[13] 499 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[23] 757 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un131_I1Oi1 60 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNI9C6GO[12] 892 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNIA0I5CT1 780 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11_Z[26] 276 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[8] 843 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[3] 843 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[3] 717 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/IoI01 289 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[9] 818 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIO1CS7[4] 895 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_166 648 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[5] 515 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_0[0] 559 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[7] 488 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/il111 119 172
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_2_iv_i_RNO_2[2] 628 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[10] 482 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[0] 170 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[20] 718 186
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[14] 495 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[4] 165 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[25] 936 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[15] 622 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[27] 720 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[25] 661 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[12] 711 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[13] 714 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[7] 973 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[26] 868 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_7 828 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[2] 701 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_RNO[0] 409 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_d_1_RNIBU5HQA2 772 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[3] 331 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[10] 921 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mcause_excpt_code_wr_data_0_cZ[4] 818 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[27] 351 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[14].BUFD_BLK 566 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[15] 964 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[4] 712 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[34] 723 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IOI11 248 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O0iO1 337 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[5] 250 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[19] 520 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_29_1 645 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/un1_Ioli0_1_0 372 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[6] 250 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001[2] 168 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[3] 506 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[8] 510 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[39] 444 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[1] 158 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[12] 811 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNI62LV4[7] 245 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1[15] 390 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/rrex_1 100 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_write 734 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs1_complete_ex_s_RNIRTD29R 778 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[19] 969 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_error_sig 818 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OliOo_5 184 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/gen_bit_no_reset.state_val[0] 787 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[7] 877 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[3] 717 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_1[1] 720 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[19] 92 166
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_2_sqmuxa 31 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[28] 975 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1iO1 205 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[25] 707 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][30] 893 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[11] 298 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/wr_en_data_or 829 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un17_ioIO1 155 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_3_RNO[3] 823 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[5] 756 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNO[4] 740 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[13] 274 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_231 696 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[43] 950 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.IOoIo[0] 363 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1075 700 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNIVDG1K92 821 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_i_a2_0_0_0_12 793 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI9FM4C[5] 670 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1[21] 335 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[12] 289 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[2] 240 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[5] 392 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[8] 271 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[0] 366 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_2[6] 140 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[13] 316 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0_RNO_2 791 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[31] 830 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[3] 208 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0] 525 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_i_req_ready_1 785 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[7] 291 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[16] 418 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[5] 498 253
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[21] 83 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[14] 725 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[7] 171 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[11] 639 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[7] 463 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[4] 397 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un25_ool01[1] 180 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_572 648 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lI0o1_1[1] 66 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[20] 820 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_16 700 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[16] 298 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/stall_retr 786 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_133 665 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[20] 717 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0_a2_1 117 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[14] 614 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_14[1] 403 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[9] 365 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[10] 430 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lolIo 65 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[8] 483 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/o0io1 80 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m53 147 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ii1o1_RNO 88 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[8] 488 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01_0_sqmuxa_i_o5 170 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[19] 522 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[17] 358 235
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[19] 38 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_3[7] 547 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/olOOo_RNO 141 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[29] 904 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[7] 54 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[6] 1000 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[28] 869 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[3] 301 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_1_2 613 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_7_0_RNO 855 174
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/last_bit[0] 523 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1273 699 219
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_state_ns_1_0_.m16_1 509 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_d_resp_type[6] 769 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/gen_bit_reset.state_val_12_u[0] 787 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg_4[4] 649 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNINHVQ8[32] 739 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[16] 916 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil15 507 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_op_sel_1_0_.m15 661 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[18] 679 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[4] 266 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[35] 237 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[12] 260 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_1 52 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[7] 340 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_55[11] 295 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a0_2_RNI2NRL4 783 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[6] 534 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l01o1 109 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1 238 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[24] 950 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_246 674 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[6] 264 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lo0i1_RNO_0 253 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[18] 733 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places[2] 913 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[5] 771 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_c_0_0 771 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[17] 653 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OlOI1 380 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[0] 758 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo[3] 240 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[5] 755 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO1Oo 219 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[3] 570 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][0] 892 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3 830 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[2] 410 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[29] 766 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_599 709 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNIB64LE[2] 790 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_intce[64] 833 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_0[7] 385 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/l1o01 82 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[38] 617 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[0] 743 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[3] 39 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[7] 233 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[14] 555 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1_0[15] 362 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_808 758 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1036 637 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[1] 674 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[4] 851 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[5] 242 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_176 751 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0_4 591 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[1] 346 237
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0]_3[0] 750 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[17] 686 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[10] 735 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[7] 92 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_12_0_RNO 846 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_0 723 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_3_200_a2 259 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i11Oo_0[3] 213 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_97 674 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment_RNO 824 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[9] 842 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_Z[0] 186 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[19] 740 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[3] 360 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex[1] 732 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[9] 240 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_440 690 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[10] 407 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/i0001[8] 169 193
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[3] 480 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_i_x2[1] 201 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un3_I0IOo_1 134 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[5] 722 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oi1o1_1 91 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[37] 731 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[11] 720 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[2] 193 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[21] 721 192
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNI4M5KC_0[0] 20 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_next_buff_resp_wr_ptr_1_sqmuxa 635 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_9 826 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[10] 489 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[7] 821 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_RNIFEGPS1[0] 748 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_cnt.xmit_bit_sel_3_a3[0] 534 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[26] 470 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un18_Oo001_1 200 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmstatus_allany_havereset10_0_a3_RNIIO92L 826 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftIR_4_iv_i[0] 654 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[7] 485 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12_1 669 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[30] 523 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data[0] 714 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[20] 592 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[5] 711 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[5] 214 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_3_1_0 518 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[11] 816 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[20] 469 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[2] 466 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35_1[1] 981 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_124 758 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIO11_1 93 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[28] 819 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_in_write[1] 705 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[8] 298 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[14] 725 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01_0_sqmuxa_0_a5 169 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[5] 326 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_1_0[1] 483 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[0] 406 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_41 686 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[13] 483 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[16] 290 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lI1l1 506 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0iO1 346 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[6] 289 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[9] 170 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_2_0[13] 818 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_15 764 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[8] 276 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/ioIl1 464 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[20] 842 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[0] 280 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m63_0 299 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[1] 133 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[9] 789 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[32] 477 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv[17] 723 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[30] 926 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_795 758 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_389 691 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[0] 368 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo_RNO_0[3] 154 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1002 686 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_4[1] 350 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un59_OOOI1[11] 393 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_7[9] 848 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[13] 359 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO_0[3] 716 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[4] 798 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[32] 330 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_8 841 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_632 770 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[1] 448 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5] 667 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un3_dmi_rd_0_a2 726 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIIi1 308 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[21] 464 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[12] 862 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[12] 489 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[7] 321 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[47] 812 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_537 699 210
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_ac0_5 37 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[2] 771 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr[11] 779 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[38] 819 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_stxs_bitsel_3_1.CO2 601 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[10] 250 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_RNO[0] 81 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[13] 408 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_addr_align[1][1] 763 142
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un10_countnext_axbxc1 600 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_960 614 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_3[1] 788 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.un291_rv32i_dec_sw_csr_wr_op_0 717 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un19_O0io1_1_0 96 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[6] 770 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[31] 459 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[20] 393 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[24] 686 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[18] 927 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_6 318 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_a4 824 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_201 688 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[4] 472 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[5] 946 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_913 757 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[15] 543 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/un1_Ioli0_1_0 335 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[29] 482 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_2_RNO_0 827 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[46] 384 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7 759 147
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_alldone 572 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_3[10] 388 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[3] 307 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[7] 875 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb_iv_0_o2_RNIVVRAO 776 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[15] 911 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[24] 345 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[18] 666 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[2] 459 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[9] 373 186
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNIM7072[4] 491 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_1_0 135 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[0] 241 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_0[0] 64 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[24] 861 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[9] 114 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand1_mux_sel_1_0_iv[1] 828 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_0[13] 139 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_69[11] 359 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_ready 791 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_2[17] 204 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_698 649 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_1[0] 63 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[14] 904 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m5s4 775 138
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state[1] 563 211
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[3] 557 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_464 628 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[12] 912 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[18] 1000 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_0[30] 739 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[2] 330 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[19] 588 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_103 744 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[15] 804 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[13] 702 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[3] 728 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001[1] 186 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UDRCAP 434 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[6] 877 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIPFRQ8[15] 778 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_branch_reg_RNI97KDL 793 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[0] 477 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_788 613 216
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[1] 482 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[7] 355 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[0] 356 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[18] 903 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[4] 62 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI1o1_i_0_o2 87 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/cmderr_ff[2] 838 118
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[1] 46 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[15] 416 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_m0[6] 510 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[11] 248 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[4] 276 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state133 601 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_RNO_0 751 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_753 705 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[7] 537 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[14] 887 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[10] 876 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[7] 948 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[13] 71 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[9] 614 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[11] 312 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[10] 519 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[29] 613 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[15] 259 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un4_IoOOo_NE 124 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[4] 845 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[1] 527 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I1111 76 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1_2[0] 409 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l11Oo[0] 218 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4949_24 686 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_1[30] 157 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[3] 141 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[7] 265 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[4] 761 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Oi0l1[0] 475 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[0] 338 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[4] 286 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un89_ool01 194 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_2_1 439 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[11] 708 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[6] 375 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[31].BUFD_BLK 639 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.un1_o1ol1 304 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[30] 734 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_84 733 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[8] 391 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[20] 731 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[26] 989 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0_5 589 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[30] 784 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un3_OilI1_i_o3 396 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_midbit 596 208
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[25] 483 243
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[9] 795 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[10] 742 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[0] 744 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[9] 777 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[21] 850 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[18] 794 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l1ol1[7] 445 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[4] 597 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[24] 837 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[0] 250 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[20] 496 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOii1_0_a3_0_1 145 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ill01[8] 210 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1126 650 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[9] 82 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iIiO1 270 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01[6] 164 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ooio1[5] 57 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[7] 717 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs2_rd_valid.m12_0_1 673 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_95 732 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[39] 743 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.TCG[3] 137 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_22_N_3L3 801 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[27] 841 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[3] 210 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[9] 257 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_1 390 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_887 818 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_a2_1[7] 724 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_40 625 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int[1] 779 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[1] 150 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[4] 198 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_37[8] 961 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO[3] 827 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[19] 875 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].un1_lIII110 469 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_bit_reset.state_val[0] 786 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[0] 512 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[10] 115 181
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[12] 468 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[6] 914 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[19] 938 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2[29] 930 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_oI0i1 213 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt_5_7_206_a2 408 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_iloOo_c3_RNIEO6GT 252 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[30] 890 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr[1] 700 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[2] 890 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_strb[0] 775 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo 324 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[14] 295 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[23] 543 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[37] 816 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1[6] 338 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/un1_Ioli0_1_0 300 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[11] 366 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_instr_decoded_iv_0 686 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[16] 869 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[13] 836 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_970 627 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_o2[22] 222 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01 109 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[3] 661 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[6] 314 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un25_i0Oo1_ac0_7 282 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[5] 841 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_shifter_unit_op_sel_0_.m8_e_1 718 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[4] 893 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[0] 280 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_shifter_unit_places_2_0_.m19_1 697 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_11_RNI6P1TI 722 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOi11 458 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m12 161 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12] 683 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[20] 864 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_gpr_valid 858 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1ll1 481 190
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_3[1] 26 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[9] 200 223
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tmsenb 595 118
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_pktsel_RNO 565 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_op_abort_ex_1 832 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[40] 708 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0_RNO[5] 324 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[4] 529 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m6 40 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[9] 878 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a1_0 796 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un96_lIlo1_1 303 198
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3[2] 14 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_o1oOo_1 230 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un63_i11Io 529 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0_a3_0_1[2] 841 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[10] 638 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Iloi1_i_0_a3_2 253 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/un9_empty_rd_1 706 120
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[10] 46 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_515 685 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[16] 266 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[29] 806 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[19] 414 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[25] 675 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[12] 255 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiOOo 130 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_474 763 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrfn_1 284 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[30] 315 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1OOo 238 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[9] 142 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[16] 730 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1_0[7] 72 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_o2_3 86 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_tick 598 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[23] 282 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[6] 244 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[5] 180 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/p_APB_0_Read.prdata18_0_a2 601 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_602 664 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_valid_reg 729 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_727 771 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_35[8] 340 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oiol1 316 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_a2_0_0[0] 160 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_1[4] 282 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOoo1_i_1 85 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[19] 972 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_507 686 219
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[1] 625 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[29] 808 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OI0i1_10_0_a3 264 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[16] 535 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lIOl1 426 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_ready_reg 809 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/un1_Ioli0_1_0_0 354 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[9] 949 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un17_ool01 181 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[6] 103 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI44EG5[5] 265 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1011 272 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/l1lOo[15] 135 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[30] 987 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[30] 518 172
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/samples[2] 523 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[12] 729 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[15] 280 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[6] 262 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sresetn_4_i_o2 515 255
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[47] 619 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_1 122 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m41_2_0_1 111 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[25] 451 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[0] 121 205
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code[4] 13 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[57] 937 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_15_RNO_0 878 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_790 685 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m150 362 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1o11 403 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[12] 841 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_3[3] 373 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[1] 60 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[29] 178 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un12_I1oo1_5 131 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25[9] 350 219
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[22] 485 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[8] 711 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[18] 542 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[1] 151 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_645 684 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_829 763 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[17] 309 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[50] 839 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[29] 702 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt[7] 234 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2135_0 649 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i1II1 376 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[7] 464 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[19] 922 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[9] 754 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[15] 370 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_2_0 134 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_RNO_2[1] 819 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_dummy_target 769 150
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_axbxc5 17 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un51_I1Oi1_1 50 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[6] 339 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[13] 900 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[18] 411 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[22] 812 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[17] 332 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/endofshift_2 589 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0[2] 848 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[0] 354 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1257 625 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_4 420 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[8] 854 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[3] 847 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oli11 436 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_989 708 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[12] 90 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO[1] 519 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.receive_count_3_i_x2[3] 521 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_ld_req_buff_addr_misalign_iv 702 150
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[15] 48 222
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[28] 62 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[13] 229 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IlO11 84 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/IilI1 301 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/un1_Ioli0_1_0 357 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[55] 634 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[14] 685 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[37] 323 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[20] 987 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_11_RNO_0 806 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[2] 875 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un63_I1Oi1_1 42 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[19] 841 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt[2] 297 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[0] 429 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_25[5] 343 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[11] 345 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[38] 395 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_4[1] 130 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[18] 480 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[10] 337 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[14] 363 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_1[5] 242 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/OolIo_2_0_.m6 50 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[17] 285 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01[0] 304 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O1Ol1 430 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[3] 621 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[11] 622 210
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[10] 503 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[19] 914 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_mux_sel_0_iv[0] 724 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[4] 853 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0Ii1 243 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0_1_0[0] 336 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[7] 370 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/data_out_d[16] 565 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[7] 205 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][4] 871 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[0] 210 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[1] 329 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[7] 50 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_iO0o1 139 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[3] 180 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIo01_0_a2_2 109 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un10_next_buff_resp_wr_ptr 626 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_wr_sel_2[2] 718 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[4] 299 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4[2] 518 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[4] 251 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[6] 887 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un1_ii1i1[0] 335 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[3] 353 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m11 62 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4912 663 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[62] 646 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[15] 213 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[2] 847 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[0] 510 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[22] 601 175
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/un1_rx_bit_cnt_1.CO1 527 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_87[11] 371 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[7] 509 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un2_cpu_i_req_ready 773 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_cmb7_i_o3_RNIFL5ND 769 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[8] 740 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Iiol1 316 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/mem_rdata34_0_0_RNIDMOIC 759 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[2] 187 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31_2[15] 970 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_33[9] 341 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[8] 157 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1[7] 853 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[4] 311 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[26] 659 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_apb 782 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[15] 117 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1iOo 237 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0[18] 184 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0[1] 400 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_i1Il1_RNO 490 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[29] 911 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[30] 867 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0_a2_3[7] 117 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_10_0_a2[15] 128 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op[2] 736 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[31] 928 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1[3] 157 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[7] 884 133
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_count_RNO[3] 525 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[27] 853 142
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[7] 588 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[23] 801 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs1_completing_ex_0_RNIRC024I1 770 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[7] 111 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/wr_data 780 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0_RNO 433 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[14] 94 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[57] 616 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0_RNI9RU7D 761 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[3] 507 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[2] 505 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIP2FO8 411 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[30] 457 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[21] 673 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Ilo11 424 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[9] 122 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_a2[31] 748 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[3] 256 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[43] 374 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[2] 206 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un12_OOOI1[14] 425 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_3_0_a2[15] 124 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[6] 870 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[10] 870 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[12] 132 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[25] 475 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1076 673 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[0] 702 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[0] 783 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[11] 320 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[17] 565 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_1 330 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.empty_r 502 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_valid_2_0 839 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[17] 852 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[7] 291 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[8] 260 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_2_a3_1 805 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1182 809 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[15] 278 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/IilI1 417 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/oII01[7] 361 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/OioIo90_RNI404DC2 168 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/o0iI1 492 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[26] 484 244
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[3] 418 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[10] 653 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[5] 231 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4[1] 46 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oiIl18 460 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[2] 791 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[11] 114 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[8] 749 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Oo0o1 100 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2 95 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un5_m3_i_a3 812 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[17] 759 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[20] 346 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs3_rd_valid_ex 748 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a6_0_1 51 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[4] 741 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[47] 623 184
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync[1] 21 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[18] 902 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[13] 560 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_ndmreset 821 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[21] 804 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[28] 973 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1_0_a2_0[22] 391 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[7] 699 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[11] 367 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[26] 722 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[6] 783 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/OOil1 311 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_i_a8_5[3] 153 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_825 698 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo[4] 206 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un9_Olii1lto4_0 149 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2]_RNILPGP9[0] 886 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[3] 147 208
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[3] 39 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[10] 199 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un1_o01O1_0 460 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[7] 137 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_1[25] 199 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[8] 537 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un137_OOOI1_cZ[18] 461 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[24] 757 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.lloIo 238 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[19] 868 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_486 698 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[17] 757 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].un6_req_buff_load_os 832 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo_RNO_0 206 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[30] 998 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[0] 853 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[5] 186 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_0 674 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[22] 783 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0[0] 417 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_o1i11_0_a2_3 343 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/toggle_hart_soft_reset 634 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOo01_Z[1] 75 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[2] 347 183
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1_1[0] 498 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[3] 481 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[0] 734 133
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_23_RNI7FA6M5 36 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[10] 202 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/liI11 323 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[16] 891 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_368 661 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/II111 328 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[4] 277 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[7] 486 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[5] 776 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[1] 791 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_IOoi1_4 389 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[3] 952 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[17] 439 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[25] 772 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[1] 122 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/IilIo_1_RNO_0 67 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_2_iv[8] 707 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[5] 300 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[8] 538 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un29_loOo1_i 344 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.OlIo1_0 235 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[5] 711 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_6_RNIBNTPJO3 799 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_write_mux 737 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1137 648 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_read_gpr_rs1_ex.gen_rs1_exu_stall.un6_gpr_rs1_stall_exu 750 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[28] 474 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[1] 209 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_s_32_RNO 851 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[15] 475 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[11] 48 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_iloI1_2[11] 468 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[9] 854 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_I1iOo 220 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_861 817 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[13] 251 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[3] 360 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[30] 867 165
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_cnt.rx_filtered_2_i_o2 522 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[18] 524 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[10] 313 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[23] 575 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_30[2] 381 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[0] 846 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[8] 659 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e_0 687 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_lm_0[5] 312 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[2] 349 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i01I1[12] 414 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[2] 724 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[4] 539 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[15] 642 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/oOIl1[6] 511 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[14] 49 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un6_I0io1_1[0] 99 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[4] 469 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2 804 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[10] 274 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OiiOo_1[3] 158 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[13] 506 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic1725 736 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_csr_rd_data_ready_3_0_RNICPD96 853 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1184 710 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1] 705 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[8] 97 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[15] 833 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[2] 57 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[3] 333 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[20] 393 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/liIo1 292 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[0] 231 196
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_par_calc.rx_parity_calc_2 516 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_N_4L7 738 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[24] 236 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_m_1[4] 688 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[6] 340 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m20 636 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un107_I1Oi1 56 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[6] 315 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[11] 731 144
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[17].BUFD_BLK 594 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_i_retr 757 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[3] 742 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m17_2_0 110 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[10] 733 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][9] 901 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[29] 732 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_a2_3[4] 765 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[17] 595 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[6] 32 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt[9] 248 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[3] 235 172
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_wmux_0_RNIVNTG1[5] 45 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[16] 356 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[17] 940 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[4] 723 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[15] 296 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/un1_Ioli0_1_0 290 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[0] 269 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state21_1_1 781 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iil01_RNO 150 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2_d_2_0 652 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1_5_i_m2_i_m2[19] 44 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2s2_0_a2_0 768 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt_RNO[13] 277 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/un1_oOo11_1_i 164 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un73_OOOI1[13] 416 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_rd_byte_en[2] 701 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un2_rs1_rd_hzd_4 730 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[8] 610 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[6] 360 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[7] 50 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1775_0 91 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[11] 336 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2 49 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[7] 367 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[3] 860 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[6] 924 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2115_4 678 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[29] 870 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[9] 877 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[1] 153 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_1[5] 522 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instr_completing_retr_d 816 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/I0Io1_Z[3] 361 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr_4[0] 634 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ill01[3] 189 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[15] 766 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_243 708 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_capture_reg_RNIJ6N8I1 802 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[15] 93 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[40] 949 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[23] 938 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a2 737 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_140 625 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[2] 88 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_250 685 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[27] 613 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[2] 853 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[7] 509 256
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[6] 87 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[9] 421 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[17] 61 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0] 481 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_1_4 776 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[22] 374 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[15] 411 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un2_O1Il1[0] 459 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oI101[1] 101 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[11].BUFD_BLK 625 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[14] 852 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[15] 868 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14[10] 961 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo[3] 263 184
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/reset_lane 16 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.awe0 625 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[21] 394 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[10] 312 175
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[9] 41 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[5] 853 159
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4[3] 43 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[7] 403 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[0] 476 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[13] 529 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[24] 371 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/N_130_i 674 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oil01[0] 161 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[14] 503 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un62_o1Oi1 73 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[6] 713 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[0] 600 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[12] 845 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[1] 483 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[9] 120 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_a4_sx 825 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[9] 848 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[0] 829 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_addr[4] 753 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[9] 876 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[7] 39 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[30] 159 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[9] 614 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_427 651 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_378 720 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_1_iv_0_0[3] 748 174
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[6] 42 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un95_ool01 193 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un3_Oll01_3 162 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOI11_0_a2 140 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[3] 852 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt[8] 384 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[26] 826 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[2] 272 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[19] 524 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_39_u_2[2] 1000 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[11] 709 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[63] 642 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_1[3] 210 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_31_RNIIOLBU1 801 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[24] 892 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[17] 705 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[18] 887 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[20] 815 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[8] 877 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv_1_tz[1] 133 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_T_l_En_0_a2_0 597 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iiol1 302 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[2] 589 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[54] 615 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[2] 323 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[2] 193 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_1[0] 769 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[23] 443 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0[8] 859 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[7] 388 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m74_0_a3 138 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_0_0 75 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_14_1 682 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_871 808 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_3 376 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[4] 574 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[19] 865 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[14] 272 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[1] 218 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[16] 429 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[4] 25 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[35] 734 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[0] 458 210
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[23].BUFD_BLK 638 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[5] 366 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_0[1] 820 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Ol0i1_m3_0_a2 218 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[20] 386 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[14] 337 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[1] 749 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o1001[7] 199 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[18] 95 205
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UDRSH 600 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[18] 593 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/I0lOo[0] 152 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO0Oo 231 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ii0l1[0] 470 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_m1_e_0 806 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[29] 500 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Ioi11 357 192
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[7] 34 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[2] 894 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[1] 621 118
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_11_RNIM2LRM 26 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[3] 124 181
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[22].BUFD_BLK 593 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata1_sw_rd_sel 852 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[7] 648 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[15] 828 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[16] 295 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0[2] 221 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_26[0] 377 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ool01_2[7] 179 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913_2 667 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[1] 124 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[29] 815 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/OoO01_0_sqmuxa_i 593 183
set_location fifo_to_tpsram_bridge_0/fifo_rd_en_u_i_o2 479 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_41[8] 956 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNIOQR5C[21] 674 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[19] 728 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1160 660 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o0oOo 247 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ilIi1 312 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[2] 507 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb_RNO[2] 685 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[7] 511 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[23] 288 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[5] 154 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_operand1_mux_sel_0_a2_0_2[0] 682 165
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_1 435 6
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[16] 741 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_o3[1] 646 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[19] 594 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[1] 346 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[7] 720 198
set_location Core_reset_pf_0/Core_reset_pf_0/dff_9[0] 841 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_d_1 776 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_67[11] 287 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[23] 879 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_0[3] 156 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[17] 778 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[0] 186 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[18] 545 184
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[22] 478 250
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io[5] 54 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[12] 305 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[15] 127 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/l1I01 375 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[5] 37 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_294 624 210
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/tx_alldone 572 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un1_req_count_i_RNI38RFLN 826 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_TCM_byte_shim.un7_cpu_d_req_wr_byte_en_sel 710 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_o2[0] 157 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[34] 609 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0iOo[7] 213 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_1[21] 791 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1[19] 472 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[18] 792 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01_RNII5V8F[2] 302 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_853 625 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[11] 714 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/N_110_i 819 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_9[0] 216 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[17] 701 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[5] 207 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_344 745 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIl11_Z[1] 363 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[5] 500 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_alu_op_sel_1_iv_RNO[0] 663 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_23_0_RNO 873 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_431 624 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[11] 565 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[1] 409 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[39] 953 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[17] 854 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_732 807 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[1] 432 211
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1_i_m2[6] 470 243
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe 606 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[1] 210 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0_1_0[0] 275 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[3] 420 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[12] 55 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un30_OIoO1 99 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[34] 235 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[12] 146 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.debug_mode 797 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i1oOo[4] 244 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[12] 127 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[35] 601 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[25] 504 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_258 806 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/i0l11 341 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iio01_RNO 78 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_6 839 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[1] 228 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[31] 730 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[6] 268 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un171_I1Oi1_0 50 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shift_op_complete_ex_0 781 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI16R57U3 780 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[1] 916 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[10] 909 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_0_RNICHBA5T 772 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[2] 421 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[20] 849 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[26] 629 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un13_oI0i1_1 214 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_fiforead 562 202
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[7] 26 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[29] 685 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[14] 591 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto4_1 219 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[10] 218 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_13_RNO 862 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[19] 409 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/wr_gray_ptr_5[0] 698 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/hipri_req_ptr_RNO[0] 778 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIOA2JA 850 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0_1_0[0] 328 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1067 781 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[3] 498 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_o6 50 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_OOii1_0_a2 152 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a2_1[4] 153 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un41_ool01 183 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_data[1][2] 803 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[28] 715 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[31] 925 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[13] 778 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00015 170 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[18] 384 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[10] 325 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_m7_i_o4 814 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_16_0_RNO 874 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[9] 606 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/emi_resp_head_uncompressed_full_0_a2 702 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[31] 360 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[1] 450 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_retr_0_0 814 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted[5] 817 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[17] 744 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IliOo_NE 215 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un1_ex_retr_pipe_curr_pc_retr 746 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_4[17] 60 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o0111 102 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_valid_cnst.m31 613 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[7] 856 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[30] 807 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[3] 468 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/gen_bit_reset.state_val_RNO[0] 816 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i11I1_Z[4] 429 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14] 672 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[36] 720 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO[13] 226 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un73_OOOI1[6] 409 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[18] 902 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[30] 740 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1_0[4] 79 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[18] 866 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_sn_m4 749 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0[7] 720 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo[11] 224 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 514 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_286 651 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lol01[7] 196 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a2_2[4] 144 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[3] 572 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[6] 919 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_branch_cond_exce[0] 776 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[18] 73 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_3[11] 387 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[3] 348 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[5] 863 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1O11 118 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/i0Ol1 420 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0iOo 226 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_9[3] 847 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[31] 829 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[31] 495 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[31] 935 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[12] 127 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[17] 890 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_wr_ptr[0] 833 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[16] 454 216
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[18] 470 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m209 358 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[12] 920 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1200 672 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_cnst_i_RNO[4] 883 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNICPK9D 770 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iOl11 342 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_d 800 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNI59A5T71[0] 733 150
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[1] 480 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[5] 338 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[12] 228 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_24 767 183
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/un4_fifo_rd_en_0 492 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[29] 689 183
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[24] 67 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[10] 438 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[56] 965 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo_i_o2_0[3] 277 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_a2[31] 803 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[4] 189 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[26] 379 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[7] 791 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_immediate_0_iv[0] 760 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2[5] 951 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/case_dec_gpr_rs2_rd_sel_2_sqmuxa_RNI49OMR5 757 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[7] 383 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OOIo1 326 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/interrupt_taken_0 817 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_480 719 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[8] 709 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[26] 879 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[11] 779 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0_o3 96 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z[39] 455 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[2] 221 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[0] 741 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[2] 389 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Ol001[2] 203 190
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[10] 18 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_24_RNO_1 879 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[8] 349 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[9] 839 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[1] 368 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_data[14] 751 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[23] 612 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_0_tz[20] 234 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lio11 463 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_x2_RNIVDP1I 169 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_ptr_0[0] 764 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[12] 861 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[20] 471 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[15] 350 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ol0i1lto5 218 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/empty_rd 703 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3[4] 101 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_0[0] 703 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNI8LK9D 746 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiiOo[0] 197 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[7] 530 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv[1] 723 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[30] 458 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 234 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[8] 771 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_3 313 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[15] 771 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[26] 825 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[9] 484 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNIDGO7J[6] 694 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_7_u_1[29] 951 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[0] 273 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[25] 739 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0[6] 661 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[3] 103 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[16] 962 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[9] 373 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[2] 185 202
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/tune_st_s3_i 35 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][22] 871 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmcontrol_dmactive4_0_a3_RNIVTR8H 821 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[48] 599 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[25] 686 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv_0[4] 685 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_0[7] 572 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[13] 842 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[15] 64 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_RNIFJ3KL 724 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4913_2_0 645 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr[1] 698 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loli1 328 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lil11 290 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lO0Oo 235 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[7] 543 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_UDRUPD 432 6
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_1_iv[5] 658 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_lm_0[4] 314 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv_RNO_0[1] 688 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[31] 713 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[7] 457 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo[3] 269 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[29] 804 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[9] 659 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[30] 609 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_gpr_wr_valid_RNI9OFR8 720 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[4] 156 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[12] 404 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_7[5] 314 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[16] 72 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_1[3] 766 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[15] 889 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[11] 622 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_lm_0[8] 384 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[5] 673 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[28] 474 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un27_I1Oi1_2 48 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_access_mem_error_u_0_a2_6 884 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7] 691 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[19] 731 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_3_sqmuxa_0_a2_1_5 811 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[23] 570 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1103 768 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[7] 49 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_fence_ex 720 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1_RNIN92R7[2] 110 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[16] 841 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_24[1] 348 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[0] 181 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[18] 376 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[12] 842 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[22] 650 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[16] 455 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[1] 723 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_401 663 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1177 651 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oiII1 364 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[16] 912 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_702 648 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[9] 306 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result192_1_RNISHFFMD 928 192
set_location fifo_to_tpsram_bridge_0/state[1] 471 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_850 655 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt[2] 381 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/OOi11 422 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[19] 935 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky_10_iv_i[0] 569 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[6] 717 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_o12 739 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr_s_s_RNI3ANUG2 816 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[9] 837 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[2] 341 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[19] 915 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[17] 456 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un10_I0io1_0_0 98 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clock_rx_re_RNIS69MA 609 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_5 743 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m101 346 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[21] 611 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[10] 523 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo_5 138 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_a0_3_1_RNIBFPQ8D 813 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/O0l11_Z[7] 410 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IOoI1 411 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/lI001_RNO 201 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[3] 368 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[7] 232 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1oOo[2] 241 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un25_I1oo1 86 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6] 642 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[12] 257 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOOIo[0] 176 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[3] 489 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un8_l00o1_3 49 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[25] 910 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_923 650 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_463 673 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_a2_7[13] 710 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[9] 357 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[11] 727 135
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/un1_tx_parity_1_sqmuxa_0 535 165
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_tckgo_2_sqmuxa_0_tz 627 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[7] 263 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI1i1_i_o2[4] 373 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[20] 887 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[4] 469 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un64_OIoO1[1] 121 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[21] 712 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[8] 121 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[11] 211 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un11_oioOo_1 204 180
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[2].BUFD_BLK 593 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_valid_retr_2_1 827 153
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[26] 66 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_lm_0[4] 312 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/IilI1_RNO 417 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[29] 864 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iio11 431 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[9] 212 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lioi1 145 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[31] 896 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_lo0i1_2 252 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[11] 84 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[7] 856 129
set_location Core_reset_pf_0/Core_reset_pf_0/dff_2[0] 828 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[1].buff_valid[1] 810 154
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[29] 479 244
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[1] 866 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0_0[14] 726 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2112_2 662 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_0[3] 710 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[9] 520 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[22] 812 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[30] 828 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[22] 858 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un530_lIlo1lto3 243 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[5] 337 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[2] 109 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[4] 729 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[2] 231 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[1] 56 202
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[15] 614 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[1] 124 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25_1[10] 352 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[20] 288 178
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCON/tx_fifo_write_sig_0_sqmuxa 441 186
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[3] 47 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[8] 326 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[26] 946 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[19] 952 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un18_Oo001 196 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/iolIo_1_0_.m4 39 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[5] 279 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[11] 910 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[18] 931 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_46[11] 376 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0ii1_2 120 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[25] 908 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[7] 554 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[8] 311 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_gray_ptr_5[0] 696 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[52] 597 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt[2] 302 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[8] 420 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[1] 690 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[7] 913 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[13] 230 171
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[25] 478 244
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIHBFGI[6] 563 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIoOo 232 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[30] 402 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lo0l1[0] 500 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0[15] 224 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1169 768 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftIR_ne_0_3 653 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff[0] 752 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_6[6] 504 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[6] 873 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[14] 349 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0[1] 147 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[4] 854 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[28] 674 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[27] 900 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[5] 696 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/I1ll1 456 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utime_rd_data[1] 707 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[11] 950 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[30] 872 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[4] 305 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l1lIo.m5 131 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_ns_i_i_m2[1] 474 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[5] 160 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex[1] 786 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[18].BUFD_BLK 592 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[10] 570 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10] 663 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_status_mpie_wr_en 768 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[18] 896 148
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[3] 483 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[22] 706 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_is_hword_high_only_u_RNO 885 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0_0[23] 282 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[5] 97 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[5] 627 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[10] 742 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a2_1 354 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[6] 660 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/empty_out 608 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNIRJFFD[7] 717 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lliO1_Z[7] 359 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_1[0] 136 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt[8] 272 226
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[9] 61 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[9] 403 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[8] 665 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[2] 304 225
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/reset_lane_RNIJDIL7 13 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[2] 746 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_1 565 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[0] 511 190
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_28 78 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[11] 265 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_2[2] 244 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1156 615 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01 402 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[16] 771 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111 264 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[1] 430 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un189_I1Oi1 62 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_2[9] 386 213
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[2] 496 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ii0i1_RNO 297 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[16] 706 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[4] 301 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[19] 777 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[18] 872 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[13] 284 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.N_715_i 180 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/III11 297 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[44] 952 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[6] 793 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_lm_0[6] 304 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_RNIBQJDE 763 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[10] 927 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[24] 926 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[13] 382 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/o0ol1[9] 443 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[1] 610 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oIoO1_RNIBVKRO 290 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[19] 716 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[7] 464 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[23] 550 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiI11_i_o2_4 146 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[3] 302 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_count_0_sqmuxa 631 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[21] 726 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OlIo1 235 214
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[4] 621 115
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un137_i11Io[3] 505 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_1_sqmuxa_1_2 602 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[28] 896 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[16] 961 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[5] 865 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_769 626 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OO0l1_0[5] 445 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lIol1_8_0_a2[0] 288 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[6] 228 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un83_I1Oi1 43 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1[1] 732 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_gray_ptr_2[0] 707 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[24] 602 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl15 493 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[12] 710 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[10] 408 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_a2_0[1] 413 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[21] 851 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[19] 951 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[10] 810 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_I1iIo_1 496 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[6] 516 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo_RNO[0] 154 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[10] 649 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un3_loOo1_0_a2 356 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_wr_data_reg_9_cZ[23] 757 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[5] 703 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_473 804 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1_0_a3[15] 372 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1_RNO 132 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[19] 911 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_956 637 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[21] 871 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_198 734 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_212 625 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[11] 322 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[9] 150 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[2] 185 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3[4] 842 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][14] 887 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[12] 607 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_38_RNI3TSFL 741 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_15[4] 367 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/un1_Ioli0_1_0 327 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_13[11] 279 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] 505 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/un1_iOI01_1_i_0 337 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_O0oi1_0_a2 337 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[8] 803 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2 782 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_525 723 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1000 661 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[13] 501 213
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[2].BUFD_BLK 602 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1_4[12] 437 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[29] 456 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[3] 901 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[13] 529 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/mnemonic537 839 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[9] 387 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_1_0 40 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[10] 126 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[20] 805 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt[2] 341 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[15] 710 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNIHNUT5 471 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[5] 251 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[1] 432 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lllOo[0] 154 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/I1lIo_2_0_.m5 133 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[5] 259 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[7] 920 160
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re_q2 604 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[11] 785 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[2] 801 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[8] 775 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_o2 105 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[8] 339 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[2] 75 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loi01[3] 94 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_lsu_op_1_iv[0] 649 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OlOOo_0_a3_1 127 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid47 733 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[23] 566 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[28] 366 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1[14] 356 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[43] 259 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[29] 942 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[6] 236 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_operand0_mux_sel_1_iv_2[0] 726 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_61 662 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1[3] 377 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[22] 943 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_685 697 147
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[0] 636 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Iiil1 537 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[20] 878 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[0] 777 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_33 763 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[13] 352 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_549 674 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_0[1] 85 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0iOo_5 152 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/illi1 252 169
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[5] 575 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/OO0Io_0_0_1_0_.N_13_i 96 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1I1 456 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[7] 715 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[11] 119 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/abs_cmd_transfer_ff 843 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[6] 169 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1[1] 509 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[10] 243 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[26] 988 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[3] 863 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/I1I01[0] 306 169
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[14] 506 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/buff_wr_ptr[0] 764 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un29_il0Oo_1 222 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[6] 388 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1206 698 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4956_8 684 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[4] 480 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO[7] 926 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_4[26] 480 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_operand_sel_1_iv[1] 760 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_1_2_1 765 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[17] 839 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[9] 841 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ioi01 114 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/IilI1 471 193
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk6.un5_almostfulli_assertlto9_i_a2 484 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[17] 410 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNIU12C5T1 790 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[12] 332 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[5] 215 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/un1_OOOI1[19] 393 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_Z[0] 817 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.IOoIo[0] 478 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[17] 726 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_4 374 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[7] 696 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_3[1] 700 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[23] 710 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[20] 816 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iIo01_i_0_a2_2_3 106 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_49[8] 940 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[29] 394 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/I0IO1[1] 212 187
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un82_fine_sel_1_ac0_3 29 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[1] 228 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5] 660 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_469 673 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_6_182_a2 262 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[5] 187 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt[11] 399 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[24] 454 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_valid_iv_0 775 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[4] 869 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iio01 78 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[56] 600 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_o2[5] 787 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[31] 718 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_1[8] 110 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[18] 216 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_961 627 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un19_IoOi1_i 244 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[9] 49 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[25] 835 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un8_iloOo_c3_RNI420PL 256 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2[28] 278 165
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UTDI 590 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oOi11_1 463 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[17] 845 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[10] 422 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[32] 741 121
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[14] 49 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic852_2 662 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_1_RNO 805 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[4] 823 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e_2 675 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[19] 682 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[3] 253 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un6_I0io1[0] 101 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/olii1[2] 146 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOOIo[0] 162 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a3[1] 747 129
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_par_calc.rx_parity_calc_4_u 518 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un35_iloOo_ac0_3 253 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO0i1 301 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv[7] 613 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[9] 430 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2132 685 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[10] 798 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[21] 677 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[22] 850 144
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_bit_cnt_0_sqmuxa_0_a2 508 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z[2] 182 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[3] 307 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/oio01 90 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_3 801 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_779 685 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[7] 262 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[5] 280 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/write_en 757 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[24] 477 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[1] 300 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0_a2[3] 417 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[6] 504 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[4] 154 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[29] 462 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IoO11_RNIB91PE 114 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[11] 544 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m75_2_1 132 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ooo01 106 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[9] 853 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[5] 852 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][10] 880 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[15] 107 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[9] 450 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[4] 174 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[5] 530 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00018 171 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[10] 845 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_lm_0[2] 312 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[9] 344 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_2 732 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_745 745 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Ooil1 527 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[5] 271 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3_1[2] 170 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001[1] 170 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNID84LE[3] 783 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4948_18 685 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[9] 813 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[17] 726 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[13] 850 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[2] 242 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_7 301 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[27] 883 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/gen_bit_no_reset.state_val[9] 863 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[1] 282 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[28] 975 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[48] 820 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_856 649 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[12] 58 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_rxbusy 557 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2[25] 745 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[13] 348 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][16] 865 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1132 696 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[18] 589 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[4] 205 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/i1i01 112 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[23] 715 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[15] 801 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/O10l1_0[0] 491 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IOOIo[0] 202 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/hipri_req_ptr_RNO[3] 777 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[8] 188 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_2[2] 745 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[9] 59 190
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[5] 18 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[9] 853 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1li1_RNO_6 264 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/i0101_Z[14] 116 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[4] 57 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[3] 167 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o1I11 228 187
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[4] 40 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[5] 58 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1190 757 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/un1_Ioli0_1_0 390 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[11] 672 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0[12] 192 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ooli1 333 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_3[25] 681 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1110 674 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[16] 960 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_1_axbxc5 14 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[9] 515 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt[10] 337 202
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[6] 595 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[26] 239 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[22] 857 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[17] 565 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[9] 405 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/I1001[1] 180 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[30] 824 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/II1l1[8] 519 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[2] 206 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1[9] 249 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OiIOo 143 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_648 726 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[31] 843 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[2] 517 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIOF68E[18] 664 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_255 698 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[1] 462 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oOiOo[1] 280 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Oo1l1 395 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[15] 801 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/o10Oo_3 224 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_compressed 719 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51[9] 925 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_2 395 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[19] 950 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[23] 847 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_o7_0[4] 146 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_4_RNO 436 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[1] 475 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[6] 126 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram1_[36] 728 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[30] 732 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1 576 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_busyerror_ff 760 118
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.lloIo 288 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[1] 338 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[16] 550 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/lOiO1 293 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[27] 684 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[8] 425 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1_4 217 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[29] 896 165
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[1] 68 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[38] 630 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[11] 915 144
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_q_1.CO0 564 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lilIo56_1 132 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l0001[9] 184 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[6] 518 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[5] 865 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_lm_0[2] 336 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[20] 860 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[10] 265 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[14] 247 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[8] 519 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_wr_byte_en_2[1] 709 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[29] 394 189
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[13] 512 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[1] 331 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[6] 325 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[6] 230 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[0] 377 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_resp_rd_data[2] 666 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_479 661 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/un1_IIOO1_1_0 433 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[4] 277 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ioOo1_1 299 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_next_dividend_0_sqmuxa 931 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[9] 743 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i0ll1 467 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_54[11] 385 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[0] 416 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_sqmuxa_3_2_RNIEHFCRE 810 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO_4[4] 676 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[16] 932 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[4] 403 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i[9] 687 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_RNO[18] 684 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un7_Tc0_l_En_0_a2 571 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_1[6] 277 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[17] 261 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO[2] 902 186
set_location Core_reset_pf_0/Core_reset_pf_0/un1_PLL_POWERDOWN_B_i 1060 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_971 767 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_333 660 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[3] 843 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ooiOo_0[7] 189 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/iIol1 438 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[12] 818 132
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[3] 545 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_emi_resp_rd_data[5] 816 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[12] 344 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_4[28] 380 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/un1_oiI01_1.SUM[2] 192 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Tc0_h_En_0_a2_RNI88OH8 572 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/IoOI1 335 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1097 650 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[3].BUFD_BLK 601 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[2] 297 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O1oi1[3] 327 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs1_rd_sel_1_iv_RNO[1] 690 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[12] 228 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_66 733 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val[1] 827 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1017 726 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[1] 318 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[4] 397 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[4] 455 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNISH7VA[11] 719 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[43] 563 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[7] 361 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[21] 939 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1134 673 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[11] 846 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/olol1[1] 432 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m24 109 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[4] 168 204
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg1Seq.controlReg15_0 508 165
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[5] 542 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[1] 408 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[10] 131 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[1] 122 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[5] 602 187
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[3] 21 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/machine_implicit_wr_mtval_tval_wr_en_RNO_0 827 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[4] 105 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_3_0 820 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[6] 523 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_4[9] 204 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[6] 191 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[23] 908 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[13] 532 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo14_0_a2_0 517 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_21_RNO_1 852 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[24] 475 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_8[12] 794 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un29_ool01 192 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1[6] 74 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12_1_sx_RNI6H24CH3 797 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[9] 398 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_iv_RNO_1 687 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[22] 387 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_12[11] 285 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[2] 332 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[19] 759 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[18] 919 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0io1 81 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[27] 690 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNI724LE[0] 795 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[18] 462 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[20] 444 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[2] 405 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un73_OOOI1[5] 402 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_wr_op_ex_RNIIHD136[1] 769 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[15] 175 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iOii1 140 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ilIO1[0] 250 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iOoi1[3] 371 165
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_wr_pointer_q_1.CO2 554 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[2] 591 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.implicit_wr_dpc_pc_en 835 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[11] 853 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2125_4 684 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[8] 797 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[1] 778 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[7] 871 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata[12] 608 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_lm_0[0] 340 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[6] 414 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o0Oi1 150 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[1] 318 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[20] 890 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1[9] 258 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[31] 233 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[9] 410 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un128_OOOI1[28] 476 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un55_I1Oi1 49 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[6] 724 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0[1] 288 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[3] 431 181
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg4_3 604 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOi01 72 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[3] 315 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1021 769 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_is_subsys_hart_soft_reg_2 781 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_14 692 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_690 697 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un16_oI0i1 209 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[25] 857 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_i_o4[4] 358 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[10] 131 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_283 649 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[16] 234 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_8_sx 810 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_o12_4 747 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_wr_illegal_i_a12_7_1 739 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_180 732 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[5] 388 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lIIi1 302 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ioil1[1] 528 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/PRDDATA[3] 553 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0_1_0[0] 307 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_9[0] 48 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[11] 42 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_498 709 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[15].BUFD_BLK 591 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1140 805 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/un1_read_rx_byte 504 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/wr_en_data 837 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_5[19] 870 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_lm_0[3] 396 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0_1 769 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[3] 855 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1[11] 527 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/start_m8_1 767 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[27] 848 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[10] 267 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[22] 829 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_data_resp_compressed[15] 651 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[15] 796 189
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[4] 488 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_31[7] 253 213
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[0] 495 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIF1U1J[10] 216 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[10] 443 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[9] 678 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_alu_op_complete_ex_0_a3_2 765 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/iiIIo_RNI99L88[5] 264 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[10] 873 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lOi11_0 466 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_operand_sel_ex[1] 760 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[6] 516 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[4] 440 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un27_I1Oi1_1 37 192
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[5].BUFD_BLK 590 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oOo[0] 250 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_8[31] 413 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Iio01 73 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1221 679 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[28] 876 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[3] 83 181
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_4_u_1_0 528 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[24] 943 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[35] 734 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/oI001_RNO[2] 168 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/l00019 169 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_state[0] 761 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/lII01[6] 371 172
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[7] 592 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[31] 512 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ioo01 101 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[3] 310 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/oiOOo 130 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0[7] 118 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[1] 518 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[17] 860 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_first6 608 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[6] 338 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[13] 940 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_wr_sel_reg[0] 738 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/data_rd[0] 708 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un9_O0oi1_11 336 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[11] 230 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[30] 749 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pstrb[2] 685 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[22] 446 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_16[19] 469 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[23] 774 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_740 636 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2_0_7 599 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1_RNO[14] 493 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[11] 851 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_RNO 848 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/countnext_1[2] 600 120
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_state 603 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/un1_Ioli0_1_0 357 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[10] 429 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[7] 481 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_11_0_RNO 857 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_i_o2[24] 729 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIVTT4D 739 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/OiOi1 278 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[1] 205 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[20] 903 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[5] 604 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960 705 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[12] 742 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IiOi1_RNI29J25 332 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic848_RNI13T1N 708 156
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[8] 40 229
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[4] 188 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[4] 706 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/I01l1[10] 422 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un2_IoOi1_0_a2_4 242 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[6] 201 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[5] 598 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[18] 708 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un7_I1oo1 126 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0] 473 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[10] 787 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNITHVJB[10] 252 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[19] 949 156
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q_3[4] 571 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_435 769 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/dbreak_retr 748 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1[29] 469 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_1[25] 621 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_iv_1[1] 699 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[17] 283 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/O0oi1_0[14] 351 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I019 301 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[10] 247 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[10] 512 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[1] 828 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.hstrst_rx_1 105 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[5] 392 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[25] 451 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_o3[2] 841 132
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[6] 32 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[11] 817 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1 401 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4912_0 660 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1047 684 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[22] 618 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/oiI01_5_2[1] 181 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_ss6 819 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[16] 912 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[4] 160 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[3] 778 129
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[16].BUFD_BLK 590 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/un1_Ioli0_1_0 295 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_valid43 739 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_o4[7] 181 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[11] 623 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0Ii1 289 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[18].BUFD_BLK 625 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[2] 278 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[18] 887 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata2_sw_rd_sel 840 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[5] 476 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[5] 246 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[27] 402 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_rd_byte_en_int[3] 790 130
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.o11Io.il1Io_1[26] 65 229
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_unit_places_0[0] 696 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/interrupt_taken_a1_0 798 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_ff_4 744 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lO011 360 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IOI11 112 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[18] 73 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOO11 73 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[0] 133 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[41] 956 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI0l1[0] 476 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/iioi1[0] 132 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_rs1_rd_valid.m18_2_0 746 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[8] 238 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[26] 468 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/OIoi1[10] 353 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[7] 748 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1[2] 375 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/ioio1[14] 49 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[9] 198 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m11_1_0 704 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2[1] 675 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[22] 728 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[18] 716 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/lo001[0] 189 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[21] 987 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_303 626 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[32] 409 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_resp_ready 825 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4[0] 592 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2[22] 870 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_2[3] 60 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Oil01_RNIC3T3J 144 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850 640 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/l0l01[5] 172 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNIU0S5C[24] 680 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[1] 914 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_0_sqmuxa_1 805 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un7_l1I01_5 405 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[25] 951 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/olIO1[7] 194 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[21] 724 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_1[12] 876 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_713 749 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/rx_cmdsize_4_1_RNO 603 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_0[28] 794 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lii01 80 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[5] 592 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[27] 900 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[18] 451 217
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_valid 501 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[32] 740 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_384 659 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m31_1 157 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_lm_0[1] 376 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[20] 925 189
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[23] 481 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01_0_sqmuxa_i_x2_RNIGOTPC 168 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sresetn_4_i_0 486 255
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/framing_error_RNO 503 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[8] 314 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[29] 709 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_23[0] 364 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_0[1] 840 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/data_0_reg_5_m1_0[22] 837 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[11] 712 136
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/status_byte[1] 567 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[6] 346 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_1[0] 187 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO1Oo_0 221 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[21] 527 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[22] 393 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[22] 445 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[10] 839 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os_RNID148D 783 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[12] 925 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[25] 476 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_2 673 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[7] 41 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[16] 974 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/write_en_0 705 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_m2_1_0_1 776 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[23] 869 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[6] 832 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_834 745 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_flush_i 628 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[8] 305 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[6] 523 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[1] 413 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_965 735 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_shift.rx_bit_cnt_4[0] 522 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_79[11] 365 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un19_i0O11[5] 84 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[1] 637 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2119_1 661 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_valid_ex_2_RNO 697 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int[2] 864 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[18] 864 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[0] 194 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[14] 808 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1199 816 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[25] 685 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_3[0] 103 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[11] 418 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1229 733 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[15] 395 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/un9_IOIOo_1 133 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[9] 209 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[8] 792 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1119 614 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[3] 145 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[1].buff_data[1]_RNIAKDAI[10] 791 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2 39 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNICF984[17] 939 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[3] 712 154
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/un1_data_out_dx_31 607 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[12] 604 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1224 624 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_8 644 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un6_OoI01_2 300 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29_1[2] 340 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/OIil1 385 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_560 770 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[17] 906 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_11[0] 423 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[18] 287 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_retr_d_d_0 820 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic850_RNIERC8F 640 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[21] 917 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[7] 558 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_43 694 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[24] 925 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[12] 607 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1[8] 408 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[24] 972 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_0_0[0] 612 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[13] 905 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[5] 413 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[25] 453 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[12] 522 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[4] 75 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data[0][0] 781 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1[6] 204 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[8] 394 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_0[18] 446 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o0Ol1 442 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_busy_1_sqmuxa_1_0 553 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_3[12] 974 177
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[21] 59 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un21_i0O11_i_a2_0 89 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[3] 182 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1101_2_iv_0_0 107 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[6] 25 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[1] 491 181
set_location CoreAPB3_0_0/CoreAPB3_0_0/iPSELS[0] 596 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv[4] 41 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[5] 230 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IoIi1[12] 258 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[15] 476 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_wr_rd_state_ns_0_a3_0[0] 721 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[20] 278 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_1[11] 384 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[6] 397 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[8] 830 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[2] 351 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1069 747 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram3_[0] 717 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1] 707 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[15] 256 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/lOii1_0_0 146 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oioI1[5] 495 184
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[3] 547 169
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[5] 537 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_29[2] 383 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_0_sqmuxa_0_a2 567 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[31] 875 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[12] 807 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[11] 313 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state7 564 66
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_bit_sel[0] 534 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1_2[6] 462 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[22] 737 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iOll1[12] 532 199
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_state_1_sqmuxa_2_0 626 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_938 684 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[23] 781 124
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNO[1] 15 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/interrupt_could_commit_0 781 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_valid_int_0_sqmuxa 779 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[3] 241 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[9] 735 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[23] 602 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[11] 851 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[3] 728 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[2] 384 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m26_1_0 39 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[2] 376 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un13_lolIo 49 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[20] 747 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[6] 768 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26[17] 851 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[3] 61 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex_RNO[2] 759 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[22] 923 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_1_0[15] 844 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[11] 289 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[6].BUFD_BLK 589 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[3] 547 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un10_o1ii1_3 144 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmcontrol_ndmreset13_4_0_o2_0_RNI620SL1 840 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[4] 322 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ooOOo 140 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[8] 502 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un219_I1Oi1 48 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st_RNO[3] 734 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNI1ORQ8[19] 735 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[15] 411 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[6] 284 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1172 649 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_1 708 228
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg1[5] 489 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/buff_ready_reg 789 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2__RNIU4RO5[14] 679 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_1_0[3] 703 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01_0_sqmuxa_0 168 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err 786 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_21[20] 169 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[6] 181 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[28] 794 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m18 38 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[8] 868 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[4] 238 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_405 783 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt[2] 312 223
set_location fifo_to_tpsram_bridge_0/ram_w_addr[10] 479 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47_2[6] 999 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[4] 328 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[18] 61 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[11] 420 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_N_9_mux_i_2_1 818 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0[7] 149 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[2] 713 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_731 685 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_2_sqmuxa_1_i_a2_4 831 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/IilI1 334 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i0l01[8] 224 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[7] 573 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[3] 336 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[6] 216 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_0[7] 199 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[1] 595 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[24] 683 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[17] 95 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_23[20] 203 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/state_val_14[0] 787 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_en_ex 722 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_637 745 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m16_1_0 159 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[19] 83 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[12] 834 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_736 706 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/lIOo1 335 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115 672 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/buff_wr_strb[0] 788 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3[7] 684 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un6_alu_op_complete_ex_0_RNIE8JK3 798 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[5] 852 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk2.un5_OIiIo 438 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[29] 938 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[64] 833 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_12[0] 536 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a5_2[2] 673 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_2[8] 808 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[34] 609 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[21] 357 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lOio1 86 202
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[6] 463 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_3[12] 793 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111_2 324 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[8] 219 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un3_iiiI1_1_0 462 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[13] 763 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[16] 211 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_656 654 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_lm_0[11] 324 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOlOo[1] 146 178
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[6] 562 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_975 660 216
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[15] 64 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[15] 348 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[18] 868 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o1IOo_RNI4E64A 152 177
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata[7] 589 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_valid_retr 809 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_m3[1] 846 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001_RNO[9] 180 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt[7] 323 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_ii0Oolto2 229 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[8] 870 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/un1_iOI01_1_i_0 269 207
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_0[0] 24 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_bcu_op_sel_iv_1_a8_0_1 648 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[16] 612 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_570 697 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[26] 219 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[8] 537 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_3 387 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_1[24] 462 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/O1OOo 137 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I1lIo_2_0_.m11 62 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/wr_pointer_d_1_sqmuxa_2 617 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[7] 317 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[1] 401 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1149 637 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[26] 329 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_Ilio1_0 85 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a2[1] 746 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0[41] 270 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Io1I1_Z[5] 446 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[20] 816 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[0] 492 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l1O11_0_a2_0_19_10 85 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/ioO01 509 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[35] 828 193
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/cdr_start5_0_a2 16 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a4[3] 672 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_159 717 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_gpr_wr_mux_sel_0_a6_0[0] 674 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a3_2[12] 181 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[28] 474 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_31_RNO_0 855 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/sw_csr_addr[8] 755 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[5] 696 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[4] 412 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data[16] 865 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_s_5_RNO 607 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_2_0[30] 986 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iiOOo 122 172
set_location CFG0_GND_INST 504 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt[2] 336 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[22] 423 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/o0O11_i_o2 83 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_804 735 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_0[27] 276 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[2] 840 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[24] 872 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_Z[29] 796 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0_a2_1[0] 624 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[12] 308 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/IIiO1 266 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m43 162 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_1[5] 142 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1174 757 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[40] 619 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[1] 890 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNI71FGI[1] 570 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_898 744 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/shiftDR_1_sqmuxa 660 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[5] 423 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[34] 467 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[23] 936 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[4] 496 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNIHM8GO[25] 886 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[49] 948 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_5 705 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[21] 450 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[4] 97 193
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_strobe_1_sqmuxa_0 603 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_1[4] 594 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un5_l1ll1_0 464 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt[3] 607 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_4[5] 851 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[21] 462 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr[10] 880 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[20] 883 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[40] 588 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i1I015 360 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_fence 697 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m67 156 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn 837 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt[11] 251 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/loIi1_RNO[5] 259 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_4[29] 352 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[7] 505 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[1] 387 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Ool01[5] 176 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/O00o1_N_3_mux_i 78 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.un1_instruction_19_RNIUJOOA 685 156
set_location fifo_to_tpsram_bridge_0/ram_w_addr[6] 475 256
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[16] 51 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[0] 350 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[26] 720 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[5] 479 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4954 701 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/O0Io1_5[12] 255 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m111 355 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[10] 604 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_558 719 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[20] 596 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txzeros 598 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[22] 865 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[4] 511 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[23] 908 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/empty_rd 697 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[8] 127 205
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_5_2[7] 594 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/tckgo_RNO 629 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0 775 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt[0] 211 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[47] 958 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1 697 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0] 727 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un161_lIlo1lto15_4_RNI1SNO9 316 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[7] 818 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/access_valid_i_o3 745 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/oiIIo[2] 274 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[9] 543 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[12] 282 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[7] 818 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_valid_c_0 794 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKY2[4] 724 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/lliO1_1_iv[1] 130 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[6] 973 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[11] 261 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[56] 840 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_first_3_f0 604 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt[3] 285 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OIIo1_0[3] 419 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo_3 236 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_mnemonic846_9 702 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[16] 279 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_lsu_op_ex_1[0] 742 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0[5] 120 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_23 933 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0iOo[6] 182 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[22] 902 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg[8] 867 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[3] 371 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk2.OOIl1[11] 546 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIN0CS7[3] 899 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[28] 735 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0ii1_2_0_a2_0 141 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_prescale_counter_1.CO1 878 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[16] 333 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state[0] 781 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[25] 453 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_6_RNO 463 192
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[2] 495 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_908 612 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[10] 765 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[24] 900 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1_Z[36] 390 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_11 97 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[11] 784 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lloI1 480 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_req_op_2 743 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_RNO[24] 245 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/oOio1 85 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[2] 146 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_sn_m11 591 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[17] 874 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_26[9] 349 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[15] 815 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I00o1_1_a2_0_0 48 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt_m2[3] 803 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[8] 363 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[21] 273 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/i0oo1 69 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32m.rv32m_dec_gpr_wr_valid 643 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[4] 972 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[9] 335 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/un1_o0IO1[0] 213 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_bcu_op_sel.m4_0_1 681 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ilo11 314 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[27] 606 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_6[11] 291 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[1] 147 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmstatus_allany_havereset 826 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lIoi1[13] 371 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[15] 852 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_lsu_op_retr[0] 803 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_244 690 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[16] 334 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[4] 239 214
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[4] 550 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_gpr_wr_sel_ex[2] 720 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[8] 921 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1165 769 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[1] 854 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stx_async_reset_ok_2 588 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[7] 498 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[3] 624 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce_0[5] 852 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_m1_1_0[26] 987 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_239 697 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[28] 843 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[14] 738 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[6] 444 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9_2[30] 734 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oo0I1 482 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[3] 478 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[5] 252 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[7] 867 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_701 768 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR_8_0_iv_i[4] 672 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[10] 229 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oo1I1[7] 318 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_4_RNO_1 864 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[0] 891 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_291 825 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_core_reset_1 829 168
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[3] 69 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[7] 277 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101_Z[1] 89 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[12] 861 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[8] 589 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_bcu_op_sel_ex_RNI5NIE7 794 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[11] 793 120
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_pktend 608 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_8 749 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[11] 712 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/write_en_RNIHEV46 704 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo[2] 281 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un1_O1Oo1_3 295 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/no_flush_req_os_RNIK26RI 789 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[1].lIII1_44[13] 485 195
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[7] 500 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_607 707 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il101ce[10] 131 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[26] 481 243
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_706 696 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[14] 131 201
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[23] 55 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[3].lIII1_62[29] 469 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_mtx_bitsel_1.CO2 574 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/un105_OOOI1[28] 466 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[60] 647 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oOl01[2] 184 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[15] 556 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/buff_rd_ptr_0_0[0] 735 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/IilI1 281 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oO1Oo_1 237 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[16] 376 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[58] 960 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt[7] 260 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[0] 323 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[1] 241 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1262 636 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[13] 408 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[28] 471 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[7] 263 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_i_m2_1[16] 875 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51_RNIF2FDB1[9] 943 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_lm_0[9] 228 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_1[0] 255 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_193 744 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i[22] 857 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[15] 399 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[8] 900 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[33] 830 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[1] 357 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_byte_en_reg[2] 693 148
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/control2[1] 591 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lOlOo 160 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3_0_5 73 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[0] 326 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I1oi1_0_a2_3 331 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IOIOo 142 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_2[25] 936 159
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELB_LANE[0] 38 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[11] 560 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_completing_ex_1 778 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[10] 119 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[19] 344 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un3_il0i1lto15_4_0 217 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[4] 299 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[38] 238 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/o0iO1_Z[31] 334 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel_1_sqmuxa_3 564 210
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[4] 502 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[12] 406 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_ns_i_0[3] 556 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_2[0] 684 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[6] 453 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[10] 304 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_51 708 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_0[26] 908 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_222 804 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[6] 338 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs1_rd_valid_reg 740 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m41_1 49 177
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state[1] 15 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_RNO[1] 264 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/llio1 96 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[9] 408 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_resp_ready_int 755 136
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int26 768 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0Ii1 247 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un5_Ol0o1[1] 81 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO_0[1] 616 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data[23] 748 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[31] 496 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[21] 689 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_lm_0[1] 246 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_a2_1_a2[15] 129 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/gen_init_term.un11_wr_data 821 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0[24] 800 135
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[24] 476 241
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_0 336 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2_0_m2[4] 708 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[23] 889 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/O1il1[3] 411 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.O0Il1_RNI2FI59[2] 469 213
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UIREG_3 433 6
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[11] 757 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO[8] 704 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O1001[2] 194 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[14] 131 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1[21] 762 120
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC1_stxs_txready 605 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIl11_Z[7] 383 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_330 721 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_9[1] 281 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[9] 410 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oIO11[1] 87 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/cause_excpt_code_excpt[0] 822 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_30[6] 313 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[27] 782 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a2[0] 363 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[31] 166 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2_0_1[2] 840 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_589 759 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[0] 449 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Oii11 355 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[24] 889 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[4] 406 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15] 647 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1776_0 84 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[6] 396 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_RNO[3] 710 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/un12_lolIo 121 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[21] 932 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_resp_rd_data_sig[3] 660 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51_RNIE1FDB1[8] 973 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_wr_req_ff 744 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[28] 405 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[11] 411 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[20] 402 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[3] 610 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/o1o01 76 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo[1] 280 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[8] 409 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[6] 350 207
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[4] 36 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo56_1 74 183
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_1_sqmuxa_5 625 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/ioOOo 126 171
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[17] 481 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un1_next_iab_rd_alignment_0_sqmuxa_i_o2 762 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Ii0I1_Z[10] 537 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_0[3] 181 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[17] 811 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[23] 828 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO_0[0] 254 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m_i_m2[22] 855 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_RNO[6] 817 192
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/tx_byte[1] 540 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[5] 399 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[11] 878 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[3] 891 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_210 672 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/OIo11[9] 303 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2 841 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/I1Ii1[7] 410 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[22] 999 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_12_RNO_1 804 195
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/SPISS[0] 599 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18[18] 392 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o1il1_1[6] 531 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/rd_pointer_q_3[4] 640 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[5] 476 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_962 756 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[42] 572 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[8] 368 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_0[1] 61 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/update_dout 501 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7] 694 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_44[9] 924 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt[9] 315 232
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[16] 896 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[12] 902 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/shifter_unit_places_0[2] 731 159
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_1_sqmuxa_0 596 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[29] 917 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[33] 945 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[5] 229 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[9] 897 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[3] 481 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/un7_ool01[7] 192 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[15] 638 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[2] 590 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[5] 361 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[6] 342 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_135 709 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[7] 234 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[31] 905 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[25] 661 151
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[8] 513 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_debug_exit 828 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0iIo 547 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lliO1[4] 350 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_2[1] 707 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[21] 693 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/i0oi1[1] 144 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iOo_0 221 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[3] 211 204
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/wr_pointer_q_3[2] 567 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0_0[16] 169 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo[7] 157 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[3] 569 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[5] 749 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[3] 182 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/oIlo1[5] 229 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[53] 603 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[15] 250 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/olio1 84 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/precnt[2] 419 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[27] 839 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_sn_N_8_mux_i_i_o2_RNI3OI13 552 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[4] 365 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_4[12] 324 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO_1[2] 382 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_1[21] 889 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un7_liii1 135 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[17] 939 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_lm_0[11] 192 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/rtc_count[8] 636 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/IIIl1 536 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/lO1i1_0[28] 292 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0] 709 136
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[12] 547 181
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_lm_0[9] 39 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[5] 986 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[1] 863 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oO111[1] 233 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux_0[7] 732 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_10[1] 372 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_8 337 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_785 769 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/empty_out_RNICU0A6 610 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_resp_error_sig_N_3L3 827 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un86_OilI1[15] 410 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m28 403 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/sticky[0] 569 202
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[8] 501 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[25] 872 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_31[0] 361 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iil01[0] 162 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[1] 847 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNIDJM4C[7] 711 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[3] 57 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IloI1_Z[2] 516 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][12] 904 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un5_IOoi1_4 384 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[10] 128 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/lsu_op_ex_pipe_reg[0] 762 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_651 648 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[7] 154 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[8] 783 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIEH984[19] 923 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[4] 721 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_692 648 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[11] 728 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/i0Oo1[2] 279 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[8] 775 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1_2[33] 399 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_597 638 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[20] 965 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[14] 361 234
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_0[3] 712 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[32] 478 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_1 733 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[31] 835 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un331_lIlo1_2 320 195
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel_2_sqmuxa 47 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[14] 913 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[31] 867 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_209 624 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_1[3] 381 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[12] 974 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[5] 372 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/gen_bit_reset.state_val_RNO[0] 874 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[0] 302 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[10] 290 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_oI1I18_1 459 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk3.un31_Oi1O1[26] 469 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout[4] 477 247
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[4] 412 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[11] 423 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[5] 895 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_11 672 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_datahold_0_sqmuxa_3 561 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[29] 937 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[20] 797 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_1[2] 731 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo[6] 276 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oli01_0_a3_0[0] 73 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_62[0] 960 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_6[0] 60 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[8] 349 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[2] 454 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3_1[12] 102 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[36] 948 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIOI1_1[28] 374 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[4] 300 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_O1I019_1 300 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[4] 95 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_1_5 788 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1_35[1] 468 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[33] 476 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_688 619 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2_2[0] 819 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[8] 42 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[22] 253 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_5[8] 305 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[0] 126 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[10] 935 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[14] 237 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_257 691 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1I1[10] 560 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lilIo53 73 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un36_Ioli0_0_a2_3_a2_RNI9FUT5 317 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[8] 396 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[10] 248 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2127_0 648 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/div_divisor[48] 951 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_813 687 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un17_iIlo1lto10_fc_1 265 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[8] 236 196
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_0_sqmuxa_1 575 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1_0 333 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[21] 235 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1_11[24] 447 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_RNO[10] 319 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[11] 798 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[16] 793 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[23] 703 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[26] 676 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/sel_early[1] 737 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/gnt_0_tz[0] 765 153
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io[15] 48 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[30] 674 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[23] 865 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_16_RNO_0 835 195
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[19].BUFD_BLK 589 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m28 37 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo[0] 284 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[15] 104 187
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[2] 459 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_218 637 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[22] 640 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_89 648 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_a2_0[1] 791 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oOI11_0_a3 139 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_972 763 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a2_0[8] 800 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un20_oI0i1_3_RNI81TOD 234 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[6] 156 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m154 383 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I1OIo 225 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_a2_1[1] 84 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_56 709 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_0[17] 767 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m15 252 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[23] 550 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[24] 468 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[35] 940 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_RNI95I4J[11] 528 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/o0001[3] 191 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_gray_ptr_in_write[1] 700 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[10] 394 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[26] 998 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_300 661 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[7] 852 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_fence_os[0] 829 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[3] 370 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/IOII1[10] 428 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[3] 303 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Ol0i1_0_0_a3_2 264 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I1l01[4] 201 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_i_req_valid_3 781 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[7] 456 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames[1] 610 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0[2] 683 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a2_77[11] 336 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_6[12] 288 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1[9] 227 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1180 768 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un3_IioOo 217 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rcv_sm.rx_state18_NE_i 519 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_20[8] 324 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_852 731 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[10] 511 249
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[7] 370 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[14] 289 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/un1_Ill01_40_1.SUM_0_o4_1[3] 167 201
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[1] 566 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_RNO[2] 303 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[15] 314 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/state_val_17[25] 845 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_sel_reg[5] 731 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/llIo1_2_f0 289 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10] 692 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_10[0] 316 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[5] 80 190
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_RNO[3] 618 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_0_a2_1[1] 672 156
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/receive_full_int_1_sqmuxa_i 504 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_lm_0[10] 360 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_3[27] 174 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_3[18] 547 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[0] 474 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[5] 345 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[8] 277 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[30] 724 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_o0iIo 465 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iI011[9] 376 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[0] 924 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[13] 414 211
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_2_sqmuxa_1 36 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_apb_0_a2_0_4 779 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_access_valid_0_a3[0] 744 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/paddr[23] 815 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2121.rv32c_dec_mnemonic2121_RNIQQOP41 714 156
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel_19_iv_4[5] 44 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24[4] 388 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 523 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt[16] 262 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IIII1[3] 513 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][28] 879 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO0l1_3[2] 527 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[3] 386 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/i1o01 80 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_lm_0[10] 427 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[5] 426 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Ooll1 482 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_14[22] 348 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[11] 324 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1_RNIJ52R7[0] 109 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1099 625 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/iOOo1 325 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/ol001[1] 190 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_3[5] 960 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[15] 793 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_13[10] 276 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/iIo11_iv[26] 276 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O1l01[1] 188 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1019 698 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_lm_0[8] 276 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[25] 567 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_gpr_ex_attbs_rd_ex.gen_debug_gpr_rd_sel_pipeline.de_ex_pipe_gpr_rs2_rd_sel_ex_2_0_0[2] 697 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[16] 934 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[14] 284 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/subsys_cfg_d_req_valid_0_a2_1 777 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[24] 945 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m15_1_0 36 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_7[2] 200 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[12] 95 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.tdata1_sw_rd_sel_2_0 813 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_lm_0[0] 239 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_105 734 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_40[5] 314 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_Z[27] 743 136
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_bitcnt[4] 602 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[9] 343 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[8] 202 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_addr[24] 818 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4960_5 706 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex_2[25] 868 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_8 731 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un7_IOoi1_2 389 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_operand_3[11] 923 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/un1_Ioli0_1_0 366 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un10_l1ll1_6 429 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[23] 74 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[1].req_buff_resp_fault[1][2] 775 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[31] 908 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Iolo1[21] 394 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[1] 510 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[30] 746 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[3] 87 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/next_state21_a1 783 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[23] 328 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iiOIo_1 223 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1[19] 716 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[15] 307 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un11_I10i1lto15_5 225 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[1] 542 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o1l01_0_sqmuxa_0_a5_1 163 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[23].BUFD_BLK 588 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[18] 588 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[17] 938 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/I1O11_0_o2 119 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[17] 899 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_41[1] 348 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_l1I01_0 391 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg_10_iv_0[8] 612 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_148 744 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1087 747 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gpr_rs2_rd_data_valid_7_0 730 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1051 693 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un11_i0lo1[7] 348 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un24_cpu_i_req_is_apb_19_8 809 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[25] 721 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[13] 736 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/i_access_misalign_error_retr 751 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[3] 76 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/iOo01_i_a2_0_0 113 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oIoI1_1[9] 403 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo[8] 162 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[5] 417 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oO1l1_u_2_0 468 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_error 804 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_0[2] 109 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.l1Oi1[3] 72 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/oIo11_0_a2_0_x4[7] 198 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dtm_req_data[7] 705 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/lIlIo_RNO 269 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[7] 205 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_dmactive 823 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[53] 632 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/full_out_RNO 610 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lOoI1 414 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.debug_active_retr5 784 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4958_7 684 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_369 696 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[5] 824 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[11] 375 226
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/un10_buff_resp_head_compressed_RNIF0SPP 715 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[10] 857 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l0OI1_Z[3] 443 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[15] 117 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_RNI8DL4C[0] 703 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_tcm0_2_0 868 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[15] 283 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[23] 974 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[28] 786 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ilo01_0 113 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_11[27] 960 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_3_0[2] 216 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_780 732 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[31] 912 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_0[14] 728 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_4[1] 790 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un314_lIlo1lto15_3_0_4 256 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un12_I1Oi1_2 40 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[5] 210 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1251 648 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/command_reg_state_4_i_o2[3] 852 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/i11Io_5[4] 479 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0] 483 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/operand1_mux_sel_1_iv_RNO[0] 798 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_6[29] 326 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[1] 707 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_0_1[15] 137 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un111_I1Oi1_2_0 46 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO0018 181 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0_RNO[26] 824 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_552 782 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[30] 648 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/un1_iOI01_1_i_0 274 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[7] 149 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_sw_csr_rd_op_cnst_1 700 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[19] 390 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_0[6] 129 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12] 680 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ili01_RNI42K8A_0 96 183
set_location fifo_to_tpsram_bridge_0/ram_w_addr[7] 476 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/T_l_En_0_a2 606 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Iol11_Z[3] 417 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oo101_RNO 108 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG3_16 727 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_10[8] 252 213
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw_36[2] 552 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Iiio1_0_a3 72 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un51_I1Oi1_2 48 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_u[26] 972 168
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/fine_sel[0] 29 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_16 704 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[2] 877 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_27[8] 337 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un9_IlIi1 295 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_shifter_unit_op_sel_ex_1[0] 764 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[5] 430 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ol0o1[2] 73 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1121 768 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[8] 272 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4953_5 680 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[43] 563 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[23] 238 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I0io1_4[0] 96 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[8] 314 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[20].BUFD_BLK 624 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[21] 891 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[2] 540 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_wr_ptr[0] 634 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_lm_0[2] 373 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/lI0i1_0_a3 318 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[11] 854 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/un1_Ioli0_1_0_0 391 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un18_OilI1_0_a2_0 350 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/lll01[7] 212 199
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/dout_4[12] 505 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_10_0_RNO 841 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0_i_m3[31] 563 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O1io1 70 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_de_ex.de_ex_pipe_curr_pc_ex[26] 767 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0OIo 225 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[4] 198 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_1 803 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/un1_Ioli0_1_0 319 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_768 673 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_810 624 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1_RNIQPJ3N 764 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un4_l1I01 373 171
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/coarse_sel_RNO[0] 34 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_txzeros_4_f0 598 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[20] 972 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[0].lIII1[3] 470 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un4_IlIi1_3 240 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[24] 752 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[5] 272 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[12] 228 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/csr_reg_rd_sel.dcsr_debugger_rd_sel_10 824 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[17] 843 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[4] 742 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_25[10] 363 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt[1] 358 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/OlI11[17] 94 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_a9_4_1_RNIO0MNI 613 111
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_2[12] 897 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/next_buff_valid[1] 814 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[2] 888 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_78[18] 997 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_addr_req[0][3] 886 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/sticky_reset_reg 792 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNO[28] 888 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[18] 999 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[5] 100 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_I1oo1_1_tz_1 88 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[32] 321 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[7] 91 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_1 797 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/IIoI1_Z[2] 388 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[30] 996 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_156 636 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[12] 415 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_29[11] 348 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_d_req_wr_byte_en[2] 708 150
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.O01Io_RNIMTGD1 59 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[16] 662 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_47 637 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1049 708 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_20[9] 402 192
set_location fifo_to_tpsram_bridge_0/un1_fifo_data_out_1_22 480 252
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[48] 956 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[27] 925 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/ex_retr_pipe_fence_i_retr_2_RNI3S88F 829 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[12] 450 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[1] 670 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[12] 395 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un5_oIIi1 241 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/oo0i1 258 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNIDG984[18] 855 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/un3_rs2_rd_hzd_2 742 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_RNO[2] 332 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Oolo1[4] 388 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/oo1Io_1 433 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient[24] 898 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[14] 784 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg_state[2] 848 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_1[1] 237 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1_RNI76ICHS1 794 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8] 686 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lol11_Z[3] 427 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/llli1_RNO_2 300 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1l11_Z[0] 230 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_gpr_rs1_rd_sel_0_iv_0_tz[3] 689 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result195_2_3_0_RNI6IDNHB 805 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iI1l1[2].lIII1_53[19] 472 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[21] 604 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/ex_retr_pipe_curr_instr_enc_retr[0] 776 148
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/oIl11_Z[5] 297 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[0] 211 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/oIo11_7_0_a2_1[8] 276 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_723 764 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[7] 320 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[9] 368 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[0] 459 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[27] 315 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[7] 267 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I11o1_i_o2_0[0] 102 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_137 806 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_addr_int_16_iv_0_m2[16] 813 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[32] 401 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[12] 131 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15[21] 991 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[16] 888 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_a12_6 746 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI1Oo_RNO 208 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_RNO[1] 251 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/gen_bit_reset.state_val[0] 873 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/oO001_Z[1] 187 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[8] 386 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_60_u[0] 972 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_867 720 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/lO1I1[4] 536 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][3] 895 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIoOo_RNO 220 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/O1Oi1[10] 43 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[10] 385 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_379 660 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0__RNITLTQ8[26] 808 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2_0_0_0[6] 231 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_31_RNI2SGCO 802 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m15_2_0 14 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/i00i1_i_a2_0_0[14] 223 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mscratch_rd_data[8] 929 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[11] 837 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[49] 830 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_O1oOo[1] 245 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[27] 466 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[5] 556 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[27] 405 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[6] 859 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/o1Ol1_3_0_1 439 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[0] 602 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un9_Ol0O1_RNIB5FGI[3] 412 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1[31] 942 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1259 672 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[41] 822 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_wr_rd_state_ns_0[0] 786 147
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[20] 501 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[17] 948 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1254 624 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/un1_spi_clk_count18_3 560 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[11].BUFD_BLK 565 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_734 661 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[2] 433 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.l0i11_ns_0_a2[19] 226 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0] 317 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a4_0_1[0] 60 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[8] 779 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2123.rv32c_dec_mnemonic2123_1 648 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1_4[0] 263 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate_13_m_1[6] 691 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/un1_lilIo56_2 72 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_mnemonic2121.rv32c_dec_mnemonic2121 684 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_iv_0_a2_1[2] 744 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata[1] 589 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1195 769 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/iIOI1 368 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m64_0 290 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[4] 871 139
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[15] 563 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/IilI1_RNO 353 198
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[13] 603 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_12 797 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[21] 694 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1115 636 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[5] 862 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/IOo01_Z[9] 122 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.OI1O1[29] 501 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un50_OilI1[14] 383 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[19] 491 250
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[3] 226 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/I1Oi1[1] 37 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un16_cpu_i_req_is_apb_23_1 792 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[21] 949 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oII11 137 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/OIl01[2] 146 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m4 158 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[6] 210 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0] 524 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[19] 888 144
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[7] 488 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[8] 359 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111 324 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Oi1l1[8] 548 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r[8] 465 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_buff_fence_os_1[0] 828 147
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_a9_2 600 114
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff_9_0_iv_0[9] 735 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m8_1_0 48 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_778 781 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[5] 215 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[21] 517 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO[0] 830 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1267 697 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[34] 261 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/I0l01[7] 188 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/cpu_d_req_addr_sel[11] 728 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[57] 636 175
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count[2] 605 121
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[12] 892 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[21] 404 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_a2_0[24] 722 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[0] 193 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[8] 649 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_lm_0[4] 288 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNI6QHQ6[8] 698 132
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io[9] 45 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[1] 144 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a3_2[2] 845 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_4[17] 406 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1292 713 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1189 660 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt[4] 331 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/O11I1_Z[0] 425 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/un1_Ioli0_1_0 346 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[11] 415 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/dmcontrol_resumereq 822 124
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_916 660 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[16] 663 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1212 684 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/raddr_mux_loop_l1.un10_req_wr_data_mux[25] 764 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[55] 623 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[4] 410 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Ioli0_i[21] 394 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[1] 289 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/o0I01_3[3] 301 198
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[32].BUFD_BLK 637 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_addr_req[2][1] 883 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/iIo11_iv_0_x2_0[22] 180 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_d[0]_0_sqmuxa 553 192
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_10_RNI818323 25 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un5_llOo1_1 335 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_lm_0[8] 228 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[7] 443 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_7[23] 455 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0OIo_0_a2 227 177
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/p_CtrlReg1Seq.controlReg15 514 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[10] 782 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[4] 155 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[29] 835 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[9] 786 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m231 359 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IOoi1_4 398 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_RNO[0] 94 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[48] 617 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1[19] 524 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_1[6] 864 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[30] 328 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[31] 725 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_i_0_0[3] 135 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[7] 888 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O10i1_RNO[14] 220 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1Ii1[6] 415 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1311 687 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_969 768 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_head_addr_1[5] 883 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0__RNI944LE[1] 780 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_3[2] 698 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m24_1_0 170 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5[22] 829 126
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/start_cnt[0] 13 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/io1l1[2] 542 193
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB 1155 162
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[0] 263 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[21] 551 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/dmi_outputs_and_dtmcs_resets.dtmcs_resets_active_low.dtmcs_dmireset 688 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_24[10] 399 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_lm_0[6] 346 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/iiOI1_2 408 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val[11] 842 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[18] 938 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_lm_0[0] 266 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_633 733 174
set_location COREFIFO_C0_0/COREFIFO_C0_0/RDATA_r[21] 503 247
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_csr_ctrl_pipeline.ex_retr_pipe_sw_csr_addr_retr_2[1] 739 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/cpu_d_req_wr_data_reg_9[8] 729 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_877 752 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/reg_write.tx_hold_reg4_0_0 513 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_15_1[25] 957 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[1] 212 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[1] 670 133
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_30[18] 998 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[7] 663 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[1] 333 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[4] 184 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_22 685 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0oOo_RNO[0] 241 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/I11I1[6] 498 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0_2[29] 857 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[26] 249 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/precnt_6_5_188_a2 260 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[15] 301 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i1il1 508 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[6] 361 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_640 744 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_45 636 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/un10_oiIIo_1_ac0_1 275 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[37] 390 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/un1_cfg_ssel_1_sqmuxa_2_1 612 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[0] 329 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un1_i0I01_1_0_0 320 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[6] 778 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[25] 748 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un1_soft_reset_taken_retr_s_s 814 144
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_q[0] 600 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oi1Oo 223 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.llIl1[21] 461 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_448 714 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[2] 800 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/un12_lOII1[29] 401 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/req_resp_addr_align[0] 765 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_rv32c_dec_mnemonic2112_2_1 670 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4959_8 689 171
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UDRUPD 434 6
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[0] 439 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_sel_1_iv_0[1] 716 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[20] 754 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[25] 378 199
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.baud_cntr[9] 490 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un4_l00o1_3 38 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[9] 302 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_8[2] 255 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_byte_en_int_13_m2_2[3] 777 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/O00o1[3] 116 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[13] 124 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_27[3] 368 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/IIoi1_11 363 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1_8[29] 456 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l1ii1[13] 108 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/IIii1[0] 186 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_107 720 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[9] 675 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1_RNI8CA84[22] 880 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/o0OOo[5] 121 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[25] 912 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Oo1I1_Z[3] 415 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o1li1[3] 354 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_950 720 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/lIi11 445 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_0[6] 49 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.OI1i0[9] 47 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/io0i1_0_a3_0_0 319 171
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_2_sqmuxa_i 606 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_6_m[26] 925 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[2] 318 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_sbcs_busy_ff13 748 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[14] 482 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[13] 935 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[3] 779 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.un1_oIiOo_0[3] 276 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[9] 922 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0]_3[2] 741 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1145 696 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter[6] 894 133
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_10_RNIHL8GT 24 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[6] 123 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_wr_data_reg[19] 734 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[16] 708 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un12_valid_sba_0_o2 818 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_lm_0[1] 358 207
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/controlReg2[1] 485 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2[1] 217 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[27] 873 157
set_location CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/PRDATA_0_iv_0_cZ[5] 568 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/data_rd[31] 727 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Olo01_0 110 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[11] 887 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[35] 614 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Iol01[2] 194 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[13] 762 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_27_RNO_1 859 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[25] 787 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[6] 750 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n4 312 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[6] 775 124
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_Ol1I18 459 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_13[1] 277 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state[0][0] 762 145
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a2_4[4] 180 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1]_RNINQ6GO[19] 867 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un3_instr_inhibit_ex_4 753 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[11] 318 235
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/int_raw[0] 574 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/i0011_Z[5] 279 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[10] 862 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un34_l1I01 372 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_454 674 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/utimeh_rd_data[31] 833 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/gen_bit_reset.state_val[22] 847 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Ii101_Z[14] 106 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/exu_result_mux_sel_1_iv_RNO[0] 723 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_704 731 189
set_location Core_reset_pf_0/Core_reset_pf_0/dff_12[0] 846 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_816 733 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/IIoO1[13] 124 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_51[8] 941 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[27] 870 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_sw_csr_addr_ex[7] 746 169
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_1[5] 774 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt[3] 271 214
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/parity_err 517 160
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_lm_0[6] 302 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_o12_4 734 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_gpr_reg[13] 917 178
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/iPRDATA[0] 486 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/l11o1_RNO[1] 88 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[19] 522 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_0[4] 711 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1242 613 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_ba_err_0_sqmuxa_2 792 117
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[6] 63 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OIO11 94 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_debug.set_step_debug_enter_pending_0 760 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_18 934 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_csr_rd_en 863 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3_56 864 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_4_2[1] 588 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[23] 738 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1[2] 145 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/IilI1_RNO 297 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_466 636 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[1].buff_valid[1] 742 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4952_5 672 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/un1_cpu_d_req_ready_sig_d_0 769 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/state_val_24[8] 838 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il1o1_0_a2_0_1 91 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/genblk3.shift_active_high.shift_active_low.shiftDR_ne_0_3 655 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/prdata_reg[25] 633 181
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/middle_dout[17] 484 250
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_mux_sel_iv_RNO[1] 728 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/IOOi1_RNO_6 79 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1oO1[0] 238 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_28[3] 268 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count_RNO_5[1] 824 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m202 354 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[9] 546 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][21] 872 154
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[3] 513 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_0[10] 397 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/iab_resp_complete_1_1_0 703 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[4] 372 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lioOo[10] 223 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[7] 212 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OllOo[5] 120 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo_5 37 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[18] 758 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_979 756 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/csr_rd_illegal_i_m2 741 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/il0o1[7] 72 190
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count[7] 596 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[14] 768 160
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend[23] 890 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_10 628 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[8] 320 207
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state137_RNI7PQT9 624 114
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/o10l1_3[6] 462 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[19] 834 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data[0][5] 787 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_o2[1] 817 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/llii1[11] 151 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_1 809 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_4[4] 851 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr[1] 718 154
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[4] 588 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory_ram0_[11] 725 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/un5_ioIO1_NE 181 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_215 696 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ooOi1_RNO 236 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[19] 391 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.i1Oi1[19] 80 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0_a3_1_1[0] 816 120
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0[3] 704 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/OII11_Z[5] 142 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5_1[59] 951 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_284 775 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un1_OilI1[7] 358 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[22] 548 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_lsu_op_0_a4[1] 672 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_drop[0] 757 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_IIiO1_1 308 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lOO11_0[8] 106 180
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r_fwft[9] 511 256
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtimecmp[26] 605 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[3] 336 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl018_0_a5 163 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/precnt[22] 280 205
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_2_c2 19 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/l1iIo 573 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt[2] 839 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[11] 232 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[26] 391 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_lm_0[3] 273 222
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_cnt[3] 16 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[9] 318 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_ff_4_0[2] 838 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/iioo1_RNIO9H6E 138 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01[8] 227 201
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[26] 474 240
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/O1li1 335 172
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk3.sc_r6_i_x2 500 249
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_0 726 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OIiOo[3] 312 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/oooi1 136 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[28] 902 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IiOIo 231 187
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO_2 654 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_132 757 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_491 661 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[6] 340 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rd_rs3_complete_ex_s_RNI8URB86 773 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/un1_iOI01_1_i_0 315 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[18] 203 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_792 780 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_uar_err_ff_6_iv_i 764 132
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/rd_pointer_q[1] 610 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/gen_bit_reset.state_val_37_0[7] 920 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_1_iv_0_a7[4] 150 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[5] 42 205
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNI6NV62[0] 469 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[36] 467 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_3_m[2] 697 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_2[14] 559 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3[10] 872 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_debug_gpr_ctrl_pipeline.ex_retr_pipe_gpr_wr_sel_retr_2[5] 713 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un35_I1Oi1_1 38 186
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_0_22_i_4 635 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[2] 856 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/IIoO1[1] 239 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/CoreAPB3_0_0_APBmslave2_PRDATA_m_cZ[8] 535 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_state[3] 823 127
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un123_I1Oi1_2 36 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt[1] 319 202
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_q_1.CO0 613 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[4].BUFD_BLK 600 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[8] 151 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/II0i1[7] 291 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_531 756 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/OiO11_Z[1] 122 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_lm_0[6] 288 204
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/loli0_1_0_a2_0[24] 351 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_m8_0_a3_0_2_a0_0 834 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_lm_0[11] 322 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff[26] 803 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_2[3] 790 138
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_1_sqmuxa 879 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_curr_instr_enc_ex[6] 778 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt[3] 338 238
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1[3] 152 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_603 673 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_0[10] 565 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/ioI11 316 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_6[12] 404 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[8] 266 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_35[18] 984 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[4] 752 142
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[13] 550 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[0] 464 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_2_a3 811 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[13] 795 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.IloIo 233 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_634 696 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[15] 563 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_lm_0[8] 240 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un1_OoiOo_1[7] 231 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[1] 697 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.pwdata[21] 694 148
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_re 552 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1[0] 78 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/O1I01_RNIOEBO8[0] 309 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/IilIo 119 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val[13] 852 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_12[1] 325 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxp_frames_4[1] 610 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/ll0i1[9] 239 172
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/genblk1.un67_o1Oi1[4] 48 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11[15] 96 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[6] 927 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt[13] 259 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[14] 543 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/fence_0_2 725 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1[3] 452 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[13] 501 214
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/CFG2_BLKX2[3] 724 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[11] 313 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[4] 431 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/I00o1[2] 49 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[23] 936 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_completing_retr_3_0 799 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/debug_state_ns_0[1] 824 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/req_buffer_reg_sel_i_o2_0[1] 784 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_i_req_is_tcm0_4_2_sx 802 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_completing_ex_a1_2 757 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_0_m3[1] 750 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/o01I1_1[18] 459 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1003 805 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/oll01[8] 204 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_lm_0[2] 312 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[46] 824 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/last_iab_rd_alignment 827 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_1[0] 456 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/lo1I1_Z[4] 315 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[57] 844 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[17] 94 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_emi_req_rd_byte_en_2[1] 696 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_0[30] 885 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_1[21] 864 186
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.iI1Io[17] 64 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_26_m[17] 821 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/lioIo_0[8] 158 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_937 720 225
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/UTDO 609 115
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/alloc_resp_qual 803 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_o2_3[15] 709 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand0_valid_u_RNIF99UVE 800 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_2[9] 131 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[1] 453 201
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/un1_NxtPrdata23_0 509 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_11 672 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_24[3] 390 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/ooOo1[1] 347 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/loiO1[15] 282 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2115_RNIMTARA 694 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1__RNI03S5C[25] 682 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[10] 986 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/req_addr_mux[31] 812 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk1.un2_o1ol1_0 310 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/apb_d_req_valid_3_0 785 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_476 648 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Ol0O1_3[24] 400 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[31] 881 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/genblk3.IoIl1[0] 488 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_i_3_0_RNIDP5VF[15] 673 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[24] 851 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un1_wr_pointer_q_1.CO2 618 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Io0i1_RNO_0 278 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[61] 641 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[9] 574 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/i1Il1_RNO[12] 506 201
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[12].BUFD_BLK 564 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1303 612 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI[35] 726 127
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96[20] 986 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[26] 908 157
set_location Core_reset_pf_0/Core_reset_pf_0/dff_8[0] 844 70
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[29] 736 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_28 664 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Olli1[2] 303 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_o01O1_1.BNC1 489 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_1 417 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_0[9] 199 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/un3_OilI1_i 399 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[2] 486 220
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/cpu_d_req_addr_reg[5] 737 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/I0oi1[9] 329 166
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un1_o1ll1_16 317 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11[10] 77 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/command_reg[3] 750 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8_2[18] 668 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1_RNO[4] 214 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un1_o01O1 492 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/gen_bit_reset.state_val_22_0[2] 817 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[3] 897 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0[2] 186 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[6] 820 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_3[9] 455 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[23] 450 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data[0][9] 784 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_m[10] 443 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/gen_bit_no_reset.state_val[22] 854 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/o0iO1[19] 281 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[21] 674 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_71 672 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[17] 927 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[25] 926 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m51_2_1_1 38 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt[8] 307 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_220 733 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_tcm0_i_decode.un8_cpu_i_req_is_tcm0lto18_10_RNIRSJ9QO3 793 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/iiI11[1] 370 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/ram_init_soft_debug_reset 813 156
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un2_l01Io_21 61 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[34] 608 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_a2[2] 841 135
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_22[4] 324 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[13] 691 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_27_2 667 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[10] 83 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_sel_1_iv_0[2] 719 168
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_bitsel[0] 575 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][29] 887 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[22] 393 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[22] 900 147
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_6[23] 793 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[8] 411 205
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag[0] 31 217
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/immediate_0[2] 836 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_14_0[31] 948 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data_ram0_[4] 785 154
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/un1_dmi_req_command_0_a3_RNIANK9D 774 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_19_0_RNO 871 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[19] 60 204
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UIREG_7 432 3
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result193_a0_3_1 744 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[2] 658 130
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_5[7] 404 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr_2[1] 843 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/gen_bit_reset.state_val_33[18] 862 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l10l1_2[5] 490 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt[11] 282 208
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/iIiOo[2] 283 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[3] 336 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[17] 686 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/un19_l1I01_1 380 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_432 708 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_lm_0[0] 279 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/machine_implicit_wr_mtval_tval_wr_data_m2[12] 848 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/lioo1[0] 95 192
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata_cZ[3] 598 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_5[20] 900 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/ll111 106 175
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_pktsel 610 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/o0lo1_0_a3[4] 313 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/iIl01[4] 245 181
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state_0_sqmuxa_RNIEDGGK 612 111
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_O00i1_4 216 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/resp_count_Z[1] 816 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_1[3] 912 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_32[1] 299 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_ptr_RNI5NJ77[0] 697 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/gen_m3_2 794 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv[26] 882 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt[13] 212 220
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m180 338 180
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/CLK_DIV[2] 590 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0_2[5] 563 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/pwdata_8[26] 657 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[26] 842 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[19] 687 133
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i1OI1[9] 559 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/alloc_req_buff_1_1_0 778 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un61_I0i11_1.un33_i_a2_4[2] 216 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_3[12] 36 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_valid[0] 739 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_immediate_ex[21] 826 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/debug_op_wr_data[23] 921 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un1_instruction_12 764 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/un1_iOI01_1_0_a3_i 380 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/lOII1[27] 402 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt[8] 365 235
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[16] 696 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/iiIl1[11] 552 184
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[0].BUFD_BLK 564 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/O01l1[0] 431 202
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt[8] 392 226
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OoiOo[3] 233 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IllOo_0_0_a3[4] 162 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32c.rv32c_dec_mnemonic2123_1 662 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1oi1[4] 155 175
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt[11] 290 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_17[20] 189 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_0[1] 842 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotientce[6] 867 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_2[17] 840 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/de_ex_pipe_alu_op_sel_ex[3] 763 157
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_resp_valid41 821 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[33] 251 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_11[6] 199 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/wr_ptr_RNI6QHQ6[0] 703 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Oiio1_Z[11] 78 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic4920_1 677 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[15] 592 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[6] 541 187
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC2_msrxp_pktsel_RNIB5HSE 607 189
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/state[0] 617 115
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_102 724 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/il0Oo 215 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/instr_is_lsu_ldstr_ex_0_0_RNICTBGR72 777 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1225 723 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/i1l01[5] 181 211
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt[9] 312 208
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/debug_sysbus_resp_rd_data_0[2] 704 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_2_0[20] 877 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[15] 900 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Ioo01 109 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_result_reg_int[32] 833 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/cmderr_cmb_0_sqmuxa_2_i_a2_0_0_2 817 123
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[12].BUFD_BLK 624 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/O1OI1_Z[10] 549 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/oIll1 461 181
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/mtvec_rd_data[30] 792 138
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_21[5] 373 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_17[17] 416 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/csr_op_wr_data_1_cZ[26] 886 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un31_oIiOo_1.I0iOo[0] 188 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt[0] 384 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo_RNIAJD3M[0] 228 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_501 653 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.olIl1[17] 456 217
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[4] 621 208
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/clk_div_val_reg[3] 596 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/gen_req_buff_loop[0].req_buff_resp_state_valid[0] 773 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_exu_result_reg_int_4[61] 837 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_13[1] 317 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[7] 750 139
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[13] 496 214
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i1ol1[22] 381 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01_1[10] 120 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_848 675 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_6 672 141
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/bufd_gen[29].BUFD_BLK 636 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/prdata_7_2[25] 615 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[10] 265 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0[25] 740 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_27[11] 360 213
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/NxtPrdata_5_1[7] 486 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_604 732 222
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[10].BUFD_BLK 588 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat13 685 129
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OooOo[2] 235 196
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/O0001[2] 194 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/o0il1_8_0_1[1] 412 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_1[26] 690 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_42[0] 370 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_3[7] 828 132
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32c_dec_immediate[3] 665 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOiOo[2] 282 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_9[8] 190 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/dividend[11] 924 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/oloI1_1[15] 399 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/next_req_is_hword_high_only_u 878 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_rd_req_cmb_f0_RNO 768 117
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[20] 516 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/un7_gpr_rd_rs3_completing_ex_0_RNI7RKA6 782 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/l0Io1_Z[27] 242 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_alu_op_sel_4_.m8_e_1_0 665 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un2_lIo01_i_0_a2 92 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/irq_sw_enable 790 141
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_lm_0[8] 203 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/oii11 344 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/l0i11[8] 233 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_823 648 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/l0oOo_RNO[1] 262 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_12[6] 201 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/gen_bit_reset.state_val[14] 862 145
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/req_addr_mux_3_cZ[2] 762 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[13] 655 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_2[18] 441 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/valid_out 810 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/apb_prdata_net[25] 633 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt[11] 366 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/genblk4.iO1O1[15] 556 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_valid_6_i_a2_0_2 823 144
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/gen_bit_reset.state_val_12_u[0] 804 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/I1II1[3] 363 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01[0] 73 166
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/rv32i_dec_exu_result_mux_sel_0[0] 633 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_60 696 219
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/count_19_iv_63_i_a9 619 117
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/de_ex_pipe_shifter_unit_op_sel_ex7 768 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_lm_0[11] 396 222
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_23[5] 328 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_907 684 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/un3_mtvec_warl_wr_en_8[0] 834 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1130 672 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_228 714 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/i0il1[7] 419 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_358 780 213
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_266 636 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/oI0i1 212 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_rs2_rd_valid_dbgpipe_0_RNO 762 147
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag[0] 12 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_331 745 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk3.i0ol1[2] 433 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places_valid_0_0 849 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_336 756 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_lm_0[59] 635 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loOo1_0[5] 345 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[3] 239 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/N_247_i 357 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/rd_ptr[0] 697 127
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO[2] 552 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_div_divisor_5[16] 948 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/oolIo_i_a2_6[0] 108 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[8] 206 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/O1Oo1[0] 280 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/cpu_d_req_is_subsys_cfg_0_a2 775 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/un5_Ol0O1[17] 574 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_RNIASLDF[4] 444 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/l01I1 460 202
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/gen_buff_loop[0].buff_valid[0] 796 151
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IIiOo[3] 312 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/IlIo1 277 196
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR2_16 780 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_shifter_places[0] 918 165
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_3 529 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/l0O11_RNO[1] 77 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O1iO1_Z[17] 276 190
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/sc_r[0] 493 253
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIIC98E[25] 670 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_851 748 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11[10] 198 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_Z[31] 595 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Il0i1[9] 239 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/oIoi1[6] 360 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_0[2] 435 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un24_lsu_emi_req_rd_byte_en 841 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Oi1O1_1[24] 475 174
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_state_RNO[4] 555 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_96_2[31] 934 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt[1] 300 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.ramout_1[15] 647 180
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/tx_hold_reg[0] 551 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_lm_0[8] 384 231
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp[16] 884 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_lm_0[6] 391 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/IiO11_Z[7] 126 178
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_46_u[2] 997 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ooi01[8] 98 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/un1_Ioli0_1 321 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_0[26] 694 186
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/cfg_ssel[3] 596 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_460 636 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.un3_branch_cond_ex[0] 761 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data[3] 828 141
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_31[6] 998 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/un5_l0iIo 433 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/OIo11_RNO[7] 172 171
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state[2] 539 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt[2] 421 223
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt[8] 401 223
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/debug_csr_op_rd_data_0[16] 836 147
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/O0l01[4] 204 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO0l1_1[3] 490 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[13] 914 178
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/l1oO1_0_tz 288 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un1_OIio1_0 84 198
set_location COREFIFO_C0_0/COREFIFO_C0_0/int_MEMRD_fwft_1[23] 482 246
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/li101_Z[1] 116 184
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/bcu_op_completing_ex_4_a0_2_RNIVRV8HL1 780 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_241 744 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/OoI11_Z[12] 417 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_76 684 222
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_state[1] 783 133
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_2_0 619 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/un16_i11Io 528 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/O1O11[19] 88 175
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1297 686 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_1_iv_0_m2[21] 746 123
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/rdata[5] 599 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1_4[36] 462 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i0lIo_i_o3_0[0] 156 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1217 804 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt[2] 273 232
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un2_Ol0i1_3 216 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_pipe_debug_enter_req_ex_retr.ex_retr_pipe_curr_pc_retr[11] 772 157
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/o0OI1_Z[16] 546 181
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_18_1[16] 384 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0[10] 110 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/un34_fifo_mem_d_31 619 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_0_iv_2[29] 840 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_0_a3[27] 386 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_402 670 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/OlIIo[0] 269 187
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/i0I01_n2 318 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l0ol1[3] 417 205
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/gen_buff_loop[0].buff_data.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data_ram1_[0] 782 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/OIoO1_1[6] 94 192
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/gpr_wr_data_retr_3_2[9] 876 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1037 660 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt[13] 335 238
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_operand1[29] 907 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_RNO_0[22] 741 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/O0I11 145 193
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_188 651 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDR[2] 678 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/gen_shift_register_active_high.gen_shift_register_active_low.shiftDMI_7_iv_RNO[28] 740 120
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/I0IIo_i_a3_0_30_29[20] 168 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_47[2] 996 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_143 757 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ili01[3] 127 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_2[14] 935 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/I0ol1[7] 452 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un17_o1Ii1.un17_o1Ii1_axbxc4 429 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_8_m[18] 887 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un15_next_res_pos_neg_22 901 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/raddr_mux_loop_l1.un10_req_wr_data_mux[4] 652 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_i_a3_14[0] 276 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/un49_lIlo1lto15_2 241 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_0_reg_5_1[11] 852 132
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/o0l01[9] 179 205
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/un1_Ioli0_1_0 353 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_lm_0_1_0[0] 327 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/l0101_Z[1] 124 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/IO1l1[7] 457 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/lIlOo[7] 162 199
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/un5_llOo1_2 333 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/I1OI1_Z[3] 507 184
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/SYNC3_msrxp_pktsel 609 190
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/lsu_op_complete_retr_0_0_1 815 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/ll0i1[2] 217 190
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt[8] 208 211
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/tcm0_i_req_valid_2_1_RNI4S3512 807 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[1].buff_entry_addr_req[1][23] 893 148
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_1[24] 958 168
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/rx_shift[5] 497 169
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/o1Oi1_1[6] 70 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/lIlo1[23] 328 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[26] 814 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[17] 452 217
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_state_ns[4] 533 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/loO11_0_a2 116 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/o1o11 367 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/o0lIo_1_0_.m15 60 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/valid_out 796 150
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2__RNIUO98E[29] 751 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_21[5] 320 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/un3_I0io1_8 108 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/oolIo_i_a2_2_0[0] 43 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/lolIo 48 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/data_csr_reg[17] 906 142
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbdata_ff[25] 733 130
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/gen_apb_byte_shim.apb_st[1] 738 151
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_2 726 210
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_1089 684 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/olOIo_0_a3[5] 192 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1ii1_0_3[14] 111 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_lm_0[2] 240 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/iolIo_1_0_.m23_0 108 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/rd_ptr[0] 702 121
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/OilI1_0_i_a3_14[9] 300 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/loi11 357 193
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/i0lo1_13[5] 336 231
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/ooil1[5] 540 187
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_616 753 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_lm_0[3] 369 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/genblk6.il1I1[17] 372 199
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_91_u[3] 960 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/i0OI1_Z[30] 527 172
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/lsu_expipe_resp_rd_data_0_m3[2] 840 135
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/gen_bit_no_reset.state_val[2] 800 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/I0IIo[14] 259 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/OOOI1_9[30] 325 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/IioO1_RNO_0[5] 133 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/OR4_276 672 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbcs_access_ff_3_i_m2[0] 751 123
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/lIO11 88 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_valid_3_0_i 708 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sba_req_wr_data_int_10_0_iv_0_m2_1[27] 745 126
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/ifu_expipe_resp_ireg_1_a2_5[31] 729 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/dmi_rdata_0_iv_0[10] 789 123
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un23_rtc_tick_RNIVF55H 626 156
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/genblk1.ilIl1[9] 487 217
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_lm_0[1] 264 213
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/lOoO1[0] 285 184
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync[0] 22 184
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/ool01_3[5] 180 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/IioOo_0[15] 250 201
set_location CORESPI_0_0/CORESPI_0_0/USPI/URF/PRDDATA[1] 564 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_0 360 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0 804 206
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_5 504 233
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0 732 179
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0 552 197
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0 888 170
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0 540 206
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 468 233
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0 588 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0 660 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0 864 170
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0 588 206
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_3 396 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/RAM64x12_PHYS_0 804 170
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0 624 197
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 432 233
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0 732 233
set_location PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C3 468 260
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0 912 170
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0 732 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0 924 170
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0 564 197
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0 840 206
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_6 468 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0 660 206
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_7 540 233
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0 624 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0 768 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0 696 179
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_3 432 206
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_0 468 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0 768 179
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_1 504 179
set_location PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C2 540 260
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_2 360 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0 876 170
set_location PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0 588 260
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0 696 233
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_2 504 206
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_1 324 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0 696 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0 624 206
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0 804 179
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0 900 170
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_4 432 179
set_location PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1 504 260
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0 612 197
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_IoIi1_1_s_1_4178 228 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_4_cry_0 408 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0 440 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_s_4164 305 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_s_4147 336 234
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1_RNI3RFPT 480 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_s_4132 888 132
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0 39 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ioi01_0_I_1 84 180
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_4173 36 225
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_2_cry_0 24 210
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNI4M5KC[0] 12 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_s_4157 312 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_s_4155 370 216
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0 806 189
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un1_Ol1Io_1_s_1_4174 36 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_i0oi1_1_s_1_4180 324 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_s_4170 312 237
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un60_iloOo_cry_0 240 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0 567 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_6_cry_0 35 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M 492 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131 564 165
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_RNIFC6I61[8] 456 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_s_4128 72 165
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6 501 255
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_0 36 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_I1Ii1_s_1_4179 408 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_s_4129 448 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNINK1DG[1] 876 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1_RNIB2E1D 300 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0 264 198
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_cry_0 12 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0 912 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_4166 288 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1_2_cry_0 492 189
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s_4130 588 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i1oOo_1_s_1_4176 228 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_s_4139 420 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_s_4169 240 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_IOIl1_cry_0 471 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0 851 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_s_4133 831 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un26_i0O11_cry_0 84 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_4167 240 225
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_cry_0 12 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_io1l1_cry_0 540 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_s_4168 192 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_1 867 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_s_4137 276 210
set_location fifo_to_tpsram_bridge_0/state_RNIL1B5B[1] 467 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_s_4154 359 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_4162 238 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OOll1_RNO_4 516 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0 915 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_s_4141 264 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un8_i00i1_cry_0 204 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0 888 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_RNIS9C3J 240 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_o1Ii1_cry_0 420 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_s_4160 312 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1_2_cry_0 432 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_IioOo_s_1_4175 228 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_s_4158 300 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_cry_cy[0] 156 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_s_4161 336 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_39_RNI9UD73 504 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_4172 263 228
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1 890 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_olli1_cry_0 267 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_RNI7ILUL 411 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_I0iOo_1_s_1_4177 192 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_s_4159 288 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un1_rtc_count_cry_0_cy 627 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14[0] 855 150
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_RNO_6 213 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_s_4163 360 228
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0 564 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_4127 912 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_s_4146 396 225
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNIT8GH5[8] 480 234
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_0 492 252
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1_RNI8RK0M 444 192
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_5_cry_0 36 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_i00i1_cry_0 204 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/OO0o1_cry_0 414 219
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0 889 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un42_i0oi1_cry_0 144 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_s_4153 373 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_s_4138 396 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_s_4136 216 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_cry_0 540 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_s_4142 252 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un7_iIol1_cry_0 438 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_s_4145 300 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_s_4143 354 201
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un90_fine_sel_cry_0 36 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_s_4165 276 234
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_4171 192 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_s_4150 324 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_s_4156 312 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_s_4152 252 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1_RNINAN5K1[0] 492 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_1_cry_0_0 421 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_RNO_6 261 189
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un8_l1ll1_cry_0 441 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0 777 126
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_i0li1_a_4_cry_0 267 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_s_4151 308 210
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sc_r_fwft_cry_0 487 255
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0 335 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0 264 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_s_4135 336 210
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_RNIM931E[1] 72 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un7_il0Oo_cry_0 252 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_s_4148 384 228
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_s_4140 372 219
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_0_cry_0 447 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0 890 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_s_4149 276 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy 856 192
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_o1Ii1_cry_0 420 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14[1] 855 144
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_s_4134 378 225
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_RNI6F57F[0] 84 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_1 525 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_s_4144 336 225
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy 894 153
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0 600 198
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/xmit_sel.tx_2_u_2_1_0_wmux 540 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted_2_1_0_wmux[2] 843 129
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[28] 897 171
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[23] 843 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m34_1_0_wmux 27 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[16] 895 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m96_1_0_wmux 402 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[24] 846 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m71_1_0_wmux 387 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[4] 858 174
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux[6] 21 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m160_1_0_wmux 381 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m263_1_1_wmux 375 180
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux[3] 18 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[22] 840 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m192_1_0_wmux 339 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[17] 893 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[3] 366 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m55_1_0_wmux 123 207
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[5] 845 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[8] 948 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[14] 984 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[21] 852 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m69_1_0_wmux 291 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m175_1_1_wmux 378 183
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux[2] 15 198
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m214_1_0_wmux 351 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[19] 855 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m65_1_0_wmux 147 201
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux[3] 12 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[25] 864 159
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[13] 936 165
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[8] 855 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[1] 376 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[9] 924 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[5] 984 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[1] 936 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[6] 996 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m7_1_0_wmux 24 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[10] 855 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/m21_1_0_wmux 168 183
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_9_1_0_wmux 621 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[7] 972 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/un1_lsu_expipe_resp_access_aborted_2_1_0_wmux[1] 840 129
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux[4] 24 204
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[2] 996 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m297_1_0_wmux 375 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[30] 828 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[26] 840 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m41_1_0_wmux 108 207
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m51_1_0_wmux 252 186
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[10] 984 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[12] 972 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[7] 363 195
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[11] 960 156
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[6] 843 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[27] 870 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/I0lIo_4_0_.m56_1_0_wmux 36 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[18] 858 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[9] 855 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[13] 846 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m17_1_0_wmux 120 207
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_11_1_0_wmux 618 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[6] 374 198
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[14] 891 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m164_1_0_wmux 372 183
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[3] 948 153
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/lsu_align_result_95_2_1_0_wmux[4] 984 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/i0lIo_1_0_0_.m13_1_0_wmux 12 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[12] 843 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[29] 840 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m312_1_0_wmux 363 174
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[5] 312 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[7] 852 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m27_1_0_wmux 399 168
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_mp_pmux_32_1_0_wmux 948 183
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/i1oIo_5_0_.m10_1_0_wmux 156 189
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[20] 867 159
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux[5] 18 216
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out_2_13_2_0_wmux 612 201
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[11] 849 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_i_m4_1_0_wmux[2] 849 177
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m187_1_0_wmux 336 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m280_1_0_wmux 372 180
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[3] 852 153
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m44_1_0_wmux 396 168
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m330_1_0_wmux 360 174
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_1_0_wmux[15] 828 171
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[4] 375 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m302_1_0_wmux 360 180
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/m60_0_1_0_wmux 288 186
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[0] 360 195
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_4_3_0_wmux[6] 15 216
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m236_1_0_wmux 348 177
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_operand1_3_i_m4_1_0_wmux[31] 873 159
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/IioO1_3_1_0_wmux[2] 372 195
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/o0lIo_6_0_.m29_1_0_0_wmux 144 201
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/m18_1_0_wmux 384 165
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/l0lIo_0_0_1_0_.m13_1_0_0_wmux 120 213
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_3_3_0_wmux[5] 12 216
set_location COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1_RGB0 582 120
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB0 583 260
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1 577 233
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB10 583 68
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB2 583 233
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB3 577 206
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4 583 206
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5 577 179
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6 583 179
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB7 577 149
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB8 583 149
set_location PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB9 583 122
set_location PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB0 580 205
set_location PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB1 580 178
set_location PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1_RGB0 579 204
set_location PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1_RGB1 579 177
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_0_CC_0 492 254
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_CC_0 501 257
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/genblk8.full_r_RNI0A2M6_CC_1 504 257
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memraddr_r_RNIT8GH5[8]_CC_0 480 236
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/memwaddr_r_RNIFC6I61[8]_CC_0 456 236
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sc_r_fwft_cry_0_CC_0 487 257
set_location COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/un1_sc_r_fwft_cry_0_CC_1 492 257
set_location CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_clk_count_s_4130_CC_0 588 203
set_location CORESPI_0_0/CORESPI_0_0/USPI/URXF/counter_d_cry_0_0_CC_0 564 191
set_location CORESPI_0_0/CORESPI_0_0/USPI/UTXF/counter_d_cry_0_0_CC_0 600 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/iIl01_cry_cy[0]_CC_0 156 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/ioi01_0_I_1_CC_0 84 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/olO11_RNIM931E[1]_CC_0 72 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_s_4128_CC_0 72 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/OOi01_s_4128_CC_1 84 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/oOO11_RNI6F57F[0]_CC_0 84 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un26_i0O11_cry_0_CC_0 84 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/un26_i0O11_cry_0_CC_1 96 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/li001_RNIS9C3J_CC_0 240 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_IOIl1_cry_0_CC_0 471 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un1_IOIl1_cry_0_CC_1 480 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_1_CC_0 525 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_1_CC_1 528 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_39_RNI9UD73_CC_0 504 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/un4_oiOl1_0_I_39_RNI9UD73_CC_1 516 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_s_4129_CC_0 448 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/l0ll1_s_4129_CC_1 456 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M_CC_0 492 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/loIl1_RNIAEP7M_CC_1 504 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1_RNINAN5K1[0]_CC_0 492 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OoIl1_RNINAN5K1[0]_CC_1 504 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/OOll1_RNO_4_CC_0 516 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un8_l1ll1_cry_0_CC_0 441 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/un8_l1ll1_cry_0_CC_1 444 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_0_cry_0_CC_0 447 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_0_cry_0_CC_1 456 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_1_cry_0_0_CC_0 421 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/ilol1_1_cry_0_0_CC_1 432 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1_RNI8RK0M_CC_0 444 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un12_IOIl1_RNI8RK0M_CC_1 456 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0_CC_0 440 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un1_I0ol1_3_0_m_cry_2_0_CC_1 444 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un7_iIol1_cry_0_CC_0 438 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/un7_iIol1_cry_0_CC_1 444 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1_2_cry_0_CC_0 432 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/I1il1_2_cry_0_CC_1 444 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1_2_cry_0_CC_0 492 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/l1il1_2_cry_0_CC_1 504 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_RNI7ILUL_CC_0 411 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_i0il1_RNI7ILUL_CC_1 420 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un1_O1il1_4_cry_0_CC_0 408 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_io1l1_cry_0_CC_0 540 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_cry_0_CC_0 540 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/un2_Oi1l1_cry_0_CC_1 552 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1_RNIB2E1D_CC_0 300 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/iOIi1_RNIB2E1D_CC_1 312 182
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_i0li1_a_4_cry_0_CC_0 267 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_i0li1_a_4_cry_0_CC_1 276 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un12_o1Ii1_cry_0_CC_0 420 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_i00i1_cry_0_CC_0 204 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un18_i00i1_cry_0_CC_1 216 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_RNO_6_CC_0 213 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un1_I10i1_2_RNO_6_CC_1 216 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un23_o1Ii1_cry_0_CC_0 420 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_I1Ii1_s_1_4179_CC_0 408 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_IoIi1_1_s_1_4178_CC_0 228 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_IoIi1_1_s_1_4178_CC_1 240 167
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_olli1_cry_0_CC_0 267 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un6_olli1_cry_0_CC_1 276 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un8_i00i1_cry_0_CC_0 204 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/un8_i00i1_cry_0_CC_1 216 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0_CC_0 335 161
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0_CC_1 336 161
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un11_O0oi1_cry_0_CC_2 348 161
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/un6_i0oi1_1_s_1_4180_CC_0 324 176
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_RNO_6_CC_0 261 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/O0li1_RNO_6_CC_1 264 191
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un42_i0oi1_cry_0_CC_0 144 173
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un4_I0iOo_1_s_1_4177_CC_0 192 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un60_iloOo_cry_0_CC_0 240 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i1oOo_1_s_1_4176_CC_0 228 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_i1oOo_1_s_1_4176_CC_1 240 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_IioOo_s_1_4175_CC_0 228 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un6_IioOo_s_1_4175_CC_1 240 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/un7_il0Oo_cry_0_CC_0 252 185
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0_CC_0 264 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0_CC_1 276 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/OO0o1_cry_0_CC_2 288 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0_CC_0 264 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0_CC_1 276 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/OO0o1_cry_0_CC_2 288 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_4172_CC_0 263 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_4172_CC_1 264 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/precnt_s_4172_CC_2 276 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_4171_CC_0 192 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/precnt_s_4171_CC_1 204 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_s_4170_CC_0 312 239
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/precnt_s_4170_CC_1 324 239
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_s_4169_CC_0 240 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/precnt_s_4169_CC_1 252 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_s_4168_CC_0 192 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/precnt_s_4168_CC_1 204 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_4167_CC_0 240 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/precnt_s_4167_CC_1 252 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_4166_CC_0 288 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/precnt_s_4166_CC_1 300 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_s_4165_CC_0 276 236
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/precnt_s_4165_CC_1 288 236
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_s_4163_CC_0 360 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/precnt_s_4163_CC_1 372 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_4162_CC_0 238 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_4162_CC_1 240 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/precnt_s_4162_CC_2 252 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_s_4149_CC_0 276 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/precnt_s_4149_CC_1 288 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_s_4148_CC_0 384 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/precnt_s_4148_CC_1 396 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_s_4147_CC_0 336 236
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/precnt_s_4147_CC_1 348 236
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/OO0o1_cry_0_CC_0 414 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/OO0o1_cry_0_CC_1 420 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_s_4145_CC_0 300 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/precnt_s_4145_CC_1 312 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_s_4144_CC_0 336 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/precnt_s_4144_CC_1 348 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_s_4143_CC_0 354 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/precnt_s_4143_CC_1 360 203
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_s_4142_CC_0 252 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/precnt_s_4142_CC_1 264 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_s_4141_CC_0 264 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/precnt_s_4141_CC_1 276 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_s_4140_CC_0 372 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/precnt_s_4140_CC_1 384 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_s_4139_CC_0 420 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/precnt_s_4139_CC_1 432 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_s_4138_CC_0 396 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/precnt_s_4138_CC_1 408 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_s_4137_CC_0 276 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/precnt_s_4137_CC_1 288 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_s_4136_CC_0 216 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/precnt_s_4136_CC_1 228 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_s_4135_CC_0 336 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/precnt_s_4135_CC_1 348 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_s_4134_CC_0 378 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/precnt_s_4134_CC_1 384 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_s_4164_CC_0 305 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/precnt_s_4164_CC_1 312 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_s_4161_CC_0 336 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/precnt_s_4161_CC_1 348 200
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_s_4160_CC_0 312 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/precnt_s_4160_CC_1 324 230
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_s_4159_CC_0 288 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/precnt_s_4159_CC_1 300 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_s_4158_CC_0 300 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/precnt_s_4158_CC_1 312 194
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_s_4157_CC_0 312 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/precnt_s_4157_CC_1 324 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_s_4156_CC_0 312 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/precnt_s_4156_CC_1 324 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_s_4155_CC_0 370 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/precnt_s_4155_CC_1 372 218
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_s_4154_CC_0 359 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/precnt_s_4154_CC_1 360 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_s_4153_CC_0 373 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/precnt_s_4153_CC_1 384 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_s_4152_CC_0 252 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/precnt_s_4152_CC_1 264 221
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_s_4151_CC_0 308 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/precnt_s_4151_CC_1 312 212
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_s_4150_CC_0 324 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/precnt_s_4150_CC_1 336 209
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_s_4146_CC_0 396 227
set_location CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/precnt_s_4146_CC_1 408 227
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_4173_CC_0 36 227
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_4173_CC_1 48 227
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Il1Io_s_4173_CC_2 60 227
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0_CC_0 39 230
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0_CC_1 48 230
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/genblk1.Ol1Io10_a_4_cry_0_CC_2 60 230
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un1_Ol1Io_1_s_1_4174_CC_0 36 221
set_location CORETSE_0_inst_0/CORETSE_0_0/i.OI/un1_Ol1Io_1_s_1_4174_CC_1 48 221
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1_RNI3RFPT_CC_0 480 161
set_location CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_cntr7_1_RNI3RFPT_CC_1 492 161
set_location fifo_to_tpsram_bridge_0/state_RNIL1B5B[1]_CC_0 467 257
set_location fifo_to_tpsram_bridge_0/state_RNIL1B5B[1]_CC_1 468 257
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131_CC_0 564 167
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131_CC_1 588 167
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131_CC_2 600 167
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131_CC_3 612 167
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131_CC_4 624 167
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/mtime_count_out_s_4131_CC_5 636 167
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un1_rtc_count_cry_0_cy_CC_0 627 155
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un1_rtc_count_cry_0_cy_CC_1 636 155
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_0 567 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_1 588 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_2 600 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_3 612 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_4 624 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/un5_m_timer_irq_cry_0_CC_5 636 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/counter_s_4132_CC_0 888 134
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_0 777 128
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_1 780 128
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_2 792 128
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/sbaddr_ff_6_cry_0_0_CC_3 804 128
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_0 851 173
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_1 852 173
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_2 864 173
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/bcu_result_cry_0_CC_3 876 173
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14[0]_CC_0 855 152
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14[0]_CC_1 864 152
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14[1]_CC_0 855 146
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/gen_tdata1_2.trigger_match_RNO_14[1]_CC_1 864 146
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_0 806 191
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_1 816 191
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/exu_alu_result_int_cry_0_CC_2 828 191
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/mul_div_cnt_s_4133_CC_0 831 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_4127_CC_0 912 200
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_4127_CC_1 924 200
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/next_dividend_s_0_4127_CC_2 936 200
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNINK1DG[1]_CC_0 876 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNINK1DG[1]_CC_1 888 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/quotient_RNINK1DG[1]_CC_2 900 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0_CC_0 890 185
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0_CC_1 900 185
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un120_exu_alu_result_cry_0_CC_2 912 185
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_0 888 182
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_1 900 182
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un128_exu_alu_result_cry_0_CC_2 912 182
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_1_CC_0 867 185
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un152_exu_alu_result_1_I_1_CC_1 876 185
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0_CC_0 915 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0_CC_1 924 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un16_next_div_divisor_1_cry_0_CC_2 936 176
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_0 912 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_1 924 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_2 936 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_3 948 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_4 960 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un1_dividend_cry_0_CC_5 972 203
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy_CC_0 856 194
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy_CC_1 864 194
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un23_mulh_mc_0_cry_1_cy_CC_2 876 194
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1_CC_0 890 194
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1_CC_1 900 194
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_0_cry_1_CC_2 912 194
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0_CC_0 889 191
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0_CC_1 900 191
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/un6_exu_alu_result_1_cry_0_CC_2 912 191
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy_CC_0 894 155
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy_CC_1 900 155
set_location MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/un3_next_req_fetch_ptr_cry_1_cy_CC_2 912 155
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un18_fine_sel_cry_0_CC_0 36 200
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_5_cry_0_CC_0 36 209
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_6_cry_0_CC_0 35 212
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_dll_90_code_6_cry_0_CC_1 36 212
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un1_fine_sel_2_cry_0_CC_0 24 212
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un41_fine_sel_cry_0_CC_0 12 209
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un68_fine_sel_cry_0_CC_0 12 212
set_location PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/un90_fine_sel_cry_0_CC_0 36 203
set_location PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/state_RNI4M5KC[0]_CC_0 12 182