@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v":70:8:70:28|Synthesizing module miv_rv32_hart_cfg_pkg in library work. @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":73:8:73:19|Synthesizing module miv_rv32_pkg in library work. @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v":69:8:69:26|Synthesizing module miv_rv32_subsys_pkg in library work. @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":314:0:314:5|Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit in library work. @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":77:0:77:5|Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit in library work. Selecting top level module top @N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":22:7:22:19|Component COREJTAGDEBUG not found in library "work" or "__hyper__lib__", but found in library COREJTAGDEBUG_LIB @N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v":27:0:27:6|Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":121:7:121:10|Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":333:7:333:11|Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":21:7:21:48|Synthesizing module Core_reset_pf_Core_reset_pf_0_CORERESET_PF in library work. Running optimization stage 1 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF ....... Finished optimization stage 1 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v":21:7:21:19|Synthesizing module Core_reset_pf in library work. Running optimization stage 1 on Core_reset_pf ....... Finished optimization stage 1 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 234MB peak: 235MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 1 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 237MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b1 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0110 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000010 SL2=16'b0000000000000100 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z1 @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z1 ....... Finished optimization stage 1 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 237MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v":57:7:57:16|Synthesizing module CoreAPB3_0 in library work. Running optimization stage 1 on CoreAPB3_0 ....... Finished optimization stage 1 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 237MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":19:7:19:40|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_COREFIFO in library work. FAMILY=32'b00000000000000000000000000011010 SYNC=32'b00000000000000000000000000000001 RE_POLARITY=32'b00000000000000000000000000000000 WE_POLARITY=32'b00000000000000000000000000000000 RWIDTH=32'b00000000000000000000000000100000 WWIDTH=32'b00000000000000000000000000100000 RDEPTH=32'b00000000000000000000010000000000 WDEPTH=32'b00000000000000000000010000000000 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 CTRL_TYPE=32'b00000000000000000000000000000010 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 AE_STATIC_EN=32'b00000000000000000000000000000000 AF_STATIC_EN=32'b00000000000000000000000000000000 AEVAL=32'b00000000000000000000000000000100 AFVAL=32'b00000000000000000000001111111100 PIPE=32'b00000000000000000000000000000001 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000001 ECC=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 NUM_STAGES=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 RAM_OPT=32'b00000000000000000000000000000000 DIE_SIZE=32'b00000000000000000000000000001111 WMSB_DEPTH=32'b00000000000000000000000000001010 RMSB_DEPTH=32'b00000000000000000000000000001010 WDEPTH_CAL=32'b00000000000000000000000000001001 RDEPTH_CAL=32'b00000000000000000000000000001001 RESET_POLARITY=32'b00000000000000000000000000000000 RCLK_EDGE=32'b00000000000000000000000000000001 WCLK_EDGE=32'b00000000000000000000000000000001 Generated name = COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":20:7:20:51|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr in library work. WRITE_WIDTH=32'b00000000000000000000000000100000 WRITE_DEPTH=32'b00000000000000000000000000001010 FULL_WRITE_DEPTH=32'b00000000000000000000010000000000 READ_WIDTH=32'b00000000000000000000000000100000 READ_DEPTH=32'b00000000000000000000000000001010 FULL_READ_DEPTH=32'b00000000000000000000010000000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000001 WCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 AF_FLAG_STATIC=32'b00000000000000000000000000000000 AE_FLAG_STATIC=32'b00000000000000000000000000000000 AFULL_VAL=32'b00000000000000000000001111111100 AEMPTY_VAL=32'b00000000000000000000000000000100 ESTOP=32'b00000000000000000000000000000001 FSTOP=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000001 REGISTER_RADDR=32'b00000000000000000000000000000001 READ_DVALID=32'b00000000000000000000000000000000 WRITE_ACK=32'b00000000000000000000000000000000 OVERFLOW_EN=32'b00000000000000000000000000000000 UNDERFLOW_EN=32'b00000000000000000000000000000000 WRCNT_EN=32'b00000000000000000000000000000000 RDCNT_EN=32'b00000000000000000000000000000000 ECC=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 WDEPTH_CAL=32'b00000000000000000000000000001001 RDEPTH_CAL=32'b00000000000000000000000000001001 Generated name = COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":173:29:173:37|Removing wire neg_reset, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register full_reg. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":371:4:371:9|Pruning unused register sc_w[10:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":331:6:331:11|Pruning unused register we_f_i. Make sure that there are no unused intermediate registers. @W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|All reachable assignments to genblk8.wack_r assign 0, register removed by optimization. @W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|All reachable assignments to genblk8.overflow_r assign 0, register removed by optimization. @W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|All reachable assignments to underflow_r assign 0, register removed by optimization. @W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|All reachable assignments to dvld_r assign 0, register removed by optimization. @W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":275:3:275:8|All reachable assignments to rdcnt[10:0] assign 0, register removed by optimization. @W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":248:3:248:8|All reachable assignments to wrcnt[10:0] assign 0, register removed by optimization. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 236MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":20:7:20:45|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft in library work. RDEPTH=32'b00000000000000000000000000001010 WWIDTH=32'b00000000000000000000000000100000 RWIDTH=32'b00000000000000000000000000100000 WCLK_HIGH=32'b00000000000000000000000000000001 RCLK_HIGH=32'b00000000000000000000000000000001 RESET_LOW=32'b00000000000000000000000000000000 WRITE_LOW=32'b00000000000000000000000000000000 READ_LOW=32'b00000000000000000000000000000000 PREFETCH=32'b00000000000000000000000000000000 FWFT=32'b00000000000000000000000000000001 SYNC=32'b00000000000000000000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 RDEPTH_CAL=32'b00000000000000000000000000001001 Generated name = COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":254:38:254:55|Removing redundant assignment. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":119:27:119:32|Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":125:27:125:33|Removing wire aresetn, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":132:27:132:32|Removing wire empty1, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":140:8:140:17|Removing wire reset_wclk, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":141:8:141:17|Removing wire reset_rclk, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":358:3:358:8|Pruning unused register we_p_r. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":244:3:244:8|Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":233:4:233:9|Pruning unused register re_p_d. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":214:3:214:8|Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":214:3:214:8|Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":578:7:578:13|Synthesizing module RAM1K20 in library work. Running optimization stage 1 on RAM1K20 ....... Finished optimization stage 1 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":500:7:500:9|Synthesizing module GND in library work. Running optimization stage 1 on GND ....... Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":504:7:504:9|Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v":5:7:5:41|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top in library work. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top ....... Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":4:7:4:43|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper in library work. RWIDTH=32'b00000000000000000000000000100000 WWIDTH=32'b00000000000000000000000000100000 RDEPTH=32'b00000000000000000000000000001010 WDEPTH=32'b00000000000000000000000000001010 SYNC=32'b00000000000000000000000000000001 PIPE=32'b00000000000000000000000000000001 CTRL_TYPE=32'b00000000000000000000000000000010 SYNC_RESET=32'b00000000000000000000000000000000 RAM_OPT=32'b00000000000000000000000000000000 Generated name = COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s ....... @W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":46:26:46:37|*Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":47:26:47:37|*Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":48:26:48:36|*Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":49:26:49:36|*Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":211:36:211:46|Removing wire pf_MEMRADDR, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":217:36:217:39|Removing wire pf_Q, as there is no assignment to it. @W: CG184 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":236:36:236:45|Removing wire DVLD_async, as it has the load but no drivers. @W: CG184 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":238:36:238:44|Removing wire DVLD_sync, as it has the load but no drivers. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":241:36:241:42|Removing wire pf_dvld, as there is no assignment to it. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":250:36:250:44|Object reg_valid is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":264:36:264:41|Object reg_RD is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":283:8:283:17|Removing wire reset_rclk, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":284:8:284:17|Removing wire reset_wclk, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":285:8:285:19|Removing wire reset_sync_r, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":286:8:286:19|Removing wire reset_sync_w, as there is no assignment to it. Running optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1175:3:1175:8|Pruning unused register RDATA_ext_r1[31:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1165:3:1165:8|Pruning unused register RDATA_ext_r[31:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register REN_d2. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register REN_d3. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register RE_d2. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register RE_d3. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1088:3:1088:8|Pruning unused register RDATA_r2[31:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1078:3:1078:8|Pruning unused register RDATA_r1[31:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1068:3:1068:8|Pruning unused register RDATA_r_pre[31:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1058:3:1058:8|Pruning unused register fwft_Q_r[31:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":490:3:490:8|Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":490:3:490:8|Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v":49:7:49:17|Synthesizing module COREFIFO_C0 in library work. Running optimization stage 1 on COREFIFO_C0 ....... Finished optimization stage 1 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":22:7:22:19|Synthesizing module COREJTAGDEBUG in library COREJTAGDEBUG_LIB. FAMILY=32'b00000000000000000000000000011010 NUM_DEBUG_TGTS=32'b00000000000000000000000000000001 TGT_ACTIVE_HIGH_RESET_0=32'b00000000000000000000000000000000 IR_CODE_TGT_0=8'b01010101 TGT_ACTIVE_HIGH_RESET_1=32'b00000000000000000000000000000000 IR_CODE_TGT_1=8'b01010110 TGT_ACTIVE_HIGH_RESET_2=32'b00000000000000000000000000000000 IR_CODE_TGT_2=8'b01010111 TGT_ACTIVE_HIGH_RESET_3=32'b00000000000000000000000000000000 IR_CODE_TGT_3=8'b01011000 TGT_ACTIVE_HIGH_RESET_4=32'b00000000000000000000000000000000 IR_CODE_TGT_4=8'b01011001 TGT_ACTIVE_HIGH_RESET_5=32'b00000000000000000000000000000000 IR_CODE_TGT_5=8'b01011010 TGT_ACTIVE_HIGH_RESET_6=32'b00000000000000000000000000000000 IR_CODE_TGT_6=8'b01011011 TGT_ACTIVE_HIGH_RESET_7=32'b00000000000000000000000000000000 IR_CODE_TGT_7=8'b01011100 TGT_ACTIVE_HIGH_RESET_8=32'b00000000000000000000000000000000 IR_CODE_TGT_8=8'b01011101 TGT_ACTIVE_HIGH_RESET_9=32'b00000000000000000000000000000000 IR_CODE_TGT_9=8'b01011110 TGT_ACTIVE_HIGH_RESET_10=32'b00000000000000000000000000000000 IR_CODE_TGT_10=8'b01011111 TGT_ACTIVE_HIGH_RESET_11=32'b00000000000000000000000000000000 IR_CODE_TGT_11=8'b01100000 TGT_ACTIVE_HIGH_RESET_12=32'b00000000000000000000000000000000 IR_CODE_TGT_12=8'b01100001 TGT_ACTIVE_HIGH_RESET_13=32'b00000000000000000000000000000000 IR_CODE_TGT_13=8'b01100010 TGT_ACTIVE_HIGH_RESET_14=32'b00000000000000000000000000000000 IR_CODE_TGT_14=8'b01100011 TGT_ACTIVE_HIGH_RESET_15=32'b00000000000000000000000000000000 IR_CODE_TGT_15=8'b01100100 UJTAG_BYPASS=32'b00000000000000000000000000000000 UJTAG_SEC_EN=1'b0 DELAY_NUM=32'b00000000000000000000000000100010 IR_CODE_TGT=128'b01100100011000110110001001100001011000000101111101011110010111010101110001011011010110100101100101011000010101110101011001010101 TGT_ACTIVE_HIGH_RESET=16'b0000000000000000 USE_NEW_UJTAG=32'b00000000000000000000000000000001 USE_UJTAG_WRAPPER=32'b00000000000000000000000000000000 USE_UJTAG_SEC=32'b00000000000000000000000000000000 Generated name = COREJTAGDEBUG_Z5 @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":1442:7:1442:11|Synthesizing module UJTAG in library work. Running optimization stage 1 on UJTAG ....... Finished optimization stage 1 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v":20:7:20:24|Synthesizing module corejtagdebug_bufd in library COREJTAGDEBUG_LIB. DELAY_NUM=32'b00000000000000000000000000100010 Generated name = corejtagdebug_bufd_34s @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":229:7:229:10|Synthesizing module BUFD in library work. Running optimization stage 1 on BUFD ....... Finished optimization stage 1 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) Running optimization stage 1 on corejtagdebug_bufd_34s ....... Finished optimization stage 1 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 238MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v":47:7:47:27|Synthesizing module COREJTAGDEBUG_UJ_JTAG in library COREJTAGDEBUG_LIB. FAMILY=32'b00000000000000000000000000011010 SYNC_RESET=32'b00000000000000000000000000000000 DELAY_NUM=32'b00000000000000000000000000100010 IR_CODE_TGT=8'b01010101 NUM_LEAD_PAD_BITS=8'b00000000 NUM_TRAIL_PAD_BITS=8'b00000000 Generated name = COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 Running optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 ....... Finished optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB) @N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":489:7:489:12|Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB) @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|Removing wire UTRSTB, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|Removing wire UTMS, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":169:8:169:52|Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":176:8:176:52|Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":183:8:183:52|Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":190:8:190:52|Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":241:28:241:37|Removing wire iURSTB_inv, as there is no assignment to it. Running optimization stage 1 on COREJTAGDEBUG_Z5 ....... @W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|*Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|*Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. Finished optimization stage 1 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v":56:7:56:22|Synthesizing module COREJTAGDEBUG_C0 in library work. Running optimization stage 1 on COREJTAGDEBUG_C0 ....... Finished optimization stage 1 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 237MB peak: 239MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":31:7:31:12|Synthesizing module spi_rf in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000010000 ZEROS=32'b00000000000000000000000000000000 Generated name = spi_rf_32s_16s_0 Running optimization stage 1 on spi_rf_32s_16s_0 ....... @W: CL208 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":134:0:134:5|All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization. Finished optimization stage 1 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v":24:7:24:17|Synthesizing module spi_control in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000010000 Generated name = spi_control_16s Running optimization stage 1 on spi_control_16s ....... Finished optimization stage 1 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 238MB peak: 239MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":25:7:25:14|Synthesizing module spi_fifo in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 PTR_WIDTH=32'b00000000000000000000000000000101 Generated name = spi_fifo_16s_32s_5 Running optimization stage 1 on spi_fifo_16s_32s_5 ....... Finished optimization stage 1 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 240MB peak: 241MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v":24:7:24:18|Synthesizing module spi_clockmux in library CORESPI_LIB. Running optimization stage 1 on spi_clockmux ....... Finished optimization stage 1 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 240MB peak: 241MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":29:7:29:18|Synthesizing module spi_chanctrl in library CORESPI_LIB. SPH=1'b0 SPO=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 CFG_CLKRATE=32'b00000000000000000000000000010000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000000100 MTX_IDLE1=4'b0000 MTX_IDLE2=4'b0001 MTX_MOTSTART=4'b0010 MTX_TISTART1=4'b0011 MTX_TISTART2=4'b0100 MTX_NSCSTART1=4'b0101 MTX_NSCSTART2=4'b0110 MTX_SHIFT1=4'b0111 MTX_SHIFT2=4'b1000 MTX_END=4'b1001 STXS_IDLE=1'b0 STXS_SHIFT=1'b1 MOTMODE=1'b1 TIMODE=1'b0 NSCMODE=1'b0 MOTNOSSEL=1'b1 NSCNOSSEL=1'b0 cfg_framesizeM1=32'b00000000000000000000000000001111 Generated name = spi_chanctrl_Z6 @W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":195:12:195:22|Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":196:12:196:22|Removing wire resetn_rx_p, as there is no assignment to it. @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":200:12:200:22|Removing wire resetn_rx_r, as there is no assignment to it. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":222:12:222:36|Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on spi_chanctrl_Z6 ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":1130:0:1130:5|Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":719:0:719:5|Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers. @W: CL177 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":343:0:343:5|Sharing sequential element cfg_enable_P1 and merging msrx_async_reset_ok. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":29:7:29:9|Synthesizing module spi in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000010000 SPO=1'b0 SPH=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 Generated name = spi_32s_16s_32s_16s_0_0_1_0s Running optimization stage 1 on spi_32s_16s_32s_16s_0_0_1_0s ....... Finished optimization stage 1 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v":27:0:27:6|Synthesizing module CORESPI in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000010000 CFG_MODE=32'b00000000000000000000000000000000 CFG_MOT_MODE=32'b00000000000000000000000000000000 CFG_MOT_SSEL=32'b00000000000000000000000000000001 CFG_TI_NSC_CUSTOM=32'b00000000000000000000000000000000 CFG_TI_NSC_FRC=32'b00000000000000000000000000000000 CFG_TI_JMB_FRAMES=32'b00000000000000000000000000000000 CFG_NSC_OPERATION=32'b00000000000000000000000000000000 SPS=1'b1 SPO=1'b0 SPH=1'b0 Generated name = CORESPI_Z7 Running optimization stage 1 on CORESPI_Z7 ....... Finished optimization stage 1 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v":32:7:32:15|Synthesizing module CORESPI_0 in library work. Running optimization stage 1 on CORESPI_0 ....... Finished optimization stage 1 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_DECODER ....... Finished optimization stage 1 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s ....... Finished optimization stage 1 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s ....... Finished optimization stage 1 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 241MB peak: 242MB) Running optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s ....... Finished optimization stage 1 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 242MB peak: 243MB) Running optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s ....... Finished optimization stage 1 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 245MB) Running optimization stage 1 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s ....... Finished optimization stage 1 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 243MB peak: 245MB) Running optimization stage 1 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s ....... Finished optimization stage 1 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 ....... Finished optimization stage 1 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_AMCXFIF_HST_Z8 ....... Finished optimization stage 1 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_AMCXFIF_CLKRST_26s_1s ....... Finished optimization stage 1 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_SIB_SYNC_2FLP_1s_26s_1s ....... Finished optimization stage 1 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on OiOI1_26s_11s_12s_32s_2s_0s ....... Finished optimization stage 1 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 246MB peak: 256MB) Running optimization stage 1 on CTSE_PETMC_TOP_1s_26s ....... Finished optimization stage 1 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 247MB peak: 256MB) Running optimization stage 1 on CTSE_PECRC_1s_26s ....... Finished optimization stage 1 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 247MB peak: 256MB) Running optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s ....... Finished optimization stage 1 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 248MB peak: 256MB) Running optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s ....... Finished optimization stage 1 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 261MB) Running optimization stage 1 on CTSE_PERMC_TOP_1s_26s ....... Finished optimization stage 1 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 263MB) Running optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s ....... Finished optimization stage 1 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 263MB) Running optimization stage 1 on CTSE_PEMGT_1s_26s ....... Finished optimization stage 1 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEHST_1s_26s ....... Finished optimization stage 1 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PECAR_26s_1s ....... Finished optimization stage 1 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s ....... Finished optimization stage 1 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s ....... Finished optimization stage 1 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_STORE_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s ....... Finished optimization stage 1 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_26s ....... Finished optimization stage 1 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_MMCXWOL_1s_26s ....... Finished optimization stage 1 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_SI_SAL_26s ....... Finished optimization stage 1 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_TSMAC_TOP_Z9 ....... Finished optimization stage 1 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_CLKRST_26s_1s ....... Finished optimization stage 1 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s ....... Finished optimization stage 1 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_ECC_0s_26s_16s ....... Only the first 100 messages of id 'CL190' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL190' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL190} -count unlimited' in the Tcl shell. Finished optimization stage 1 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s ....... Finished optimization stage 1 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 254MB peak: 263MB) Running optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s ....... Finished optimization stage 1 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB) Running optimization stage 1 on CTSE_MSGMII_CNVTXI_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB) Running optimization stage 1 on CTSE_MSGMII_CNVTXO_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 263MB) Running optimization stage 1 on CTSE_T8B10B ....... Finished optimization stage 1 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 263MB) Running optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s ....... Finished optimization stage 1 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 259MB peak: 263MB) Running optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 ....... Finished optimization stage 1 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 263MB) Running optimization stage 1 on CTSE_R10B8B ....... Finished optimization stage 1 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 260MB peak: 263MB) Running optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s ....... Finished optimization stage 1 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB) Running optimization stage 1 on CTSE_PEANX_SYNC_1s_26s ....... Finished optimization stage 1 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB) Running optimization stage 1 on CTSE_MSGMII_PEANX_TOP_1s_26s ....... Finished optimization stage 1 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 264MB peak: 267MB) Running optimization stage 1 on CTSE_PETBM_26s_0s_1s ....... Finished optimization stage 1 on CTSE_PETBM_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_PETCR_26s_1s ....... Finished optimization stage 1 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s ....... Finished optimization stage 1 on CTSE_MSGMII_TBI_26s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_MSGMII_CNVRXI_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_MSGMII_CNVRXO_26s ....... Finished optimization stage 1 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s ....... Finished optimization stage 1 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_CORETSE_TOP_Z10 ....... Finished optimization stage 1 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 ....... Finished optimization stage 1 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) Running optimization stage 1 on CORETSE_Z11 ....... Finished optimization stage 1 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":31:7:31:15|Synthesizing module CORETSE_0 in library work. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":270:0:270:10|Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on CORETSE_0 ....... Finished optimization stage 1 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v":38:7:38:45|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work. BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s ....... Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 267MB peak: 268MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 TX_FIFO=32'b00000000000000000000000000000000 tx_idle=32'b00000000000000000000000000000000 tx_load=32'b00000000000000000000000000000001 start_bit=32'b00000000000000000000000000000010 tx_data_bits=32'b00000000000000000000000000000011 parity_bit=32'b00000000000000000000000000000100 tx_stop_bit=32'b00000000000000000000000000000101 delay_state=32'b00000000000000000000000000000110 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s @W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible. @W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":356:21:356:29|Removing redundant assignment. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":30:7:30:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 receive_states_rx_idle=32'b00000000000000000000000000000000 receive_states_rx_data_bits=32'b00000000000000000000000000000001 receive_states_rx_stop_bit=32'b00000000000000000000000000000010 receive_states_rx_wait_state=32'b00000000000000000000000000000011 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":254:23:254:35|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":280:18:280:25|Removing redundant assignment. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @W: CL177 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":501:0:501:5|Sharing sequential element clear_framing_error_en and merging clear_parity_en. Add a syn_preserve attribute to the element to prevent sharing. Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) @N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_COREUART in library work. TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":390:22:390:33|Removing redundant assignment. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":136:8:136:17|Object data_ready is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":376:0:376:5|Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":326:0:326:5|Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":293:0:293:5|Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":159:0:159:5|Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Only the first 100 messages of id 'CG364' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CG364' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG364} -count unlimited' in the Tcl shell. FAMILY=32'b00000000000000000000000000011010 TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 BAUD_VALUE=32'b00000000000000000000000000000001 FIXEDMODE=32'b00000000000000000000000000000000 PRG_BIT8=32'b00000000000000000000000000000000 PRG_PARITY=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":254:31:254:41|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":275:31:275:41|Removing redundant assignment. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":158:20:158:30|Object controlReg3 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 ....... Finished optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Running optimization stage 1 on CoreUARTapb_0 ....... Finished optimization stage 1 on CoreUARTapb_0 (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Running optimization stage 1 on fifo_to_tpsram_bridge ....... Finished optimization stage 1 on fifo_to_tpsram_bridge (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) Running optimization stage 1 on INBUF_DIFF ....... Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 268MB peak: 269MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 RESP_ERROR_WIDTH=32'b00000000000000000000000000000010 BUFF_DEPTH=32'b00000000000000000000000000000011 LOG2_BUFF_DEPTH=32'b00000000000000000000000000000010 MI_I_MEM=32'b00000000000000000000000000000000 Generated name = miv_rv32_ifu_iab_32s_2s_3s_2s_0s Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s ....... Finished optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 270MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 l_core_reset_vector=32'b10000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 IAB_BUFF_DEPTH=32'b00000000000000000000000000000011 LOG2_IAB_BUFF_DEPTH=32'b00000000000000000000000000000010 MAX_IFU_EMI_OS=32'b00000000000000000000000000000011 LOG2_MAX_IFU_EMI_OS=32'b00000000000000000000000000000010 RESP_ERROR_WIDTH=32'b00000000000000000000000000000010 IFU_MEM_ERROR_BIT=32'b00000000000000000000000000000000 IFU_PARITY_ERROR_BIT=32'b00000000000000000000000000000001 Generated name = miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 Running optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 ....... Finished optimization stage 1 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 269MB peak: 270MB) D_ADDR_WIDTH=32'b00000000000000000000000000100000 REQ_BUFF_DEPTH=32'b00000000000000000000000000000010 LOG2_REQ_BUFF_DEPTH=32'b00000000000000000000000000000001 OS_COUNT_WIDTH=32'b00000000000000000000000000000010 MAX_OS=32'b00000000000000000000000000000010 Generated name = miv_rv32_lsu_32s_2s_1s_2s_2s @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19009:38:19009:51|Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19017:38:19017:57|Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19020:38:19020:53|Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19021:38:19021:58|Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19022:38:19022:62|Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19023:38:19023:67|Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19024:38:19024:49|Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19025:38:19025:49|Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19026:38:19026:56|Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19027:38:19027:52|Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_lsu_32s_2s_1s_2s_2s ....... Finished optimization stage 1 on miv_rv32_lsu_32s_2s_1s_2s_2s (CPU Time 0h:00m:00s, Memory Used current: 270MB peak: 271MB) GEN_DECODE_RV32I=1'b1 GEN_DECODE_RV32M=32'b00000000000000000000000000000001 GEN_DECODE_RV32C=32'b00000000000000000000000000000001 GEN_DECODE_RV32F=32'b00000000000000000000000000000000 Generated name = miv_rv32_idecode_1_1s_1s_0s Running optimization stage 1 on miv_rv32_idecode_1_1s_1s_0s ....... Finished optimization stage 1 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 281MB peak: 282MB) CHECK_ILLEGAL=32'b00000000000000000000000000000001 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_decode_1s_1s_0s Running optimization stage 1 on miv_rv32_csr_decode_1s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 281MB peak: 282MB) USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 cfg_div_en=32'b00000000000000000000000000000001 cfg_fast_mul=32'b00000000000000000000000000000000 cfg_slow_mul=32'b00000000000000000000000000000001 Generated name = miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 @W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10740:32:10740:42|Index into variable mul_mp could be out of range ; a simulation mismatch is possible. @W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10740:32:10740:42|Index into variable mul_mp could be out of range ; a simulation mismatch is possible. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10766:32:10766:40|Object fpu_frm_i is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10767:32:10767:35|Object op_i is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":843:10:843:11|Object status_o.NV is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":844:10:844:11|Object status_o.DZ is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":845:10:845:11|Object status_o.OF is declared but not assigned. Either assign a value or remove the declaration. @W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":846:10:846:11|Object status_o.UF is declared but not assigned. Either assign a value or remove the declaration. Only the first 100 messages of id 'CG133' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CG133' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG133} -count unlimited' in the Tcl shell. Running optimization stage 1 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 ....... Finished optimization stage 1 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) Running optimization stage 1 on miv_rv32_bcu ....... Finished optimization stage 1 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) IRQ_STICKY_CAPTURE=32'b00000000000000000000000000000000 Generated name = miv_rv32_irq_reg_0s Running optimization stage 1 on miv_rv32_irq_reg_0s ....... Finished optimization stage 1 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 Generated name = miv_rv32_priv_irq_2s_0_0 Running optimization stage 1 on miv_rv32_priv_irq_2s_0_0 ....... Finished optimization stage 1 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) CHECK_ILLEGAL=32'b00000000000000000000000000000000 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_decode_0s_1s_0s Running optimization stage 1 on miv_rv32_csr_decode_0s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 310MB peak: 330MB) WIDTH=32'b00000000000000000000000000000101 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_5s_1s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000011 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_3s_1s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_3s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000001 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_1s_1s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_1s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000001 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_1s_0s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_0s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000011111 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_31s_0s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_31s_0s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000000101 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=5'b00000 Generated name = miv_rv32_csr_gpr_state_reg_5s_1s_0 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_0s_0s Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_0s_0s ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_trigger_bus_width=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_compressed=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 Generated name = miv_rv32_csr_privarch_Z15 WIDTH=32'b00000000000000000000000000011110 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=30'b100000000000000000000000000001 Generated name = miv_rv32_csr_gpr_state_reg_30s_1s_536870913 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 311MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_0 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_0 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b10000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) Running optimization stage 1 on miv_rv32_csr_privarch_Z15 ....... @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4310:6:4310:26|Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Finished optimization stage 1 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 D_ADDR_WIDTH=32'b00000000000000000000000000100000 I_DATA_BYTES=32'b00000000000000000000000000000100 D_DATA_BYTES=32'b00000000000000000000000000000100 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 l_core_cfg_trigger_bus_width=32'b00000000000000000000000000000010 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 l_core_cfg_gpr_fwd_hzd=1'b0 Generated name = miv_rv32_expipe_Z16 ECC_ENABLE=32'b00000000000000000000000000000000 l_core_cfg_gpr_fwd_hzd=1'b0 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 GPR_DEPTH=32'b00000000000000000000000000100000 Generated name = miv_rv32_gpr_ram_0s_0_0s_32s @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6111:72:6111:89|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6112:72:6112:89|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6113:72:6113:89|Removing redundant assignment. d_width=32'b00000000000000000000000000100000 addr_width_gpr=32'b00000000000000000000000000000110 mem_depth=32'b00000000000000000000000000100000 Generated name = miv_rv32_gpr_ram_array_32s_6s_32s Running optimization stage 1 on miv_rv32_gpr_ram_array_32s_6s_32s ....... @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32 @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32 @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32 Finished optimization stage 1 on miv_rv32_gpr_ram_array_32s_6s_32s (CPU Time 0h:00m:00s, Memory Used current: 312MB peak: 330MB) Running optimization stage 1 on miv_rv32_gpr_ram_0s_0_0s_32s ....... Finished optimization stage 1 on miv_rv32_gpr_ram_0s_0_0s_32s (CPU Time 0h:00m:00s, Memory Used current: 313MB peak: 330MB) Running optimization stage 1 on miv_rv32_expipe_Z16 ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10390:2:10390:7|Pruning unused register sreset. Make sure that there are no unused intermediate registers. @N: CL189 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9191:4:9191:9|Register bit gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5] is always 0. @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9191:4:9191:9|Pruning register bit 5 of gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB) I_ADDR_WIDTH=32'b00000000000000000000000000100000 D_ADDR_WIDTH=32'b00000000000000000000000000100000 I_DATA_BYTES=32'b00000000000000000000000000000100 D_DATA_BYTES=32'b00000000000000000000000000000100 l_core_cfg_hw_debug=32'b00000000000000000000000000000001 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_core_cfg_hw_compressed=32'b00000000000000000000000000000001 l_core_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=32'b00000000000000000000000000000010 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 Generated name = miv_rv32_hart_Z17 Running optimization stage 1 on miv_rv32_hart_Z17 ....... Finished optimization stage 1 on miv_rv32_hart_Z17 (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB) BUFF_WIDTH=32'b00000000000000000000000000000110 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_6s_2s_1s_1s Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB) BUFF_WIDTH=32'b00000000000000000000000000001011 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_11s_2s_1s_1s Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 314MB peak: 330MB) WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000011000000010000000011001000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_50397384 Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 ....... Finished optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) BUFF_WIDTH=32'b00000000000000000000000000000111 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_7s_2s_1s_1s Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Opening data file miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block from directory . @W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur Running optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_buffer_7s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) REGS_ADDR_WIDTH=32'b00000000000000000000000000001100 ECC_ENABLE=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_gpr_ded_reset_en=1'b1 ICACHE_EN=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 REQ_BUFF_WIDTH=32'b00000000000000000000000000000111 REQ_BUFF_DEPTH=32'b00000000000000000000000000000010 LOG2_REQ_BUFF_DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s Running optimization stage 1 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s ....... Finished optimization stage 1 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s (CPU Time 0h:00m:00s, Memory Used current: 315MB peak: 330MB) CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_ADDR_WIDTH=32'b00000000000000000000000000100000 AHB_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 ECC_ENABLE=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_tcm1_present=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 ICACHE_EN=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 MAX_OS_I_TRX=32'b00000000000000000000000000000010 LOG2_MAX_OS_I_TRX=32'b00000000000000000000000000000001 MAX_OS_D_TRX=32'b00000000000000000000000000000010 LOG2_MAX_OS_D_TRX=32'b00000000000000000000000000000001 Generated name = miv_rv32_subsys_interconnect_Z18 Running optimization stage 1 on miv_rv32_subsys_interconnect_Z18 ....... Finished optimization stage 1 on miv_rv32_subsys_interconnect_Z18 (CPU Time 0h:00m:00s, Memory Used current: 290MB peak: 330MB) FAMILY=32'b00000000000000000000000000011010 CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_REGISTER_IO=32'b00000000000000000000000000000001 AHB_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 SUBSYS_CFG_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_UDMA_PRESENT=32'b00000000000000000000000000000000 TCM0_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM0_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM0_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 TCM_TAS_ADDR_WIDTH=32'b00000000000000000000000000100000 USE_BUS_PARITY=32'b00000000000000000000000000000000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM1_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM1_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_apb_start_addr=32'b01100000000000000000000000000000 l_apb_end_addr=32'b01101111111111111111111111111111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_udma_ctrl_start_addr=32'b00001111111111111111111111100000 l_udma_ctrl_end_addr=32'b00001111111111111111111111110001 l_subsys_cfg_start_addr=32'b00000000000000000110000000000000 l_subsys_cfg_end_addr=32'b00000000000000000110111111111111 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 l_tcm1_start_addr=32'b00000000000000001010000000000000 l_tcm1_end_addr=32'b00000000000000001010001000000000 l_tcm_tas_udma_ctrl_start_addr=32'b00001111111111111111111111101110 l_tcm_tas_udma_ctrl_end_addr=32'b00001111111111111111111111101111 l_tcm_tas_tcm0_start_addr=32'b00001111111111111111111111100100 l_tcm_tas_tcm0_end_addr=32'b00001111111111111111111111100101 l_tcm_tas_tcm1_start_addr=32'b00001111111111111111111111101100 l_tcm_tas_tcm1_end_addr=32'b00001111111111111111111111101101 l_subsys_cfg_tcm_tas_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_tas_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_tcm1_present=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_apb_present=32'b00000000000000000000000000000001 l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 l_hart_cfg_hw_debug=32'b00000000000000000000000000000001 l_hart_cfg_num_triggers=32'b00000000000000000000000000000010 l_hart_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_hart_cfg_hw_compressed=32'b00000000000000000000000000000001 l_hart_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_hart_reset_vector=32'b10000000000000000000000000000000 l_hart_static_mtvec_base=32'b10000000000000000000000000000100 l_hart_cfg_static_mtvec_base=1'b0 l_hart_cfg_static_mtvec_mode=1'b1 l_hart_static_mtvec_mode=2'b00 l_hart_num_sys_ext_irqs=32'b00000000000000000000000000000000 l_hart_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_hart_cfg_time_count_width=32'b00000000000000000000000001000000 RAM_SB_IN_WIDTH=32'b00000000000000000000000000000100 RAM_SB_OUT_WIDTH=32'b00000000000000000000000000000100 l_hart_cfg_lsu_fwd=1'b0 l_hart_cfg_csr_fwd=1'b0 l_hart_cfg_exu_fwd=1'b0 l_hart_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 INTERNAL_MTIME=32'b00000000000000000000000000000001 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000001 MTIME_PRESCALER=32'b00000000000000000000000001100100 BOOTROM_SRC_START_ADDR=32'b10000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b10000000000000000011111111111111 BOOTROM_DEST_ADDR=32'b01000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 ICACHE_EN=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 TCM_REGS=32'b00000000000000000000000000000000 I_REGS=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 ICACHE_DEPTH=32'b00000000000000000000000100000000 TCM0_DEPTH=32'b00000000000000001001000000000000 TCM0_WIDTH=32'b00000000000000000000000000010000 TCM1_DEPTH=32'b00000000000000000000000010000001 l_hart_total_sys_ext_irqs=32'b00000000000000000000000000000010 Generated name = miv_rv32_ipcore_Z19 l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 Generated name = miv_rv32_debug_dtm_jtag_1s @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16165:67:16165:73|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16173:67:16173:73|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16193:48:16193:54|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16194:48:16194:54|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16195:48:16195:54|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16196:48:16196:55|Removing redundant assignment. @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16380:45:16380:49|Removing redundant assignment. Running optimization stage 1 on miv_rv32_debug_dtm_jtag_1s ....... Finished optimization stage 1 on miv_rv32_debug_dtm_jtag_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB) WIDTH=32'b00000000000000000000000000101001 RESET_SYNC_WR_2_RD=32'b00000000000000000000000000000001 DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_debug_fifo_41s_1s_1s Running optimization stage 1 on miv_rv32_debug_fifo_41s_1s_1s ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15811:0:15811:5|Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers. @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Found RAM fifo_memory, depth=2, width=41 @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15791:0:15791:5|Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on miv_rv32_debug_fifo_41s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB) WIDTH=32'b00000000000000000000000000100010 RESET_SYNC_WR_2_RD=32'b00000000000000000000000000000001 DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_debug_fifo_34s_1s_1s Running optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15811:0:15811:5|Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers. @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Found RAM fifo_memory, depth=2, width=34 @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15791:0:15791:5|Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 1 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 291MB peak: 330MB) Running optimization stage 1 on miv_rv32_debug_sba ....... Finished optimization stage 1 on miv_rv32_debug_sba (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) Running optimization stage 1 on miv_rv32_debug_du ....... @W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal. @W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers. Finished optimization stage 1 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 Generated name = miv_rv32_subsys_debug_1s Running optimization stage 1 on miv_rv32_subsys_debug_1s ....... Finished optimization stage 1 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) NUM_REQS=32'b00000000000000000000000000000010 USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 Generated name = miv_rv32_rr_pri_arb_2s_1s_1s NUM_REQS=32'b00000000000000000000000000000010 Generated name = miv_rv32_fixed_arb_2s Running optimization stage 1 on miv_rv32_fixed_arb_2s ....... Finished optimization stage 1 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) Running optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s ....... Finished optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) APB_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_REGISTER_IO=32'b00000000000000000000000000000001 l_subsys_cfg_apb_byte_shim=1'b1 IDLE_ST=3'b000 SETUP_ST=3'b001 ACCESS_ST=3'b010 BH_READ_0_ST=3'b011 BH_READ_1_ST=3'b100 BH_WRITE_ST=3'b101 Generated name = miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 @N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6281:36:6281:48|Removing redundant assignment. Running optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 ....... Finished optimization stage 1 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) NUM_REQS=32'b00000000000000000000000000000011 USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 Generated name = miv_rv32_rr_pri_arb_3s_1s_1s NUM_REQS=32'b00000000000000000000000000000011 Generated name = miv_rv32_fixed_arb_3s Running optimization stage 1 on miv_rv32_fixed_arb_3s ....... Finished optimization stage 1 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) Running optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s ....... Finished optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 297MB peak: 330MB) FAMILY=32'b00000000000000000000000000011010 UDMA_PRESENT=32'b00000000000000000000000000000000 TCM_TAS_PRESENT=32'b00000000000000000000000000000000 DEBUG_PRESENT=32'b00000000000000000000000000000001 CPU_I_PRESENT=32'b00000000000000000000000000000001 CPU_D_PRESENT=32'b00000000000000000000000000000001 USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 RAM_SB_IN_WIDTH=32'b00000000000000000000000000000100 RAM_SB_OUT_WIDTH=32'b00000000000000000000000000000100 RAM_DEPTH=32'b00000000000000000010010000000000 TCM_ADDR_WIDTH=32'b00000000000000000000000000010000 ECC_ENABLE=32'b00000000000000000000000000000000 ROM=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR=32'b00000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b00000000000000000000000000000000 BOOTROM_DEST_ADDR=32'b00000000000000000000000000000000 TCM_REGS=32'b00000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 l_subsys_cfg_tcm_byte_shim=32'b00000000000000000000000000000001 RAM_DATA_WIDTH=32'b00000000000000000000000000100000 CPU_D_DEBUG_PRESENT=32'b00000000000000000000000000000001 NUM_REQUESTERS=32'b00000000000000000000000000000010 RAM_WEN_WIDTH=32'b00000000000000000000000000000001 UDMA_TAS_PRESENT=32'b00000000000000000000000000000000 BH_INIT=2'b00 BH_READ=2'b01 BH_WRITE=2'b10 Generated name = miv_rv32_subsys_tcm_Z20 Running optimization stage 1 on OR4 ....... Finished optimization stage 1 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on CFG2 ....... Finished optimization stage 1 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on CFG3 ....... Finished optimization stage 1 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on OR2 ....... Finished optimization stage 1 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 318MB peak: 330MB) Running optimization stage 1 on INV ....... Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 319MB peak: 330MB) RAM_DEPTH=32'b00000000000000000010010000000000 ADDR_WIDTH=32'b00000000000000000000000000001110 RAMINDEX_0=488'b00000000000000000101000001000110010111110101010001010000010100110101001001000001010011010101111101001101010000010101100001011111001100000010010100111001001100100011000100110110001011010011100100110010001100010011011000100101001100110011001000101101001100110011001000100101010100000100111101010111010001010101001000100101001100000010010100110000001001010101010001010111010011110010110101010000010011110101001001010100001001010100010101000011010000110101111101000101010011100010110100110000 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RAMINDEX_127=504'b000000000000000001010000010001100101111101010100010100000101001101010010010000010100110101011111010011010100000101011000010111110011000000100101001110010011001000110001001101100010110100111001001100100011000100110110001001010011001100110010001011010011001100110010001001010101000001001111010101110100010101010010001001010011000100110010001101110010010100110000001001010101010001010111010011110010110101010000010011110101001001010100001001010100010101000011010000110101111101000101010011100010110100110000 Generated name = miv_rv32_ram_singleport_lp_Z21 Running optimization stage 1 on miv_rv32_ram_singleport_lp_Z21 ....... @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25538:12:25538:44|Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25498:12:25498:43|Removing instance miv_rv32_ram_singleport_lp_R20C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25465:27:25465:41|Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25376:12:25376:43|Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25295:12:25295:43|Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25265:27:25265:41|Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25182:12:25182:43|Removing instance miv_rv32_ram_singleport_lp_R24C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25159:27:25159:41|Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25104:27:25104:40|Removing instance \CFG2_BLKY2[6] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25049:12:25049:43|Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24993:12:24993:43|Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24990:27:24990:33|Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24953:12:24953:43|Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24901:12:24901:44|Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24863:12:24863:43|Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24853:27:24853:41|Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24804:12:24804:43|Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24764:12:24764:43|Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24686:12:24686:44|Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24667:27:24667:41|Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24622:12:24622:44|Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24548:12:24548:43|Removing instance miv_rv32_ram_singleport_lp_R31C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24502:27:24502:41|Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24492:27:24492:41|Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24490:28:24490:34|Removing instance CFG3_22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24451:12:24451:43|Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24412:12:24412:43|Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24308:12:24308:43|Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24268:12:24268:43|Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24254:28:24254:34|Removing instance CFG3_11 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24231:27:24231:32|Removing instance CFG3_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24202:28:24202:34|Removing instance CFG3_21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24148:12:24148:43|Removing instance miv_rv32_ram_singleport_lp_R25C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24142:27:24142:41|Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24105:12:24105:43|Removing instance miv_rv32_ram_singleport_lp_R28C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24033:12:24033:43|Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24029:27:24029:40|Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23903:12:23903:44|Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23864:12:23864:44|Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23805:12:23805:43|Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23799:27:23799:40|Removing instance \CFG2_BLKY2[7] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23753:12:23753:44|Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23685:12:23685:43|Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23662:27:23662:40|Removing instance \CFG2_BLKY2[5] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23601:12:23601:44|Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23540:27:23540:41|Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23490:12:23490:43|Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23440:12:23440:43|Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23401:12:23401:44|Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23338:12:23338:43|Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23292:27:23292:41|Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23222:12:23222:43|Removing instance miv_rv32_ram_singleport_lp_R26C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23130:12:23130:43|Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23092:12:23092:43|Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23071:27:23071:41|Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23012:12:23012:43|Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22972:12:22972:44|Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22882:27:22882:41|Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22821:12:22821:43|Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22779:12:22779:43|Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22733:12:22733:43|Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22687:12:22687:43|Removing instance miv_rv32_ram_singleport_lp_R27C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22671:27:22671:41|Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22665:27:22665:41|Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22600:12:22600:43|Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22556:12:22556:44|Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22510:12:22510:43|Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22433:27:22433:41|Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22330:12:22330:43|Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22260:12:22260:43|Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22193:12:22193:43|Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22147:12:22147:43|Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22094:12:22094:43|Removing instance miv_rv32_ram_singleport_lp_R29C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21997:12:21997:44|Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21988:27:21988:41|Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21943:12:21943:43|Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21894:12:21894:43|Removing instance miv_rv32_ram_singleport_lp_R30C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21848:12:21848:43|Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21845:27:21845:40|Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21838:28:21838:33|Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21814:27:21814:41|Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21791:27:21791:41|Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21713:12:21713:44|Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21667:12:21667:43|Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21589:12:21589:43|Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21586:27:21586:41|Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21578:27:21578:41|Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21562:27:21562:41|Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21440:12:21440:43|Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21385:12:21385:43|Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21341:27:21341:41|Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21304:12:21304:43|Removing instance miv_rv32_ram_singleport_lp_R18C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21236:12:21236:44|Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21193:12:21193:43|Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21098:28:21098:33|Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Only the first 100 messages of id 'CL168' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL168' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL168} -count unlimited' in the Tcl shell. Finished optimization stage 1 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 332MB peak: 333MB) Running optimization stage 1 on miv_rv32_subsys_tcm_Z20 ....... @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10961:2:10961:7|Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers. @W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10961:2:10961:7|Pruning unused register tcm_tas_access_disable_reg. Make sure that there are no unused intermediate registers. @W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11237:2:11237:7|Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal. @W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 1 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 334MB) @W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1481:45:1481:63|Port-width mismatch for port cpu_i_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1494:45:1494:63|Port-width mismatch for port cpu_d_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1509:45:1509:66|Port-width mismatch for port udma_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. @W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1526:44:1526:64|Port-width mismatch for port tcm_tas_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port. INTERNAL_MTIME=32'b00000000000000000000000000000001 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000001 MTIME_PRESCALER=32'b00000000000000000000000001100100 SYNC_RESET=32'b00000000000000000000000000000001 l_mtime_addr_u=32'b00000010000000001011111111111100 l_mtimecmp_addr_u=32'b00000010000000000100000000000100 Generated name = miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 Running optimization stage 1 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 ....... Finished optimization stage 1 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on miv_rv32_ipcore_Z19 ....... Finished optimization stage 1 on miv_rv32_ipcore_Z19 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) FAMILY=32'b00000000000000000000000000011010 RESET_VECTOR_ADDR_1=16'b1000000000000000 RESET_VECTOR_ADDR_0=16'b0000000000000000 DEBUGGER=32'b00000000000000000000000000000001 I_TRACE=32'b00000000000000000000000000000000 AXI_INITIATOR_TYPE=32'b00000000000000000000000000000000 AXI_TARGET_MIRROR=32'b00000000000000000000000000000000 AXI_START_ADDR_1=16'b0110000000000000 AXI_START_ADDR_0=16'b0000000000000000 AXI_END_ADDR_1=16'b0110111111111111 AXI_END_ADDR_0=16'b1111111111111111 AHB_INITIATOR_TYPE=32'b00000000000000000000000000000000 AHB_TARGET_MIRROR=32'b00000000000000000000000000000000 AHB_START_ADDR_1=16'b1000000000000000 AHB_START_ADDR_0=16'b0000000000000000 AHB_END_ADDR_1=16'b1000111111111111 AHB_END_ADDR_0=16'b1111111111111111 APB_INITIATOR_TYPE=32'b00000000000000000000000000000001 APB_TARGET_MIRROR=32'b00000000000000000000000000000000 APB_START_ADDR_1=16'b0110000000000000 APB_START_ADDR_0=16'b0000000000000000 APB_END_ADDR_1=16'b0110111111111111 APB_END_ADDR_0=16'b1111111111111111 TCM_PRESENT=32'b00000000000000000000000000000001 TCM_START_ADDR_1=16'b1000000000000000 TCM_START_ADDR_0=16'b0000000000000000 TCM_END_ADDR_1=16'b1000000000000000 TCM_END_ADDR_0=16'b1000111111111111 TCM_TAS_PRESENT=32'b00000000000000000000000000000000 TAS_START_ADDR_1=16'b0100000000000000 TAS_START_ADDR_0=16'b0000000000000000 TAS_END_ADDR_1=16'b0100000000000000 TAS_END_ADDR_0=16'b0011111111111111 C_EXT=32'b00000000000000000000000000000001 F_EXT=32'b00000000000000000000000000000000 M_EXT=32'b00000000000000000000000000000001 GEN_MUL_TYPE=32'b00000000000000000000000000000000 VECTORED_INTERRUPTS=32'b00000000000000000000000000000000 NUM_EXT_IRQS=32'b00000000000000000000000000000000 FWD_REGS=32'b00000000000000000000000000000000 ECC_ENABLE=32'b00000000000000000000000000000000 NO_MACC_BLK=32'b00000000000000000000000000000000 INTERNAL_MTIME=32'b00000000000000000000000000000001 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000001 MTIME_PRESCALER=32'b00000000000000000000000001100100 GPR_REGS=32'b00000000000000000000000000000000 BOOTROM_PRESENT=32'b00000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR_UPPER=16'b1000000000000000 BOOTROM_SRC_START_ADDR_LOWER=16'b0000000000000000 BOOTROM_SRC_END_ADDR_UPPER=16'b1000000000000000 BOOTROM_SRC_END_ADDR_LOWER=16'b0011111111111111 BOOTROM_DEST_ADDR_UPPER=16'b0100000000000000 BOOTROM_DEST_ADDR_LOWER=16'b0000000000000000 ICACHE_EN=32'b00000000000000000000000000000000 MI_I_MEM=32'b00000000000000000000000000000000 TCM_REGS=32'b00000000000000000000000000000000 I_REGS=32'b00000000000000000000000000000000 MIV_HART_ID=32'b00000000000000000000000000000000 l_miv_rv32_version=32'b00000011000000010000000011001000 USE_BUS_PARITY=32'b00000000000000000000000000000000 TCM0_UDMA_PRESENT=32'b00000000000000000000000000000000 APB_REGISTER_IO=32'b00000000000000000000000000000001 CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_ADDR_WIDTH=32'b00000000000000000000000000100000 AHB_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 SUBSYS_CFG_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM0_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM0_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 TCM_TAS_ADDR_WIDTH=32'b00000000000000000000000000100000 MAX_EXT_IRQS=32'b00000000000000000000000000001000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM1_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM1_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 l_subsys_cfg_axi_present=32'b00000000000000000000000000000000 l_subsys_cfg_ahb_present=32'b00000000000000000000000000000000 l_subsys_cfg_apb_present=32'b00000000000000000000000000000001 l_subsys_cfg_hart_debug=32'b00000000000000000000000000000001 l_hart_cfg_hw_debug=32'b00000000000000000000000000000001 l_hart_cfg_num_triggers=32'b00000000000000000000000000000010 l_subsys_cfg_tcm_tas_present=32'b00000000000000000000000000000000 l_subsys_cfg_tcm0_tas_present=32'b00000000000000000000000000000000 l_apb_start_addr=32'b01100000000000000000000000000000 l_apb_end_addr=32'b01101111111111111111111111111111 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001000111111111111 l_tcm_tas_tcm0_start_addr=32'b00001111111111111111111111100100 l_tcm_tas_tcm0_end_addr=32'b00001111111111111111111111100101 l_axi_start_addr=32'b00001111111111111111111111100110 l_axi_end_addr=32'b00001111111111111111111111100111 l_ahb_start_addr=32'b00001111111111111111111111101000 l_ahb_end_addr=32'b00001111111111111111111111101001 l_tcm1_start_addr=32'b00000000000000001010000000000000 l_tcm1_end_addr=32'b00000000000000001010001000000000 l_tcm_tas_tcm1_start_addr=32'b00001111111111111111111111101100 l_tcm_tas_tcm1_end_addr=32'b00001111111111111111111111101101 l_tcm_tas_udma_ctrl_start_addr=32'b00001111111111111111111111101110 l_tcm_tas_udma_ctrl_end_addr=32'b00001111111111111111111111101111 l_udma_ctrl_start_addr=32'b00001111111111111111111111100000 l_udma_ctrl_end_addr=32'b00001111111111111111111111110001 l_subsys_cfg_start_addr=32'b00000000000000000110000000000000 l_subsys_cfg_end_addr=32'b00000000000000000110111111111111 l_hart_cfg_time_count_width=32'b00000000000000000000000001000000 l_subsys_cfg_tcm0_present=32'b00000000000000000000000000000001 l_subsys_cfg_tcm1_present=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR=32'b10000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b10000000000000000011111111111111 BOOTROM_DEST_ADDR=32'b01000000000000000000000000000000 l_hart_reset_vector=32'b10000000000000000000000000000000 l_hart_mtvec_offset=28'b0000000000000000000000000100 l_hart_static_mtvec_base=32'b10000000000000000000000000000100 l_hart_cfg_static_mtvec_base=1'b0 l_hart_cfg_static_mtvec_mode=1'b1 l_hart_static_mtvec_mode=2'b00 l_hart_cfg_hw_compressed=32'b00000000000000000000000000000001 l_hart_cfg_hw_sp_float=32'b00000000000000000000000000000000 l_hart_cfg_hw_multiply_divide=32'b00000000000000000000000000000001 l_hart_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_hart_num_sys_ext_irqs=32'b00000000000000000000000000000000 l_hart_cfg_lsu_fwd=1'b0 l_hart_cfg_csr_fwd=1'b0 l_hart_cfg_exu_fwd=1'b0 l_hart_cfg_gpr_type=1'b0 l_icache_en=32'b00000000000000000000000000000000 l_mi_i_mem=32'b00000000000000000000000000000000 Generated name = MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v":343:13:343:33|Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it. Running optimization stage 1 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 ....... Finished optimization stage 1 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v":305:34:305:52|Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on MIV_RV32_C0 ....... Finished optimization stage 1 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PLL ....... Finished optimization stage 1 on PLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_CCC_0_PF_CCC_0_0_PF_CCC ....... Finished optimization stage 1 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_CCC_0 ....... Finished optimization stage 1 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on INIT ....... Finished optimization stage 1 on INIT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on BANKEN ....... Finished optimization stage 1 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR ....... Finished optimization stage 1 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on pf_init_monitor_0 ....... Finished optimization stage 1 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) ST_RSWT=2'b00 ST_RWAT=2'b01 ST_LSWT=2'b10 ST_LWAT=2'b11 STEP=32'b00000000000000000000000000000011 COMP0_STEP=32'b00000000000000000000000000000000 COMP1_STEP=32'b00000000000000000000000000000100 COMP2_STEP=32'b00000000000000000000000000000001 COMP3_STEP=32'b00000000000000000000000000000001 EYEWIDTH=3'b001 Generated name = CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 Running optimization stage 1 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 ....... Finished optimization stage 1 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on OUTBUF_DIFF ....... Finished optimization stage 1 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on IOD ....... Finished optimization stage 1 on IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:45:70:45|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:54:70:54|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":64:23:64:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":67:13:67:13|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:34:49:34|Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:46:49:46|Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:59:49:59|Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:17:50:17|Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:26:50:26|Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:41:50:41|Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:55:50:55|Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:69:50:69|Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:21:51:21|Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:35:51:35|Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:49:51:49|Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:65:51:65|Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:19:52:19|Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:34:52:34|Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:59:52:59|Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:20:54:20|Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:36:54:36|Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":59:21:59:21|Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:23:94:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:32:94:32|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on LANECTRL ....... Finished optimization stage 1 on LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) ENABLE_PAUSE_EXTENSION=2'b00 Generated name = PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it. Running optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL ....... Finished optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on RCLKINT ....... Finished optimization stage 1 on RCLKINT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_C0 ....... Finished optimization stage 1 on PF_IOD_CDR_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on HS_IO_CLK ....... Finished optimization stage 1 on HS_IO_CLK (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) @W: CG168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":47:27:47:36|Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on DLL ....... Finished optimization stage 1 on DLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on ICB_CLKDIV ....... Finished optimization stage 1 on ICB_CLKDIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on COREDELAYCODE_TIP ....... Finished optimization stage 1 on COREDELAYCODE_TIP (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) ENABLE_PAUSE_EXTENSION=2'b00 Generated name = PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 @W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it. Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_IOD_CDR_CCC_C0 ....... Finished optimization stage 1 on PF_IOD_CDR_CCC_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM ....... Finished optimization stage 1 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on PF_TPSRAM_C0 ....... Finished optimization stage 1 on PF_TPSRAM_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on SSDetect ....... Finished optimization stage 1 on SSDetect (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 1 on top ....... Finished optimization stage 1 on top (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on top ....... Finished optimization stage 2 on top (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on SSDetect ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v":24:12:24:18|Input port bits 9 to 7 of rx_data[9:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on SSDetect (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_TPSRAM_C0 ....... Finished optimization stage 2 on PF_TPSRAM_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM ....... Finished optimization stage 2 on PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0 ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 ....... @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":15:7:15:9|Input CLK is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":15:12:15:16|Input RESET is unused. Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on COREDELAYCODE_TIP ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v":59:0:59:5|Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on COREDELAYCODE_TIP (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on ICB_CLKDIV ....... Finished optimization stage 2 on ICB_CLKDIV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC ....... Finished optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on DLL ....... Finished optimization stage 2 on DLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on HS_IO_CLK ....... Finished optimization stage 2 on HS_IO_CLK (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0 ....... @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v":70:13:70:20|Input DLL_LOCK is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v":77:13:77:20|Input PLL_LOCK is unused. Finished optimization stage 2 on PF_IOD_CDR_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on RCLKINT ....... Finished optimization stage 2 on RCLKINT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 ....... @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":15:7:15:9|Input CLK is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":15:12:15:16|Input RESET is unused. Finished optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on LANECTRL ....... Finished optimization stage 2 on LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD ....... Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD ....... @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":31:7:31:13|Input FAB_CLK is unused. Finished optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on IOD ....... Finished optimization stage 2 on IOD (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on OUTBUF_DIFF ....... Finished optimization stage 2 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|Trying to extract state machine for register tune_st. Extracted state machine for register tune_st State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on pf_init_monitor_0 ....... Finished optimization stage 2 on pf_init_monitor_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR ....... Finished optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on BANKEN ....... Finished optimization stage 2 on BANKEN (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on INIT ....... Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_CCC_0 ....... Finished optimization stage 2 on PF_CCC_0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC ....... Finished optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on PLL ....... Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on MIV_RV32_C0 ....... Finished optimization stage 2 on MIV_RV32_C0 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 ....... Finished optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 ....... @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13005:27:13005:40|Input mtime_count_in is unused. Finished optimization stage 2 on miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 ....... Finished optimization stage 2 on miv_rv32_ram_singleport_lp_Z21 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on INV ....... Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on OR2 ....... Finished optimization stage 2 on OR2 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on CFG3 ....... Finished optimization stage 2 on CFG3 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on CFG2 ....... Finished optimization stage 2 on CFG2 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on OR4 ....... Finished optimization stage 2 on OR4 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_subsys_tcm_Z20 ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Trying to extract state machine for register cpu_d_wr_rd_state. Extracted state machine for register cpu_d_wr_rd_state State machine has 3 reachable states with original encodings of: 00 01 10 @W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10831:49:10831:62|Input port bits 1 to 0 of cpu_i_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10844:49:10844:62|Input port bits 1 to 0 of cpu_d_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size. @A: CL153 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10889:49:10889:62|*Unassigned bits of tcm_ram_sb_out[3:0] are referenced and tied to 0 -- simulation mismatch possible. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10821:49:10821:64|Input subsys_parity_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10830:49:10830:68|Input cpu_i_req_rd_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10832:49:10832:64|Input cpu_i_req_addr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10834:49:10834:64|Input cpu_i_resp_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10840:49:10840:68|Input cpu_d_req_rd_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10842:49:10842:62|Input cpu_d_req_read is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10843:49:10843:63|Input cpu_d_req_write is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10845:49:10845:64|Input cpu_d_req_addr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10847:49:10847:67|Input cpu_d_req_wr_data_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10849:49:10849:64|Input cpu_d_resp_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10855:49:10855:62|Input udma_req_valid is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10857:49:10857:67|Input udma_req_rd_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10858:49:10858:67|Input udma_req_wr_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10859:49:10859:61|Input udma_req_read is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10860:49:10860:62|Input udma_req_write is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10861:49:10861:61|Input udma_req_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10862:49:10862:63|Input udma_req_addr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10863:49:10863:60|Input udma_req_len is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10864:49:10864:64|Input udma_req_wr_data is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10865:49:10865:66|Input udma_req_wr_data_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10867:49:10867:63|Input udma_resp_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10874:49:10874:70|Input tcm_dma_access_disable is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10875:49:10875:70|Input tcm_tas_access_disable is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10876:49:10876:65|Input tcm_tas_req_valid is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10878:49:10878:70|Input tcm_tas_req_rd_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10879:49:10879:70|Input tcm_tas_req_wr_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10880:49:10880:64|Input tcm_tas_req_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10881:49:10881:66|Input tcm_tas_req_addr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10882:49:10882:67|Input tcm_tas_req_wr_data is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10883:49:10883:69|Input tcm_tas_req_wr_data_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10885:49:10885:66|Input tcm_tas_resp_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10890:49:10890:61|Input tcm_ram_sb_in is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10891:49:10891:71|Input tcm_ecc_error_injection is unused. Finished optimization stage 2 on miv_rv32_subsys_tcm_Z20 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_fixed_arb_3s ....... Finished optimization stage 2 on miv_rv32_fixed_arb_3s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr. Extracted state machine for register hipri_req_ptr State machine has 7 reachable states with original encodings of: 001 010 011 100 101 110 111 Finished optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Trying to extract state machine for register gen_apb_byte_shim.apb_st. Extracted state machine for register gen_apb_byte_shim.apb_st State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6063:49:6063:64|Input subsys_parity_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6070:49:6070:68|Input cpu_i_req_rd_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6072:49:6072:64|Input cpu_i_req_addr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6074:49:6074:64|Input cpu_i_resp_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6080:49:6080:68|Input cpu_d_req_rd_byte_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6083:49:6083:64|Input cpu_d_req_addr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6087:49:6087:64|Input cpu_d_resp_ready is unused. Finished optimization stage 2 on miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5 (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_fixed_arb_2s ....... Finished optimization stage 2 on miv_rv32_fixed_arb_2s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr. Extracted state machine for register hipri_req_ptr State machine has 3 reachable states with original encodings of: 01 10 11 Finished optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_subsys_debug_1s ....... Finished optimization stage 2 on miv_rv32_subsys_debug_1s (CPU Time 0h:00m:00s, Memory Used current: 333MB peak: 353MB) Running optimization stage 2 on miv_rv32_debug_du ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14736:0:14736:8|Trying to extract state machine for register debug_state. Extracted state machine for register debug_state State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Trying to extract state machine for register command_reg_state. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13800:39:13800:52|Input dmi_resp_ready is unused. Finished optimization stage 2 on miv_rv32_debug_du (CPU Time 0h:00m:00s, Memory Used current: 334MB peak: 353MB) Running optimization stage 2 on miv_rv32_debug_sba ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|Trying to extract state machine for register sba_state. Extracted state machine for register sba_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on miv_rv32_debug_sba (CPU Time 0h:00m:01s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s ....... Finished optimization stage 2 on miv_rv32_debug_fifo_34s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_debug_fifo_41s_1s_1s ....... Finished optimization stage 2 on miv_rv32_debug_fifo_41s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_debug_dtm_jtag_1s ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|Trying to extract state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat. Extracted state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat State machine has 4 reachable states with original encodings of: 00 01 10 11 @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Trying to extract state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState. Extracted state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15942:48:15942:60|Input dtm_req_ready is unused. Finished optimization stage 2 on miv_rv32_debug_dtm_jtag_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_ipcore_Z19 ....... @A: CL153 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":545:47:545:65|*Unassigned bits of ahb_i_resp_last_net are referenced and tied to 0 -- simulation mismatch possible. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":191:50:191:60|Input m_timer_irq is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":227:50:227:72|Input tcm1_cpu_access_disable is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":228:50:228:72|Input tcm1_dma_access_disable is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":229:50:229:72|Input tcm1_tas_access_disable is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":230:50:230:62|Input tcm_tas_paddr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":231:50:231:64|Input tcm_tas_paddr_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":232:50:232:62|Input tcm_tas_pprot is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":233:50:233:61|Input tcm_tas_psel is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":234:50:234:64|Input tcm_tas_penable is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":235:50:235:63|Input tcm_tas_pwrite is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":236:50:236:63|Input tcm_tas_pwdata is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":237:50:237:65|Input tcm_tas_pwdata_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":248:50:248:63|Input tcm1_ram_sb_in is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":252:50:252:60|Input axi_aclk_en is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":261:50:261:60|Input axi_arready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":264:50:264:58|Input axi_rresp is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":265:50:265:58|Input axi_rdata is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":266:50:266:58|Input axi_rlast is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":267:50:267:56|Input axi_rid is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":269:50:269:59|Input axi_rvalid is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":270:50:270:61|Input axi_r_data_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":280:50:280:60|Input axi_awready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":286:50:286:59|Input axi_wready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":289:50:289:58|Input axi_bresp is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":290:50:290:56|Input axi_bid is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":292:50:292:59|Input axi_bvalid is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":305:50:305:59|Input ahb_hrdata is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":306:50:306:61|Input ahb_hrdata_p is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":307:50:307:59|Input ahb_hready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":308:50:308:58|Input ahb_hresp is unused. Finished optimization stage 2 on miv_rv32_ipcore_Z19 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_subsys_interconnect_Z18 ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2494:49:2494:66|Input port bits 11 to 0 of cfg_apb_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2495:49:2495:64|Input port bits 11 to 0 of cfg_apb_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2500:49:2500:73|Input port bits 11 to 0 of cfg_subsys_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2501:49:2501:71|Input port bits 11 to 0 of cfg_subsys_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2502:49:2502:67|Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2503:49:2503:65|Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2492:49:2492:66|Input cfg_axi_start_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2493:49:2493:64|Input cfg_axi_end_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2496:49:2496:66|Input cfg_ahb_start_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2497:49:2497:64|Input cfg_ahb_end_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2498:49:2498:72|Input cfg_udma_ctrl_start_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2499:49:2499:70|Input cfg_udma_ctrl_end_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2504:49:2504:67|Input cfg_tcm1_start_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2505:49:2505:65|Input cfg_tcm1_end_addr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2575:49:2575:63|Input apb_trx_os_d_rd is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2576:49:2576:63|Input apb_trx_os_d_wr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2604:49:2604:64|Input tcm0_trx_os_d_rd is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2605:49:2605:64|Input tcm0_trx_os_d_wr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2611:49:2611:64|Input tcm1_i_req_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2621:49:2621:64|Input tcm1_d_req_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2635:49:2635:64|Input tcm1_trx_os_d_rd is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2636:49:2636:64|Input tcm1_trx_os_d_wr is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2642:49:2642:63|Input axi_i_req_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2647:49:2647:63|Input axi_i_resp_last is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2653:49:2653:63|Input axi_d_req_ready is unused. @N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2668:49:2668:63|Input axi_trx_os_d_rd is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Finished optimization stage 2 on miv_rv32_subsys_interconnect_Z18 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4490:49:4490:71|Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4495:49:4495:68|Input port bits 31 to 3 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_buffer_7s_2s_1s_1s ....... @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=7 Finished optimization stage 2 on miv_rv32_buffer_7s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_50397384 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_buffer_11s_2s_1s_1s ....... @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=11 Finished optimization stage 2 on miv_rv32_buffer_11s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_buffer_6s_2s_1s_1s ....... @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=6 Finished optimization stage 2 on miv_rv32_buffer_6s_2s_1s_1s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_hart_Z17 ....... Finished optimization stage 2 on miv_rv32_hart_Z17 (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_gpr_ram_array_32s_6s_32s ....... @W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6360:31:6360:36|Input port bit 5 of waddr0[5:0] is unused Finished optimization stage 2 on miv_rv32_gpr_ram_array_32s_6s_32s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s ....... Finished optimization stage 2 on miv_rv32_gpr_ram_0s_0_0s_32s (CPU Time 0h:00m:00s, Memory Used current: 350MB peak: 355MB) Running optimization stage 2 on miv_rv32_expipe_Z16 ....... Finished optimization stage 2 on miv_rv32_expipe_Z16 (CPU Time 0h:00m:01s, Memory Used current: 345MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_536870913 (CPU Time 0h:00m:00s, Memory Used current: 345MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_privarch_Z15 ....... @W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":1854:60:1854:72|Input port bit 1 of excpt_trigger[1:0] is unused Finished optimization stage 2 on miv_rv32_csr_privarch_Z15 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_decode_0s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_priv_irq_2s_0_0 ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6896:43:6896:57|Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on miv_rv32_priv_irq_2s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_irq_reg_0s ....... Finished optimization stage 2 on miv_rv32_irq_reg_0s (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_bcu ....... Finished optimization stage 2 on miv_rv32_bcu (CPU Time 0h:00m:00s, Memory Used current: 346MB peak: 364MB) Running optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 ....... @W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Finished optimization stage 2 on miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 (CPU Time 0h:00m:02s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s ....... Finished optimization stage 2 on miv_rv32_csr_decode_1s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s ....... Finished optimization stage 2 on miv_rv32_idecode_1_1s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s ....... @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Finished optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 ....... Finished optimization stage 2 on miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s ....... @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=16 @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32 @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2 @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2 Finished optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on INBUF_DIFF ....... Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on fifo_to_tpsram_bridge ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|Trying to extract state machine for register state. Extracted state machine for register state State machine has 2 reachable states with original encodings of: 00 01 Finished optimization stage 2 on fifo_to_tpsram_bridge (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0 ....... Finished optimization stage 2 on CoreUARTapb_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":104:20:104:24|Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size. @A: CL153 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":158:20:158:30|*Unassigned bits of controlReg3[2:0] are referenced and tied to 0 -- simulation mismatch possible. Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s ....... Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":286:0:286:5|Trying to extract state machine for register rx_state. Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Trying to extract state machine for register xmit_state. Extracted state machine for register xmit_state State machine has 6 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s ....... Finished optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CORETSE_0 ....... Finished optimization stage 2 on CORETSE_0 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 ....... Finished optimization stage 2 on CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CORETSE_Z11 ....... Finished optimization stage 2 on CORETSE_Z11 (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CORE_26s_0s_18s_0s ....... Finished optimization stage 2 on CTSE_MSGMII_CORE_26s_0s_18s_0s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CNVRXO_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVRXO_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_CNVRXI_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVRXI_26s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_TBI_26s_0s_0s_1s ....... Finished optimization stage 2 on CTSE_MSGMII_TBI_26s_0s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PETCR_26s_1s ....... Finished optimization stage 2 on CTSE_PETCR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_PETBM_26s_0s_1s ....... Finished optimization stage 2 on CTSE_PETBM_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 377MB peak: 397MB) Running optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s ....... Finished optimization stage 2 on CTSE_MSGMII_PEANX_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 397MB) Running optimization stage 2 on CTSE_PEANX_SYNC_1s_26s ....... Finished optimization stage 2 on CTSE_PEANX_SYNC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 397MB) Running optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s ....... Extracted state machine for register lI101 State machine has 4 reachable states with original encodings of: 00 01 10 11 Finished optimization stage 2 on CTSE_PEREX_PCS_0s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_R10B8B ....... Finished optimization stage 2 on CTSE_R10B8B (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 ....... Finished optimization stage 2 on CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s ....... Finished optimization stage 2 on CTSE_PETEX_TOP_26s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_T8B10B ....... Finished optimization stage 2 on CTSE_T8B10B (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_MSGMII_CNVTXO_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVTXO_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_MSGMII_CNVTXI_26s ....... Finished optimization stage 2 on CTSE_MSGMII_CNVTXI_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s ....... Finished optimization stage 2 on CTSE_RX4096X36_12s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s ....... Finished optimization stage 2 on CTSE_TX2048X40_11s_26s_1s_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_CORETSE_TOP_Z10 ....... Finished optimization stage 2 on CTSE_CORETSE_TOP_Z10 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_ECC_0s_26s_16s ....... Finished optimization stage 2 on CTSE_ECC_0s_26s_16s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s ....... Finished optimization stage 2 on CTSE_PEMSTAT_LINC_ECC_16s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_CLKRST_26s_1s ....... Finished optimization stage 2 on CTSE_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_SI_SAL_26s ....... Finished optimization stage 2 on CTSE_SI_SAL_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_MMCXWOL_1s_26s ....... Finished optimization stage 2 on CTSE_MMCXWOL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s ....... Finished optimization stage 2 on CTSE_PEMSTAT_EIM_26s_1s_0s (CPU Time 0h:00m:01s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_STORE_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_STORE_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SINCNF_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SINCHD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_SINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_LADD_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_LINC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s ....... Finished optimization stage 2 on CTSE_PEMSTAT_CNTRL_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s ....... Finished optimization stage 2 on CTSE_SIB_SYNC_PULSE_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_TSMAC_TOP_Z9 ....... Finished optimization stage 2 on CTSE_TSMAC_TOP_Z9 (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s ....... Finished optimization stage 2 on CTSE_PE_MCXMAC_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PECAR_26s_1s ....... Finished optimization stage 2 on CTSE_PECAR_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEHST_1s_26s ....... Finished optimization stage 2 on CTSE_PEHST_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PEMGT_1s_26s ....... Extracted state machine for register l0i11 State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Finished optimization stage 2 on CTSE_PEMGT_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s ....... Finished optimization stage 2 on CTSE_PE_MCXMAC_CORE_26s_0_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PERMC_TOP_1s_26s ....... Finished optimization stage 2 on CTSE_PERMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s ....... Finished optimization stage 2 on CTSE_PERFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 378MB peak: 398MB) Running optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s ....... Finished optimization stage 2 on CTSE_PETFN_TOP_26s_0s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_PECRC_1s_26s ....... Finished optimization stage 2 on CTSE_PECRC_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_PETMC_TOP_1s_26s ....... Finished optimization stage 2 on CTSE_PETMC_TOP_1s_26s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s ....... Finished optimization stage 2 on OiOI1_26s_11s_12s_32s_2s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s ....... Finished optimization stage 2 on CTSE_SIB_SYNC_2FLP_1s_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s ....... Finished optimization stage 2 on CTSE_AMCXFIF_CLKRST_26s_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXFIF_HST_Z8 ....... Finished optimization stage 2 on CTSE_AMCXFIF_HST_Z8 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 ....... Finished optimization stage 2 on CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s ....... Finished optimization stage 2 on CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s ....... Extracted state machine for register genblk1.O0Il1 State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 Finished optimization stage 2 on CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s ....... Finished optimization stage 2 on CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s ....... Finished optimization stage 2 on CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s ....... Finished optimization stage 2 on CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s ....... Finished optimization stage 2 on CTSE_TSM_SYSREG_26s_1s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CTSE_DECODER ....... Finished optimization stage 2 on CTSE_DECODER (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CORESPI_0 ....... Finished optimization stage 2 on CORESPI_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CORESPI_Z7 ....... Finished optimization stage 2 on CORESPI_Z7 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on spi_32s_16s_32s_16s_0_0_1_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on spi_chanctrl_Z6 ....... @W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Trying to extract state machine for register mtx_state. Extracted state machine for register mtx_state State machine has 6 reachable states with original encodings of: 0000 0001 0010 0111 1000 1001 Finished optimization stage 2 on spi_chanctrl_Z6 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on spi_clockmux ....... Finished optimization stage 2 on spi_clockmux (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on spi_fifo_16s_32s_5 ....... @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=1 @N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=16 Finished optimization stage 2 on spi_fifo_16s_32s_5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on spi_control_16s ....... Finished optimization stage 2 on spi_control_16s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on spi_rf_32s_16s_0 ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on spi_rf_32s_16s_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREJTAGDEBUG_C0 ....... Finished optimization stage 2 on COREJTAGDEBUG_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CLKINT ....... Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 ....... Finished optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on BUFD ....... Finished optimization stage 2 on BUFD (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on corejtagdebug_bufd_34s ....... Finished optimization stage 2 on corejtagdebug_bufd_34s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on UJTAG ....... Finished optimization stage 2 on UJTAG (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREJTAGDEBUG_Z5 ....... Finished optimization stage 2 on COREJTAGDEBUG_Z5 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREFIFO_C0 ....... Finished optimization stage 2 on COREFIFO_C0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_LSRAM_top (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on VCC ....... Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on GND ....... Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on RAM1K20 ....... Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 ....... Finished optimization stage 2 on COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CoreAPB3_0 ....... Finished optimization stage 2 on CoreAPB3_0 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on CoreAPB3_Z1 ....... @W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Finished optimization stage 2 on CoreAPB3_Z1 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Finished optimization stage 2 on COREAPB3_MUXPTOB3 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on Core_reset_pf ....... Finished optimization stage 2 on Core_reset_pf (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF ....... @N: CL135 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":58:0:58:5|Found sequential shift dff with address depth of 16 words and data bit width of 1. Finished optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on BIBUF ....... Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) Running optimization stage 2 on AND2 ....... Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 380MB peak: 398MB) For a summary of runtime per design unit, please see file: ========================================================== @L: E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\layer0.duruntime