0 1 1 1 0
0 0 0 1 0 0 0 12 nlvsdcanvas1 3492 1.3
inst,AND2_2, -pg 1 -lvl 1 -y 30,,,,0,,,,,,
inst,BIBUF_0, -pg 1 -lvl 1 -y 130,,,,0,,,,,,
inst,COREJTAGDEBUG_C0_0, -pg 1 -lvl 1 -y 180,280 177,TCK;TDI;TDO;TGT_TCK_0;TGT_TDI_0;TGT_TDO_0;TGT_TMS_0;TGT_TRSTN_0;TMS;TRSTB;,,0,,,,,,
inst,CORESPI_0_0, -pg 1 -lvl 2 -y 130,190 377,SPISS[0];SPISS[1];SPISS[2];SPISS[3];SPISS[4];SPISS[5];SPISS[6];SPISS[7];,,0,,,,,,
inst,CORETSE_0, -pg 1 -lvl 2 -y 560,300 617,ANX_STATE[0];ANX_STATE[1];ANX_STATE[2];ANX_STATE[3];ANX_STATE[4];ANX_STATE[5];ANX_STATE[6];ANX_STATE[7];ANX_STATE[8];ANX_STATE[9];,,0,,,,,,
inst,CoreAPB3_0_0, -pg 1 -lvl 1 -y 230,210 117,,,0,,,,,,
inst,CoreUARTapb_0, -pg 1 -lvl 3 -y -70,190 177,,,0,,,,,,
inst,Core_reset_pf_0, -pg 1 -lvl 1 -y 290,310 237,,,0,,,,,,
inst,INBUF_DIFF_0, -pg 1 -lvl 3 -y 100,,,,0,,,,,,
inst,MIV_RV32_C0_0, -pg 1 -lvl 3 -y 300,310 277,EXT_IRQ;JTAG_TCK;JTAG_TDI;JTAG_TDO;JTAG_TDO_DR;JTAG_TMS;JTAG_TRSTN;,,0,,,,,,
inst,PF_CCC_0_0, -pg 1 -lvl 3 -y 100,290 97,,,0,,,,,,
inst,PF_IOD_CDR_C0_0, -pg 1 -lvl 1 -y -190,240 177,,,0,,,,,,
inst,PF_IOD_CDR_CCC_C0_0, -pg 1 -lvl 1 -y -20,180 117,,,0,,,,,,
inst,SSDetect_0, -pg 1 -lvl 2 -y 310,200 117,,,0,,,,,,
inst,pf_init_monitor_0_0, -pg 1 -lvl 3 -y 770,280 337,,,0,,,,,,
inst,top,,,,,0,,,,,,
net,AND2_2_Y,,
net,BIBUF_0_Y,,
net,COREJTAGDEBUG_C0_0_TGT_TCK_0,,
net,COREJTAGDEBUG_C0_0_TGT_TDI_0,,
net,COREJTAGDEBUG_C0_0_TGT_TMS_0,,
net,COREJTAGDEBUG_C0_0_TGT_TRSTN_0,,
net,CORETSE_0_MDO,,
net,CORETSE_0_MDOEN,,
net,CORETSE_0_MRXBYTEVALID,,
net,CORETSE_0_MRXDAT,,
net,CORETSE_0_MRXEOF,,
net,CORETSE_0_MRXRDY,,
net,CORETSE_0_MRXSOF,,
net,CORETSE_0_MTXACPT,,
net,CORETSE_0_TCG,,
net,CoreAPB3_0_0_APBmslave0,,
net,CoreAPB3_0_0_APBmslave1,,
net,CoreAPB3_0_0_APBmslave2,,
net,Core_reset_pf_0_PLL_POWERDOWN_B,,
net,INBUF_DIFF_0_Y,,
net,LINK_OK,,
net,MIV_RV32_C0_0_APB_INITIATOR,,
net,MIV_RV32_C0_0_JTAG_TDO,,
net,PF_CCC_0_0_OUT0_FABCLK_0,,
net,PF_CCC_0_0_PLL_LOCK_0,,
net,PF_IOD_CDR_C0_0_RX_CLK_R,,
net,PF_IOD_CDR_C0_0_RX_DATA,,
net,PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS,,
net,PF_IOD_CDR_CCC_C0_0_PLL_LOCK,,
net,PF_IOD_CDR_CCC_C0_0_TX_CLK_G,,
net,PHY_MDC,,
net,PHY_MDIO,,
net,PHY_RST,,
net,RD_BC_ERROR,,
net,REFCLK_N,,
net,REFCLK_P,,
net,REF_CLK_0,,
net,RESET_N,,
net,RX,,
net,RX_N,,
net,RX_P,,
net,SPISCLKO,,
net,SPISDI,,
net,SPISDO,,
net,SPISS,,
net,SSDetect_0_stream_start,,
net,TCK,,
net,TDI,,
net,TDO,,
net,TMS,,
net,TRSTB,,
net,TX,,
net,TX_N,,
net,TX_P,,
net,pf_init_monitor_0_0_BANK_6_VDDI_STATUS,,
net,pf_init_monitor_0_0_DEVICE_INIT_DONE,,
net,pf_init_monitor_0_0_FABRIC_POR_N,,
pg,1,0 0,1,-688 -310,0,1,
port,LINK_OK, -pg 1 -lvl 1:0 -y 20,,,
port,PHY_MDC, -pg 1 -lvl 1:0 -y 40,,,
port,PHY_MDIO, -pg 1 -lvl 1:0 -y 280,,,
port,PHY_RST, -pg 1 -lvl 1:0 -y 60,,,
port,RD_BC_ERROR, -pg 1 -lvl 1:0 -y 80,,,
port,REFCLK_N, -pg 1 -lvl 0:0 -y 20,,,
port,REFCLK_P, -pg 1 -lvl 0:0 -y 40,,,
port,REF_CLK_0, -pg 1 -lvl 0:0 -y 60,,,
port,REF_CLK_SEL, -pg 1 -lvl 1:0 -y 100,,,
port,RESET_N, -pg 1 -lvl 0:0 -y 80,,,
port,RX, -pg 1 -lvl 0:0 -y 140,,,
port,RX_N, -pg 1 -lvl 0:0 -y 100,,,
port,RX_P, -pg 1 -lvl 0:0 -y 120,,,
port,SPISCLKO, -pg 1 -lvl 1:0 -y 120,,,
port,SPISDI, -pg 1 -lvl 0:0 -y 160,,,
port,SPISDO, -pg 1 -lvl 1:0 -y 140,,,
port,SPISS, -pg 1 -lvl 1:0 -y 160,,,
port,TCK, -pg 1 -lvl 0:0 -y 180,,,
port,TDI, -pg 1 -lvl 0:0 -y 200,,,
port,TDO, -pg 1 -lvl 1:0 -y 180,,,
port,TMS, -pg 1 -lvl 0:0 -y 220,,,
port,TRSTB, -pg 1 -lvl 0:0 -y 240,,,
port,TX, -pg 1 -lvl 1:0 -y 240,,,
port,TX_N, -pg 1 -lvl 1:0 -y 200,,,
port,TX_P, -pg 1 -lvl 1:0 -y 220,,,
port,coma_mode, -pg 1 -lvl 1:0 -y 260,,,
 0 0 3 0 0 0 9 instances 0 1 7 1 0
1 1
2 0 0 18 0 6 AND2_2 7
3 1
4 0 0 0 0 7 BIBUF_0 7
5 1
6 0 0 0 0 13 COREFIFO_C0_0 7
7 1
8 0 0 0 0 18 COREJTAGDEBUG_C0_0 7
9 1
10 0 0 0 0 11 CORESPI_0_0 7
11 1
12 0 0 0 0 9 CORETSE_0 7
13 1
14 0 0 0 0 12 CoreAPB3_0_0 7
15 1
16 0 0 0 0 13 CoreUARTapb_0 7
17 1
18 0 0 0 0 15 Core_reset_pf_0 7
19 1
20 0 0 0 0 12 INBUF_DIFF_0 7
21 1
22 0 0 0 0 13 MIV_RV32_C0_0 7
23 1
24 0 0 0 0 10 PF_CCC_0_0 7
25 1
26 0 0 0 0 15 PF_IOD_CDR_C0_0 7
27 1
28 0 0 0 0 19 PF_IOD_CDR_CCC_C0_0 7
29 1
30 0 0 0 0 14 PF_TPSRAM_C0_0 7
31 1
32 0 0 0 0 10 SSDetect_0 7
33 1
34 0 0 0 0 23 fifo_to_tpsram_bridge_0 7
35 1
36 0 0 0 0 19 pf_init_monitor_0_0 7
37 1
38 0 0 0 0 4 nets 7
39 1
40 0 0 66 0 8 AND2_2_Y 7
41 1
42 0 0 0 0 9 BIBUF_0_Y 7
43 1
44 0 0 0 0 19 COREFIFO_C0_0_EMPTY 7
45 1
46 0 0 0 0 15 COREFIFO_C0_0_Q 7
47 1
48 0 0 0 0 28 COREJTAGDEBUG_C0_0_TGT_TCK_0 7
49 1
50 0 0 0 0 28 COREJTAGDEBUG_C0_0_TGT_TDI_0 7
51 1
52 0 0 0 0 28 COREJTAGDEBUG_C0_0_TGT_TMS_0 7
53 1
54 0 0 0 0 30 COREJTAGDEBUG_C0_0_TGT_TRSTN_0 7
55 1
56 0 0 0 0 13 CORETSE_0_MDO 7
57 1
58 0 0 0 0 15 CORETSE_0_MDOEN 7
59 1
60 0 0 0 0 22 CORETSE_0_MRXBYTEVALID 7
61 1
62 0 0 0 0 16 CORETSE_0_MRXDAT 7
63 1
64 0 0 0 0 16 CORETSE_0_MRXEOF 7
65 1
66 0 0 0 0 16 CORETSE_0_MRXRDY 7
67 1
68 0 0 0 0 16 CORETSE_0_MRXSOF 7
69 1
70 0 0 0 0 17 CORETSE_0_MTXACPT 7
71 1
72 0 0 0 0 13 CORETSE_0_TCG 7
73 1
74 0 0 0 0 23 CoreAPB3_0_0_APBmslave0 7
75 1
76 0 0 0 0 23 CoreAPB3_0_0_APBmslave1 7
77 1
78 0 0 0 0 23 CoreAPB3_0_0_APBmslave2 7
79 1
80 0 0 0 0 31 Core_reset_pf_0_PLL_POWERDOWN_B 7
81 1
82 0 0 0 0 14 INBUF_DIFF_0_Y 7
83 1
84 0 0 0 0 7 LINK_OK 7
85 1
86 0 0 0 0 27 MIV_RV32_C0_0_APB_INITIATOR 7
87 1
88 0 0 0 0 22 MIV_RV32_C0_0_JTAG_TDO 7
89 1
90 0 0 0 0 24 PF_CCC_0_0_OUT0_FABCLK_0 7
91 1
92 0 0 0 0 21 PF_CCC_0_0_PLL_LOCK_0 7
93 1
94 0 0 0 0 24 PF_IOD_CDR_C0_0_RX_CLK_R 7
95 1
96 0 0 0 0 23 PF_IOD_CDR_C0_0_RX_DATA 7
97 1
98 0 0 0 0 30 PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS 7
99 1
100 0 0 0 0 28 PF_IOD_CDR_CCC_C0_0_PLL_LOCK 7
101 1
102 0 0 0 0 28 PF_IOD_CDR_CCC_C0_0_TX_CLK_G 7
103 1
104 0 0 0 0 7 PHY_MDC 7
105 1
106 0 0 0 0 8 PHY_MDIO 7
107 1
108 0 0 0 0 7 PHY_RST 7
109 1
110 0 0 0 0 11 RD_BC_ERROR 7
111 1
112 0 0 0 0 8 REFCLK_N 7
113 1
114 0 0 0 0 8 REFCLK_P 7
115 1
116 0 0 0 0 9 REF_CLK_0 7
117 1
118 0 0 0 0 7 RESET_N 7
119 1
120 0 0 0 0 2 RX 7
121 1
122 0 0 0 0 4 RX_N 7
123 1
124 0 0 0 0 4 RX_P 7
125 1
126 0 0 0 0 6 R_DATA 7
127 1
128 0 0 0 0 8 SPISCLKO 7
129 1
130 0 0 0 0 6 SPISDI 7
131 1
132 0 0 0 0 6 SPISDO 7
133 1
134 0 0 0 0 5 SPISS 7
135 1
136 0 0 0 0 23 SSDetect_0_stream_start 7
137 1
138 0 0 0 0 3 TCK 7
139 1
140 0 0 0 0 3 TDI 7
141 1
142 0 0 0 0 3 TDO 7
143 1
144 0 0 0 0 3 TMS 7
145 1
146 0 0 0 0 5 TRSTB 7
147 1
148 0 0 0 0 2 TX 7
149 1
150 0 0 0 0 4 TX_N 7
151 1
152 0 0 0 0 4 TX_P 7
153 1
154 0 0 0 0 34 fifo_to_tpsram_bridge_0_fifo_rd_en 7
155 1
156 0 0 0 0 34 fifo_to_tpsram_bridge_0_ram_w_addr 7
157 1
158 0 0 0 0 36 fifo_to_tpsram_bridge_0_ram_w_addr_0 7
159 1
160 0 0 0 0 36 fifo_to_tpsram_bridge_0_ram_w_addr_1 7
161 1
162 0 0 0 0 34 fifo_to_tpsram_bridge_0_ram_w_data 7
163 1
164 0 0 0 0 32 fifo_to_tpsram_bridge_0_ram_w_en 7
165 1
166 0 0 0 0 38 pf_init_monitor_0_0_BANK_6_VDDI_STATUS 7
167 1
168 0 0 0 0 36 pf_init_monitor_0_0_DEVICE_INIT_DONE 7
169 1
170 0 0 0 0 32 pf_init_monitor_0_0_FABRIC_POR_N 7
171 1
172 0 0 0 0 4 pins 7
173 1
174 0 0 277 0 8 AND2_2:A 7
175 1
176 0 0 0 0 8 AND2_2:B 7
177 1
178 0 0 0 0 8 AND2_2:Y 7
179 1
180 0 0 0 0 9 BIBUF_0:D 7
181 1
182 0 0 0 0 9 BIBUF_0:E 7
183 1
184 0 0 0 0 11 BIBUF_0:PAD 7
185 1
186 0 0 0 0 9 BIBUF_0:Y 7
187 1
188 0 0 0 0 17 COREFIFO_C0_0:CLK 7
189 1
190 0 0 0 0 18 COREFIFO_C0_0:DATA 7
191 1
192 0 0 0 0 19 COREFIFO_C0_0:EMPTY 7
193 1
194 0 0 0 0 18 COREFIFO_C0_0:FULL 7
195 1
196 0 0 0 0 15 COREFIFO_C0_0:Q 7
197 1
198 0 0 0 0 16 COREFIFO_C0_0:RE 7
199 1
200 0 0 0 0 21 COREFIFO_C0_0:RESET_N 7
201 1
202 0 0 0 0 16 COREFIFO_C0_0:WE 7
203 1
204 0 0 0 0 33 COREJTAGDEBUG_C0_0:DEBUG_TARGET_0 7
205 1
206 0 0 0 0 30 COREJTAGDEBUG_C0_0:JTAG_HEADER 7
207 1
208 0 0 0 0 22 COREJTAGDEBUG_C0_0:TCK 7
209 1
210 0 0 0 0 22 COREJTAGDEBUG_C0_0:TDI 7
211 1
212 0 0 0 0 22 COREJTAGDEBUG_C0_0:TDO 7
213 1
214 0 0 0 0 28 COREJTAGDEBUG_C0_0:TGT_TCK_0 7
215 1
216 0 0 0 0 28 COREJTAGDEBUG_C0_0:TGT_TDI_0 7
217 1
218 0 0 0 0 28 COREJTAGDEBUG_C0_0:TGT_TDO_0 7
219 1
220 0 0 0 0 28 COREJTAGDEBUG_C0_0:TGT_TMS_0 7
221 1
222 0 0 0 0 30 COREJTAGDEBUG_C0_0:TGT_TRSTN_0 7
223 1
224 0 0 0 0 22 COREJTAGDEBUG_C0_0:TMS 7
225 1
226 0 0 0 0 24 COREJTAGDEBUG_C0_0:TRSTB 7
227 1
228 0 0 0 0 19 CORESPI_0_0:APB_bif 7
229 1
230 0 0 0 0 17 CORESPI_0_0:PADDR 7
231 1
232 0 0 0 0 16 CORESPI_0_0:PCLK 7
233 1
234 0 0 0 0 19 CORESPI_0_0:PENABLE 7
235 1
236 0 0 0 0 18 CORESPI_0_0:PRDATA 7
237 1
238 0 0 0 0 18 CORESPI_0_0:PREADY 7
239 1
240 0 0 0 0 19 CORESPI_0_0:PRESETN 7
241 1
242 0 0 0 0 16 CORESPI_0_0:PSEL 7
243 1
244 0 0 0 0 19 CORESPI_0_0:PSLVERR 7
245 1
246 0 0 0 0 18 CORESPI_0_0:PWDATA 7
247 1
248 0 0 0 0 18 CORESPI_0_0:PWRITE 7
249 1
250 0 0 0 0 19 CORESPI_0_0:SPICLKI 7
251 1
252 0 0 0 0 18 CORESPI_0_0:SPIINT 7
253 1
254 0 0 0 0 19 CORESPI_0_0:SPIMODE 7
255 1
256 0 0 0 0 18 CORESPI_0_0:SPIOEN 7
257 1
258 0 0 0 0 22 CORESPI_0_0:SPIRXAVAIL 7
259 1
260 0 0 0 0 20 CORESPI_0_0:SPISCLKO 7
261 1
262 0 0 0 0 18 CORESPI_0_0:SPISDI 7
263 1
264 0 0 0 0 18 CORESPI_0_0:SPISDO 7
265 1
266 0 0 0 0 17 CORESPI_0_0:SPISS 7
267 1
268 0 0 0 0 18 CORESPI_0_0:SPISSI 7
269 1
270 0 0 0 0 20 CORESPI_0_0:SPITXRFM 7
271 1
272 0 0 0 0 19 CORETSE_0:ANX_STATE 7
273 1
274 0 0 0 0 14 CORETSE_0:APBS 7
275 1
276 0 0 0 0 13 CORETSE_0:MDC 7
277 1
278 0 0 0 0 13 CORETSE_0:MDI 7
279 1
280 0 0 0 0 13 CORETSE_0:MDO 7
281 1
282 0 0 0 0 15 CORETSE_0:MDOEN 7
283 1
284 0 0 0 0 17 CORETSE_0:MRXACPT 7
285 1
286 0 0 0 0 22 CORETSE_0:MRXBYTEVALID 7
287 1
288 0 0 0 0 16 CORETSE_0:MRXCLK 7
289 1
290 0 0 0 0 16 CORETSE_0:MRXDAT 7
291 1
292 0 0 0 0 16 CORETSE_0:MRXEOF 7
293 1
294 0 0 0 0 16 CORETSE_0:MRXRDY 7
295 1
296 0 0 0 0 16 CORETSE_0:MRXSOF 7
297 1
298 0 0 0 0 17 CORETSE_0:MTXACPT 7
299 1
300 0 0 0 0 22 CORETSE_0:MTXBYTEVALID 7
301 1
302 0 0 0 0 16 CORETSE_0:MTXCLK 7
303 1
304 0 0 0 0 16 CORETSE_0:MTXDAT 7
305 1
306 0 0 0 0 16 CORETSE_0:MTXEOF 7
307 1
308 0 0 0 0 16 CORETSE_0:MTXHWM 7
309 1
310 0 0 0 0 16 CORETSE_0:MTXRDY 7
311 1
312 0 0 0 0 16 CORETSE_0:MTXSOF 7
313 1
314 0 0 0 0 15 CORETSE_0:PADDR 7
315 1
316 0 0 0 0 14 CORETSE_0:PCLK 7
317 1
318 0 0 0 0 17 CORETSE_0:PENABLE 7
319 1
320 0 0 0 0 16 CORETSE_0:PRDATA 7
321 1
322 0 0 0 0 16 CORETSE_0:PREADY 7
323 1
324 0 0 0 0 17 CORETSE_0:PRESETN 7
325 1
326 0 0 0 0 14 CORETSE_0:PSEL 7
327 1
328 0 0 0 0 17 CORETSE_0:PSLVERR 7
329 1
330 0 0 0 0 16 CORETSE_0:PWDATA 7
331 1
332 0 0 0 0 16 CORETSE_0:PWRITE 7
333 1
334 0 0 0 0 13 CORETSE_0:RCG 7
335 1
336 0 0 0 0 19 CORETSE_0:RCG_ERROR 7
337 1
338 0 0 0 0 15 CORETSE_0:RXCLK 7
339 1
340 0 0 0 0 23 CORETSE_0:SIGNAL_DETECT 7
341 1
342 0 0 0 0 14 CORETSE_0:SYNC 7
343 1
344 0 0 0 0 20 CORETSE_0:TBI_RX_CLK 7
345 1
346 0 0 0 0 20 CORETSE_0:TBI_TX_CLK 7
347 1
348 0 0 0 0 22 CORETSE_0:TBI_TX_VALID 7
349 1
350 0 0 0 0 13 CORETSE_0:TCG 7
351 1
352 0 0 0 0 21 CORETSE_0:TSM_CONTROL 7
353 1
354 0 0 0 0 21 CORETSE_0:TSM_RX_INTR 7
355 1
356 0 0 0 0 21 CORETSE_0:TSM_TX_INTR 7
357 1
358 0 0 0 0 15 CORETSE_0:TXCLK 7
359 1
360 0 0 0 0 24 CoreAPB3_0_0:APB3mmaster 7
361 1
362 0 0 0 0 23 CoreAPB3_0_0:APBmslave0 7
363 1
364 0 0 0 0 23 CoreAPB3_0_0:APBmslave1 7
365 1
366 0 0 0 0 23 CoreAPB3_0_0:APBmslave2 7
367 1
368 0 0 0 0 18 CoreAPB3_0_0:PADDR 7
369 1
370 0 0 0 0 19 CoreAPB3_0_0:PADDRS 7
371 1
372 0 0 0 0 20 CoreAPB3_0_0:PENABLE 7
373 1
374 0 0 0 0 21 CoreAPB3_0_0:PENABLES 7
375 1
376 0 0 0 0 19 CoreAPB3_0_0:PRDATA 7
377 1
378 0 0 0 0 21 CoreAPB3_0_0:PRDATAS0 7
379 1
380 0 0 0 0 21 CoreAPB3_0_0:PRDATAS1 7
381 1
382 0 0 0 0 21 CoreAPB3_0_0:PRDATAS2 7
383 1
384 0 0 0 0 19 CoreAPB3_0_0:PREADY 7
385 1
386 0 0 0 0 21 CoreAPB3_0_0:PREADYS0 7
387 1
388 0 0 0 0 21 CoreAPB3_0_0:PREADYS1 7
389 1
390 0 0 0 0 21 CoreAPB3_0_0:PREADYS2 7
391 1
392 0 0 0 0 17 CoreAPB3_0_0:PSEL 7
393 1
394 0 0 0 0 19 CoreAPB3_0_0:PSELS0 7
395 1
396 0 0 0 0 19 CoreAPB3_0_0:PSELS1 7
397 1
398 0 0 0 0 19 CoreAPB3_0_0:PSELS2 7
399 1
400 0 0 0 0 20 CoreAPB3_0_0:PSLVERR 7
401 1
402 0 0 0 0 22 CoreAPB3_0_0:PSLVERRS0 7
403 1
404 0 0 0 0 22 CoreAPB3_0_0:PSLVERRS1 7
405 1
406 0 0 0 0 22 CoreAPB3_0_0:PSLVERRS2 7
407 1
408 0 0 0 0 19 CoreAPB3_0_0:PWDATA 7
409 1
410 0 0 0 0 20 CoreAPB3_0_0:PWDATAS 7
411 1
412 0 0 0 0 19 CoreAPB3_0_0:PWRITE 7
413 1
414 0 0 0 0 20 CoreAPB3_0_0:PWRITES 7
415 1
416 0 0 0 0 21 CoreUARTapb_0:APB_bif 7
417 1
418 0 0 0 0 25 CoreUARTapb_0:FRAMING_ERR 7
419 1
420 0 0 0 0 22 CoreUARTapb_0:OVERFLOW 7
421 1
422 0 0 0 0 19 CoreUARTapb_0:PADDR 7
423 1
424 0 0 0 0 24 CoreUARTapb_0:PARITY_ERR 7
425 1
426 0 0 0 0 18 CoreUARTapb_0:PCLK 7
427 1
428 0 0 0 0 21 CoreUARTapb_0:PENABLE 7
429 1
430 0 0 0 0 20 CoreUARTapb_0:PRDATA 7
431 1
432 0 0 0 0 20 CoreUARTapb_0:PREADY 7
433 1
434 0 0 0 0 21 CoreUARTapb_0:PRESETN 7
435 1
436 0 0 0 0 18 CoreUARTapb_0:PSEL 7
437 1
438 0 0 0 0 21 CoreUARTapb_0:PSLVERR 7
439 1
440 0 0 0 0 20 CoreUARTapb_0:PWDATA 7
441 1
442 0 0 0 0 20 CoreUARTapb_0:PWRITE 7
443 1
444 0 0 0 0 16 CoreUARTapb_0:RX 7
445 1
446 0 0 0 0 19 CoreUARTapb_0:RXRDY 7
447 1
448 0 0 0 0 16 CoreUARTapb_0:TX 7
449 1
450 0 0 0 0 19 CoreUARTapb_0:TXRDY 7
451 1
452 0 0 0 0 34 Core_reset_pf_0:BANK_x_VDDI_STATUS 7
453 1
454 0 0 0 0 34 Core_reset_pf_0:BANK_y_VDDI_STATUS 7
455 1
456 0 0 0 0 19 Core_reset_pf_0:CLK 7
457 1
458 0 0 0 0 25 Core_reset_pf_0:EXT_RST_N 7
459 1
460 0 0 0 0 30 Core_reset_pf_0:FABRIC_RESET_N 7
461 1
462 0 0 0 0 29 Core_reset_pf_0:FF_US_RESTORE 7
463 1
464 0 0 0 0 26 Core_reset_pf_0:FPGA_POR_N 7
465 1
466 0 0 0 0 25 Core_reset_pf_0:INIT_DONE 7
467 1
468 0 0 0 0 24 Core_reset_pf_0:PLL_LOCK 7
469 1
470 0 0 0 0 31 Core_reset_pf_0:PLL_POWERDOWN_B 7
471 1
472 0 0 0 0 23 Core_reset_pf_0:SS_BUSY 7
473 1
474 0 0 0 0 17 INBUF_DIFF_0:PADN 7
475 1
476 0 0 0 0 17 INBUF_DIFF_0:PADP 7
477 1
478 0 0 0 0 14 INBUF_DIFF_0:Y 7
479 1
480 0 0 0 0 27 MIV_RV32_C0_0:APB_INITIATOR 7
481 1
482 0 0 0 0 23 MIV_RV32_C0_0:APB_PADDR 7
483 1
484 0 0 0 0 25 MIV_RV32_C0_0:APB_PENABLE 7
485 1
486 0 0 0 0 24 MIV_RV32_C0_0:APB_PRDATA 7
487 1
488 0 0 0 0 24 MIV_RV32_C0_0:APB_PREADY 7
489 1
490 0 0 0 0 22 MIV_RV32_C0_0:APB_PSEL 7
491 1
492 0 0 0 0 25 MIV_RV32_C0_0:APB_PSLVERR 7
493 1
494 0 0 0 0 24 MIV_RV32_C0_0:APB_PWDATA 7
495 1
496 0 0 0 0 24 MIV_RV32_C0_0:APB_PWRITE 7
497 1
498 0 0 0 0 17 MIV_RV32_C0_0:CLK 7
499 1
500 0 0 0 0 19 MIV_RV32_C0_0:DEBUG 7
501 1
502 0 0 0 0 21 MIV_RV32_C0_0:EXT_IRQ 7
503 1
504 0 0 0 0 24 MIV_RV32_C0_0:EXT_RESETN 7
505 1
506 0 0 0 0 17 MIV_RV32_C0_0:IRQ 7
507 1
508 0 0 0 0 22 MIV_RV32_C0_0:JTAG_TCK 7
509 1
510 0 0 0 0 22 MIV_RV32_C0_0:JTAG_TDI 7
511 1
512 0 0 0 0 22 MIV_RV32_C0_0:JTAG_TDO 7
513 1
514 0 0 0 0 25 MIV_RV32_C0_0:JTAG_TDO_DR 7
515 1
516 0 0 0 0 22 MIV_RV32_C0_0:JTAG_TMS 7
517 1
518 0 0 0 0 24 MIV_RV32_C0_0:JTAG_TRSTN 7
519 1
520 0 0 0 0 20 MIV_RV32_C0_0:RESETN 7
521 1
522 0 0 0 0 28 MIV_RV32_C0_0:TIME_COUNT_OUT 7
523 1
524 0 0 0 0 24 PF_CCC_0_0:OUT0_FABCLK_0 7
525 1
526 0 0 0 0 21 PF_CCC_0_0:PLL_LOCK_0 7
527 1
528 0 0 0 0 28 PF_CCC_0_0:PLL_POWERDOWN_N_0 7
529 1
530 0 0 0 0 20 PF_CCC_0_0:REF_CLK_0 7
531 1
532 0 0 0 0 26 PF_IOD_CDR_C0_0:CDR_CLOCKS 7
533 1
534 0 0 0 0 25 PF_IOD_CDR_C0_0:CDR_START 7
535 1
536 0 0 0 0 30 PF_IOD_CDR_C0_0:DLL_DELAY_CODE 7
537 1
538 0 0 0 0 24 PF_IOD_CDR_C0_0:DLL_LOCK 7
539 1
540 0 0 0 0 30 PF_IOD_CDR_C0_0:DLL_VALID_CODE 7
541 1
542 0 0 0 0 27 PF_IOD_CDR_C0_0:HS_IO_CLK_0 7
543 1
544 0 0 0 0 29 PF_IOD_CDR_C0_0:HS_IO_CLK_180 7
545 1
546 0 0 0 0 29 PF_IOD_CDR_C0_0:HS_IO_CLK_270 7
547 1
548 0 0 0 0 28 PF_IOD_CDR_C0_0:HS_IO_CLK_90 7
549 1
550 0 0 0 0 31 PF_IOD_CDR_C0_0:HS_IO_CLK_PAUSE 7
551 1
552 0 0 0 0 24 PF_IOD_CDR_C0_0:PLL_LOCK 7
553 1
554 0 0 0 0 21 PF_IOD_CDR_C0_0:RST_N 7
555 1
556 0 0 0 0 24 PF_IOD_CDR_C0_0:RX_CLK_R 7
557 1
558 0 0 0 0 23 PF_IOD_CDR_C0_0:RX_DATA 7
559 1
560 0 0 0 0 20 PF_IOD_CDR_C0_0:RX_N 7
561 1
562 0 0 0 0 20 PF_IOD_CDR_C0_0:RX_P 7
563 1
564 0 0 0 0 22 PF_IOD_CDR_C0_0:RX_VAL 7
565 1
566 0 0 0 0 28 PF_IOD_CDR_C0_0:STREAM_START 7
567 1
568 0 0 0 0 24 PF_IOD_CDR_C0_0:TX_CLK_G 7
569 1
570 0 0 0 0 23 PF_IOD_CDR_C0_0:TX_DATA 7
571 1
572 0 0 0 0 20 PF_IOD_CDR_C0_0:TX_N 7
573 1
574 0 0 0 0 20 PF_IOD_CDR_C0_0:TX_P 7
575 1
576 0 0 0 0 26 PF_IOD_CDR_CCC_C0_0:ARST_N 7
577 1
578 0 0 0 0 30 PF_IOD_CDR_CCC_C0_0:CDR_CLOCKS 7
579 1
580 0 0 0 0 29 PF_IOD_CDR_CCC_C0_0:CDR_START 7
581 1
582 0 0 0 0 34 PF_IOD_CDR_CCC_C0_0:DLL_DELAY_CODE 7
583 1
584 0 0 0 0 28 PF_IOD_CDR_CCC_C0_0:DLL_LOCK 7
585 1
586 0 0 0 0 34 PF_IOD_CDR_CCC_C0_0:DLL_VALID_CODE 7
587 1
588 0 0 0 0 31 PF_IOD_CDR_CCC_C0_0:HS_IO_CLK_0 7
589 1
590 0 0 0 0 33 PF_IOD_CDR_CCC_C0_0:HS_IO_CLK_180 7
591 1
592 0 0 0 0 33 PF_IOD_CDR_CCC_C0_0:HS_IO_CLK_270 7
593 1
594 0 0 0 0 32 PF_IOD_CDR_CCC_C0_0:HS_IO_CLK_90 7
595 1
596 0 0 0 0 35 PF_IOD_CDR_CCC_C0_0:HS_IO_CLK_PAUSE 7
597 1
598 0 0 0 0 28 PF_IOD_CDR_CCC_C0_0:PLL_LOCK 7
599 1
600 0 0 0 0 27 PF_IOD_CDR_CCC_C0_0:REF_CLK 7
601 1
602 0 0 0 0 28 PF_IOD_CDR_CCC_C0_0:TX_CLK_G 7
603 1
604 0 0 0 0 35 PF_IOD_CDR_CCC_C0_0:TX_CLK_G_TO_CDR 7
605 1
606 0 0 0 0 18 PF_TPSRAM_C0_0:CLK 7
607 1
608 0 0 0 0 21 PF_TPSRAM_C0_0:R_ADDR 7
609 1
610 0 0 0 0 21 PF_TPSRAM_C0_0:R_DATA 7
611 1
612 0 0 0 0 21 PF_TPSRAM_C0_0:W_ADDR 7
613 1
614 0 0 0 0 21 PF_TPSRAM_C0_0:W_DATA 7
615 1
616 0 0 0 0 19 PF_TPSRAM_C0_0:W_EN 7
617 1
618 0 0 0 0 14 SSDetect_0:rck 7
619 1
620 0 0 0 0 16 SSDetect_0:rst_b 7
621 1
622 0 0 0 0 18 SSDetect_0:rx_data 7
623 1
624 0 0 0 0 23 SSDetect_0:stream_start 7
625 1
626 0 0 0 0 35 fifo_to_tpsram_bridge_0:buffer_full 7
627 1
628 0 0 0 0 27 fifo_to_tpsram_bridge_0:clk 7
629 1
630 0 0 0 0 37 fifo_to_tpsram_bridge_0:fifo_data_out 7
631 1
632 0 0 0 0 34 fifo_to_tpsram_bridge_0:fifo_empty 7
633 1
634 0 0 0 0 34 fifo_to_tpsram_bridge_0:fifo_rd_en 7
635 1
636 0 0 0 0 34 fifo_to_tpsram_bridge_0:ram_w_addr 7
637 1
638 0 0 0 0 34 fifo_to_tpsram_bridge_0:ram_w_data 7
639 1
640 0 0 0 0 32 fifo_to_tpsram_bridge_0:ram_w_en 7
641 1
642 0 0 0 0 31 fifo_to_tpsram_bridge_0:reset_n 7
643 1
644 0 0 0 0 39 fifo_to_tpsram_bridge_0:transfer_enable 7
645 1
646 0 0 0 0 34 pf_init_monitor_0_0:AUTOCALIB_DONE 7
647 1
648 0 0 0 0 38 pf_init_monitor_0_0:BANK_6_VDDI_STATUS 7
649 1
650 0 0 0 0 36 pf_init_monitor_0_0:DEVICE_INIT_DONE 7
651 1
652 0 0 0 0 32 pf_init_monitor_0_0:FABRIC_POR_N 7
653 1
654 0 0 0 0 34 pf_init_monitor_0_0:PCIE_INIT_DONE 7
655 1
656 0 0 0 0 34 pf_init_monitor_0_0:SRAM_INIT_DONE 7
657 1
658 0 0 0 0 44 pf_init_monitor_0_0:SRAM_INIT_FROM_SNVM_DONE 7
659 1
660 0 0 0 0 43 pf_init_monitor_0_0:SRAM_INIT_FROM_SPI_DONE 7
661 1
662 0 0 0 0 45 pf_init_monitor_0_0:SRAM_INIT_FROM_UPROM_DONE 7
663 1
664 0 0 0 0 35 pf_init_monitor_0_0:USRAM_INIT_DONE 7
665 1
666 0 0 0 0 45 pf_init_monitor_0_0:USRAM_INIT_FROM_SNVM_DONE 7
667 1
668 0 0 0 0 44 pf_init_monitor_0_0:USRAM_INIT_FROM_SPI_DONE 7
669 1
670 0 0 0 0 46 pf_init_monitor_0_0:USRAM_INIT_FROM_UPROM_DONE 7
671 1
672 0 0 0 0 34 pf_init_monitor_0_0:XCVR_INIT_DONE 7
673 1
674 0 0 0 0 11 top:LINK_OK 7
675 1
676 0 0 0 0 11 top:PHY_MDC 7
677 1
678 0 0 0 0 12 top:PHY_MDIO 7
679 1
680 0 0 0 0 11 top:PHY_RST 7
681 1
682 0 0 0 0 15 top:RD_BC_ERROR 7
683 1
684 0 0 0 0 12 top:REFCLK_N 7
685 1
686 0 0 0 0 12 top:REFCLK_P 7
687 1
688 0 0 0 0 13 top:REF_CLK_0 7
689 1
690 0 0 0 0 15 top:REF_CLK_SEL 7
691 1
692 0 0 0 0 11 top:RESET_N 7
693 1
694 0 0 0 0 6 top:RX 7
695 1
696 0 0 0 0 8 top:RX_N 7
697 1
698 0 0 0 0 8 top:RX_P 7
699 1
700 0 0 0 0 10 top:R_DATA 7
701 1
702 0 0 0 0 12 top:SPISCLKO 7
703 1
704 0 0 0 0 10 top:SPISDI 7
705 1
706 0 0 0 0 10 top:SPISDO 7
707 1
708 0 0 0 0 9 top:SPISS 7
709 1
710 0 0 0 0 7 top:TCK 7
711 1
712 0 0 0 0 7 top:TDI 7
713 1
714 0 0 0 0 7 top:TDO 7
715 1
716 0 0 0 0 7 top:TMS 7
717 1
718 0 0 0 0 9 top:TRSTB 7
719 1
720 0 0 0 0 6 top:TX 7
721 1
722 0 0 0 0 8 top:TX_N 7
723 1
724 0 0 0 0 8 top:TX_P 7
725 1
726 0 0 0 0 13 top:coma_mode 7
727 1
728 0 0 0 0
