top./top.sdbSDB./top_DRC.xmllog./top_manifest.txtLOG./top.vverilogSourceOTHER_FILESETOTHERHDL_FILESETHDLSmartCoreDesignSmartDesignSmartDesignActel1.0SmartCoreDesignfalseREFCLK_NintruetrueINBUF_DIFFPADNtrueREFCLK_PintruetrueINBUF_DIFFPADPtrueREF_CLK_0infalsefalsetrueRESET_NinfalsefalsetrueRX_NintruetrueINBUF_DIFFPADNtrueRX_PintruetrueINBUF_DIFFPADPtrueRXinfalsefalsetrueSPISDIinfalsefalsetrueTCKinfalsefalsetrueTDIinfalsefalsetrueTMSinfalsefalsetrueTRSTBinfalsefalsetrueLINK_OKoutfalsefalsetruePHY_MDCoutfalsefalsetruePHY_RSToutfalsefalsetrueRD_BC_ERRORoutfalsefalsetrueREF_CLK_SELoutfalsefalsetrueSPISCLKOoutfalsefalsetrueSPISDOoutfalsefalsetrueSPISSoutfalsefalsetrueTDOoutfalsefalsetrueTX_NouttruetrueOUTBUF_DIFFPADNtrueTX_PouttruetrueOUTBUF_DIFFPADPtrueTXoutfalsefalsetruecoma_modeoutfalsefalsetruePHY_MDIOinouttruetrueBIBUFPADtrueR_DATAout310falsefalsetrue