quietly set ACTELLIBNAME PolarFire
quietly set PROJECT_DIR "E:/AbhishekV/rising/ethernet_tpsram_test"
source "${PROJECT_DIR}/simulation/bfmtovec_compile.tcl";


if {[file exists ../designer/top/simulation/postlayout/_info]} {
   echo "INFO: Simulation library ../designer/top/simulation/postlayout already exists"
} else {
   file delete -force ../designer/top/simulation/postlayout 
   vlib ../designer/top/simulation/postlayout
}
vmap postlayout ../designer/top/simulation/postlayout
vmap PolarFire "E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire"
if {[file exists COREAPB3_LIB/_info]} {
   echo "INFO: Simulation library COREAPB3_LIB already exists"
} else {
   file delete -force COREAPB3_LIB 
   vlib COREAPB3_LIB
}
vmap COREAPB3_LIB "COREAPB3_LIB"
if {[file exists COREJTAGDEBUG_LIB/_info]} {
   echo "INFO: Simulation library COREJTAGDEBUG_LIB already exists"
} else {
   file delete -force COREJTAGDEBUG_LIB 
   vlib COREJTAGDEBUG_LIB
}
vmap COREJTAGDEBUG_LIB "COREJTAGDEBUG_LIB"
if {[file exists CORESPI_LIB/_info]} {
   echo "INFO: Simulation library CORESPI_LIB already exists"
} else {
   file delete -force CORESPI_LIB 
   vlib CORESPI_LIB
}
vmap CORESPI_LIB "CORESPI_LIB"

vlog -sv -work postlayout "${PROJECT_DIR}/designer/top/top_ba.v"

vsim -L PolarFire -L postlayout -L COREAPB3_LIB -L COREJTAGDEBUG_LIB -L CORESPI_LIB  -t 1ps -pli E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/pli/pf_crypto_win_me_pli.dll -sdfmax /top=${PROJECT_DIR}/designer/top/top_slow_lv_ht_ba.sdf +transport_path_delays postlayout.top
# The following lines are commented because no testbench is associated with the project
# add wave /testbench/*
# run 1000ns