INFO: Reading User SDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\top_derived_constraints.sdc. INFO: Reading User SDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\timing_user_constraints.sdc. INFO: The option "Abort flow if errors are found in SDC" is turned ON in Project Settings> Design flow page. The Place & Route tool will fail if errors are found in associated SDC files. Please uncheck the option to ignore the errors and continue running the tool. No errors or warnings found. INFO: The option "Abort flow if errors are found in PDC" is turned ON in Project Settings> Design flow page. The Place & Route tool will fail if errors are found in associated PDC files. Please uncheck the option to ignore the errors and continue running the tool ***** Place and Route Configurations ***** Timing-driven : ON Power-driven : OFF I/O Register Combining : OFF Global Pins Demotion : ON Driver Replication : OFF High-effort : ON Repair min-delay : ON Incremental : OFF Inter-clock optimization : ON INFO: Reading User PDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\io\io_constraints.pdc. 0 error(s) and 0 warning(s) Running Timing based Global Demotion. Demoted 0 global pins. Timing based Global Demotion completed successfully. Running the I/O Bank and Globals Assigner. Info: I/O Bank and Globals Assigner identified 18 fixed I/O macros, 32 unfixed I/O macros Info: I/O Bank and Globals Assigner identified bank 'Bank4' as being fixed at VCCI:2.50V VCCR:n/a Info: I/O Bank and Globals Assigner detected (1) out of (7) I/O Bank(s) with locked I/O technologies. I/O Bank and Globals Assigner completed successfully. Total time spent in I/O Bank and Globals Assigner: 9 seconds Placer V5.0 - 2025.1.0 Design: top Started: Fri Apr 17 08:38:08 2026 Initializing High-Effort Timing-Driven Placement ... Clustering ... Placing ... Improving placement ... CDC Report: Total number of CDC synchronizer driver/sink pairs : 40 Maximum distance between CDC synchronizer driver & sink: 1 cluster(s) Generated the list of CDC synchronizer pairs in cdc_synchronizer.csv. End of placement. Placer Runtime Summary : Clustering (1 pass) : 27 seconds Placement : 48 seconds Improvement : 406 seconds Placer completed successfully. Design: top Finished: Fri Apr 17 08:47:03 2026 Total CPU Time: 00:09:58 Total Elapsed Time: 00:08:55 Total Memory Usage: 1417.2 Mbytes o - o - o - o - o - o Router Design: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\topStarted: Fri Apr 17 08:47:21 2026 Router completed successfully. Design: E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top Finished: Fri Apr 17 08:48:57 2026 Total CPU Time: 00:01:55 Total Elapsed Time: 00:01:36 Total Memory Usage: 5358.0 Mbytes o - o - o - o - o - o Info: Iteration 1: Worst minimum delay slack: Total violating paths eligible for improvement: 0 Total violating paths improved: 0 Resource Usage +---------------------------+-------+--------+------------+ | Type | Used | Total | Percentage | +---------------------------+-------+--------+------------+ | 4LUT | 18818 | 299544 | 6.28 | | DFF | 8629 | 299544 | 2.88 | | Logic Element | 19822 | 299544 | 6.62 | | I/Os using I/O Registers | 0 | 512 | 0.00 | | I/O Register Flip-Flops | 0 | 1536 | 0.00 | | -- Input I/O Flip-Flops | 0 | 512 | 0.00 | | -- Output I/O Flip-Flops | 0 | 512 | 0.00 | | -- Enable I/O Flip-Flops | 0 | 512 | 0.00 | +---------------------------+-------+--------+------------+ I/O Placement +--------+-------+------------+ | Type | Count | Percentage | +--------+-------+------------+ | Locked | 21 | 39.62% | | Placed | 32 | 60.38% | +--------+-------+------------+ Completed writing pin report files.