E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/data/drcreport\warn.png
Warning
bus interface data width mismatch
There is a data width mismatch between CoreAPB3_0_0:APBmslave1:PWDATAS[0-31] and CoreUARTapb_0:APB_bif:PWDATA[0-7] which may result in a loss of data.
liberoaction://cross_probe/smartdesign/top/pins/CoreAPB3_0_0:APBmslave1