working FIFO and TPSRAM without packet flter

2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
--- a/viewdraw/viewdraw.ini
+++ b/viewdraw/viewdraw.ini
@@ -0,0 +1,63 @@
+NET               12      1       0
+COMPONENT         15      0       0
+ATTRIBUTE         14      0       0
+LABEL             15      0       0
+PIN                3      0       0
+BOX                2      0       0
+LINE               2      0       0
+CIRCLE             2      0       0
+ARC                2      0       0
+TEXT              10      0       0
+SELECTION_LAYER   15      0       0
+BORDER_LAYER      15      0       0
+VALUE_LAYER        7      0       0
+ANNO_LAYER         7      0       0
+GRID            10 
+DOTSIZE          5
+BUS_DOTSIZE     12
+BOXSIZE          5
+TEXTSIZE        10
+TEXTORIGIN       3
+BUSWIDTH         4
+BUBBLESIZE       5
+AUTOLOG         10
+SDISTANCE       10
+ADISTANCE       20
+SHEETSIZE        1
+ROUTE            2
+SCOPE            0
+TEXT_THRESHOLD   3
+NEW_ATTR_VIS     1
+BLOCKTYPE        0
+UNDO             16
+GRIDON           1 
+BORDERON         1 
+HEADERON         1 
+COMPTEXTON       1 
+TEXTON           1 
+ATTRON           1 
+LABELON          1 
+DETAIL           1 
+SNAPTOPIN        1 
+UNIQUE_LABEL     0 
+VALUESON         1 
+CONTEXT_WINDOW   0 
+NAMESON          0 
+SORTON           1 
+PNUMSON          1 
+RNUMSON          1 
+DEFSHEET         0 
+XTRAERRS         1 
+DBOXON           0 
+PRESERVE_CASE    0 
+ALLOW_VALUE_MIXED VERILOG
+NETNAME VDD        
+NETNAME GND        
+ATTR_RESET SS#1
+ATTR_RESET SS#2
+ATTR_RESET ALL_ID 
+ATTR_RESET GEN_ID 
+ATTR_RESET REFDES SYMBOL_VALUE
+DIR [pw] E:\AbhishekV\rising\ethernet_tpsram_test\viewdraw
+DIR [rm] E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer\lib\libvd\PolarFire\cells (actelcells)
+DIR [rm] E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer\lib\libvd\asicbin (builtin)