working FIFO and TPSRAM without packet flter

2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
--- a/tooldata/Libero_Project.log
+++ b/tooldata/Libero_Project.log
@@ -0,0 +1,16 @@
+Project Name: Libero_Project
+Location: E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
+Description: 
+Preferred HDL Type: Verilog
+
+#-----------------------------------------------------
+                  Device Details
+#-----------------------------------------------------
+
+Part Number    : MPF300TS-1FCG1152I
+Family         : PolarFire
+Die            : MPF300TS
+Package        : FCG1152
+Speed          : -1
+Core Voltage   : 1.05
+Range          : IND