abhishek/Ethernet-IP-Core
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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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synthesis/top.so Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<SynplifyOutput>
<result>Success</result>
<design>top</design>
<target_verilog>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm</target_verilog>
</SynplifyOutput>