abhishek/Ethernet-IP-Core
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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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synthesis/synwork/.layer0.srs_dep Normal file
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miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block