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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block
miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block

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./synwork/top_comp.srs,compile_only,Only compilation, no netlist editing or other optimization.

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Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09M-5
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
OS: Windows 10 or later
Hostname: SOFTWARE-PC
Implementation : synthesis
Synopsys HDL compiler and linker, Version comp202309synp1, Build 540R, Built Apr 29 2025 09:15:16, @
Modified Files: 5
FID: path (prevtimestamp, timestamp)
88 E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52)
128 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v (2026-04-15 21:16:35, 2026-04-15 22:42:58)
129 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v (2026-04-15 21:16:35, 2026-04-15 22:42:58)
132 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24)
134 E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v (2026-04-15 21:45:39, 2026-04-15 22:40:31)
*******************************************************************
Modules that may have changed as a result of file changes: 364
MID: lib.cell.view
0 COREAPB3_LIB.COREAPB3_MUXPTOB3.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
1 COREAPB3_LIB.CoreAPB3.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
2 COREAPB3_LIB.coreapb3_iaddr_reg.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
3 COREJTAGDEBUG_LIB.COREJTAGDEBUG.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
4 COREJTAGDEBUG_LIB.COREJTAGDEBUG_UJ_JTAG.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
5 COREJTAGDEBUG_LIB.UJTAG_WRAPPER.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
6 COREJTAGDEBUG_LIB.corejtagdebug_bufd.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
7 CORESPI_LIB.CORESPI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
8 CORESPI_LIB.spi.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
9 CORESPI_LIB.spi_chanctrl.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
10 CORESPI_LIB.spi_clockmux.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
11 CORESPI_LIB.spi_control.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
12 CORESPI_LIB.spi_fifo.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
13 CORESPI_LIB.spi_rf.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
14 work.APBM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
15 work.APBS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
16 work.BANKCTRLM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
17 work.BANKCTRL_GPIO.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
18 work.BANKCTRL_HSIO.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
19 work.BANKEN.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
20 work.CLKBUF_DIFF.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
21 work.CLKBUF_DIFF_ODT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
22 work.CORECDR4_CNTL_TIP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
23 work.COREDELAYCODE_TIP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
351 work.COREFIFO_C0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
352 work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
353 work.COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
354 work.COREFIFO_C0_COREFIFO_C0_0_corefifo_async.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
355 work.COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
356 work.COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
357 work.COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
358 work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
359 work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
360 work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
24 work.COREJTAGDEBUG_C0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
25 work.CORELNKTMR_V.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
26 work.CORESPI_0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
27 work.CORETSE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
28 work.CORETSE_0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
29 work.CRN_COMMON.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
30 work.CRN_INT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
31 work.CRYPTO.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
32 work.CRYPTO_SOC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
33 work.CTSE_AMCXFIF_CLKRST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
34 work.CTSE_AMCXFIF_HST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
35 work.CTSE_AMCXRFIF_FAB.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
36 work.CTSE_AMCXRFIF_SYS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
37 work.CTSE_AMCXTFIF_FAB.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
38 work.CTSE_AMCXTFIF_SYS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
39 work.CTSE_AMCXTFIF_WTM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
40 work.CTSE_CLKRST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
41 work.CTSE_CORETSE_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
42 work.CTSE_DECODER.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
43 work.CTSE_ECC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
44 work.CTSE_MAPBE_HST_CNV.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
45 work.CTSE_MMCXWOL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
46 work.CTSE_MSGMII_CNVRXI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
47 work.CTSE_MSGMII_CNVRXO.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
48 work.CTSE_MSGMII_CNVTXI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
49 work.CTSE_MSGMII_CNVTXO.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
50 work.CTSE_MSGMII_CORE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
51 work.CTSE_MSGMII_PEANX_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
52 work.CTSE_MSGMII_TBI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
53 work.CTSE_PEANX_SYNC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
54 work.CTSE_PECAR.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
55 work.CTSE_PECRC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
56 work.CTSE_PEHST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
57 work.CTSE_PEMGT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
58 work.CTSE_PEMSTAT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
59 work.CTSE_PEMSTAT_CNTRL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
60 work.CTSE_PEMSTAT_EIM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
61 work.CTSE_PEMSTAT_LADD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
62 work.CTSE_PEMSTAT_LINC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
63 work.CTSE_PEMSTAT_LINC_ECC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
64 work.CTSE_PEMSTAT_SADD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
65 work.CTSE_PEMSTAT_SINC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
66 work.CTSE_PEMSTAT_SINCHD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
67 work.CTSE_PEMSTAT_SINCNF.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
68 work.CTSE_PEMSTAT_STORE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
69 work.CTSE_PEREX_PCS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
70 work.CTSE_PEREX_PMA.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
71 work.CTSE_PERFN_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
72 work.CTSE_PERMC_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
73 work.CTSE_PETBM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
74 work.CTSE_PETCR.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
75 work.CTSE_PETEX_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
76 work.CTSE_PETFN_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
77 work.CTSE_PETMC_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
78 work.CTSE_PE_MCXMAC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
79 work.CTSE_PE_MCXMAC_CORE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
80 work.CTSE_PF2_RxRAM_ECC_10.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
81 work.CTSE_PF2_RxRAM_ECC_11.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
82 work.CTSE_PF2_RxRAM_ECC_12.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
83 work.CTSE_PF2_RxRAM_ECC_13.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
84 work.CTSE_PF2_RxRAM_ECC_14.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
85 work.CTSE_PF2_RxRAM_ECC_7.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
86 work.CTSE_PF2_RxRAM_ECC_8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
87 work.CTSE_PF2_RxRAM_ECC_9.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
88 work.CTSE_PF2_TxRAM_ECC_10.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
89 work.CTSE_PF2_TxRAM_ECC_11.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
90 work.CTSE_PF2_TxRAM_ECC_12.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
91 work.CTSE_PF2_TxRAM_ECC_13.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
92 work.CTSE_PF2_TxRAM_ECC_6.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
93 work.CTSE_PF2_TxRAM_ECC_7.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
94 work.CTSE_PF2_TxRAM_ECC_8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
95 work.CTSE_PF2_TxRAM_ECC_9.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
96 work.CTSE_PF_RxTPSRAM_10.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
97 work.CTSE_PF_RxTPSRAM_11.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
98 work.CTSE_PF_RxTPSRAM_12.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
99 work.CTSE_PF_RxTPSRAM_13.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
100 work.CTSE_PF_RxTPSRAM_14.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
101 work.CTSE_PF_RxTPSRAM_7.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
102 work.CTSE_PF_RxTPSRAM_8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
103 work.CTSE_PF_RxTPSRAM_9.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
104 work.CTSE_PF_TxTPSRAM_10.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
105 work.CTSE_PF_TxTPSRAM_11.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
106 work.CTSE_PF_TxTPSRAM_12.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
107 work.CTSE_PF_TxTPSRAM_13.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
108 work.CTSE_PF_TxTPSRAM_6.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
109 work.CTSE_PF_TxTPSRAM_7.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
110 work.CTSE_PF_TxTPSRAM_8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
111 work.CTSE_PF_TxTPSRAM_9.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
112 work.CTSE_R10B8B.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
113 work.CTSE_REGISTERSLICE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
114 work.CTSE_REGSLICEFULL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
115 work.CTSE_RX4096X36.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
116 work.CTSE_RX4096X36_PF.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
117 work.CTSE_RX4096X36_RTG4.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
118 work.CTSE_RX8192X36_PF2.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
119 work.CTSE_RXMEM_10.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
120 work.CTSE_RXMEM_11.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
121 work.CTSE_RXMEM_12.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
122 work.CTSE_RXMEM_13.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
123 work.CTSE_RXMEM_14.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
124 work.CTSE_RXMEM_7.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
125 work.CTSE_RXMEM_8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
126 work.CTSE_RXMEM_9.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
127 work.CTSE_SELF_DESTRUCT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
128 work.CTSE_SIB_SYNC_2FLP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
129 work.CTSE_SIB_SYNC_PULSE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
130 work.CTSE_SI_SAL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
131 work.CTSE_T8B10B.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
132 work.CTSE_TSMAC_TOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
133 work.CTSE_TSM_SYSREG.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
134 work.CTSE_TX2048X40.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
135 work.CTSE_TX2048X40_PF.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
136 work.CTSE_TX2048X40_RTG4.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
137 work.CTSE_TX4096X40_PF2.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
138 work.CTSE_TXMEM_10.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
139 work.CTSE_TXMEM_11.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
140 work.CTSE_TXMEM_12.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
141 work.CTSE_TXMEM_13.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
142 work.CTSE_TXMEM_6.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
143 work.CTSE_TXMEM_7.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
144 work.CTSE_TXMEM_8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
145 work.CTSE_TXMEM_9.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
146 work.CoreAPB3_0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
147 work.CoreUARTapb_0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
148 work.CoreUARTapb_0_CoreUARTapb_0_0_COREUART.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
149 work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
150 work.CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
151 work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
152 work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
153 work.CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
154 work.CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
155 work.CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
156 work.Core_reset_pf.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
157 work.Core_reset_pf_Core_reset_pf_0_CORERESET_PF.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
158 work.DEBUG.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
159 work.DLL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
160 work.DRI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
161 work.ENFORCE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
162 work.GLITCHDETECT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
163 work.GPSS_COMMON.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
164 work.HS_IO_CLK.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
165 work.ICB_BANKCLK.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
166 work.ICB_CLKDIV.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
167 work.ICB_CLKDIVDELAY.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
168 work.ICB_CLKINT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
169 work.ICB_CLKSTOP.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
170 work.ICB_CLKSTOP_EN.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
171 work.ICB_INT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
172 work.ICB_MUXING.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
173 work.ICB_NGMUX.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
174 work.INIT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
175 work.IOD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
176 work.LANECTRL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
177 work.LANERST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
178 work.MCHP_BLIC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
179 work.MIV_RV32_C0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
180 work.MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
181 work.OSC_RC160MHZ.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
182 work.OSC_RC200MHZ.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
183 work.OSC_RC2MHZ.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
184 work.OiOI1.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
185 work.PCIE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
186 work.PCIE_COMMON.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
187 work.PFSOC_SCSM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
188 work.PF_CCC_0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
189 work.PF_CCC_0_PF_CCC_0_0_PF_CCC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
190 work.PF_IOD_CDR_C0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
191 work.PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
192 work.PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
193 work.PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
194 work.PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
195 work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
196 work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
197 work.PF_IOD_CDR_CCC_C0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
198 work.PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
199 work.PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
200 work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
201 work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
202 work.PF_SPI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
361 work.PF_TPSRAM_C0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v (2026-04-15 21:16:35, 2026-04-15 22:42:58) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
362 work.PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v (2026-04-15 21:16:35, 2026-04-15 22:42:58) <-- (may instantiate this module)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v (2026-04-15 21:16:35, 2026-04-15 22:42:58) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
203 work.PLL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
204 work.QUADRST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
205 work.QUADRST_PCIE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
206 work.SCB.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
207 work.SSDetect.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
208 work.SYSCTRL_RESET_STATUS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
209 work.SYSRESET.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
210 work.SYS_SERVICES.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
211 work.TAMPER.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
212 work.TVS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
213 work.TX_PLL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
214 work.UPROM.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
215 work.USPI.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
216 work.VOLTAGEDETECT.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
217 work.VREFBANKDYN.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
218 work.VREFCTRL.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
219 work.XCVR.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
220 work.XCVR_64B6XB.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
221 work.XCVR_8B10B.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
222 work.XCVR_APB_LINK.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
223 work.XCVR_APB_LINK_V.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
224 work.XCVR_APB_LINK_V2.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
225 work.XCVR_DUAL_PCS.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
226 work.XCVR_PIPE.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
227 work.XCVR_PIPE_AXI0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
228 work.XCVR_PIPE_AXI1.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
229 work.XCVR_PMA.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
230 work.XCVR_REF_CLK.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
231 work.XCVR_REF_CLK_N.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
232 work.XCVR_REF_CLK_P.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
233 work.XCVR_TEST.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
234 work.XCVR_VV.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v (2026-04-15 21:56:00, 2026-04-15 22:44:52) <-- (module definition)
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
363 work.fifo_to_tpsram_bridge.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v (2026-04-15 21:45:39, 2026-04-15 22:40:31) <-- (module definition)
235 work.miv_rv32_axi_egress_buffer.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
236 work.miv_rv32_axi_egress_slip_buffer.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
237 work.miv_rv32_axi_ingress_buffer.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
238 work.miv_rv32_axi_rchan.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
239 work.miv_rv32_axi_wchan.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
240 work.miv_rv32_axi_xaddr_buffer.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
241 work.miv_rv32_axi_xaddr_buffer_slot.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
242 work.miv_rv32_bcu.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
243 work.miv_rv32_bist_decode.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
244 work.miv_rv32_bist_ecc.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
245 work.miv_rv32_bist_ecc_core.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
246 work.miv_rv32_bist_ecc_empty.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
247 work.miv_rv32_bist_ecc_read.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
248 work.miv_rv32_bist_ecc_write.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
249 work.miv_rv32_bist_err_inject.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
250 work.miv_rv32_bist_pipeline.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
251 work.miv_rv32_bist_template_dual_behav.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
252 work.miv_rv32_bistdual_behav.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
253 work.miv_rv32_bistdual_eccw.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
254 work.miv_rv32_bistdual_err_mask.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
255 work.miv_rv32_bistdual_pl_enable.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
256 work.miv_rv32_bistdual_ram_init.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
257 work.miv_rv32_bistdual_ram_stabilizer.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
258 work.miv_rv32_bistdualdata_behav.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
259 work.miv_rv32_bistmux.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
260 work.miv_rv32_bootrom.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
261 work.miv_rv32_buffer.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
262 work.miv_rv32_common_buffer_behav.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
263 work.miv_rv32_control_mvp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
264 work.miv_rv32_csr_decode.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
265 work.miv_rv32_csr_gpr_state_reg.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
266 work.miv_rv32_csr_privarch.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
267 work.miv_rv32_debug_dtm_jtag.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
268 work.miv_rv32_debug_du.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
269 work.miv_rv32_debug_fifo.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
270 work.miv_rv32_debug_sba.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
271 work.miv_rv32_div_sqrt_top_mvp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
272 work.miv_rv32_dpr_hqa_dual_storage_bistw_behav.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
273 work.miv_rv32_dpr_hqa_dual_storage_rbcw.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
274 work.miv_rv32_expipe.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
275 work.miv_rv32_exu.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
276 work.miv_rv32_fetch_unit.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
277 work.miv_rv32_fixed_arb.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
278 work.miv_rv32_fpnew_cast_multi.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
279 work.miv_rv32_fpnew_classifier.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
280 work.miv_rv32_fpnew_divsqrt_multi.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
281 work.miv_rv32_fpnew_divsqrt_th_32.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
282 work.miv_rv32_fpnew_fma.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
283 work.miv_rv32_fpnew_fma_multi.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
284 work.miv_rv32_fpnew_noncomp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
285 work.miv_rv32_fpnew_opgroup_block.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
286 work.miv_rv32_fpnew_opgroup_fmt_slice.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
287 work.miv_rv32_fpnew_opgroup_multifmt_slice.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
288 work.miv_rv32_fpnew_rounding.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
289 work.miv_rv32_fpnew_sdotp_multi.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
290 work.miv_rv32_fpnew_sdotp_multi_wrapper.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
291 work.miv_rv32_fpnew_top.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
292 work.miv_rv32_gated_clk_cell.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
293 work.miv_rv32_gpr.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
294 work.miv_rv32_gpr_ecc_bist_template.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
295 work.miv_rv32_gpr_ecc_enc_dec.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
296 work.miv_rv32_gpr_ecc_enc_dec_bistw_behav.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
297 work.miv_rv32_gpr_ram.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
298 work.miv_rv32_gpr_ram_array.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
299 work.miv_rv32_gpr_ram_init.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
300 work.miv_rv32_gpr_ram_mux.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
301 work.miv_rv32_hart.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
302 work.miv_rv32_icache_array.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
303 work.miv_rv32_icache_ram_init.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
304 work.miv_rv32_icache_ram_mux.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
305 work.miv_rv32_idecode.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
306 work.miv_rv32_ifu_iab.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
307 work.miv_rv32_ipcore.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
308 work.miv_rv32_irq_reg.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
309 work.miv_rv32_iteration_div_sqrt_mvp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
310 work.miv_rv32_logic_mux_behav_v2.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
311 work.miv_rv32_lsu.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
312 work.miv_rv32_lzc.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
313 work.miv_rv32_mul.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
314 work.miv_rv32_norm_div_sqrt_mvp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
315 work.miv_rv32_nrbd_nrsc_mvp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
316 work.miv_rv32_pa_fdsu_ctrl.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
317 work.miv_rv32_pa_fdsu_ff1.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
318 work.miv_rv32_pa_fdsu_pack_single.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
319 work.miv_rv32_pa_fdsu_prepare.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
320 work.miv_rv32_pa_fdsu_round_single.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
321 work.miv_rv32_pa_fdsu_special.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
322 work.miv_rv32_pa_fdsu_srt_single.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
323 work.miv_rv32_pa_fdsu_top.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
324 work.miv_rv32_pa_fpu_dp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
325 work.miv_rv32_pa_fpu_frbus.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
326 work.miv_rv32_pa_fpu_src_type.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
327 work.miv_rv32_popcount.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
328 work.miv_rv32_preprocess_mvp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
329 work.miv_rv32_priv_irq.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
330 work.miv_rv32_ram_dport_reg.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
331 work.miv_rv32_ram_singleport_addreg.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
332 work.miv_rv32_ram_singleport_lp.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
333 work.miv_rv32_ram_singleport_lp_ecc.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
334 work.miv_rv32_rr_arb_tree.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
335 work.miv_rv32_rr_pri_arb.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
336 work.miv_rv32_strb_to_addr.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
337 work.miv_rv32_subsys_ahb_initiator.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
338 work.miv_rv32_subsys_apb_initiator.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
339 work.miv_rv32_subsys_axi_initiator.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
340 work.miv_rv32_subsys_debug.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
341 work.miv_rv32_subsys_icache.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
342 work.miv_rv32_subsys_interconnect.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
343 work.miv_rv32_subsys_mtime_irq.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
344 work.miv_rv32_subsys_regs.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
345 work.miv_rv32_subsys_tcm.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
346 work.miv_rv32_subsys_tcm_tas_apb_target.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
347 work.miv_rv32_subsys_udma.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
348 work.pf_init_monitor_0.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
349 work.pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (may instantiate this module)
350 work.top.verilog may have changed because the following files changed:
E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v (2026-04-15 21:55:31, 2026-04-15 22:44:24) <-- (module definition)
*******************************************************************
Unmodified files: 71
FID: path (timestamp)
63 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v (2026-04-13 19:21:10)
64 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v (2026-04-13 19:16:25)
65 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v (2026-04-13 15:41:12)
66 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v (2026-04-13 15:41:12)
67 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v (2026-04-13 15:41:12)
68 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v (2026-04-13 15:41:12)
69 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v (2026-04-13 15:41:15)
70 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v (2026-04-13 15:41:15)
71 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v (2026-04-13 15:41:15)
72 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v (2026-04-13 15:41:15)
73 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v (2026-04-13 15:41:15)
74 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v (2026-04-13 15:41:15)
75 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v (2026-04-13 15:41:15)
76 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v (2026-04-13 15:41:22)
77 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v (2026-04-13 15:41:22)
78 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v (2026-04-13 15:41:14)
79 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v (2026-04-13 15:41:14)
80 E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v (2026-04-13 15:41:14)
81 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v (2026-04-13 15:41:24)
82 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v (2026-04-13 15:41:24)
83 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v (2026-04-13 15:41:24)
84 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v (2026-04-13 15:41:24)
85 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v (2026-04-13 15:41:24)
86 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v (2025-12-19 16:00:32)
87 E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v (2026-04-13 15:41:24)
89 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v (2026-04-15 18:21:52)
90 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v (2026-04-15 18:21:52)
91 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v (2026-04-15 18:21:52)
92 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v (2026-04-15 18:21:51)
93 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v (2026-04-15 18:21:52)
94 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v (2026-04-15 18:21:52)
95 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v (2026-04-15 18:21:52)
96 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v (2026-04-15 18:21:52)
97 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v (2026-04-15 18:21:52)
98 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v (2026-04-15 18:21:52)
99 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v (2026-04-13 21:41:01)
100 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v (2026-04-13 21:41:04)
101 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v (2026-04-13 21:41:12)
102 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v (2026-04-13 21:41:03)
103 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v (2026-04-13 21:41:13)
104 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v (2026-04-13 21:41:13)
105 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v (2026-04-13 21:41:13)
106 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v (2026-04-13 21:41:13)
107 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v (2026-04-13 21:41:13)
108 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v (2026-04-13 21:41:13)
109 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v (2026-04-13 21:41:13)
110 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v (2026-04-13 21:41:02)
111 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v (2026-04-13 21:41:02)
112 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v (2026-04-13 21:41:14)
113 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v (2026-04-13 21:41:14)
114 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v (2026-04-13 21:41:54)
115 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v (2026-04-13 21:41:54)
116 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v (2026-04-13 21:42:30)
117 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v (2026-04-13 21:42:10)
118 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v (2026-04-13 21:42:16)
119 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v (2026-04-13 21:42:22)
120 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v (2026-04-13 21:42:27)
121 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v (2026-04-13 21:42:29)
122 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v (2026-04-13 21:42:29)
123 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v (2026-04-13 21:42:43)
124 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v (2026-04-13 21:42:44)
125 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v (2026-04-13 21:42:46)
126 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v (2026-04-13 21:42:46)
127 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v (2026-04-13 21:42:46)
130 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v (2026-04-13 21:41:58)
131 E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v (2026-04-13 21:41:58)
133 E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v (2026-04-13 21:41:00)
59 E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v (2025-04-29 18:42:56)
60 E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\vlog\hypermods.v (2025-04-29 21:23:26)
61 E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\vlog\scemi_objects.v (2025-04-29 21:23:26)
62 E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\vlog\scemi_pipes.svh (2025-04-29 21:23:26)
*******************************************************************
Unchanged modules: 0
MID: lib.cell.view

420
synthesis/synwork/layer0.duruntime Normal file
View File

@@ -0,0 +1,420 @@
Runtime Summary:
================
* Library: work, DesignUnit: miv_rv32_subsys_tcm_Z20
Hardware Generation Phase : 0h:00m:02s
* Library: work, DesignUnit: miv_rv32_debug_sba
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: miv_rv32_ipcore_Z19
Hardware Generation Phase : 0h:00m:08s
* Library: work, DesignUnit: miv_rv32_expipe_Z16
Hardware Generation Phase : 0h:00m:01s
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: miv_rv32_csr_privarch_Z15
Hardware Generation Phase : 0h:00m:01s
* Library: work, DesignUnit: miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1
Optimization Phase : 0h:00m:02s
* Library: work, DesignUnit: miv_rv32_idecode_1_1s_1s_0s
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: CTSE_CORETSE_TOP_Z10
Hardware Generation Phase : 0h:00m:08s
* Library: work, DesignUnit: CTSE_PEMSTAT_EIM_26s_1s_0s
Optimization Phase : 0h:00m:01s
* Library: work, DesignUnit: CTSE_TSMAC_TOP_Z9
Hardware Generation Phase : 0h:00m:06s
* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_Z5
Hardware Generation Phase : 0h:00m:01s
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2
Hardware Generation Phase : 0h:00m:02s
The following design units have negligible CPU times:
=====================================================
* Library: work, DesignUnit: top
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: SSDetect
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_TPSRAM_C0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREDELAYCODE_TIP
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: pf_init_monitor_0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_CCC_0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PF_CCC_0_PF_CCC_0_0_PF_CCC
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: MIV_RV32_C0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_ram_singleport_lp_Z21
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_fixed_arb_3s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_rr_pri_arb_3s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_fixed_arb_2s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_rr_pri_arb_2s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_debug_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_debug_du
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_debug_sba
Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_debug_fifo_34s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_debug_fifo_41s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_debug_dtm_jtag_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_interconnect_Z18
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_buffer_7s_2s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_1s_50397384
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_buffer_11s_2s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_buffer_6s_2s_1s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_hart_Z17
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_gpr_ram_array_32s_6s_32s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_gpr_ram_0s_0_0s_32s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_1s_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_30s_1s_536870913
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_32s_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_5s_1s_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_31s_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_1s_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_1s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_3s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_gpr_state_reg_5s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_decode_0s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_priv_irq_2s_0_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_irq_reg_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_bcu
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1
Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_decode_1s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_idecode_1_1s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_lsu_32s_2s_1s_2s_2s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_ifu_iab_32s_2s_3s_2s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: fifo_to_tpsram_bridge
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreUARTapb_0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CORETSE_0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CORETSE_Z11
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_CORE_26s_0s_18s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_CNVRXO_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_CNVRXI_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_TBI_26s_0s_0s_1s
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PETCR_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PETBM_26s_0s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_PEANX_TOP_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEANX_SYNC_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEREX_PCS_0s_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_R10B8B
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PETEX_TOP_26s_0s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_T8B10B
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_CNVTXO_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MSGMII_CNVTXI_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_RX4096X36_12s_26s_1s_1s_4s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_TX2048X40_11s_26s_1s_1s_4s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_ECC_0s_26s_16s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_LINC_ECC_16s_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_CLKRST_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_SI_SAL_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MMCXWOL_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_26s
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_EIM_26s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_STORE_26s
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_SINCNF_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_SADD_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_SINCHD_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_SINC_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_LADD_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_LINC_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMSTAT_CNTRL_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_SIB_SYNC_PULSE_26s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PE_MCXMAC_26s_0_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PECAR_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEHST_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PEMGT_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PE_MCXMAC_CORE_26s_0_0s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PERMC_TOP_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PERFN_TOP_26s_0s_0_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PETFN_TOP_26s_0s_0_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PECRC_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_PETMC_TOP_1s_26s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: OiOI1_26s_11s_12s_32s_2s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_SIB_SYNC_2FLP_1s_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXFIF_CLKRST_26s_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXFIF_HST_Z8
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_TSM_SYSREG_26s_1s_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_DECODER
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CORESPI_0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: CORESPI_Z7
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: spi_32s_16s_32s_16s_0_0_1_0s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: spi_chanctrl_Z6
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: spi_clockmux
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: spi_fifo_16s_32s_5
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: spi_control_16s
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: CORESPI_LIB, DesignUnit: spi_rf_32s_16s_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREJTAGDEBUG_C0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: COREJTAGDEBUG_LIB, DesignUnit: corejtagdebug_bufd_34s
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREFIFO_C0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CoreAPB3_0
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: COREAPB3_LIB, DesignUnit: CoreAPB3_Z1
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: COREAPB3_LIB, DesignUnit: COREAPB3_MUXPTOB3
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: Core_reset_pf
Hardware Generation Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: Core_reset_pf_Core_reset_pf_0_CORERESET_PF
Hardware Generation Phase, Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit
Hardware Generation Phase: Negligible CPU time
* Library: work, DesignUnit: work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit
Hardware Generation Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_pkg
Hardware Generation Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_pkg
Hardware Generation Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_hart_cfg_pkg
Hardware Generation Phase: Negligible CPU time
* Library: work, DesignUnit: ICB_CLKDIV
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: DLL
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: HS_IO_CLK
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: RCLKINT
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: LANECTRL
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: IOD
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: OUTBUF_DIFF
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: BANKEN
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: INIT
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: PLL
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: INV
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: OR2
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CFG3
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CFG2
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: OR4
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_subsys_tcm_Z20
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_ipcore_Z19
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_expipe_Z16
Initial Cleanup Phase: Negligible CPU time
* Library: work, DesignUnit: miv_rv32_csr_privarch_Z15
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: INBUF_DIFF
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_CORETSE_TOP_Z10
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CTSE_TSMAC_TOP_Z9
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: CLKINT
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: BUFD
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: UJTAG
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: COREJTAGDEBUG_LIB, DesignUnit: COREJTAGDEBUG_Z5
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: VCC
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: GND
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: RAM1K20
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: BIBUF
Initial Cleanup Phase, Optimization Phase: Negligible CPU time
* Library: work, DesignUnit: AND2
Initial Cleanup Phase, Optimization Phase: Negligible CPU time

681
synthesis/synwork/layer0.fdep Normal file
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreAPB3_0\\CoreAPB3_0.v":1776096663
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\Clock_gen.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\Rx_async.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\Tx_async.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\fifo_256x8_g5.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\CoreUART.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0_0\\rtl\\vlog\\core\\CoreUARTapb.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\CoreUARTapb_0\\CoreUARTapb_0.v":1776096673
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\Core_reset_pf\\Core_reset_pf_0\\core\\corereset_pf.v":1776096662
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\Core_reset_pf\\Core_reset_pf.v":1776096662
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_hart_cfg_pkg.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_pkg.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\hart_merged\\miv_rv32_hart_merged.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_subsys_pkg.v":1766140232
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\subsys_merged\\miv_rv32_subsys_merged.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\memory\\miv_rv32_ram_singleport_lp.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\memory\\miv_rv32_ram_singleport_lp_ecc.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\MIV_RV32_C0\\MIV_RV32_C0_0\\rtl\\miv_rv32.v":1776096674
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\MIV_RV32_C0\\MIV_RV32_C0.v":1776096674
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_CCC_0\\PF_CCC_0_0\\PF_CCC_0_PF_CCC_0_0_PF_CCC.v":1776096714
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_CCC_0\\PF_CCC_0.v":1776096714
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORECDR4_CNTL_TIP\\2.0.100\\rtl\\vlog\\core\\corecdr4_cntl_tip.v":1776088270
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_LANECTRL_OVERLAY_0\\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":1776096730
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_RX_N_0\\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":1776096736
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_RX_P_0\\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":1776096742
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_TX_0\\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":1776096747
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_LANECTRL_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096749
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_LANECTRL_0\\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v":1776096749
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_C0.v":1776096750
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREDELAYCODE_TIP\\2.1.100\\rtl\\vlog\\core\\CoreDelayCode_TIP.v":1776087985
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_CCC_0\\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":1776096763
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_CLK_DIV_0\\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v":1776096764
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_LANECTRL_CORE_READER_0\\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_IOD_CDR_CCC_C0.v":1776096766
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\SSDetect.v":1776096660
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776273031
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0_0\\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776273264
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_ifu_iab_32s_2s_3s_2s_0s_buff_entry_addr_req_38460_initial_block":1776273346
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_6s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_11s_2s_1s_1s_buff_data_38460_initial_block":1776273359
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#numinternalfiles:4
#defaultlanguage:verilog
0 "E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog
1 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v" verilog
2 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v" verilog
3 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v" verilog
4 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v" verilog
5 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v" verilog
6 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v" verilog
7 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v" verilog
8 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v" verilog
9 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v" verilog
10 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v" verilog
11 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v" verilog
12 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v" verilog
13 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v" verilog
14 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v" verilog
15 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v" verilog
16 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" verilog
17 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" verilog
18 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" verilog
19 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" verilog
20 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" verilog
21 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" verilog
22 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" verilog
23 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v" verilog
24 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v" verilog
25 * "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v" verilog
26 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v" verilog
27 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" verilog
28 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" verilog
29 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" verilog
30 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v" verilog
31 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v" verilog
32 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v" verilog
33 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v" verilog
34 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v" verilog
35 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v" verilog
36 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v" verilog
37 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v" verilog
38 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v" verilog
39 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v" verilog
40 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v" verilog
41 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v" verilog
42 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v" verilog
43 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v" verilog
44 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v" verilog
45 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v" verilog
46 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v" verilog
47 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v" verilog
48 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v" verilog
49 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" verilog
50 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v" verilog
51 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v" verilog
52 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v" verilog
53 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v" verilog
54 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v" verilog
55 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v" verilog
56 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" verilog
57 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v" verilog
58 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v" verilog
59 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v" verilog
60 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v" verilog
61 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v" verilog
62 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v" verilog
63 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v" verilog
64 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v" verilog
65 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v" verilog
66 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v" verilog
67 "E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v" verilog
68 "E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v" verilog
69 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v" verilog
70 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v" verilog
71 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v" verilog
#Dependency Lists(Uses List)
0 -1
1 -1
2 -1
3 2 1
4 -1
5 -1
6 -1
7 -1
8 7
9 6 5 8 4 3
10 9
11 -1
12 11
13 -1
14 11 12 13
15 14
16 -1
17 16
18 -1
19 -1
20 -1
21 19 20 18 17
22 21
23 22
24 25
25 25
26 24 25
27 -1
28 -1
29 27 28
30 29
31 -1
32 -1
33 -1
34 -1
35 31 33 32 34
36 35
37 36
38 -1
39 38
40 -1
41 -1
42 41 40
43 -1
44 43 42 45 46
45 -1
46 -1
47 44
48 47
49 0
50 49
51 -1
52 0
53 0
54 0
55 0
56 -1
57 56 0
58 51 52 53 54 55 57
59 -1
60 0
61 0
62 -1
63 62 0
64 60 61 59 63
65 -1
66 65
67 -1
68 -1
69 0
70 69
71 39 30 10 15 23 26 37 68 48 50 70 58 64 66 67
#Dependency Lists(Users Of)
0 49 52 53 54 55 57 60 61 63 69
1 3
2 3
3 9
4 9
5 9
6 9
7 8
8 9
9 10
10 71
11 12 14
12 14
13 14
14 15
15 71
16 17
17 21
18 21
19 21
20 21
21 22
22 23
23 71
24 26
25 24 25 26
26 71
27 29
28 29
29 30
30 71
31 35
32 35
33 35
34 35
35 36
36 37
37 71
38 39
39 71
40 42
41 42
42 44
43 44
44 47
45 44
46 44
47 48
48 71
49 50
50 71
51 58
52 58
53 58
54 58
55 58
56 57
57 58
58 71
59 64
60 64
61 64
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63 64
64 71
65 66
66 71
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70 71
71 -1
#Design Unit to File Association
module work APBM 0
module work APBS 0
module work BANKCTRLM 0
module work BANKCTRL_GPIO 0
module work BANKCTRL_HSIO 0
module work BANKEN 0
module work CRN_COMMON 0
module work CRN_INT 0
module work CRYPTO 0
module work CRYPTO_SOC 0
module work DEBUG 0
module work DLL 0
module work DRI 0
module work ENFORCE 0
module work GLITCHDETECT 0
module work GPSS_COMMON 0
module work HS_IO_CLK 0
module work ICB_BANKCLK 0
module work ICB_CLKDIVDELAY 0
module work ICB_CLKDIV 0
module work ICB_CLKINT 0
module work ICB_CLKSTOP_EN 0
module work ICB_CLKSTOP 0
module work ICB_INT 0
module work ICB_MUXING 0
module work ICB_NGMUX 0
module work INIT 0
module work IOD 0
module work LANECTRL 0
module work LANERST 0
module work OSC_RC160MHZ 0
module work OSC_RC200MHZ 0
module work OSC_RC2MHZ 0
module work PCIE_COMMON 0
module work PCIE 0
module work PF_SPI 0
module work PLL 0
module work QUADRST_PCIE 0
module work QUADRST 0
module work SCB 0
module work SYSCTRL_RESET_STATUS 0
module work SYSRESET 0
module work SYS_SERVICES 0
module work TAMPER 0
module work TVS 0
module work TX_PLL 0
module work UPROM 0
module work USPI 0
module work VOLTAGEDETECT 0
module work VREFBANKDYN 0
module work VREFCTRL 0
module work XCVR_64B6XB 0
module work XCVR_8B10B 0
module work XCVR_APB_LINK 0
module work XCVR_APB_LINK_V 0
module work XCVR_APB_LINK_V2 0
module work XCVR_DUAL_PCS 0
module work XCVR_PIPE_AXI0 0
module work XCVR_PIPE_AXI1 0
module work XCVR_PIPE 0
module work XCVR_PMA 0
module work XCVR_REF_CLK_N 0
module work XCVR_REF_CLK_P 0
module work XCVR_REF_CLK 0
module work XCVR_TEST 0
module work XCVR_VV 0
module work XCVR 0
module work CORELNKTMR_V 0
module work PFSOC_SCSM 0
module work MCHP_BLIC 0
module work CLKBUF_DIFF 0
module work CLKBUF_DIFF_ODT 0
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv 1
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync 2
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_async 3
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_sync 4
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft 5
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr 6
module work COREFIFO_C0_COREFIFO_C0_0_LSRAM_top 7
module work COREFIFO_C0_COREFIFO_C0_0_ram_wrapper 8
module work COREFIFO_C0_COREFIFO_C0_0_COREFIFO 9
module work COREFIFO_C0 10
module work COREJTAGDEBUG_C0 15
module work CORESPI_0 23
module work CORETSE 24
module work CTSE_SELF_DESTRUCT 24
module work CTSE_CORETSE_TOP 24
module work CTSE_RX4096X36_PF 24
module work CTSE_PF_RxTPSRAM_7 24
module work CTSE_PF_RxTPSRAM_8 24
module work CTSE_PF_RxTPSRAM_9 24
module work CTSE_PF_RxTPSRAM_10 24
module work CTSE_PF_RxTPSRAM_11 24
module work CTSE_PF_RxTPSRAM_12 24
module work CTSE_PF_RxTPSRAM_13 24
module work CTSE_PF_RxTPSRAM_14 24
module work CTSE_TX2048X40_PF 24
module work CTSE_PF_TxTPSRAM_6 24
module work CTSE_PF_TxTPSRAM_7 24
module work CTSE_PF_TxTPSRAM_8 24
module work CTSE_PF_TxTPSRAM_9 24
module work CTSE_PF_TxTPSRAM_10 24
module work CTSE_PF_TxTPSRAM_11 24
module work CTSE_PF_TxTPSRAM_12 24
module work CTSE_PF_TxTPSRAM_13 24
module work CTSE_RX8192X36_PF2 24
module work CTSE_PF2_RxRAM_ECC_7 24
module work CTSE_PF2_RxRAM_ECC_8 24
module work CTSE_PF2_RxRAM_ECC_9 24
module work CTSE_PF2_RxRAM_ECC_10 24
module work CTSE_PF2_RxRAM_ECC_11 24
module work CTSE_PF2_RxRAM_ECC_12 24
module work CTSE_PF2_RxRAM_ECC_13 24
module work CTSE_PF2_RxRAM_ECC_14 24
module work CTSE_TX4096X40_PF2 24
module work CTSE_PF2_TxRAM_ECC_6 24
module work CTSE_PF2_TxRAM_ECC_7 24
module work CTSE_PF2_TxRAM_ECC_8 24
module work CTSE_PF2_TxRAM_ECC_9 24
module work CTSE_PF2_TxRAM_ECC_10 24
module work CTSE_PF2_TxRAM_ECC_11 24
module work CTSE_PF2_TxRAM_ECC_12 24
module work CTSE_PF2_TxRAM_ECC_13 24
module work CTSE_RX4096X36_RTG4 24
module work CTSE_RXMEM_7 24
module work CTSE_RXMEM_8 24
module work CTSE_RXMEM_9 24
module work CTSE_RXMEM_10 24
module work CTSE_RXMEM_11 24
module work CTSE_RXMEM_12 24
module work CTSE_RXMEM_13 24
module work CTSE_RXMEM_14 24
module work CTSE_TX2048X40_RTG4 24
module work CTSE_TXMEM_6 24
module work CTSE_TXMEM_7 24
module work CTSE_TXMEM_8 24
module work CTSE_TXMEM_9 24
module work CTSE_TXMEM_10 24
module work CTSE_TXMEM_11 24
module work CTSE_TXMEM_12 24
module work CTSE_TXMEM_13 24
module work CTSE_CLKRST 24
module work CTSE_TSMAC_TOP 24
module work CTSE_TX2048X40 24
module work CTSE_RX4096X36 24
module work CTSE_MSGMII_CORE 24
module work CTSE_ECC 24
module work CTSE_REGISTERSLICE 24
module work CTSE_MAPBE_HST_CNV 24
module work CTSE_DECODER 24
module work CTSE_TSM_SYSREG 24
module work OiOI1 24
module work CTSE_PE_MCXMAC 24
module work CTSE_SIB_SYNC_PULSE 24
module work CTSE_PEMSTAT 24
module work CTSE_MMCXWOL 24
module work CTSE_SIB_SYNC_2FLP 24
module work CTSE_SI_SAL 24
module work CTSE_AMCXTFIF_FAB 24
module work CTSE_AMCXTFIF_SYS 24
module work CTSE_AMCXRFIF_FAB 24
module work CTSE_AMCXRFIF_SYS 24
module work CTSE_AMCXTFIF_WTM 24
module work CTSE_AMCXFIF_HST 24
module work CTSE_AMCXFIF_CLKRST 24
module work CTSE_PEMSTAT_LINC_ECC 24
module work CTSE_MSGMII_CNVRXI 24
module work CTSE_MSGMII_CNVRXO 24
module work CTSE_MSGMII_CNVTXI 24
module work CTSE_MSGMII_CNVTXO 24
module work CTSE_MSGMII_TBI 24
module work CTSE_MSGMII_PEANX_TOP 24
module work CTSE_PEANX_SYNC 24
module work CTSE_PETEX_TOP 24
module work CTSE_PEREX_PMA 24
module work CTSE_PEREX_PCS 24
module work CTSE_PETBM 24
module work CTSE_PETCR 24
module work CTSE_PE_MCXMAC_CORE 24
module work CTSE_PEMGT 24
module work CTSE_PEHST 24
module work CTSE_PECAR 24
module work CTSE_PETMC_TOP 24
module work CTSE_PETFN_TOP 24
module work CTSE_PERFN_TOP 24
module work CTSE_PERMC_TOP 24
module work CTSE_PECRC 24
module work CTSE_PEMSTAT_CNTRL 24
module work CTSE_PEMSTAT_STORE 24
module work CTSE_PEMSTAT_EIM 24
module work CTSE_PEMSTAT_LADD 24
module work CTSE_PEMSTAT_LINC 24
module work CTSE_PEMSTAT_SADD 24
module work CTSE_PEMSTAT_SINC 24
module work CTSE_PEMSTAT_SINCHD 24
module work CTSE_PEMSTAT_SINCNF 24
module work CTSE_R10B8B 24
module work CTSE_T8B10B 24
module work CTSE_REGSLICEFULL 24
module work CORETSE_0 26
module work CoreAPB3_0 30
module work CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen 31
module work CoreUARTapb_0_CoreUARTapb_0_0_Rx_async 32
module work CoreUARTapb_0_CoreUARTapb_0_0_Tx_async 33
module work CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8 34
module work CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256 34
module work CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5 34
module work CoreUARTapb_0_CoreUARTapb_0_0_COREUART 35
module work CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb 36
module work CoreUARTapb_0 37
module work Core_reset_pf_Core_reset_pf_0_CORERESET_PF 38
module work Core_reset_pf 39
package work miv_rv32_hart_cfg_pkg 40
package work miv_rv32_pkg 41
module work miv_rv32_common_buffer_behav 42
package work work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit 42
module work miv_rv32_bcu 42
module work miv_rv32_hart 42
module work miv_rv32_fetch_unit 42
module work miv_rv32_lsu 42
module work miv_rv32_expipe 42
module work miv_rv32_csr_decode 42
module work miv_rv32_csr_privarch 42
module work miv_rv32_priv_irq 42
module work miv_rv32_csr_gpr_state_reg 42
module work miv_rv32_gpr 42
module work miv_rv32_gpr_ram 42
module work miv_rv32_gpr_ram_init 42
module work miv_rv32_gpr_ram_mux 42
module work miv_rv32_gpr_ecc_enc_dec 42
module work miv_rv32_gpr_ram_array 42
module work miv_rv32_irq_reg 42
module work miv_rv32_idecode 42
module work miv_rv32_exu 42
module work miv_rv32_mul 42
module work miv_rv32_fpnew_top 42
module work miv_rv32_ifu_iab 42
module work miv_rv32_bistdualdata_behav 42
module work miv_rv32_bistmux 42
module work miv_rv32_bistdual_behav 42
module work miv_rv32_bistdual_eccw 42
module work miv_rv32_bist_err_inject 42
module work miv_rv32_bist_ecc 42
module work miv_rv32_bistdual_err_mask 42
module work miv_rv32_bistdual_pl_enable 42
module work miv_rv32_bistdual_ram_init 42
module work miv_rv32_bistdual_ram_stabilizer 42
module work miv_rv32_logic_mux_behav_v2 42
module work miv_rv32_bist_decode 42
module work miv_rv32_bist_ecc_empty 42
module work miv_rv32_bist_ecc_core 42
module work miv_rv32_bist_ecc_write 42
module work miv_rv32_bist_ecc_read 42
module work miv_rv32_bist_pipeline 42
module work miv_rv32_bist_template_dual_behav 42
module work miv_rv32_ram_dport_reg 42
module work miv_rv32_dpr_hqa_dual_storage_bistw_behav 42
module work miv_rv32_dpr_hqa_dual_storage_rbcw 42
module work miv_rv32_gpr_ecc_bist_template 42
module work miv_rv32_gpr_ecc_enc_dec_bistw_behav 42
module work miv_rv32_fpnew_opgroup_block 42
module work miv_rv32_rr_arb_tree 42
module work miv_rv32_control_mvp 42
module work miv_rv32_iteration_div_sqrt_mvp 42
module work miv_rv32_div_sqrt_top_mvp 42
module work miv_rv32_preprocess_mvp 42
module work miv_rv32_nrbd_nrsc_mvp 42
module work miv_rv32_norm_div_sqrt_mvp 42
module work miv_rv32_fpnew_sdotp_multi_wrapper 42
module work miv_rv32_fpnew_sdotp_multi 42
module work miv_rv32_fpnew_classifier 42
module work miv_rv32_lzc 42
module work miv_rv32_fpnew_rounding 42
module work miv_rv32_fpnew_cast_multi 42
module work miv_rv32_fpnew_divsqrt_multi 42
module work miv_rv32_fpnew_fma 42
module work miv_rv32_fpnew_fma_multi 42
module work miv_rv32_fpnew_noncomp 42
module work miv_rv32_fpnew_opgroup_fmt_slice 42
module work miv_rv32_fpnew_opgroup_multifmt_slice 42
module work miv_rv32_fpnew_divsqrt_th_32 42
module work miv_rv32_popcount 42
module work miv_rv32_pa_fdsu_top 42
module work miv_rv32_pa_fpu_dp 42
module work miv_rv32_pa_fpu_frbus 42
module work miv_rv32_gated_clk_cell 42
module work miv_rv32_pa_fdsu_ctrl 42
module work miv_rv32_pa_fdsu_ff1 42
module work miv_rv32_pa_fdsu_pack_single 42
module work miv_rv32_pa_fdsu_prepare 42
module work miv_rv32_pa_fdsu_round_single 42
module work miv_rv32_pa_fdsu_special 42
module work miv_rv32_pa_fdsu_srt_single 42
module work miv_rv32_pa_fpu_src_type 42
package work miv_rv32_subsys_pkg 43
package work work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit 44
module work miv_rv32_ipcore 44
module work miv_rv32_subsys_debug 44
module work miv_rv32_subsys_interconnect 44
module work miv_rv32_subsys_apb_initiator 44
module work miv_rv32_subsys_tcm_tas_apb_target 44
module work miv_rv32_subsys_tcm 44
module work miv_rv32_subsys_axi_initiator 44
module work miv_rv32_subsys_ahb_initiator 44
module work miv_rv32_subsys_udma 44
module work miv_rv32_subsys_mtime_irq 44
module work miv_rv32_subsys_icache 44
module work miv_rv32_buffer 44
module work miv_rv32_subsys_regs 44
module work miv_rv32_rr_pri_arb 44
module work miv_rv32_strb_to_addr 44
module work miv_rv32_axi_rchan 44
module work miv_rv32_axi_wchan 44
module work miv_rv32_axi_egress_buffer 44
module work miv_rv32_axi_egress_slip_buffer 44
module work miv_rv32_axi_ingress_buffer 44
module work miv_rv32_axi_xaddr_buffer 44
module work miv_rv32_axi_xaddr_buffer_slot 44
module work miv_rv32_fixed_arb 44
module work miv_rv32_ram_singleport_addreg 44
module work miv_rv32_ram_singleport_lp_ecc 46
module work miv_rv32_ram_singleport_lp 45
module work miv_rv32_bootrom 44
module work miv_rv32_icache_ram_init 44
module work miv_rv32_icache_ram_mux 44
module work miv_rv32_icache_array 44
module work miv_rv32_debug_dtm_jtag 44
module work miv_rv32_debug_fifo 44
module work miv_rv32_debug_du 44
module work miv_rv32_debug_sba 44
module work MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32 47
module work MIV_RV32_C0 48
module work PF_CCC_0_PF_CCC_0_0_PF_CCC 49
module work PF_CCC_0 50
module work CORECDR4_CNTL_TIP 51
module work PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD 52
module work PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD 53
module work PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD 54
module work PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD 55
module work PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC 56
module work PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL 57
module work PF_IOD_CDR_C0 58
module work COREDELAYCODE_TIP 59
module work PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC 60
module work PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV 61
module work PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC 62
module work PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL 63
module work PF_IOD_CDR_CCC_C0 64
module work PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM 65
module work PF_TPSRAM_C0 66
module work SSDetect 67
module work fifo_to_tpsram_bridge 68
module work pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR 69
module work pf_init_monitor_0 70
module work top 71
module COREJTAGDEBUG_LIB corejtagdebug_bufd 11
module COREJTAGDEBUG_LIB COREJTAGDEBUG_UJ_JTAG 12
module COREJTAGDEBUG_LIB UJTAG_WRAPPER 13
module COREJTAGDEBUG_LIB COREJTAGDEBUG 14
module CORESPI_LIB spi_clockmux 16
module CORESPI_LIB spi_chanctrl 17
module CORESPI_LIB spi_fifo 18
module CORESPI_LIB spi_rf 19
module CORESPI_LIB spi_control 20
module CORESPI_LIB spi 21
module CORESPI_LIB CORESPI 22
module COREAPB3_LIB COREAPB3_MUXPTOB3 27
module COREAPB3_LIB coreapb3_iaddr_reg 28
module COREAPB3_LIB CoreAPB3 29
#identified top module
top_module top

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#XMR Information

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Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2
work, miv_rv32_subsys_tcm_Z20,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 353 MB, 35 MB, 34 MB, 1 MB, 0 MB
work, miv_rv32_debug_sba,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 355 MB, 23 MB, 0 MB, 6 MB, 16 MB
work, miv_rv32_ipcore_Z19,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 355 MB, 43 MB, 43 MB, 0 MB, 0 MB
work, miv_rv32_expipe_Z16,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:01s, 364 MB, 2 MB, 0 MB, 2 MB, 0 MB
work, miv_rv32_csr_privarch_Z15,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 364 MB, 2 MB, 1 MB, 0 MB, 1 MB
work, miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1,0h:00m:03s,0h:00m:00s,0h:00m:00s,0h:00m:02s, 397 MB, 61 MB, 0 MB, 30 MB, 32 MB
work, miv_rv32_idecode_1_1s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 397 MB, 11 MB, 10 MB, 1 MB, 0 MB
work, CTSE_CORETSE_TOP_Z10,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 398 MB, 13 MB, 13 MB, 0 MB, 0 MB
work, CTSE_PEMSTAT_EIM_26s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_TSMAC_TOP_Z9,0h:00m:06s,0h:00m:06s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
COREJTAGDEBUG_LIB, COREJTAGDEBUG_Z5,0h:00m:01s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 398 MB, 1 MB, 1 MB, 0 MB, 0 MB
work, COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
1 Library Design Unit Compile time Hardware Gen Optimization Stg1 Optimization Stg2 Peak Mem Usage Incr Mem Usage Hardware Gen Optimization Stg1 Optimization Stg2
2 work miv_rv32_subsys_tcm_Z20 0h:00m:02s 0h:00m:02s 0h:00m:00s 0h:00m:00s 353 MB 35 MB 34 MB 1 MB 0 MB
3 work miv_rv32_debug_sba 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 355 MB 23 MB 0 MB 6 MB 16 MB
4 work miv_rv32_ipcore_Z19 0h:00m:08s 0h:00m:08s 0h:00m:00s 0h:00m:00s 355 MB 43 MB 43 MB 0 MB 0 MB
5 work miv_rv32_expipe_Z16 0h:00m:02s 0h:00m:01s 0h:00m:00s 0h:00m:01s 364 MB 2 MB 0 MB 2 MB 0 MB
6 work miv_rv32_csr_privarch_Z15 0h:00m:02s 0h:00m:01s 0h:00m:00s 0h:00m:00s 364 MB 2 MB 1 MB 0 MB 1 MB
7 work miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 0h:00m:03s 0h:00m:00s 0h:00m:00s 0h:00m:02s 397 MB 61 MB 0 MB 30 MB 32 MB
8 work miv_rv32_idecode_1_1s_1s_0s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 397 MB 11 MB 10 MB 1 MB 0 MB
9 work CTSE_CORETSE_TOP_Z10 0h:00m:08s 0h:00m:08s 0h:00m:00s 0h:00m:00s 398 MB 13 MB 13 MB 0 MB 0 MB
10 work CTSE_PEMSTAT_EIM_26s_1s_0s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 398 MB 0 MB 0 MB 0 MB 0 MB
11 work CTSE_TSMAC_TOP_Z9 0h:00m:06s 0h:00m:06s 0h:00m:00s 0h:00m:00s 398 MB 0 MB 0 MB 0 MB 0 MB
12 COREJTAGDEBUG_LIB COREJTAGDEBUG_Z5 0h:00m:01s 0h:00m:01s 0h:00m:00s 0h:00m:00s 398 MB 1 MB 1 MB 0 MB 0 MB
13 work COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 0h:00m:02s 0h:00m:02s 0h:00m:00s 0h:00m:00s 398 MB 0 MB 0 MB 0 MB 0 MB

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#OPTIONS:"|-layerid|0|-orig_srs|E:\\AbhishekV\\rising\\ethernet_tpsram_test\\synthesis\\synwork\\top_comp.srs|-top|top|-prodtype|synplify_pro|-infer_seqShift|-primux|-dspmac|-pqdpadd|-fixsmult|-sdff_counter|-divnmod|-nram|-actel|-I|E:\\AbhishekV\\rising\\ethernet_tpsram_test\\synthesis\\|-I|E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib|-sysv|-devicelib|E:\\Microchip\\Libero_SoC_2025.1\\Libero_SoC\\Synplify_Pro\\lib\\generic\\acg5.v|-encrypt|-pro|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|COREJTAGDEBUG_LIB|-lib|COREJTAGDEBUG_LIB|-lib|COREJTAGDEBUG_LIB|-lib|COREJTAGDEBUG_LIB|-lib|work|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|CORESPI_LIB|-lib|work|-lib|work|-lib|work|-lib|COREAPB3_LIB|-lib|COREAPB3_LIB|-lib|COREAPB3_LIB|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_nstagessync.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_async.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_sync.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_fwft.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\corefifo_sync_scntr.v":1776257512
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\COREFIFO_C0\\COREFIFO_C0_0\\rtl\\vlog\\core\\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v":1776257512
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CoreAPB3\\4.2.100\\rtl\\vlog\\core\\coreapb3_muxptob3.v":1776075074
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_hart_cfg_pkg.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\hart_merged\\miv_rv32_hart_merged.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\pkg\\miv_rv32_subsys_pkg.v":1766140232
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\subsys_merged\\miv_rv32_subsys_merged.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\memory\\miv_rv32_ram_singleport_lp.v":1776075084
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Microsemi\\MiV\\MIV_RV32\\3.1.200\\memory\\miv_rv32_ram_singleport_lp_ecc.v":1776075084
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_CCC_0\\PF_CCC_0_0\\PF_CCC_0_PF_CCC_0_0_PF_CCC.v":1776096714
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_CCC_0\\PF_CCC_0.v":1776096714
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\CORECDR4_CNTL_TIP\\2.0.100\\rtl\\vlog\\core\\corecdr4_cntl_tip.v":1776088270
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_LANECTRL_OVERLAY_0\\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":1776096730
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_RX_N_0\\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":1776096736
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_RX_P_0\\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":1776096742
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_IOD_CDR_TX_0\\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":1776096747
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_C0\\PF_LANECTRL_0\\PF_LANECTRL_PAUSE_SYNC.v":1776096749
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\Actel\\DirectCore\\COREDELAYCODE_TIP\\2.1.100\\rtl\\vlog\\core\\CoreDelayCode_TIP.v":1776087985
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_CCC_0\\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":1776096763
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_IOD_CDR_CCC_C0\\PF_CLK_DIV_0\\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v":1776096764
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#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0_0\\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\PF_TPSRAM_C0\\PF_TPSRAM_C0.v":1776273178
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\SSDetect.v":1776096660
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\hdl\\fifo_to_tpsram_bridge.v":1776273031
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0_0\\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\pf_init_monitor_0\\pf_init_monitor_0.v":1776096718
#CUR:"E:\\AbhishekV\\rising\\ethernet_tpsram_test\\component\\work\\top\\top.v":1776273264
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#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
#CUR:"miv_rv32_buffer_7s_2s_1s_1s_buff_data_38460_initial_block":1776273360
0 "E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog
1 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v" verilog
2 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v" verilog
3 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v" verilog
4 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v" verilog
5 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v" verilog
6 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v" verilog
7 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v" verilog
8 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v" verilog
9 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v" verilog
10 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v" verilog
11 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v" verilog
12 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v" verilog
13 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v" verilog
14 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v" verilog
15 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v" verilog
16 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" verilog
17 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" verilog
18 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" verilog
19 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" verilog
20 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" verilog
21 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" verilog
22 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" verilog
23 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v" verilog
24 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v" verilog
25 * "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v" verilog
26 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v" verilog
27 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" verilog
28 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" verilog
29 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" verilog
30 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v" verilog
31 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v" verilog
32 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v" verilog
33 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v" verilog
34 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v" verilog
35 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v" verilog
36 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v" verilog
37 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v" verilog
38 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v" verilog
39 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v" verilog
40 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v" verilog
41 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v" verilog
42 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v" verilog
43 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v" verilog
44 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v" verilog
45 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v" verilog
46 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v" verilog
47 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v" verilog
48 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v" verilog
49 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" verilog
50 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v" verilog
51 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v" verilog
52 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v" verilog
53 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v" verilog
54 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v" verilog
55 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v" verilog
56 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" verilog
57 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v" verilog
58 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v" verilog
59 "E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v" verilog
60 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v" verilog
61 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v" verilog
62 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v" verilog
63 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v" verilog
64 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v" verilog
65 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v" verilog
66 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v" verilog
67 "E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v" verilog
68 "E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v" verilog
69 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v" verilog
70 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v" verilog
71 "E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v" verilog
#Dependency Lists(Uses List)
0 -1
1 -1
2 -1
3 1 2
4 -1
5 -1
6 -1
7 -1
8 7
9 3 4 8 5 6
10 9
11 -1
12 11
13 -1
14 13 12 11
15 14
16 -1
17 16
18 -1
19 -1
20 -1
21 17 18 20 19
22 21
23 22
24 25
25 25
26 25 24
27 -1
28 -1
29 28 27
30 29
31 -1
32 -1
33 -1
34 -1
35 34 32 33 31
36 35
37 36
38 -1
39 38
40 -1
41 -1
42 40 41
43 -1
44 46 45 42 43
45 -1
46 -1
47 44
48 47
49 0
50 49
51 -1
52 0
53 0
54 0
55 0
56 -1
57 0 56
58 57 55 54 53 52 51
59 -1
60 0
61 0
62 -1
63 0 62
64 63 59 61 60
65 -1
66 65
67 -1
68 -1
69 0
70 69
71 67 66 64 58 70 50 48 68 37 26 23 15 10 30 39
#Dependency Lists(Users Of)
0 69 63 61 60 57 55 54 53 52 49
1 3
2 3
3 9
4 9
5 9
6 9
7 8
8 9
9 10
10 71
11 14 12
12 14
13 14
14 15
15 71
16 17
17 21
18 21
19 21
20 21
21 22
22 23
23 71
24 26
25 26 25 24
26 71
27 29
28 29
29 30
30 71
31 35
32 35
33 35
34 35
35 36
36 37
37 71
38 39
39 71
40 42
41 42
42 44
43 44
44 47
45 44
46 44
47 48
48 71
49 50
50 71
51 58
52 58
53 58
54 58
55 58
56 57
57 58
58 71
59 64
60 64
61 64
62 63
63 64
64 71
65 66
66 71
67 71
68 71
69 70
70 71
71 -1
#Design Unit to File Association
module COREAPB3_LIB CoreAPB3 29
module COREAPB3_LIB coreapb3_iaddr_reg 28
module COREAPB3_LIB COREAPB3_MUXPTOB3 27
module CORESPI_LIB CORESPI 22
module CORESPI_LIB spi 21
module CORESPI_LIB spi_control 20
module CORESPI_LIB spi_rf 19
module CORESPI_LIB spi_fifo 18
module CORESPI_LIB spi_chanctrl 17
module CORESPI_LIB spi_clockmux 16
module COREJTAGDEBUG_LIB COREJTAGDEBUG 14
module COREJTAGDEBUG_LIB UJTAG_WRAPPER 13
module COREJTAGDEBUG_LIB COREJTAGDEBUG_UJ_JTAG 12
module COREJTAGDEBUG_LIB corejtagdebug_bufd 11
module work top 71
module work pf_init_monitor_0 70
module work pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR 69
module work fifo_to_tpsram_bridge 68
module work SSDetect 67
module work PF_TPSRAM_C0 66
module work PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM 65
module work PF_IOD_CDR_CCC_C0 64
module work PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL 63
module work PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC 62
module work PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV 61
module work PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC 60
module work COREDELAYCODE_TIP 59
module work PF_IOD_CDR_C0 58
module work PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL 57
module work PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC 56
module work PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD 55
module work PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD 54
module work PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD 53
module work PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD 52
module work CORECDR4_CNTL_TIP 51
module work PF_CCC_0 50
module work PF_CCC_0_PF_CCC_0_0_PF_CCC 49
module work MIV_RV32_C0 48
module work MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32 47
module work miv_rv32_debug_sba 44
module work miv_rv32_debug_du 44
module work miv_rv32_debug_fifo 44
module work miv_rv32_debug_dtm_jtag 44
module work miv_rv32_icache_array 44
module work miv_rv32_icache_ram_mux 44
module work miv_rv32_icache_ram_init 44
module work miv_rv32_bootrom 44
module work miv_rv32_ram_singleport_lp 45
module work miv_rv32_ram_singleport_lp_ecc 46
module work miv_rv32_ram_singleport_addreg 44
module work miv_rv32_fixed_arb 44
module work miv_rv32_axi_xaddr_buffer_slot 44
module work miv_rv32_axi_xaddr_buffer 44
module work miv_rv32_axi_ingress_buffer 44
module work miv_rv32_axi_egress_slip_buffer 44
module work miv_rv32_axi_egress_buffer 44
module work miv_rv32_axi_wchan 44
module work miv_rv32_axi_rchan 44
module work miv_rv32_strb_to_addr 44
module work miv_rv32_rr_pri_arb 44
module work miv_rv32_subsys_regs 44
module work miv_rv32_buffer 44
module work miv_rv32_subsys_icache 44
module work miv_rv32_subsys_mtime_irq 44
module work miv_rv32_subsys_udma 44
module work miv_rv32_subsys_ahb_initiator 44
module work miv_rv32_subsys_axi_initiator 44
module work miv_rv32_subsys_tcm 44
module work miv_rv32_subsys_tcm_tas_apb_target 44
module work miv_rv32_subsys_apb_initiator 44
module work miv_rv32_subsys_interconnect 44
module work miv_rv32_subsys_debug 44
module work miv_rv32_ipcore 44
module work miv_rv32_pa_fpu_src_type 42
module work miv_rv32_pa_fdsu_srt_single 42
module work miv_rv32_pa_fdsu_special 42
module work miv_rv32_pa_fdsu_round_single 42
module work miv_rv32_pa_fdsu_prepare 42
module work miv_rv32_pa_fdsu_pack_single 42
module work miv_rv32_pa_fdsu_ff1 42
module work miv_rv32_pa_fdsu_ctrl 42
module work miv_rv32_gated_clk_cell 42
module work miv_rv32_pa_fpu_frbus 42
module work miv_rv32_pa_fpu_dp 42
module work miv_rv32_pa_fdsu_top 42
module work miv_rv32_popcount 42
module work miv_rv32_fpnew_divsqrt_th_32 42
module work miv_rv32_fpnew_opgroup_multifmt_slice 42
module work miv_rv32_fpnew_opgroup_fmt_slice 42
module work miv_rv32_fpnew_noncomp 42
module work miv_rv32_fpnew_fma_multi 42
module work miv_rv32_fpnew_fma 42
module work miv_rv32_fpnew_divsqrt_multi 42
module work miv_rv32_fpnew_cast_multi 42
module work miv_rv32_fpnew_rounding 42
module work miv_rv32_lzc 42
module work miv_rv32_fpnew_classifier 42
module work miv_rv32_fpnew_sdotp_multi 42
module work miv_rv32_fpnew_sdotp_multi_wrapper 42
module work miv_rv32_norm_div_sqrt_mvp 42
module work miv_rv32_nrbd_nrsc_mvp 42
module work miv_rv32_preprocess_mvp 42
module work miv_rv32_div_sqrt_top_mvp 42
module work miv_rv32_iteration_div_sqrt_mvp 42
module work miv_rv32_control_mvp 42
module work miv_rv32_rr_arb_tree 42
module work miv_rv32_fpnew_opgroup_block 42
module work miv_rv32_gpr_ecc_enc_dec_bistw_behav 42
module work miv_rv32_gpr_ecc_bist_template 42
module work miv_rv32_dpr_hqa_dual_storage_rbcw 42
module work miv_rv32_dpr_hqa_dual_storage_bistw_behav 42
module work miv_rv32_ram_dport_reg 42
module work miv_rv32_bist_template_dual_behav 42
module work miv_rv32_bist_pipeline 42
module work miv_rv32_bist_ecc_read 42
module work miv_rv32_bist_ecc_write 42
module work miv_rv32_bist_ecc_core 42
module work miv_rv32_bist_ecc_empty 42
module work miv_rv32_bist_decode 42
module work miv_rv32_logic_mux_behav_v2 42
module work miv_rv32_bistdual_ram_stabilizer 42
module work miv_rv32_bistdual_ram_init 42
module work miv_rv32_bistdual_pl_enable 42
module work miv_rv32_bistdual_err_mask 42
module work miv_rv32_bist_ecc 42
module work miv_rv32_bist_err_inject 42
module work miv_rv32_bistdual_eccw 42
module work miv_rv32_bistdual_behav 42
module work miv_rv32_bistmux 42
module work miv_rv32_bistdualdata_behav 42
module work miv_rv32_ifu_iab 42
module work miv_rv32_fpnew_top 42
module work miv_rv32_mul 42
module work miv_rv32_exu 42
module work miv_rv32_idecode 42
module work miv_rv32_irq_reg 42
module work miv_rv32_gpr_ram_array 42
module work miv_rv32_gpr_ecc_enc_dec 42
module work miv_rv32_gpr_ram_mux 42
module work miv_rv32_gpr_ram_init 42
module work miv_rv32_gpr_ram 42
module work miv_rv32_gpr 42
module work miv_rv32_csr_gpr_state_reg 42
module work miv_rv32_priv_irq 42
module work miv_rv32_csr_privarch 42
module work miv_rv32_csr_decode 42
module work miv_rv32_expipe 42
module work miv_rv32_lsu 42
module work miv_rv32_fetch_unit 42
module work miv_rv32_hart 42
module work miv_rv32_bcu 42
module work miv_rv32_common_buffer_behav 42
module work Core_reset_pf 39
module work Core_reset_pf_Core_reset_pf_0_CORERESET_PF 38
module work CoreUARTapb_0 37
module work CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb 36
module work CoreUARTapb_0_CoreUARTapb_0_0_COREUART 35
module work CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5 34
module work CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256 34
module work CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8 34
module work CoreUARTapb_0_CoreUARTapb_0_0_Tx_async 33
module work CoreUARTapb_0_CoreUARTapb_0_0_Rx_async 32
module work CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen 31
module work CoreAPB3_0 30
module work CORETSE_0 26
module work CTSE_REGSLICEFULL 24
module work CTSE_T8B10B 24
module work CTSE_R10B8B 24
module work CTSE_PEMSTAT_SINCNF 24
module work CTSE_PEMSTAT_SINCHD 24
module work CTSE_PEMSTAT_SINC 24
module work CTSE_PEMSTAT_SADD 24
module work CTSE_PEMSTAT_LINC 24
module work CTSE_PEMSTAT_LADD 24
module work CTSE_PEMSTAT_EIM 24
module work CTSE_PEMSTAT_STORE 24
module work CTSE_PEMSTAT_CNTRL 24
module work CTSE_PECRC 24
module work CTSE_PERMC_TOP 24
module work CTSE_PERFN_TOP 24
module work CTSE_PETFN_TOP 24
module work CTSE_PETMC_TOP 24
module work CTSE_PECAR 24
module work CTSE_PEHST 24
module work CTSE_PEMGT 24
module work CTSE_PE_MCXMAC_CORE 24
module work CTSE_PETCR 24
module work CTSE_PETBM 24
module work CTSE_PEREX_PCS 24
module work CTSE_PEREX_PMA 24
module work CTSE_PETEX_TOP 24
module work CTSE_PEANX_SYNC 24
module work CTSE_MSGMII_PEANX_TOP 24
module work CTSE_MSGMII_TBI 24
module work CTSE_MSGMII_CNVTXO 24
module work CTSE_MSGMII_CNVTXI 24
module work CTSE_MSGMII_CNVRXO 24
module work CTSE_MSGMII_CNVRXI 24
module work CTSE_PEMSTAT_LINC_ECC 24
module work CTSE_AMCXFIF_CLKRST 24
module work CTSE_AMCXFIF_HST 24
module work CTSE_AMCXTFIF_WTM 24
module work CTSE_AMCXRFIF_SYS 24
module work CTSE_AMCXRFIF_FAB 24
module work CTSE_AMCXTFIF_SYS 24
module work CTSE_AMCXTFIF_FAB 24
module work CTSE_SI_SAL 24
module work CTSE_SIB_SYNC_2FLP 24
module work CTSE_MMCXWOL 24
module work CTSE_PEMSTAT 24
module work CTSE_SIB_SYNC_PULSE 24
module work CTSE_PE_MCXMAC 24
module work OiOI1 24
module work CTSE_TSM_SYSREG 24
module work CTSE_DECODER 24
module work CTSE_MAPBE_HST_CNV 24
module work CTSE_REGISTERSLICE 24
module work CTSE_ECC 24
module work CTSE_MSGMII_CORE 24
module work CTSE_RX4096X36 24
module work CTSE_TX2048X40 24
module work CTSE_TSMAC_TOP 24
module work CTSE_CLKRST 24
module work CTSE_TXMEM_13 24
module work CTSE_TXMEM_12 24
module work CTSE_TXMEM_11 24
module work CTSE_TXMEM_10 24
module work CTSE_TXMEM_9 24
module work CTSE_TXMEM_8 24
module work CTSE_TXMEM_7 24
module work CTSE_TXMEM_6 24
module work CTSE_TX2048X40_RTG4 24
module work CTSE_RXMEM_14 24
module work CTSE_RXMEM_13 24
module work CTSE_RXMEM_12 24
module work CTSE_RXMEM_11 24
module work CTSE_RXMEM_10 24
module work CTSE_RXMEM_9 24
module work CTSE_RXMEM_8 24
module work CTSE_RXMEM_7 24
module work CTSE_RX4096X36_RTG4 24
module work CTSE_PF2_TxRAM_ECC_13 24
module work CTSE_PF2_TxRAM_ECC_12 24
module work CTSE_PF2_TxRAM_ECC_11 24
module work CTSE_PF2_TxRAM_ECC_10 24
module work CTSE_PF2_TxRAM_ECC_9 24
module work CTSE_PF2_TxRAM_ECC_8 24
module work CTSE_PF2_TxRAM_ECC_7 24
module work CTSE_PF2_TxRAM_ECC_6 24
module work CTSE_TX4096X40_PF2 24
module work CTSE_PF2_RxRAM_ECC_14 24
module work CTSE_PF2_RxRAM_ECC_13 24
module work CTSE_PF2_RxRAM_ECC_12 24
module work CTSE_PF2_RxRAM_ECC_11 24
module work CTSE_PF2_RxRAM_ECC_10 24
module work CTSE_PF2_RxRAM_ECC_9 24
module work CTSE_PF2_RxRAM_ECC_8 24
module work CTSE_PF2_RxRAM_ECC_7 24
module work CTSE_RX8192X36_PF2 24
module work CTSE_PF_TxTPSRAM_13 24
module work CTSE_PF_TxTPSRAM_12 24
module work CTSE_PF_TxTPSRAM_11 24
module work CTSE_PF_TxTPSRAM_10 24
module work CTSE_PF_TxTPSRAM_9 24
module work CTSE_PF_TxTPSRAM_8 24
module work CTSE_PF_TxTPSRAM_7 24
module work CTSE_PF_TxTPSRAM_6 24
module work CTSE_TX2048X40_PF 24
module work CTSE_PF_RxTPSRAM_14 24
module work CTSE_PF_RxTPSRAM_13 24
module work CTSE_PF_RxTPSRAM_12 24
module work CTSE_PF_RxTPSRAM_11 24
module work CTSE_PF_RxTPSRAM_10 24
module work CTSE_PF_RxTPSRAM_9 24
module work CTSE_PF_RxTPSRAM_8 24
module work CTSE_PF_RxTPSRAM_7 24
module work CTSE_RX4096X36_PF 24
module work CTSE_CORETSE_TOP 24
module work CTSE_SELF_DESTRUCT 24
module work CORETSE 24
module work CORESPI_0 23
module work COREJTAGDEBUG_C0 15
module work COREFIFO_C0 10
module work COREFIFO_C0_COREFIFO_C0_0_COREFIFO 9
module work COREFIFO_C0_COREFIFO_C0_0_ram_wrapper 8
module work COREFIFO_C0_COREFIFO_C0_0_LSRAM_top 7
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr 6
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft 5
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_sync 4
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_async 3
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync 2
module work COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv 1
module work CLKBUF_DIFF_ODT 0
module work CLKBUF_DIFF 0
module work MCHP_BLIC 0
module work PFSOC_SCSM 0
module work CORELNKTMR_V 0
module work XCVR 0
module work XCVR_VV 0
module work XCVR_TEST 0
module work XCVR_REF_CLK 0
module work XCVR_REF_CLK_P 0
module work XCVR_REF_CLK_N 0
module work XCVR_PMA 0
module work XCVR_PIPE 0
module work XCVR_PIPE_AXI1 0
module work XCVR_PIPE_AXI0 0
module work XCVR_DUAL_PCS 0
module work XCVR_APB_LINK_V2 0
module work XCVR_APB_LINK_V 0
module work XCVR_APB_LINK 0
module work XCVR_8B10B 0
module work XCVR_64B6XB 0
module work VREFCTRL 0
module work VREFBANKDYN 0
module work VOLTAGEDETECT 0
module work USPI 0
module work UPROM 0
module work TX_PLL 0
module work TVS 0
module work TAMPER 0
module work SYS_SERVICES 0
module work SYSRESET 0
module work SYSCTRL_RESET_STATUS 0
module work SCB 0
module work QUADRST 0
module work QUADRST_PCIE 0
module work PLL 0
module work PF_SPI 0
module work PCIE 0
module work PCIE_COMMON 0
module work OSC_RC2MHZ 0
module work OSC_RC200MHZ 0
module work OSC_RC160MHZ 0
module work LANERST 0
module work LANECTRL 0
module work IOD 0
module work INIT 0
module work ICB_NGMUX 0
module work ICB_MUXING 0
module work ICB_INT 0
module work ICB_CLKSTOP 0
module work ICB_CLKSTOP_EN 0
module work ICB_CLKINT 0
module work ICB_CLKDIV 0
module work ICB_CLKDIVDELAY 0
module work ICB_BANKCLK 0
module work HS_IO_CLK 0
module work GPSS_COMMON 0
module work GLITCHDETECT 0
module work ENFORCE 0
module work DRI 0
module work DLL 0
module work DEBUG 0
module work CRYPTO_SOC 0
module work CRYPTO 0
module work CRN_INT 0
module work CRN_COMMON 0
module work BANKEN 0
module work BANKCTRL_HSIO 0
module work BANKCTRL_GPIO 0
module work BANKCTRLM 0
module work APBS 0
module work APBM 0

13
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Library, Design Unit ,Compile time , Hardware Gen ,Optimization Stg1 ,Optimization Stg2 , Peak Mem Usage, Incr Mem Usage, Hardware Gen ,Optimization Stg1 ,Optimization Stg2
work, miv_rv32_subsys_tcm_Z20,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 353 MB, 35 MB, 34 MB, 1 MB, 0 MB
work, miv_rv32_debug_sba,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 355 MB, 23 MB, 0 MB, 6 MB, 16 MB
work, miv_rv32_ipcore_Z19,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 355 MB, 43 MB, 43 MB, 0 MB, 0 MB
work, miv_rv32_expipe_Z16,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:01s, 364 MB, 2 MB, 0 MB, 2 MB, 0 MB
work, miv_rv32_csr_privarch_Z15,0h:00m:02s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 364 MB, 2 MB, 1 MB, 0 MB, 1 MB
work, miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1,0h:00m:03s,0h:00m:00s,0h:00m:00s,0h:00m:02s, 397 MB, 61 MB, 0 MB, 30 MB, 32 MB
work, miv_rv32_idecode_1_1s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 397 MB, 11 MB, 10 MB, 1 MB, 0 MB
work, CTSE_CORETSE_TOP_Z10,0h:00m:08s,0h:00m:08s,0h:00m:00s,0h:00m:00s, 398 MB, 13 MB, 13 MB, 0 MB, 0 MB
work, CTSE_PEMSTAT_EIM_26s_1s_0s,0h:00m:01s,0h:00m:00s,0h:00m:00s,0h:00m:01s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
work, CTSE_TSMAC_TOP_Z9,0h:00m:06s,0h:00m:06s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
COREJTAGDEBUG_LIB, COREJTAGDEBUG_Z5,0h:00m:01s,0h:00m:01s,0h:00m:00s,0h:00m:00s, 398 MB, 1 MB, 1 MB, 0 MB, 0 MB
work, COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2,0h:00m:02s,0h:00m:02s,0h:00m:00s,0h:00m:00s, 398 MB, 0 MB, 0 MB, 0 MB, 0 MB
1 Library Design Unit Compile time Hardware Gen Optimization Stg1 Optimization Stg2 Peak Mem Usage Incr Mem Usage Hardware Gen Optimization Stg1 Optimization Stg2
2 work miv_rv32_subsys_tcm_Z20 0h:00m:02s 0h:00m:02s 0h:00m:00s 0h:00m:00s 353 MB 35 MB 34 MB 1 MB 0 MB
3 work miv_rv32_debug_sba 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 355 MB 23 MB 0 MB 6 MB 16 MB
4 work miv_rv32_ipcore_Z19 0h:00m:08s 0h:00m:08s 0h:00m:00s 0h:00m:00s 355 MB 43 MB 43 MB 0 MB 0 MB
5 work miv_rv32_expipe_Z16 0h:00m:02s 0h:00m:01s 0h:00m:00s 0h:00m:01s 364 MB 2 MB 0 MB 2 MB 0 MB
6 work miv_rv32_csr_privarch_Z15 0h:00m:02s 0h:00m:01s 0h:00m:00s 0h:00m:00s 364 MB 2 MB 1 MB 0 MB 1 MB
7 work miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1 0h:00m:03s 0h:00m:00s 0h:00m:00s 0h:00m:02s 397 MB 61 MB 0 MB 30 MB 32 MB
8 work miv_rv32_idecode_1_1s_1s_0s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 397 MB 11 MB 10 MB 1 MB 0 MB
9 work CTSE_CORETSE_TOP_Z10 0h:00m:08s 0h:00m:08s 0h:00m:00s 0h:00m:00s 398 MB 13 MB 13 MB 0 MB 0 MB
10 work CTSE_PEMSTAT_EIM_26s_1s_0s 0h:00m:01s 0h:00m:00s 0h:00m:00s 0h:00m:01s 398 MB 0 MB 0 MB 0 MB 0 MB
11 work CTSE_TSMAC_TOP_Z9 0h:00m:06s 0h:00m:06s 0h:00m:00s 0h:00m:00s 398 MB 0 MB 0 MB 0 MB 0 MB
12 COREJTAGDEBUG_LIB COREJTAGDEBUG_Z5 0h:00m:01s 0h:00m:01s 0h:00m:00s 0h:00m:00s 398 MB 1 MB 1 MB 0 MB 0 MB
13 work COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2 0h:00m:02s 0h:00m:02s 0h:00m:00s 0h:00m:00s 398 MB 0 MB 0 MB 0 MB 0 MB

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fsm_encoding {21416041617} onehot
fsm_state_encoding {21416041617} MTX_IDLE1 {000001}
fsm_state_encoding {21416041617} MTX_IDLE2 {000010}
fsm_state_encoding {21416041617} MTX_MOTSTART {000100}
fsm_state_encoding {21416041617} MTX_SHIFT1 {001000}
fsm_state_encoding {21416041617} MTX_SHIFT2 {010000}
fsm_state_encoding {21416041617} MTX_END {100000}
fsm_registers {21416041617} {mtx_state[5]} {mtx_state[4]} {mtx_state[3]} {mtx_state[2]} {mtx_state[1]} {mtx_state[0]}
fsm_encoding {28441204044120416} onehot
fsm_state_encoding {28441204044120416} 0000 {00001}
fsm_state_encoding {28441204044120416} 1000 {00010}
fsm_state_encoding {28441204044120416} 1100 {00100}
fsm_state_encoding {28441204044120416} 1110 {01000}
fsm_state_encoding {28441204044120416} 1111 {10000}
fsm_registers {28441204044120416} {genblk1®O0Il1[4]} {genblk1®O0Il1[3]} {genblk1®O0Il1[2]} {genblk1®O0Il1[1]} {genblk1®O0Il1[0]}
fsm_encoding {28483865048386515} onehot
fsm_state_encoding {28483865048386515} 00000 {00000000000000000000000000000001}
fsm_state_encoding {28483865048386515} 00001 {00000000000000000000000000000010}
fsm_state_encoding {28483865048386515} 00010 {00000000000000000000000000000100}
fsm_state_encoding {28483865048386515} 00011 {00000000000000000000000000001000}
fsm_state_encoding {28483865048386515} 00100 {00000000000000000000000000010000}
fsm_state_encoding {28483865048386515} 00101 {00000000000000000000000000100000}
fsm_state_encoding {28483865048386515} 00110 {00000000000000000000000001000000}
fsm_state_encoding {28483865048386515} 00111 {00000000000000000000000010000000}
fsm_state_encoding {28483865048386515} 01000 {00000000000000000000000100000000}
fsm_state_encoding {28483865048386515} 01001 {00000000000000000000001000000000}
fsm_state_encoding {28483865048386515} 01010 {00000000000000000000010000000000}
fsm_state_encoding {28483865048386515} 01011 {00000000000000000000100000000000}
fsm_state_encoding {28483865048386515} 01100 {00000000000000000001000000000000}
fsm_state_encoding {28483865048386515} 01101 {00000000000000000010000000000000}
fsm_state_encoding {28483865048386515} 01110 {00000000000000000100000000000000}
fsm_state_encoding {28483865048386515} 01111 {00000000000000001000000000000000}
fsm_state_encoding {28483865048386515} 10000 {00000000000000010000000000000000}
fsm_state_encoding {28483865048386515} 10001 {00000000000000100000000000000000}
fsm_state_encoding {28483865048386515} 10010 {00000000000001000000000000000000}
fsm_state_encoding {28483865048386515} 10011 {00000000000010000000000000000000}
fsm_state_encoding {28483865048386515} 10100 {00000000000100000000000000000000}
fsm_state_encoding {28483865048386515} 10101 {00000000001000000000000000000000}
fsm_state_encoding {28483865048386515} 10110 {00000000010000000000000000000000}
fsm_state_encoding {28483865048386515} 10111 {00000000100000000000000000000000}
fsm_state_encoding {28483865048386515} 11000 {00000001000000000000000000000000}
fsm_state_encoding {28483865048386515} 11001 {00000010000000000000000000000000}
fsm_state_encoding {28483865048386515} 11010 {00000100000000000000000000000000}
fsm_state_encoding {28483865048386515} 11011 {00001000000000000000000000000000}
fsm_state_encoding {28483865048386515} 11100 {00010000000000000000000000000000}
fsm_state_encoding {28483865048386515} 11101 {00100000000000000000000000000000}
fsm_state_encoding {28483865048386515} 11110 {01000000000000000000000000000000}
fsm_state_encoding {28483865048386515} 11111 {10000000000000000000000000000000}
fsm_registers {28483865048386515} {l0i11[31]} {l0i11[30]} {l0i11[29]} {l0i11[28]} {l0i11[27]} {l0i11[26]} {l0i11[25]} {l0i11[24]} {l0i11[23]} {l0i11[22]} {l0i11[21]} {l0i11[20]} {l0i11[19]} {l0i11[18]} {l0i11[17]} {l0i11[16]} {l0i11[15]} {l0i11[14]} {l0i11[13]} {l0i11[12]} {l0i11[11]} {l0i11[10]} {l0i11[9]} {l0i11[8]} {l0i11[7]} {l0i11[6]} {l0i11[5]} {l0i11[4]} {l0i11[3]} {l0i11[2]} {l0i11[1]} {l0i11[0]}
fsm_encoding {28507173050717314} sequential
fsm_state_encoding {28507173050717314} 00 {00}
fsm_state_encoding {28507173050717314} 01 {01}
fsm_state_encoding {28507173050717314} 10 {10}
fsm_state_encoding {28507173050717314} 11 {11}
fsm_registers {28507173050717314} {lI101_1[1]} {lI101_1[0]}
fsm_encoding {38119011913} onehot
fsm_state_encoding {38119011913} tx_idle {000001}
fsm_state_encoding {38119011913} tx_load {000010}
fsm_state_encoding {38119011913} start_bit {000100}
fsm_state_encoding {38119011913} tx_data_bits {001000}
fsm_state_encoding {38119011913} parity_bit {010000}
fsm_state_encoding {38119011913} tx_stop_bit {100000}
fsm_registers {38119011913} {xmit_state[5]} {xmit_state[4]} {xmit_state[3]} {xmit_state[2]} {xmit_state[1]} {xmit_state[0]}
fsm_encoding {37286028612} sequential
fsm_state_encoding {37286028612} 00 {00}
fsm_state_encoding {37286028612} 01 {01}
fsm_state_encoding {37286028612} 10 {10}
fsm_state_encoding {37286028612} 11 {11}
fsm_registers {37286028612} {rx_state[1]} {rx_state[0]}
fsm_encoding {734544511} sequential
fsm_state_encoding {734544511} IDLE {0}
fsm_state_encoding {734544511} WRITE {1}
fsm_registers {734544511} {state[0]}
fsm_encoding {4916013121601310} onehot
fsm_state_encoding {4916013121601310} TEST_LOGIC_RESET {0000000000000001}
fsm_state_encoding {4916013121601310} RUN_TEST_IDLE {0000000000000010}
fsm_state_encoding {4916013121601310} SELECT_DR {0000000000000100}
fsm_state_encoding {4916013121601310} CAPTURE_DR {0000000000001000}
fsm_state_encoding {4916013121601310} SHIFT_DR {0000000000010000}
fsm_state_encoding {4916013121601310} EXIT1_DR {0000000000100000}
fsm_state_encoding {4916013121601310} PAUSE_DR {0000000001000000}
fsm_state_encoding {4916013121601310} EXIT2_DR {0000000010000000}
fsm_state_encoding {4916013121601310} UPDATE_DR {0000000100000000}
fsm_state_encoding {4916013121601310} SELECT_IR {0000001000000000}
fsm_state_encoding {4916013121601310} CAPTURE_IR {0000010000000000}
fsm_state_encoding {4916013121601310} SHIFT_IR {0000100000000000}
fsm_state_encoding {4916013121601310} EXIT1_IR {0001000000000000}
fsm_state_encoding {4916013121601310} PAUSE_IR {0010000000000000}
fsm_state_encoding {4916013121601310} EXIT2_IR {0100000000000000}
fsm_state_encoding {4916013121601310} UPDATE_IR {1000000000000000}
fsm_registers {4916013121601310} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[15]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[14]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[13]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[12]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[11]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[10]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[9]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[8]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[7]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[6]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[5]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[4]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[3]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[2]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[1]} {gen_current_state_register_active_high®gen_current_state_register_active_low®currTapState[0]}
fsm_encoding {491613512161359} sequential
fsm_state_encoding {491613512161359} 00 {00}
fsm_state_encoding {491613512161359} 01 {01}
fsm_state_encoding {491613512161359} 10 {10}
fsm_state_encoding {491613512161359} 11 {11}
fsm_registers {491613512161359} {gen_shift_register_active_high®gen_shift_register_active_low®dtmcs_dmistat[1]} {gen_shift_register_active_high®gen_shift_register_active_low®dtmcs_dmistat[0]}
fsm_encoding {49151920151928} sequential
fsm_state_encoding {49151920151928} IDLE {00}
fsm_state_encoding {49151920151928} START {01}
fsm_state_encoding {49151920151928} BUSTFR {10}
fsm_state_encoding {49151920151928} RETN {11}
fsm_registers {49151920151928} {sba_state[1]} {sba_state[0]}
fsm_encoding {49147360147367} onehot
fsm_state_encoding {49147360147367} INIT_DBG {000001}
fsm_state_encoding {49147360147367} RUNNING {000010}
fsm_state_encoding {49147360147367} HALT_WAIT_ACK {000100}
fsm_state_encoding {49147360147367} HALT_STATE {001000}
fsm_state_encoding {49147360147367} COMMAND_ACCESS_STATE {010000}
fsm_state_encoding {49147360147367} RESUME_WAIT_ACT {100000}
fsm_registers {49147360147367} {debug_state[5]} {debug_state[4]} {debug_state[3]} {debug_state[2]} {debug_state[1]} {debug_state[0]}
fsm_encoding {49103912103916} sequential
fsm_state_encoding {49103912103916} 01 {00}
fsm_state_encoding {49103912103916} 10 {01}
fsm_state_encoding {49103912103916} 11 {10}
fsm_registers {49103912103916} {hipri_req_ptr[1]} {hipri_req_ptr[0]}
fsm_encoding {496231662315} onehot
fsm_state_encoding {496231662315} IDLE_ST {000001}
fsm_state_encoding {496231662315} SETUP_ST {000010}
fsm_state_encoding {496231662315} ACCESS_ST {000100}
fsm_state_encoding {496231662315} BH_READ_0_ST {001000}
fsm_state_encoding {496231662315} BH_READ_1_ST {010000}
fsm_state_encoding {496231662315} BH_WRITE_ST {100000}
fsm_registers {496231662315} {gen_apb_byte_shim®apb_st[5]} {gen_apb_byte_shim®apb_st[4]} {gen_apb_byte_shim®apb_st[3]} {gen_apb_byte_shim®apb_st[2]} {gen_apb_byte_shim®apb_st[1]} {gen_apb_byte_shim®apb_st[0]}
fsm_encoding {49103912103914} onehot
fsm_state_encoding {49103912103914} 001 {0000001}
fsm_state_encoding {49103912103914} 010 {0000010}
fsm_state_encoding {49103912103914} 011 {0000100}
fsm_state_encoding {49103912103914} 100 {0001000}
fsm_state_encoding {49103912103914} 101 {0010000}
fsm_state_encoding {49103912103914} 110 {0100000}
fsm_state_encoding {49103912103914} 111 {1000000}
fsm_registers {49103912103914} {hipri_req_ptr[6]} {hipri_req_ptr[5]} {hipri_req_ptr[4]} {hipri_req_ptr[3]} {hipri_req_ptr[2]} {hipri_req_ptr[1]} {hipri_req_ptr[0]}
fsm_encoding {49110562110563} sequential
fsm_state_encoding {49110562110563} BH_INIT {00}
fsm_state_encoding {49110562110563} BH_READ {01}
fsm_state_encoding {49110562110563} BH_WRITE {10}
fsm_registers {49110562110563} {cpu_d_wr_rd_state[1]} {cpu_d_wr_rd_state[0]}
fsm_encoding {5611701172} sequential
fsm_state_encoding {5611701172} ST_RSWT {00}
fsm_state_encoding {5611701172} ST_RWAT {01}
fsm_state_encoding {5611701172} ST_LSWT {10}
fsm_state_encoding {5611701172} ST_LWAT {11}
fsm_registers {5611701172} {tune_st[1]} {tune_st[0]}
fsm_encoding {64590591} sequential
fsm_state_encoding {64590591} 00 {00}
fsm_state_encoding {64590591} 01 {01}
fsm_state_encoding {64590591} 10 {10}
fsm_state_encoding {64590591} 11 {11}
fsm_registers {64590591} {state[1]} {state[0]}

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#List of actual used RTLs.
File Type IN_PROJECT/INCLUDED/LIBRARY
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\include.v" verilog INCLUDED
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v" verilog IN PROJECT
"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v" verilog IN PROJECT