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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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synthesis/syntmp/cmdrec_premap.log Normal file
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E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis -flow prepass -gcc_prepass -osrd E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -qsap E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm -conchk_prepass E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt -freq 100.000 -tcl E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_mult.srs -devicelib E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\syntmp\top.plg -osyn E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synwork\top_prem.srd -prjdir E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\ -prjname top_syn -log E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
relcom:..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\m_generic.exe -mp 4 -prjfile ..\scratchproject.prs -prodtype synplify_pro -encrypt -pro -rundir ..\..\synthesis -flow prepass -gcc_prepass -osrd ..\synwork\top_prem.srd -qsap ..\top.sap -part MPF300T -package FCG1152 -grade -1 -async_globalthreshold 800 -continue_on_error -infer_seqShift -widemult_decomp_old_equation 0 -seqshift_to_uram 1 -rom_map_logic 1 -polarfire_ram_init 1 -gclkint_threshold 1000 -rgclkint_threshold 100 -clkint_rgclkint_limit 1 -low_power_gated_clock 0 -gclk_resource_count 24 -report_preserve_cdc -min_cdc_sync_flops 2 -unsafe_cdc_netlist_property 0 -pack_uram_addr_reg 1 -act_wide_mul_size 35 -maxfan 10000 -clock_globalthreshold 2 -globalthreshold 5000 -low_power_ram_decomp 0 -opcond COMTC -report_path 4000 -disable_ramindex 0 -rep_clkint_driver 1 -microsemi_enhanced_flow 1 -resolveMultipleDriver -ternary_adder_decomp 66 -async_clkint_removal 1 -remove_async_clkint 0 -RWCheckOnRam 0 -local_tmr_rename -summaryfile ..\synlog\report\top_premap.xml -merge_inferred_clocks 0 -top_level_module top -implementation synthesis -ovm ..\top.vm -conchk_prepass ..\top_cck.rpt -freq 100.000 -tcl ..\..\designer\top\synthesis.fdc ..\synwork\top_mult.srs -devicelib ..\..\..\..\..\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v -ologparam top.plg -osyn ..\synwork\top_prem.srd -prjdir ..\ -prjname top_syn -log ..\synlog\top_premap.srr -sn 2023.09 -jobname "premap"
rc:1 success:1 runtime:15
file:..\scratchproject.prs|io:o|time:1776258082|size:12250|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\top.sap|io:o|time:1776273488|size:51500|exec:0|csum:
file:..\top.vm|io:o|time:1776270794|size:6521569|exec:0|csum:
file:..\top_cck.rpt|io:o|time:1776273487|size:16263|exec:0|csum:
file:..\..\designer\top\synthesis.fdc|io:i|time:1776273292|size:5771|exec:0|csum:3A3A4EA7D21F09C3C622797FF0E37F94
file:..\synwork\top_mult.srs|io:i|time:1776273473|size:16492|exec:0|csum:8A8FBA27CAD8D4F9ABE7B311078B4CA3
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\lib\generic\acg5.v|io:i|time:1745932376|size:43686|exec:0|csum:C5B8CD150154D193C7B0D4301122DDFB
file:top.plg|io:o|time:1776273475|size:0|exec:0|csum:
file:..\synwork\top_prem.srd|io:o|time:1776273483|size:1522539|exec:0|csum:
file:..\synlog\top_premap.srr|io:o|time:1776273488|size:50209|exec:0|csum:
file:..\..\..\..\..\microchip\libero_soc_2025.1\libero_soc\synplify_pro\bin64\m_generic.exe|io:i|time:1745934934|size:52771328|exec:1|csum:C59F16B7E4C6332FFA351C39C6E2D2D6