working FIFO and TPSRAM without packet flter
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synthesis/synlog/report/highrel.rpt
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synthesis/synlog/report/highrel.rpt
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synthesis/synlog/report/metrics.db
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synthesis/synlog/report/metrics.db
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synthesis/synlog/report/top_compiler_notes.txt
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synthesis/synlog/report/top_compiler_notes.txt
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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@N: CG1349 : | Running Verilog Compiler in System Verilog mode
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":437:13:437:25|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":449:13:449:24|Read directive translate_on.
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@N: CG347 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":160:38:160:50|Read a parallel_case directive.
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@N: CG347 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":223:34:223:46|Read a parallel_case directive.
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@N: CG347 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v":69:31:69:43|Read a parallel_case directive.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":796:18:796:30|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":798:18:798:29|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":1536:18:1536:30|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":1550:18:1550:29|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21267:12:21267:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21316:12:21316:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21861:20:21861:32|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":21877:20:21877:31|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":22391:12:22391:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":22459:12:22459:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25452:12:25452:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25460:12:25460:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25769:12:25769:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":25777:12:25777:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27214:20:27214:32|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27217:20:27217:31|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27227:20:27227:32|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27237:20:27237:31|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27242:12:27242:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":27300:12:27300:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28378:20:28378:32|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28381:20:28381:31|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28391:20:28391:32|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28401:20:28401:31|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28406:12:28406:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":28464:12:28464:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":40250:14:40250:26|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":40254:14:40254:25|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41809:12:41809:24|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41814:12:41814:23|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41866:18:41866:30|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":41880:18:41880:29|Read directive translate_on.
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@N: CG334 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42004:14:42004:26|Read directive translate_off.
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@N: CG333 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42037:14:42037:25|Read directive translate_on.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v":70:8:70:28|Synthesizing module miv_rv32_hart_cfg_pkg in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":73:8:73:19|Synthesizing module miv_rv32_pkg in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v":69:8:69:26|Synthesizing module miv_rv32_subsys_pkg in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":314:0:314:5|Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v_unit in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":77:0:77:5|Synthesizing module work_E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v_unit in library work.
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@N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
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@N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":22:7:22:19|Component COREJTAGDEBUG not found in library "work" or "__hyper__lib__", but found in library COREJTAGDEBUG_LIB
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@N: CG775 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v":27:0:27:6|Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":121:7:121:10|Synthesizing module AND2 in library work.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":333:7:333:11|Synthesizing module BIBUF in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":21:7:21:48|Synthesizing module Core_reset_pf_Core_reset_pf_0_CORERESET_PF in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v":21:7:21:19|Synthesizing module Core_reset_pf in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3 in library COREAPB3_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v":57:7:57:16|Synthesizing module CoreAPB3_0 in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":19:7:19:40|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_COREFIFO in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":20:7:20:51|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":20:7:20:45|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft in library work.
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@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":254:38:254:55|Removing redundant assignment.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":578:7:578:13|Synthesizing module RAM1K20 in library work.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":500:7:500:9|Synthesizing module GND in library work.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":504:7:504:9|Synthesizing module VCC in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v":5:7:5:41|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":4:7:4:43|Synthesizing module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v":49:7:49:17|Synthesizing module COREFIFO_C0 in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":22:7:22:19|Synthesizing module COREJTAGDEBUG in library COREJTAGDEBUG_LIB.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":1442:7:1442:11|Synthesizing module UJTAG in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v":20:7:20:24|Synthesizing module corejtagdebug_bufd in library COREJTAGDEBUG_LIB.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":229:7:229:10|Synthesizing module BUFD in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v":47:7:47:27|Synthesizing module COREJTAGDEBUG_UJ_JTAG in library COREJTAGDEBUG_LIB.
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@N: CG364 :"E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\lib\generic\acg5.v":489:7:489:12|Synthesizing module CLKINT in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v":56:7:56:22|Synthesizing module COREJTAGDEBUG_C0 in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":31:7:31:12|Synthesizing module spi_rf in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v":24:7:24:17|Synthesizing module spi_control in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":25:7:25:14|Synthesizing module spi_fifo in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v":24:7:24:18|Synthesizing module spi_clockmux in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":29:7:29:18|Synthesizing module spi_chanctrl in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":29:7:29:9|Synthesizing module spi in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v":27:0:27:6|Synthesizing module CORESPI in library CORESPI_LIB.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v":32:7:32:15|Synthesizing module CORESPI_0 in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":31:7:31:15|Synthesizing module CORETSE_0 in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v":38:7:38:45|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work.
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@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":356:21:356:29|Removing redundant assignment.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":30:7:30:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async in library work.
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@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":254:23:254:35|Removing redundant assignment.
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@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":280:18:280:25|Removing redundant assignment.
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@N: CG364 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":31:7:31:44|Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_COREUART in library work.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":390:22:390:33|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":254:31:254:41|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":275:31:275:41|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6111:72:6111:89|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6112:72:6112:89|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6113:72:6113:89|Removing redundant assignment.
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Found RAM mem_xf, depth=32, width=32
|
||||
@N: CL189 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9191:4:9191:9|Register bit gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5] is always 0.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16165:67:16165:73|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16173:67:16173:73|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16193:48:16193:54|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16194:48:16194:54|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16195:48:16195:54|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16196:48:16196:55|Removing redundant assignment.
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16380:45:16380:49|Removing redundant assignment.
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Found RAM fifo_memory, depth=2, width=41
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Found RAM fifo_memory, depth=2, width=34
|
||||
@N: CG179 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6281:36:6281:48|Removing redundant assignment.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":15:7:15:9|Input CLK is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":15:12:15:16|Input RESET is unused.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v":59:0:59:5|Trying to extract state machine for register state.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v":70:13:70:20|Input DLL_LOCK is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v":77:13:77:20|Input PLL_LOCK is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":15:7:15:9|Input CLK is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":15:12:15:16|Input RESET is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":31:7:31:13|Input FAB_CLK is unused.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|Trying to extract state machine for register tune_st.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13005:27:13005:40|Input mtime_count_in is unused.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Trying to extract state machine for register cpu_d_wr_rd_state.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10821:49:10821:64|Input subsys_parity_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10830:49:10830:68|Input cpu_i_req_rd_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10832:49:10832:64|Input cpu_i_req_addr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10834:49:10834:64|Input cpu_i_resp_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10840:49:10840:68|Input cpu_d_req_rd_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10842:49:10842:62|Input cpu_d_req_read is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10843:49:10843:63|Input cpu_d_req_write is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10845:49:10845:64|Input cpu_d_req_addr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10847:49:10847:67|Input cpu_d_req_wr_data_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10849:49:10849:64|Input cpu_d_resp_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10855:49:10855:62|Input udma_req_valid is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10857:49:10857:67|Input udma_req_rd_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10858:49:10858:67|Input udma_req_wr_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10859:49:10859:61|Input udma_req_read is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10860:49:10860:62|Input udma_req_write is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10861:49:10861:61|Input udma_req_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10862:49:10862:63|Input udma_req_addr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10863:49:10863:60|Input udma_req_len is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10864:49:10864:64|Input udma_req_wr_data is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10865:49:10865:66|Input udma_req_wr_data_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10867:49:10867:63|Input udma_resp_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10874:49:10874:70|Input tcm_dma_access_disable is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10875:49:10875:70|Input tcm_tas_access_disable is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10876:49:10876:65|Input tcm_tas_req_valid is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10878:49:10878:70|Input tcm_tas_req_rd_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10879:49:10879:70|Input tcm_tas_req_wr_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10880:49:10880:64|Input tcm_tas_req_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10881:49:10881:66|Input tcm_tas_req_addr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10882:49:10882:67|Input tcm_tas_req_wr_data is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10883:49:10883:69|Input tcm_tas_req_wr_data_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10885:49:10885:66|Input tcm_tas_resp_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10890:49:10890:61|Input tcm_ram_sb_in is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10891:49:10891:71|Input tcm_ecc_error_injection is unused.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Trying to extract state machine for register gen_apb_byte_shim.apb_st.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6063:49:6063:64|Input subsys_parity_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6070:49:6070:68|Input cpu_i_req_rd_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6072:49:6072:64|Input cpu_i_req_addr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6074:49:6074:64|Input cpu_i_resp_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6080:49:6080:68|Input cpu_d_req_rd_byte_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6083:49:6083:64|Input cpu_d_req_addr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6087:49:6087:64|Input cpu_d_resp_ready is unused.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Trying to extract state machine for register hipri_req_ptr.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14736:0:14736:8|Trying to extract state machine for register debug_state.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Trying to extract state machine for register command_reg_state.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13800:39:13800:52|Input dmi_resp_ready is unused.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|Trying to extract state machine for register sba_state.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|Trying to extract state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Trying to extract state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15942:48:15942:60|Input dtm_req_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":191:50:191:60|Input m_timer_irq is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":227:50:227:72|Input tcm1_cpu_access_disable is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":228:50:228:72|Input tcm1_dma_access_disable is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":229:50:229:72|Input tcm1_tas_access_disable is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":230:50:230:62|Input tcm_tas_paddr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":231:50:231:64|Input tcm_tas_paddr_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":232:50:232:62|Input tcm_tas_pprot is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":233:50:233:61|Input tcm_tas_psel is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":234:50:234:64|Input tcm_tas_penable is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":235:50:235:63|Input tcm_tas_pwrite is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":236:50:236:63|Input tcm_tas_pwdata is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":237:50:237:65|Input tcm_tas_pwdata_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":248:50:248:63|Input tcm1_ram_sb_in is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":252:50:252:60|Input axi_aclk_en is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":261:50:261:60|Input axi_arready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":264:50:264:58|Input axi_rresp is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":265:50:265:58|Input axi_rdata is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":266:50:266:58|Input axi_rlast is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":267:50:267:56|Input axi_rid is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":269:50:269:59|Input axi_rvalid is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":270:50:270:61|Input axi_r_data_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":280:50:280:60|Input axi_awready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":286:50:286:59|Input axi_wready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":289:50:289:58|Input axi_bresp is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":290:50:290:56|Input axi_bid is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":292:50:292:59|Input axi_bvalid is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":305:50:305:59|Input ahb_hrdata is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":306:50:306:61|Input ahb_hrdata_p is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":307:50:307:59|Input ahb_hready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":308:50:308:58|Input ahb_hresp is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2492:49:2492:66|Input cfg_axi_start_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2493:49:2493:64|Input cfg_axi_end_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2496:49:2496:66|Input cfg_ahb_start_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2497:49:2497:64|Input cfg_ahb_end_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2498:49:2498:72|Input cfg_udma_ctrl_start_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2499:49:2499:70|Input cfg_udma_ctrl_end_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2504:49:2504:67|Input cfg_tcm1_start_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2505:49:2505:65|Input cfg_tcm1_end_addr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2575:49:2575:63|Input apb_trx_os_d_rd is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2576:49:2576:63|Input apb_trx_os_d_wr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2604:49:2604:64|Input tcm0_trx_os_d_rd is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2605:49:2605:64|Input tcm0_trx_os_d_wr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2611:49:2611:64|Input tcm1_i_req_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2621:49:2621:64|Input tcm1_d_req_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2635:49:2635:64|Input tcm1_trx_os_d_rd is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2636:49:2636:64|Input tcm1_trx_os_d_wr is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2642:49:2642:63|Input axi_i_req_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2647:49:2647:63|Input axi_i_resp_last is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2653:49:2653:63|Input axi_d_req_ready is unused.
|
||||
@N: CL159 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2668:49:2668:63|Input axi_trx_os_d_rd is unused.
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=7
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=11
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found RAM gen_buff_loop[0].buff_data, depth=2, width=6
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=16
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|Trying to extract state machine for register state.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":286:0:286:5|Trying to extract state machine for register rx_state.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Trying to extract state machine for register xmit_state.
|
||||
@N: CL201 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Trying to extract state machine for register mtx_state.
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=1
|
||||
@N: CL134 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|Found RAM fifo_mem_q, depth=32, width=16
|
||||
@N: CL135 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v":58:0:58:5|Found sequential shift dff with address depth of 16 words and data bit width of 1.
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
41
synthesis/synlog/report/top_compiler_runstatus.xml
Normal file
41
synthesis/synlog/report/top_compiler_runstatus.xml
Normal file
@@ -0,0 +1,41 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
The file contains the job information from compiler to be displayed as part of the summary report.
|
||||
*******************************************************************************************-->
|
||||
|
||||
<job_run_status name="compiler">
|
||||
<report_link name="Detailed report">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr</data>
|
||||
<title>Synopsys HDL Compiler</title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
<data>Completed </data>
|
||||
</job_status>
|
||||
<job_info>
|
||||
<info name="Notes">
|
||||
<data>236</data>
|
||||
<report_link name="more"><data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>403</data>
|
||||
<report_link name="more"><data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
<data>0</data>
|
||||
<report_link name="more"><data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_compiler_errors.txt</data></report_link>
|
||||
</info>
|
||||
<info name="CPU Time">
|
||||
<data>-</data>
|
||||
</info>
|
||||
<info name="Real Time">
|
||||
<data>00h:02m:53s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1776273469</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
404
synthesis/synlog/report/top_compiler_warnings.txt
Normal file
404
synthesis/synlog/report/top_compiler_warnings.txt
Normal file
@@ -0,0 +1,404 @@
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":21:13:21:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":61:13:61:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":88:13:88:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":118:13:118:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":168:13:168:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":213:13:213:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":232:13:232:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":281:13:281:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":335:13:335:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":657:13:657:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":761:13:761:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":795:13:795:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1059:13:1059:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1369:13:1369:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1396:13:1396:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1441:13:1441:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1474:13:1474:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1492:13:1492:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1518:13:1518:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1559:13:1559:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1581:13:1581:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1599:13:1599:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1616:13:1616:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1635:13:1635:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1652:13:1652:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1681:13:1681:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1712:13:1712:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":1802:13:1802:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2026:13:2026:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2187:13:2187:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2203:13:2203:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2219:13:2219:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2235:13:2235:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2267:13:2267:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":2648:13:2648:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3661:13:3661:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3732:13:3732:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3861:13:3861:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3879:13:3879:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3896:13:3896:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3911:13:3911:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3926:13:3926:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":3953:13:3953:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4067:13:4067:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4098:13:4098:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4144:13:4144:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4255:13:4255:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4439:13:4439:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4480:13:4480:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4506:13:4506:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4523:13:4523:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":4600:13:4600:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":5364:13:5364:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6174:13:6174:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6283:13:6283:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6321:13:6321:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":6394:13:6394:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":7283:13:7283:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":8340:13:8340:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":9299:13:9299:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10035:13:10035:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10750:13:10750:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10784:13:10784:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10820:13:10820:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10867:13:10867:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":10901:13:10901:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":11767:13:11767:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12810:13:12810:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12822:15:12822:27|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12831:13:12831:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12843:13:12843:25|User defined pragma syn_black_box detected
|
||||
@W: CG100 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\syn_comps.v":12856:13:12856:25|User defined pragma syn_black_box detected
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":805:7:805:17|Net resetn_rx_s is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":430844:0:430844:4|Net ooOI1 is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":430859:0:430859:4|Net ioOI1 is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":476678:0:476678:4|Net oI0i0 is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":476693:0:476693:4|Net Ol0i0 is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548082:0:548082:4|Net l0iIo is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548102:0:548102:4|Net o0iIo is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548122:0:548122:4|Net i0iIo is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548142:0:548142:4|Net O1iIo is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548162:0:548162:4|Net I1iIo is not declared.
|
||||
@W: CG1337 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v":548182:0:548182:4|Net l1iIo is not declared.
|
||||
@W: CS138 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":26989:0:26931:8|Macro definition for RAM_BIST_VIEW_BEHAV not found. Cannot undefine.
|
||||
@W: CS138 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":26990:0:26931:8|Macro definition for RAM_BIST_VIEW not found. Cannot undefine.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":29121:14:29121:28|Unrecognized synthesis directive dc_script_begin. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":29124:14:29124:26|Unrecognized synthesis directive dc_script_end. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":33910:104:33910:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":34706:104:34706:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35086:104:35086:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35316:104:35316:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35536:104:35536:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":35932:104:35932:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":36264:104:36264:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":36476:104:36476:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":36692:104:36692:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37011:104:37011:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37227:104:37227:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37457:104:37457:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":37837:104:37837:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":38116:104:38116:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":38316:104:38316:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":38581:104:38581:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CG104 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":39241:39:39241:39|Unsized number in concatenation is 32 bits
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":39806:106:39806:105|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42208:104:42208:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CS141 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":42549:104:42549:103|Unrecognized synthesis directive sync_set_reset. Verify the correct directive name.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":173:29:173:37|Removing wire neg_reset, as there is no assignment to it.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register full_reg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":371:4:371:9|Pruning unused register sc_w[10:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":331:6:331:11|Pruning unused register we_f_i. Make sure that there are no unused intermediate registers.
|
||||
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|All reachable assignments to genblk8.wack_r assign 0, register removed by optimization.
|
||||
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|All reachable assignments to genblk8.overflow_r assign 0, register removed by optimization.
|
||||
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|All reachable assignments to underflow_r assign 0, register removed by optimization.
|
||||
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":485:4:485:9|All reachable assignments to dvld_r assign 0, register removed by optimization.
|
||||
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":275:3:275:8|All reachable assignments to rdcnt[10:0] assign 0, register removed by optimization.
|
||||
@W: CL207 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v":248:3:248:8|All reachable assignments to wrcnt[10:0] assign 0, register removed by optimization.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":119:27:119:32|Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":125:27:125:33|Removing wire aresetn, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":132:27:132:32|Removing wire empty1, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":140:8:140:17|Removing wire reset_wclk, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":141:8:141:17|Removing wire reset_rclk, as there is no assignment to it.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":358:3:358:8|Pruning unused register we_p_r. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":244:3:244:8|Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":233:4:233:9|Pruning unused register re_p_d. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":214:3:214:8|Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v":214:3:214:8|Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers.
|
||||
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":46:26:46:37|*Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":47:26:47:37|*Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":48:26:48:36|*Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v":49:26:49:36|*Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":211:36:211:46|Removing wire pf_MEMRADDR, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":217:36:217:39|Removing wire pf_Q, as there is no assignment to it.
|
||||
@W: CG184 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":236:36:236:45|Removing wire DVLD_async, as it has the load but no drivers.
|
||||
@W: CG184 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":238:36:238:44|Removing wire DVLD_sync, as it has the load but no drivers.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":241:36:241:42|Removing wire pf_dvld, as there is no assignment to it.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":250:36:250:44|Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":264:36:264:41|Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":283:8:283:17|Removing wire reset_rclk, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":284:8:284:17|Removing wire reset_wclk, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":285:8:285:19|Removing wire reset_sync_r, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":286:8:286:19|Removing wire reset_sync_w, as there is no assignment to it.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1175:3:1175:8|Pruning unused register RDATA_ext_r1[31:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1165:3:1165:8|Pruning unused register RDATA_ext_r[31:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register REN_d2. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register REN_d3. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register RE_d2. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register RE_d3. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1100:3:1100:8|Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1088:3:1088:8|Pruning unused register RDATA_r2[31:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1078:3:1078:8|Pruning unused register RDATA_r1[31:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1068:3:1068:8|Pruning unused register RDATA_r_pre[31:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":1058:3:1058:8|Pruning unused register fwft_Q_r[31:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":503:3:503:8|Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":490:3:490:8|Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v":490:3:490:8|Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|Removing wire UTRSTB, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|Removing wire UTMS, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":169:8:169:52|Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":176:8:176:52|Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":183:8:183:52|Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":190:8:190:52|Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":241:28:241:37|Removing wire iURSTB_inv, as there is no assignment to it.
|
||||
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":31:8:31:13|*Output UTRSTB has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@W: CL318 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v":32:8:32:11|*Output UTMS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output.
|
||||
@W: CL208 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":134:0:134:5|All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization.
|
||||
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":195:12:195:22|Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":196:12:196:22|Removing wire resetn_rx_p, as there is no assignment to it.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":200:12:200:22|Removing wire resetn_rx_r, as there is no assignment to it.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":222:12:222:36|Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":1130:0:1130:5|Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":719:0:719:5|Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers.
|
||||
@W: CL177 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":343:0:343:5|Sharing sequential element cfg_enable_P1 and merging msrx_async_reset_ok. Add a syn_preserve attribute to the element to prevent sharing.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v":270:0:270:10|Input MTXCFRM on instance CORETSE_0_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
|
||||
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
|
||||
@W: CL177 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v":501:0:501:5|Sharing sequential element clear_framing_error_en and merging clear_parity_en. Add a syn_preserve attribute to the element to prevent sharing.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":136:8:136:17|Object data_ready is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":376:0:376:5|Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":326:0:326:5|Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":293:0:293:5|Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v":159:0:159:5|Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":158:20:158:30|Object controlReg3 is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18721:3:18721:9|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19009:38:19009:51|Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19017:38:19017:57|Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19020:38:19020:53|Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19021:38:19021:58|Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19022:38:19022:62|Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19023:38:19023:67|Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19024:38:19024:49|Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19025:38:19025:49|Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19026:38:19026:56|Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19027:38:19027:52|Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10740:32:10740:42|Index into variable mul_mp could be out of range ; a simulation mismatch is possible.
|
||||
@W: CG1340 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10740:32:10740:42|Index into variable mul_mp could be out of range ; a simulation mismatch is possible.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10766:32:10766:40|Object fpu_frm_i is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10767:32:10767:35|Object op_i is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":843:10:843:11|Object status_o.NV is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":844:10:844:11|Object status_o.DZ is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":845:10:845:11|Object status_o.OF is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CG133 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v":846:10:846:11|Object status_o.UF is declared but not assigned. Either assign a value or remove the declaration.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4310:6:4310:26|Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":10390:2:10390:7|Pruning unused register sreset. Make sure that there are no unused intermediate registers.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9191:4:9191:9|Pruning register bit 5 of gen_gpr_ex_attbs_rd_ex.de_ex_pipe_gpr_rs1_rd_sel_ex[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CG532 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10042:1:10042:7|Within an initial block, only Verilog force statements and memory initialization statements and initialization of entire variable are recognized, and all other content is ignored. Simulation mismatch may occur
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15811:0:15811:5|Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15791:0:15791:5|Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15811:0:15811:5|Pruning unused register wr_gray_ptr_in_read[1:0]. Make sure that there are no unused intermediate registers.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15791:0:15791:5|Pruning register bit 1 of rd_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15785:0:15785:5|Pruning register bit 1 of wr_ptr[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal.
|
||||
@W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14337:0:14337:8|Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25538:12:25538:44|Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25498:12:25498:43|Removing instance miv_rv32_ram_singleport_lp_R20C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25465:27:25465:41|Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25376:12:25376:43|Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25295:12:25295:43|Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25265:27:25265:41|Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25182:12:25182:43|Removing instance miv_rv32_ram_singleport_lp_R24C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25159:27:25159:41|Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25104:27:25104:40|Removing instance \CFG2_BLKY2[6] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":25049:12:25049:43|Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24993:12:24993:43|Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24990:27:24990:33|Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24953:12:24953:43|Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24901:12:24901:44|Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24863:12:24863:43|Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24853:27:24853:41|Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24804:12:24804:43|Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24764:12:24764:43|Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24686:12:24686:44|Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24667:27:24667:41|Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24622:12:24622:44|Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24548:12:24548:43|Removing instance miv_rv32_ram_singleport_lp_R31C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24502:27:24502:41|Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24492:27:24492:41|Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24490:28:24490:34|Removing instance CFG3_22 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24451:12:24451:43|Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24412:12:24412:43|Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24308:12:24308:43|Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24268:12:24268:43|Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24254:28:24254:34|Removing instance CFG3_11 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24231:27:24231:32|Removing instance CFG3_1 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24202:28:24202:34|Removing instance CFG3_21 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24148:12:24148:43|Removing instance miv_rv32_ram_singleport_lp_R25C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24142:27:24142:41|Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24105:12:24105:43|Removing instance miv_rv32_ram_singleport_lp_R28C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24033:12:24033:43|Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":24029:27:24029:40|Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23903:12:23903:44|Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23864:12:23864:44|Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23805:12:23805:43|Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23799:27:23799:40|Removing instance \CFG2_BLKY2[7] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23753:12:23753:44|Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23685:12:23685:43|Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23662:27:23662:40|Removing instance \CFG2_BLKY2[5] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23601:12:23601:44|Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23540:27:23540:41|Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23490:12:23490:43|Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23440:12:23440:43|Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23401:12:23401:44|Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23338:12:23338:43|Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23292:27:23292:41|Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23222:12:23222:43|Removing instance miv_rv32_ram_singleport_lp_R26C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23130:12:23130:43|Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23092:12:23092:43|Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23071:27:23071:41|Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":23012:12:23012:43|Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22972:12:22972:44|Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22882:27:22882:41|Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22821:12:22821:43|Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22779:12:22779:43|Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22733:12:22733:43|Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22687:12:22687:43|Removing instance miv_rv32_ram_singleport_lp_R27C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22671:27:22671:41|Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22665:27:22665:41|Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22600:12:22600:43|Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22556:12:22556:44|Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22510:12:22510:43|Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22433:27:22433:41|Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22330:12:22330:43|Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22260:12:22260:43|Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22193:12:22193:43|Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22147:12:22147:43|Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":22094:12:22094:43|Removing instance miv_rv32_ram_singleport_lp_R29C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21997:12:21997:44|Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21988:27:21988:41|Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21943:12:21943:43|Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21894:12:21894:43|Removing instance miv_rv32_ram_singleport_lp_R30C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21848:12:21848:43|Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21845:27:21845:40|Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21838:28:21838:33|Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21814:27:21814:41|Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21791:27:21791:41|Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21713:12:21713:44|Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21667:12:21667:43|Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21589:12:21589:43|Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21586:27:21586:41|Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21578:27:21578:41|Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21562:27:21562:41|Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21440:12:21440:43|Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21385:12:21385:43|Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21341:27:21341:41|Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21304:12:21304:43|Removing instance miv_rv32_ram_singleport_lp_R18C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21236:12:21236:44|Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21193:12:21193:43|Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v":21098:28:21098:33|Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10961:2:10961:7|Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL169 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10961:2:10961:7|Pruning unused register tcm_tas_access_disable_reg. Make sure that there are no unused intermediate registers.
|
||||
@W: CL265 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11237:2:11237:7|Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal.
|
||||
@W: CL271 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
|
||||
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1481:45:1481:63|Port-width mismatch for port cpu_i_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
|
||||
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1494:45:1494:63|Port-width mismatch for port cpu_d_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
|
||||
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1509:45:1509:66|Port-width mismatch for port udma_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
|
||||
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":1526:44:1526:64|Port-width mismatch for port tcm_tas_req_addr. The port definition is 16 bits, but the actual port connection bit width is 32. Adjust either the definition or the instantiation of this port.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v":343:13:343:33|Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it.
|
||||
@W: CS263 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v":305:34:305:52|Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:45:70:45|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:54:70:54|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":64:23:64:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":67:13:67:13|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:34:49:34|Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:46:49:46|Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:59:49:59|Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:17:50:17|Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:26:50:26|Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:41:50:41|Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:55:50:55|Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:69:50:69|Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:21:51:21|Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:35:51:35|Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:49:51:49|Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:65:51:65|Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:19:52:19|Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:34:52:34|Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:59:52:59|Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:20:54:20|Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:36:54:36|Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":59:21:59:21|Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:23:94:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG781 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:32:94:32|Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration.
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it.
|
||||
@W: CG168 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":47:27:47:36|Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
|
||||
@W: CG360 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v":24:12:24:18|Input port bits 9 to 7 of rx_data[9:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":11056:2:11056:7|Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10831:49:10831:62|Input port bits 1 to 0 of cpu_i_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10844:49:10844:62|Input port bits 1 to 0 of cpu_d_req_addr[15:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2494:49:2494:66|Input port bits 11 to 0 of cfg_apb_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2495:49:2495:64|Input port bits 11 to 0 of cfg_apb_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2500:49:2500:73|Input port bits 11 to 0 of cfg_subsys_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2501:49:2501:71|Input port bits 11 to 0 of cfg_subsys_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2502:49:2502:67|Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":2503:49:2503:65|Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4490:49:4490:71|Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4495:49:4495:68|Input port bits 31 to 3 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6360:31:6360:36|Input port bit 5 of waddr0[5:0] is unused
|
||||
@W: CL247 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":1854:60:1854:72|Input port bit 1 of excpt_trigger[1:0] is unused
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 31 to 24 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 21 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6887:43:6887:44|Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6896:43:6896:57|Input port bits 9 to 2 of sys_ext_irq_src[9:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL279 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Pruning register bits 31 to 6 of mul_div_cnt[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19324:4:19324:9|Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v":104:20:104:24|Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL260 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
@W: CL246 :"E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
|
||||
|
||||
39
synthesis/synlog/report/top_fpga_mapper_area_report.xml
Normal file
39
synthesis/synlog/report/top_fpga_mapper_area_report.xml
Normal file
@@ -0,0 +1,39 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
The file contains the area information from mapper to be displayed as part of the summary report.
|
||||
*******************************************************************************************-->
|
||||
<report_table display_priority="1" name="Area Summary">
|
||||
<report_link name="Detailed report">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_resourceusage.rpt</data>
|
||||
<title>Resource Usage</title>
|
||||
</report_link>
|
||||
<report_link name="Hierarchical Area report">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_hier_area_report.xml</data>
|
||||
<title>Hierarchical Area Report</title>
|
||||
</report_link>
|
||||
<parameter tooltip="Total Carry Cells used" name="Carry Cells">
|
||||
<data>2335</data>
|
||||
</parameter>
|
||||
<parameter tooltip="Total Sequential Cells used" name="Sequential Cells">
|
||||
<data>7316</data>
|
||||
</parameter>
|
||||
<parameter tcl_name="dsp_used" tooltip="Total DSP Blocks used" name="DSP Blocks">
|
||||
<data>0</data>
|
||||
</parameter>
|
||||
<parameter tooltip="Total I/O Cells used" name="I/O Cells">
|
||||
<data>50</data>
|
||||
</parameter>
|
||||
<parameter tooltip="Total Global Clock Buffers used" name="Global Clock Buffers">
|
||||
<data>7</data>
|
||||
</parameter>
|
||||
<parameter tcl_name="v_ram" tooltip="Total RAM1K20 used" name="RAM1K20">
|
||||
<data>34</data>
|
||||
</parameter>
|
||||
<parameter tcl_name="v_ram" tooltip="Total RAM64x12 used" name="RAM64x12">
|
||||
<data>11</data>
|
||||
</parameter>
|
||||
<parameter tcl_name="total_luts" tooltip="Total LUTs used" name="LUTs">
|
||||
<data>15992</data>
|
||||
</parameter>
|
||||
</report_table>
|
||||
0
synthesis/synlog/report/top_fpga_mapper_errors.txt
Normal file
0
synthesis/synlog/report/top_fpga_mapper_errors.txt
Normal file
238
synthesis/synlog/report/top_fpga_mapper_hier_area.csv
Normal file
238
synthesis/synlog/report/top_fpga_mapper_hier_area.csv
Normal file
@@ -0,0 +1,238 @@
|
||||
|
||||
. Module name, SLE, CFG, ARI1, BUFFER, MACC_PA, RAM1K20, RAM64X12, GLOBAL, IO
|
||||
. top, 7316, 13657, 2335, 102, 0, 34, 11, 7, 50
|
||||
. . COREFIFO_C0, 148, 90, 58, 0, 0, 2, 0, 0, 0
|
||||
. . . COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2, 148, 90, 58, 0, 0, 2, 0, 0, 0
|
||||
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft_Z4, 68, 38, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3, 45, 17, 58, 0, 0, 0, 0, 0, 0
|
||||
. . . . COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s, 0, 0, 0, 0, 0, 2, 0, 0, 0
|
||||
. . . . . COREFIFO_C0_COREFIFO_C0_0_LSRAM_top, 0, 0, 0, 0, 0, 2, 0, 0, 0
|
||||
. . COREJTAGDEBUG_C0, 17, 117, 0, 102, 0, 0, 0, 2, 0
|
||||
. . . COREJTAGDEBUG_Z5, 17, 117, 0, 102, 0, 0, 0, 2, 0
|
||||
. . . . COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0, 17, 114, 0, 68, 0, 0, 0, 0, 0
|
||||
. . . . . corejtagdebug_bufd_34s, 0, 0, 0, 34, 0, 0, 0, 0, 0
|
||||
. . . . . corejtagdebug_bufd_34s_0, 0, 0, 0, 34, 0, 0, 0, 0, 0
|
||||
. . . . corejtagdebug_bufd_34s_2, 0, 0, 0, 34, 0, 0, 0, 0, 0
|
||||
. . CORESPI_0, 247, 345, 30, 0, 0, 0, 4, 0, 0
|
||||
. . . CORESPI_Z7, 247, 345, 30, 0, 0, 0, 4, 0, 0
|
||||
. . . . spi_32s_16s_32s_16s_0_0_1_0s, 247, 345, 30, 0, 0, 0, 4, 0, 0
|
||||
. . . . . spi_chanctrl_Z6, 168, 187, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . spi_clockmux, 0, 1, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . spi_control_16s, 0, 14, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . spi_fifo_16s_32s_5_0, 18, 29, 6, 0, 0, 0, 2, 0, 0
|
||||
. . . . . spi_fifo_16s_32s_5_1, 18, 31, 6, 0, 0, 0, 2, 0, 0
|
||||
. . . . . spi_rf_32s_16s_0, 43, 84, 0, 0, 0, 0, 0, 0, 0
|
||||
. . CORETSE_0, 4601, 6488, 1370, 0, 0, 12, 0, 0, 0
|
||||
. . . CORETSE_Z11, 4601, 6488, 1370, 0, 0, 12, 0, 0, 0
|
||||
. . . . CTSE_CORETSE_TOP_Z10, 4497, 6431, 1302, 0, 0, 12, 0, 0, 0
|
||||
. . . . . CTSE_CLKRST_26s_1s, 14, 7, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CTSE_ECC_0s_26s_16s, 44, 20, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s, 8, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_2, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_16_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_2, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_3, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17, 8, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_2, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_3, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_17_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_4, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_13_5, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CTSE_MSGMII_CORE_26s_0s_18s_0s, 1041, 1814, 113, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MSGMII_CNVRXI_26s, 208, 188, 7, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MSGMII_CNVRXO_26s, 18, 22, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MSGMII_CNVTXI_26s, 108, 108, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MSGMII_CNVTXO_26s, 24, 12, 8, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MSGMII_TBI_26s_0s_0s_1s, 681, 1483, 98, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_MSGMII_PEANX_TOP_1s_26s, 231, 194, 67, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEANX_SYNC_1s_26s, 60, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEREX_PCS_0s_26s_1s, 121, 553, 27, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_R10B8B_0, 0, 131, 21, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_R10B8B_1, 0, 158, 6, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEREX_PMA_26s_0s_1s_0_1_2_3_4, 103, 307, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PETBM_26s_0s_1s, 124, 181, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PETCR_26s_1s, 5, 3, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PETEX_TOP_26s_0s_1s, 97, 245, 4, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_T8B10B, 0, 112, 4, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CTSE_RX4096X36_12s_26s_1s_1s_4s, 0, 0, 0, 0, 0, 8, 0, 0, 0
|
||||
. . . . . CTSE_TSMAC_TOP_Z9, 3378, 4590, 1189, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MAPBE_HST_CNV_26s_0s_1s_0s_16s, 231, 257, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_DECODER, 0, 82, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_TSM_SYSREG_26s_1s_0s, 230, 171, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_MMCXWOL_1s_26s, 52, 93, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_PEMSTAT_26s, 764, 1447, 606, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEMSTAT_CNTRL_1s_26s, 65, 121, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEMSTAT_EIM_26s_1s_0s, 51, 589, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEMSTAT_STORE_26s, 648, 737, 606, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LADD_1s_26s, 25, 28, 24, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LADD_1s_26s_0, 25, 27, 24, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_0, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_1, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_10, 19, 21, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_11, 19, 21, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_2, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_3, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_4, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_5, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_6, 19, 21, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_7, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_8, 19, 22, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_LINC_1s_26s_9, 19, 21, 18, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SADD_1s_26s, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_0, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_1, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_2, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_3, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCHD_1s_26s_4, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_0, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_1, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_2, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_3, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINCNF_1s_26s_4, 13, 14, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_0, 13, 16, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_1, 13, 16, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_10, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_11, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_12, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_2, 13, 16, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_3, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_4, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_5, 13, 16, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_6, 13, 16, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_7, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_8, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PEMSTAT_SINC_1s_26s_9, 13, 15, 12, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_PE_MCXMAC_26s_0_0s_0s, 1046, 1569, 266, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PECAR_26s_1s, 13, 9, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEHST_1s_26s, 222, 71, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PEMGT_1s_26s, 111, 209, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_PE_MCXMAC_CORE_26s_0_0s_0s, 700, 1264, 266, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PERFN_TOP_26s_0s_0_1s, 223, 362, 128, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . . CTSE_PECRC_1s_26s_1, 32, 78, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PERMC_TOP_1s_26s, 117, 177, 23, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PETFN_TOP_26s_0s_0_1s, 324, 610, 79, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . . CTSE_PECRC_1s_26s_0, 32, 163, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . CTSE_PETMC_TOP_1s_26s, 36, 114, 36, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_0, 8, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_10_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_1, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SIB_SYNC_PULSE_26s_1s_0s_16, 8, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_12_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . CTSE_SI_SAL_26s, 3, 115, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . OiOI1_26s_11s_12s_32s_2s_0s, 1263, 683, 317, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXFIF_CLKRST_26s_1s, 10, 5, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXFIF_HST_Z8, 266, 68, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s, 238, 176, 33, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s, 303, 188, 62, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s, 152, 86, 60, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s, 198, 121, 88, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_AMCXTFIF_WTM_26s_12s_1s_0_0, 90, 39, 74, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . CTSE_SIB_SYNC_2FLP_1s_26s_1s_8_0, 3, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CTSE_TX2048X40_11s_26s_1s_1s_4s, 0, 0, 0, 0, 0, 4, 0, 0, 0
|
||||
. . . . CTSE_SELF_DESTRUCT_26s_1s_125000000s_25000000s_2500000s_4s_14400s_18446744072277895850_27s_14s_Z12, 104, 57, 68, 0, 0, 0, 0, 0, 0
|
||||
. . CoreAPB3_0, 0, 15, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . CoreAPB3_Z1, 0, 15, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . COREAPB3_MUXPTOB3, 0, 11, 0, 0, 0, 0, 0, 0, 0
|
||||
. . CoreUARTapb_0, 114, 134, 19, 0, 0, 0, 0, 0, 0
|
||||
. . . CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z13, 114, 134, 19, 0, 0, 0, 0, 0, 0
|
||||
. . . . CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s, 90, 107, 19, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s, 19, 10, 14, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s, 41, 68, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s, 21, 23, 5, 0, 0, 0, 0, 0, 0
|
||||
. . Core_reset_pf, 16, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . Core_reset_pf_Core_reset_pf_0_CORERESET_PF, 16, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . MIV_RV32_C0, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
|
||||
. . . MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z22, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
|
||||
. . . . miv_rv32_ipcore_Z19, 2069, 6278, 765, 0, 0, 18, 7, 0, 0
|
||||
. . . . . miv_rv32_hart_Z17, 1001, 4216, 580, 0, 0, 0, 6, 0, 0
|
||||
. . . . . . miv_rv32_expipe_Z16, 759, 3565, 546, 0, 0, 0, 6, 0, 0
|
||||
. . . . . . . miv_rv32_bcu, 0, 47, 92, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_csr_decode_1s_1s_0s, 0, 38, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_csr_privarch_Z15, 254, 697, 32, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_decode_0s_1s_0s, 0, 66, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_0, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_1, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_2, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_3, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_0s_0s_5, 1, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12, 1, 5, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_12_0, 1, 3, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_5, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_7, 1, 3, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9, 1, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_0, 1, 1, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_1, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_2, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_3, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_9_4, 1, 339, 32, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_30s_1s_536870913, 30, 1, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_31s_0s_0s, 31, 32, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_0, 32, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_0s_0s_1, 32, 33, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_0_0, 32, 34, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_0_1, 31, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_32s_1s_18446744071562067968, 32, 66, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_3s_1s_0s_0, 3, 5, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_csr_gpr_state_reg_5s_1s_0, 5, 8, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . miv_rv32_priv_irq_2s_0_0, 2, 23, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . . miv_rv32_irq_reg_0s, 1, 9, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . . . miv_rv32_irq_reg_0s_0, 1, 3, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1, 202, 1599, 422, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_gpr_ram_0s_0_0s_32s, 20, 42, 0, 0, 0, 0, 6, 0, 0
|
||||
. . . . . . . . miv_rv32_gpr_ram_array_32s_6s_32s, 0, 6, 0, 0, 0, 0, 6, 0, 0
|
||||
. . . . . . . miv_rv32_idecode_1_1s_1s_0s, 0, 1044, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_fetch_unit_32s_18446744071562067968_0s_3s_2s_3s_2s_2s_0s_1s_Z14, 220, 453, 30, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_ifu_iab_32s_2s_3s_2s_0s, 215, 213, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_lsu_32s_2s_1s_2s_2s, 22, 198, 4, 0, 0, 0, 0, 0, 0
|
||||
. . . . . miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5, 115, 172, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_rr_pri_arb_2s_1s_1s, 4, 18, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . miv_rv32_subsys_debug_1s, 664, 1043, 40, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_debug_dtm_jtag_1s, 109, 207, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_debug_du, 379, 738, 40, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_debug_sba, 166, 670, 40, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_debug_fifo_34s_1s_1s, 80, 45, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_debug_fifo_41s_1s_1s, 96, 53, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . miv_rv32_subsys_interconnect_Z18, 55, 373, 0, 0, 0, 0, 1, 0, 0
|
||||
. . . . . . miv_rv32_buffer_11s_2s_1s_1s, 29, 19, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_buffer_6s_2s_1s_1s, 17, 13, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s, 9, 28, 0, 0, 0, 0, 1, 0, 0
|
||||
. . . . . . . miv_rv32_buffer_7s_2s_1s_1s, 5, 13, 0, 0, 0, 0, 1, 0, 0
|
||||
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s, 1, 2, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_0, 1, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_csr_gpr_state_reg_1s_1s_0s_1, 1, 1, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820, 176, 270, 145, 0, 0, 0, 0, 0, 0
|
||||
. . . . . miv_rv32_subsys_tcm_Z20, 58, 169, 0, 0, 0, 18, 0, 0, 0
|
||||
. . . . . . miv_rv32_ram_singleport_lp_Z21, 0, 22, 0, 0, 0, 18, 0, 0, 0
|
||||
. . . . . . miv_rv32_rr_pri_arb_3s_1s_1s, 3, 147, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . . . . . miv_rv32_fixed_arb_3s_2, 0, 81, 0, 0, 0, 0, 0, 0, 0
|
||||
. . PF_CCC_0, 0, 0, 0, 0, 0, 0, 0, 1, 0
|
||||
. . . PF_CCC_0_PF_CCC_0_0_PF_CCC, 0, 0, 0, 0, 0, 0, 0, 1, 0
|
||||
. . PF_IOD_CDR_C0, 59, 153, 74, 0, 0, 0, 0, 2, 2
|
||||
. . . CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1, 59, 151, 74, 0, 0, 0, 0, 0, 0
|
||||
. . . PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL, 0, 1, 0, 0, 0, 0, 0, 1, 0
|
||||
. . PF_IOD_CDR_CCC_C0, 31, 22, 8, 0, 0, 0, 0, 2, 0
|
||||
. . . COREDELAYCODE_TIP, 31, 22, 8, 0, 0, 0, 0, 0, 0
|
||||
. . . PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC, 0, 0, 0, 0, 0, 0, 0, 1, 0
|
||||
. . . PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV, 0, 0, 0, 0, 0, 0, 0, 1, 0
|
||||
. . . PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . PF_TPSRAM_C0, 0, 0, 0, 0, 0, 2, 0, 0, 0
|
||||
. . . PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM, 0, 0, 0, 0, 0, 2, 0, 0, 0
|
||||
. . SSDetect, 2, 7, 0, 0, 0, 0, 0, 0, 0
|
||||
. . fifo_to_tpsram_bridge, 12, 5, 11, 0, 0, 0, 0, 0, 0
|
||||
. . pf_init_monitor_0, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
. . . pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR, 0, 0, 0, 0, 0, 0, 0, 0, 0
|
||||
|
2851
synthesis/synlog/report/top_fpga_mapper_hier_area_report.xml
Normal file
2851
synthesis/synlog/report/top_fpga_mapper_hier_area_report.xml
Normal file
File diff suppressed because it is too large
Load Diff
103
synthesis/synlog/report/top_fpga_mapper_notes.txt
Normal file
103
synthesis/synlog/report/top_fpga_mapper_notes.txt
Normal file
@@ -0,0 +1,103 @@
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_fwft.v":347:3:347:8|Removing sequential instance genblk17\.u_corefifo_fwft.reg_valid_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_fwft.v":347:3:347:8|Removing sequential instance genblk17\.u_corefifo_fwft.empty_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_COREFIFO_Z2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":645:7:645:10|ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) mapped in logic.
|
||||
@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":645:7:645:10|Found ROM spi_clk_out_2[1:0] (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) with 10 words by 2 bits.
|
||||
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19089:4:19089:7|ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic.
|
||||
@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":19089:4:19089:7|Found ROM lsu_emi_req_fence_1[2:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) with 10 words by 3 bits.
|
||||
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.
|
||||
@N: BZ173 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) mapped in logic.
|
||||
@N: MO106 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coreapb3\4.2.100\rtl\vlog\core\coreapb3.v":267:2:267:5|Found ROM CoreAPB3_0_0.CoreAPB3_0_0.iPSELS_raw_2[2:0] (in view: work.top(verilog)) with 3 words by 3 bits.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6231:6:6231:11|Removing sequential instance gen_apb_byte_shim\.pwdata_p[3:0] (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":636:3:636:8|Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memraddr_r[9:0]
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":620:3:620:8|Found counter in view:work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog) instance memwaddr_r[9:0]
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance stxs_bitcnt[4:0]
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Found counter in view:CORESPI_LIB.spi_chanctrl_Z6(verilog) instance spi_clk_count[7:0]
|
||||
@N: MF179 :|Found 17 by 17 bit equality operator ('==') un13_IIIIo (in view: work.CTSE_PETFN_TOP_26s_0s_0_1s(verilog))
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\clock_gen.v":283:6:283:11|Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.baud_cntr[12:0]
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":31:4:31:9|Found counter in view:work.fifo_to_tpsram_bridge(verilog) instance ram_w_addr[9:0]
|
||||
@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)).
|
||||
@N: FX702 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Found startup values on RAM instance u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0]
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[2:0] is 2 words by 3 bits.
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data[6:0] is 2 words by 7 bits.
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[0].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[1].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[2].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[3].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[4].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[5].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram0_[6].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[0].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[1].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[2].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[3].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[4].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[5].
|
||||
@N: FX493 |Applying initial value "0" on instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data_ram1_[6].
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory[33:0] is 2 words by 34 bits.
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.debug_req_fifo.fifo_memory[40:0] is 2 words by 41 bits.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][0] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view: work.miv_rv32_ipcore_Z19(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[0] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset\.state_val[16] (in view: work.miv_rv32_ipcore_Z19(verilog)) because it does not drive other instances.
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp_1[0] is 4 words by 1 bits.
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_error_resp[0] is 4 words by 1 bits.
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] is 4 words by 32 bits.
|
||||
@N: MF135 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|RAM MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] is 4 words by 16 bits.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing sequential instance gen_buff_loop\[0\]\.buff_entry_error_resp_1.gen_buff_loop\[0\]\.buff_entry_error_resp_1_ram3_[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s_0s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9798:4:9798:9|Removing sequential instance gen_trig_pipe_reg_ex_retr\.ex_retr_pipe_trigger_retr[1] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11446:2:11446:7|Found counter in view:work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog) instance mul_div_cnt[5:0]
|
||||
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11165:64:11165:92|Found 32 by 32 bit equality operator ('==') un152_exu_alu_result (in view: work.miv_rv32_exu_1s_1s_1s_1s_0s_0s_0s_1_0_1(verilog))
|
||||
@N: FX403 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] with specified coding style. Inferring block RAM.
|
||||
@N: FX403 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] with specified coding style. Inferring block RAM.
|
||||
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4547:53:4547:117|Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[0\]\.un2_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))
|
||||
@N: MF179 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":4547:53:4547:117|Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[1\]\.un5_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z15(verilog))
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15548:0:15548:8|Found counter in view:work.miv_rv32_debug_sba(verilog) instance counter[7:0]
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":13076:6:13076:14|Found counter in view:work.miv_rv32_subsys_mtime_irq_1s_1s_100s_1s_33603580_33570820(verilog) instance mtime_count_out[63:0]
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
|
||||
@N: MO231 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0]
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":8721:2:8721:7|Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z16(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9395:2:9395:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[5] (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_apb\.u_apb_initiator_0.u_apb_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10391:2:10391:7|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_tcm0\.u_subsys_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":463:3:463:8|Removing sequential instance COREFIFO_C0_0.COREFIFO_C0_0.genblk16\.fifo_corefifo_sync_scntr.empty_top_fwft_r (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16013:12:16013:20|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug\.u_subsys_debug_unit_0.MIV_subsys_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":286:0:286:5|Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances.
|
||||
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT I_4035
|
||||
@N: FP130 |Promoting Net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK on CLKINT I_4036
|
||||
@N: FP130 |Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT I_4037
|
||||
@N: FP130 |Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT I_4038
|
||||
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
|
||||
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF
|
||||
@N: MT615 |Found clock REF_CLK_0 with period 20.00ns
|
||||
@N: MT615 |Found clock PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R with period 8.00ns
|
||||
@N: MT615 |Found clock REFCLK_P with period 8.00ns
|
||||
@N: MT615 |Found clock TCK with period 100.00ns
|
||||
@N: MT615 |Found clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 with period 12.50ns
|
||||
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 with period 1.60ns
|
||||
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 with period 1.60ns
|
||||
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 with period 1.60ns
|
||||
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 with period 1.60ns
|
||||
@N: MT615 |Found clock PHY_MDC_CLOCK with period 350.00ns
|
||||
@N: MT615 |Found clock PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV with period 8.00ns
|
||||
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
|
||||
6
synthesis/synlog/report/top_fpga_mapper_opt_report.xml
Normal file
6
synthesis/synlog/report/top_fpga_mapper_opt_report.xml
Normal file
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
The file contains the optimization information from mapper to be displayed as part of the summary report.
|
||||
*******************************************************************************************-->
|
||||
<report_table display_priority="3" name="Optimizations Summary"></report_table>
|
||||
59
synthesis/synlog/report/top_fpga_mapper_resourceusage.rpt
Normal file
59
synthesis/synlog/report/top_fpga_mapper_resourceusage.rpt
Normal file
@@ -0,0 +1,59 @@
|
||||
Resource Usage Report for top
|
||||
|
||||
Mapping to part: mpf300tfcg1152-1
|
||||
Cell usage:
|
||||
AND2 1 use
|
||||
BANKEN 1 use
|
||||
BUFD 102 uses
|
||||
CLKINT 6 uses
|
||||
DLL 1 use
|
||||
HS_IO_CLK 4 uses
|
||||
ICB_CLKDIV 1 use
|
||||
INIT 1 use
|
||||
INV 4 uses
|
||||
IOD 5 uses
|
||||
LANECTRL 2 uses
|
||||
OR2 32 uses
|
||||
OR4 1344 uses
|
||||
PLL 2 uses
|
||||
RCLKINT 1 use
|
||||
UJTAG 1 use
|
||||
CFG1 110 uses
|
||||
CFG2 1957 uses
|
||||
CFG3 3420 uses
|
||||
CFG4 8170 uses
|
||||
|
||||
Carry cells:
|
||||
ARI1 2102 uses - used for arithmetic functions
|
||||
ARI1 233 uses - used for Wide-Mux implementation
|
||||
Total ARI1 2335 uses
|
||||
|
||||
|
||||
Sequential Cells:
|
||||
SLE 7316 uses
|
||||
|
||||
DSP Blocks: 0 of 924 (0%)
|
||||
|
||||
I/O ports: 58
|
||||
I/O primitives: 50
|
||||
BIBUF 1 use
|
||||
INBUF 4 uses
|
||||
INBUF_DIFF 2 uses
|
||||
OUTBUF 42 uses
|
||||
OUTBUF_DIFF 1 use
|
||||
|
||||
|
||||
Global Clock Buffers: 7
|
||||
|
||||
Total LUTs: 15992
|
||||
|
||||
Extra resources required for RAM and MACC_PA interface logic during P&R:
|
||||
|
||||
RAM64X12 Interface Logic : SLEs = 132; LUTs = 132;
|
||||
RAM1K20 Interface Logic : SLEs = 1224; LUTs = 1224;
|
||||
MACC_PA Interface Logic : SLEs = 0; LUTs = 0;
|
||||
MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0;
|
||||
|
||||
Total number of SLEs after P&R: 7316 + 132 + 1224 + 0 = 8672;
|
||||
Total number of LUTs after P&R: 15992 + 132 + 1224 + 0 = 17348;
|
||||
|
||||
46
synthesis/synlog/report/top_fpga_mapper_runstatus.xml
Normal file
46
synthesis/synlog/report/top_fpga_mapper_runstatus.xml
Normal file
@@ -0,0 +1,46 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
The file contains the job information from mapper to be displayed as part of the summary report.
|
||||
*******************************************************************************************-->
|
||||
<job_run_status name="Mapper">
|
||||
<report_link name="Detailed report">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr</data>
|
||||
<title></title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
<data>Completed</data>
|
||||
</job_status>
|
||||
<job_info>
|
||||
<info name="Notes">
|
||||
<data>103</data>
|
||||
<report_link name="more">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_notes.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>120</data>
|
||||
<report_link name="more">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_warnings.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
<data>0</data>
|
||||
<report_link name="more">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_fpga_mapper_errors.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="CPU Time">
|
||||
<data>0h:03m:51s</data>
|
||||
</info>
|
||||
<info name="Real Time">
|
||||
<data>0h:03m:54s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>521MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1776273723</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
101
synthesis/synlog/report/top_fpga_mapper_timing_report.xml
Normal file
101
synthesis/synlog/report/top_fpga_mapper_timing_report.xml
Normal file
@@ -0,0 +1,101 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
Max Top 5 critical clocks will be reported. For rest user needs to refer to Detailed report
|
||||
*******************************************************************************************-->
|
||||
<report_table display_priority="2" name="Timing Summary">
|
||||
<report_link name="Detailed report">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_fpga_mapper.srr</data>
|
||||
<title>START OF TIMING REPORT</title>
|
||||
</report_link>
|
||||
<row>
|
||||
<data tcl_name="clock_name">Clock Name</data>
|
||||
<data tcl_name="req_freq">Req Freq</data>
|
||||
<data tcl_name="est_freq">Est Freq</data>
|
||||
<data tcl_name="slack">Slack</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>COREJTAGDEBUG_Z5|iUDRCK_inferred_clock</data>
|
||||
<data>100.0 MHz</data>
|
||||
<data>13.4 MHz</data>
|
||||
<data>-32.246</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0</data>
|
||||
<data>80.0 MHz</data>
|
||||
<data>55.0 MHz</data>
|
||||
<data>-5.671</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R</data>
|
||||
<data>125.0 MHz</data>
|
||||
<data>116.7 MHz</data>
|
||||
<data>-0.228</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop</data>
|
||||
<data>100.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0</data>
|
||||
<data>625.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1</data>
|
||||
<data>625.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2</data>
|
||||
<data>625.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3</data>
|
||||
<data>625.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV</data>
|
||||
<data>125.0 MHz</data>
|
||||
<data>230.3 MHz</data>
|
||||
<data>3.659</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>PHY_MDC_CLOCK</data>
|
||||
<data>2.9 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>REFCLK_P</data>
|
||||
<data>125.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>REF_CLK_0</data>
|
||||
<data>50.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>TCK</data>
|
||||
<data>10.0 MHz</data>
|
||||
<data>NA</data>
|
||||
<data>NA</data>
|
||||
</row>
|
||||
<row>
|
||||
<data>System</data>
|
||||
<data>100.0 MHz</data>
|
||||
<data>26.5 MHz</data>
|
||||
<data>-27.793</data>
|
||||
</row>
|
||||
</report_table>
|
||||
120
synthesis/synlog/report/top_fpga_mapper_warnings.txt
Normal file
120
synthesis/synlog/report/top_fpga_mapper_warnings.txt
Normal file
@@ -0,0 +1,120 @@
|
||||
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
|
||||
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":261:0:261:5|Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.uUART.make_RX.last_bit[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[25] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[24] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[16]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[30] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[29] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[28] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[27] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[26] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[23] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[22] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[21] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[20] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[19] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[18] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[17] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|RAM u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop\[0\]\.buff_data[5:0] (in view: work.miv_rv32_ipcore_Z19(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15839:0:15839:5|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory.gen_subsys_debug.u_subsys_debug_unit_0.debug_resp_fifo.fifo_memory_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18735:4:18735:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9414:2:9414:7|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|RAM gen_gpr\.u_gpr_array_0.mem_xf_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
|
||||
@W: FX107 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|RAM gen_gpr\.u_gpr_array_0.mem_xf[31:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":47:0:47:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":48:0:48:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":49:0:49:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":50:0:50:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":51:0:51:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":52:0:52:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":53:0:53:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":54:0:54:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: BW150 :|Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated
|
||||
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
|
||||
@W: MT246 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v":40:53:40:58|Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
|
||||
@W: MT420 |Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK.
|
||||
@W: MT420 |Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.iUDRCK_0.
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
@W: MT447 :"e:/abhishekv/rising/ethernet_tpsram_test/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design
|
||||
0
synthesis/synlog/report/top_premap_errors.txt
Normal file
0
synthesis/synlog/report/top_premap_errors.txt
Normal file
65
synthesis/synlog/report/top_premap_notes.txt
Normal file
65
synthesis/synlog/report/top_premap_notes.txt
Normal file
@@ -0,0 +1,65 @@
|
||||
@N: MF916 |Option synthesis_strategy=base is enabled.
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11493:2:11493:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.exu_result_reg_int[64:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":11473:2:11473:7|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_exu_0.quotient[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_fflags_flags.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: FX1171 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_miv_rv32_ver_reg.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":48:26:48:36|Tristate driver A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":46:26:46:37|Tristate driver A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net A_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":49:26:49:36|Tristate driver B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_DB_DETECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_c0_corefifo_c0_0_ram_wrapper.v":47:26:47:37|Tristate driver B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) on net B_SB_CORRECT (in view: work.COREFIFO_C0_COREFIFO_C0_0_ram_wrapper_32s_32s_10_10_1s_1s_2s_0s_0s(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":169:8:169:52|Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":176:8:176:52|Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":183:8:183:52|Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":190:8:190:52|Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":32:8:32:11|Tristate driver UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTMS (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
|
||||
@N: MO111 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug.v":31:8:31:13|Tristate driver UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) on net UTRSTB (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z5(verilog)) has its enable tied to GND.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7090:6:7090:31|Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":7016:2:7016:23|Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_2s_0_0(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2565:4:2565:35|Removing instance u_csr_gpr_state_reg_fflags_flags (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4653:2:4653:23|Removing instance u_subsys_parity_en_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4904:4:4904:42|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":4923:4:4923:44|Removing instance gen_tcm0_irq_pend\.u_subsys_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_subsys_regs_12s_0s_1s_0s_1_0s_50397384_7s_2s_1s(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_lanectrl_0\pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v":107:12:107:32|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_ccc_c0\pf_lanectrl_core_reader_0\pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v":93:46:93:66|Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":111:0:111:5|Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance fifo_write (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":501:0:501:5|Removing sequential instance clear_parity_en (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[4:0] (in view: work.miv_rv32_csr_gpr_state_reg_5s_1s_0s(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
|
||||
@N: BN115 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":2594:4:2594:30|Removing instance u_csr_gpr_state_reg_frm_frm (in view: work.miv_rv32_csr_privarch_Z15(verilog)) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10461:2:10461:7|Removing sequential instance sel_reg[1:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":579:9:579:14|Removing sequential instance genblk8\.afull_r (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6376:4:6376:9|Removing sequential instance q2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":5705:4:5705:9|Removing sequential instance gen_bit_reset\.state_val[2:0] (in view: work.miv_rv32_csr_gpr_state_reg_3s_1s_0s_1(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":6361:2:6361:7|Removing sequential instance paddr_p (in view: work.miv_rv32_subsys_apb_initiator_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_valid_reg (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[0\]\.buff_data\[0\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|Removing sequential instance gen_buff_loop\[1\]\.buff_data\[1\][5:0] (in view: work.miv_rv32_buffer_7s_2s_1s_1s(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6370:4:6370:9|Removing sequential instance mem_xf_2[31:0] (in view: work.miv_rv32_gpr_ram_array_32s_6s_32s(verilog)) of type view:PrimLib.ram1(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":6097:2:6097:7|Removing sequential instance gpr_rs3_rd_sel_reg[5:0] (in view: work.miv_rv32_gpr_ram_0s_0_0s_32s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\corefifo_c0\corefifo_c0_0\rtl\vlog\core\corefifo_sync_scntr.v":438:3:438:8|Removing sequential instance genblk6\.almostemptyi (in view: work.COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr_Z3(verilog)) of type view:PrimLib.dffse(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16308:7:16308:15|Removing sequential instance genblk3\.shift_active_high\.shift_active_low\.dr_tdo (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9775:2:9775:7|Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":630:0:630:5|Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
|
||||
@N: BN362 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":9245:6:9245:11|Removing sequential instance gen_gpr_ex_attbs_rd_ex\.gen_debug_gpr_rd_sel_pipeline\.de_ex_pipe_gpr_rs3_rd_sel_ex[5:0] (in view: work.miv_rv32_expipe_Z16(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.
|
||||
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top
|
||||
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
|
||||
@N: BN225 |Writing default property annotation file E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.sap.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core\rx_async.v":286:0:286:5|There are no possible illegal states for state machine rx_state[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v":45:4:45:9|There are no possible illegal states for state machine state[1:0] (in view: work.fifo_to_tpsram_bridge(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":16135:12:16135:20|There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_debug_dtm_jtag_1s(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":15192:0:15192:8|There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_debug_sba(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corecdr4_cntl_tip\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v":117:0:117:5|There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required.
|
||||
@N: MO225 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\coredelaycode_tip\2.1.100\rtl\vlog\core\coredelaycode_tip.v":59:0:59:5|There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required.
|
||||
6
synthesis/synlog/report/top_premap_opt_report.xml
Normal file
6
synthesis/synlog/report/top_premap_opt_report.xml
Normal file
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
The file contains the optimization information from mapper to be displayed as part of the summary report.
|
||||
*******************************************************************************************-->
|
||||
<report_table display_priority="3" name="Optimizations Summary"></report_table>
|
||||
46
synthesis/synlog/report/top_premap_runstatus.xml
Normal file
46
synthesis/synlog/report/top_premap_runstatus.xml
Normal file
@@ -0,0 +1,46 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!-- *************************************************************************************
|
||||
FILE DESCRIPTION
|
||||
The file contains the job information from mapper to be displayed as part of the summary report.
|
||||
*******************************************************************************************-->
|
||||
<job_run_status name="Mapper">
|
||||
<report_link name="Detailed report">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_premap.srr</data>
|
||||
<title></title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
<data>Completed</data>
|
||||
</job_status>
|
||||
<job_info>
|
||||
<info name="Notes">
|
||||
<data>65</data>
|
||||
<report_link name="more">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_notes.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>15</data>
|
||||
<report_link name="more">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_warnings.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
<data>0</data>
|
||||
<report_link name="more">
|
||||
<data>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\report\top_premap_errors.txt</data>
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="CPU Time">
|
||||
<data>0h:00m:13s</data>
|
||||
</info>
|
||||
<info name="Real Time">
|
||||
<data>0h:00m:13s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>365MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1776273488</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
15
synthesis/synlog/report/top_premap_warnings.txt
Normal file
15
synthesis/synlog/report/top_premap_warnings.txt
Normal file
@@ -0,0 +1,15 @@
|
||||
@W: FX1183 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\core_reset_pf\core_reset_pf_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_addr_req[0][31:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[2].buff_entry_addr_req[2][31:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\hart_merged\miv_rv32_hart_merged.v":18726:4:18726:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_hart_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[1].buff_entry_addr_req[1][31:0] is being ignored due to limitations in architecture.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: BN132 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":14495:2:14495:10|Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.gen_subsys_debug.u_subsys_debug_unit_0.miv_rv32_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[1].buff_data[1][5:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_i_trx_os_buffer.gen_buff_loop[0].buff_data[0][5:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[1].buff_data[1][10:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_d_trx_os_buffer.gen_buff_loop[0].buff_data[0][10:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[1].buff_data[1][6:0] is being ignored due to limitations in architecture.
|
||||
@W: FX1172 :"e:\abhishekv\rising\ethernet_tpsram_test\component\microsemi\miv\miv_rv32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v":10047:4:10047:9|User-specified initial value defined for instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_ipcore_0.u_subsys_interconnect_0.u_subsys_regs.u_req_buffer.gen_buff_loop[0].buff_data[0][6:0] is being ignored due to limitations in architecture.
|
||||
@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\work\pf_iod_cdr_c0\pf_iod_cdr_rx_n_0\pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v":48:53:48:59|Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_netprop which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance.
|
||||
@W: MT530 :"e:\abhishekv\rising\ethernet_tpsram_test\component\actel\directcore\corejtagdebug\4.0.100\core\corejtagdebug_uj_jtag.v":215:0:215:5|Found inferred clock COREJTAGDEBUG_Z5|iUDRCK_inferred_clock which controls 184 sequential elements including COREJTAGDEBUG_C0_0.COREJTAGDEBUG_C0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance.
|
||||
@W: MF511 |Found issues with constraints. Please check constraint checker report "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top_cck.rpt" .
|
||||
Reference in New Issue
Block a user