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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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smartgen/COREFIFO_C0_work.ixf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0</name><vendor/><library/><version/><fileSets/><hwModel><views/></hwModel><vendorExtension><componentID name="COREFIFO_C0::work"/></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtension><coreDefFile path="../component/work/COREFIFO_C0/COREFIFO_C0.cxf"/></vendorExtension><vendorExtension><dependentComponent/></vendorExtension><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RESET_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FULL</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>EMPTY</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Q</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>