abhishek/Ethernet-IP-Core
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

working FIFO and TPSRAM without packet flter

Browse Source
This commit is contained in:
abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
simulation/modelsim.ini Normal file
View File

@@ -0,0 +1,10 @@
[Library]
others = $MODEL_TECH/../modelsim.ini
PolarFire = E:/Microchip/Libero_SoC_2025.1/Libero_SoC/Designer/lib/modelsimpro/precompiled/vlog/polarfire
syncad_vhdl_lib = E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Designer/lib/actel/syncad_vhdl_lib
[vcom]
VHDL93 = 1
[vsim]
IterationLimit = 5000