working FIFO and TPSRAM without packet flter

hdl/SSDetect.v

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+///////////////////////////////////////////////////////////////////////////////////////////////////
+// Company: <Name>
+//
+// File: SSDetect.v
+// File history:
+//      <Revision number>: <Date>: <Comments>
+//      <Revision number>: <Date>: <Comments>
+//      <Revision number>: <Date>: <Comments>
+//
+// Description: 
+//
+// <Description here>
+//
+// Targeted device: <Family::PolarFire> <Die::MPF300TS> <Package::FCG1152>
+// Author: <Name>
+//
+/////////////////////////////////////////////////////////////////////////////////////////////////// 
+
+`timescale 1ns / 1ps 
+
+module SSDetect( rst_b, rck, rx_data, stream_start );
+input           rst_b;
+input           rck;
+input [9:0] rx_data;  // from RX_P
+output stream_start;
+
+function is_match (input [6:0] x, input [6:0] y);
+begin
+   is_match = (x == y) | (x == ~y);
+end
+endfunction
+
+reg [1:0] rx_start;
+
+assign stream_start = rx_start[0];  // CDR starts after RX data detects two consecutive non-static words
+
+always @(posedge rck or negedge rst_b) begin  // SAR 101393, use negedge clock
+   if (!rst_b) begin
+      rx_start <= 2'd0;
+   end
+   else if (!rx_start[0]) begin  // two consecutive non-static words
+      rx_start <= is_match(rx_data[6:0], 0) ? 2'd0 : {1'b1, rx_start[1]};
+   end
+end
+
+
+endmodule
+

hdl/fifo_to_tpsram_bridge.v

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+module fifo_to_tpsram_bridge #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 10  // 1024 depth
+)(
+    input  wire                   clk,
+    input  wire                   reset_n,
+
+    // CoreFIFO Interface (FWFT Mode)
+    input  wire [DATA_WIDTH-1:0]  fifo_data_out,
+    input  wire                   fifo_empty,
+    output reg                    fifo_rd_en,
+
+    // TPSRAM Port A Interface (Write Port)
+    output reg  [ADDR_WIDTH-1:0]  ram_w_addr,
+    output reg  [DATA_WIDTH-1:0]  ram_w_data,
+    output reg                    ram_w_en,
+
+    // Control/Status
+    input  wire                   transfer_enable,
+    output reg                    buffer_full
+);
+
+    // State Encoding
+    localparam IDLE  = 2'b00,
+               WRITE = 2'b01,
+               FULL  = 2'b10;
+
+    reg [1:0] state, next_state;
+
+    // Address Counter Logic
+    always @(posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+            ram_w_addr <= 0;
+            buffer_full <= 0;
+        end else if (ram_w_en) begin
+            if (ram_w_addr == {ADDR_WIDTH{1'b1}}) begin
+                buffer_full <= 1; // Memory is topped off
+            end else begin
+                ram_w_addr <= ram_w_addr + 1;
+            end
+        end
+    end
+
+    // FSM State Transitions
+    always @(posedge clk or negedge reset_n) begin
+        if (!reset_n) state <= IDLE;
+        else          state <= next_state;
+    end
+
+    // Next State Logic
+    always @(*) begin
+        next_state = state;
+        case (state)
+            IDLE: begin
+                // Start writing if FIFO has data and RAM isn't full
+                if (!fifo_empty && transfer_enable && !buffer_full)
+                    next_state = WRITE;
+            end
+            WRITE: begin
+                if (fifo_empty || buffer_full)
+                    next_state = IDLE;
+            end
+            default: next_state = IDLE;
+        endcase
+    end
+
+    // Output Logic
+    always @(*) begin
+        fifo_rd_en = 0;
+        ram_w_en   = 0;
+        ram_w_data = fifo_data_out;
+
+        if (state == WRITE && !fifo_empty && !buffer_full) begin
+            fifo_rd_en = 1;
+            ram_w_en   = 1;
+        end
+    end
+
+endmodule