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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
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designer/top/top_layout_combinational_loops.xml Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Combinational Loop Report</title>
<text>SmartTime Version 2025.1.0.14</text>
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
<text>Date: Wed Apr 15 22:53:22 2026
</text>
<table>
<header>
</header>
<row>
<cell>Design</cell>
<cell>top</cell>
</row>
<row>
<cell>Family</cell>
<cell>PolarFire</cell>
</row>
<row>
<cell>Die</cell>
<cell>MPF300TS</cell>
</row>
<row>
<cell>Package</cell>
<cell>FCG1152</cell>
</row>
<row>
<cell>Temperature Range</cell>
<cell>-40 - 100 C</cell>
</row>
<row>
<cell>Voltage Range</cell>
<cell>1.0185 - 1.0815 V</cell>
</row>
<row>
<cell>Speed Grade</cell>
<cell>-1</cell>
</row>
<row>
<cell>Design State</cell>
<cell>Pre-Layout</cell>
</row>
</table>
<text></text>
<text></text>
<text></text>
<text>No combinational loops were detected in the design.</text>
</doc>