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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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designer/top/run_tao_adl_vt.tcl Normal file
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set_device -family {PolarFire} -die {MPF300TS} -speed {-1}
read_adl {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top.adl}
read_afl {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top.afl}
map_netlist
read_sdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\top_derived_constraints.sdc}
read_sdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\timing_user_constraints.sdc}
check_constraints {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\timing_sdc_errors.log}
estimate_jitter -report {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\timing_analysis_jitter_report.txt}
write_sdc -mode smarttime {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\timing_analysis.sdc}