working FIFO and TPSRAM without packet flter
This commit is contained in:
39
designer/top/run_placer.def
Normal file
39
designer/top/run_placer.def
Normal file
@@ -0,0 +1,39 @@
|
||||
G5PLACER_32_64_BIT_EXT=64
|
||||
DESIGN=top
|
||||
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
FAM=PolarFire
|
||||
DIE=PA5M300TS
|
||||
PACKAGE=fcg1152
|
||||
SPEED=-1
|
||||
VOLTAGE=1.05
|
||||
TEMPR=IND
|
||||
VOLTR=IND
|
||||
VCCI_1.2_VOLTR=IND
|
||||
VCCI_1.5_VOLTR=IND
|
||||
VCCI_1.8_VOLTR=IND
|
||||
VCCI_2.5_VOLTR=IND
|
||||
VCCI_3.3_VOLTR=IND
|
||||
PDC_IMPORT_HARDERROR=1
|
||||
RGB_COUNT=18
|
||||
LAYOUT_MODE=TIMING_DRIVEN
|
||||
INCREMENTAL_MODE=OFF
|
||||
PA5GDEV_IOFF_COMBINING=0
|
||||
PA5_DO_TIMING_GB_DEMOTE=1
|
||||
LAYOUTG4_POST_DRIVER_DUPLICATION=0
|
||||
PA4_LAYOUT_HIGH_EFFORT_MODE=1
|
||||
PA5_LAYOUT_HIGH_EFFORT_MODE=1
|
||||
PDPR=0
|
||||
PA4_PHYS_OPT_MODE=0
|
||||
PA5_PHYS_OPT_MODE=0
|
||||
PA4_LAYOUT_SEQ_OPT_MODE=0
|
||||
PA5_LAYOUT_SEQ_OPT_MODE=0
|
||||
RANDOM_SEED=0
|
||||
NETLIST_TYPE=EDIF
|
||||
MINDELAYG4_REPAIR=1
|
||||
MINDELAYG5_REPAIR=1
|
||||
LAYOUT_STATE=NOT_VALID
|
||||
PDC_FILE=E:\AbhishekV\rising\ethernet_tpsram_test\constraint\io\io_constraints.pdc,,
|
||||
USE_CONSTRAINT_FLOW=1
|
||||
TARGET_DEVICES_FOR_MIGRATION='PA5M300TS '
|
||||
RESTRICTPROBEPINS=1
|
||||
RESTRICTSPIPINS=0
|
||||
Reference in New Issue
Block a user