abhishek/Ethernet-IP-Core
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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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designer/top/run_g5layout_dca.def Normal file
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DESIGN=top
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
FAM=PolarFire
DIE=PA5M300TS
PACKAGE=fcg1152
NETLIST_TYPE=EDIF
SYSTEM_CONTROLLER_SUSPEND_MODE=0
DEV_MEM_INIT_FIRST_STAGE_MEMORY_TYPE=SNVM
DEV_MEM_INIT_FIRST_STAGE_START_ADDRESS=000000CA
DEV_MEM_INIT_SPI_CLOCK_DIVIDER=2
DEV_MEM_INIT_TIMEOUT=255