working FIFO and TPSRAM without packet flter
This commit is contained in:
BIN
designer/top/COMPILE/top.afl
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designer/top/COMPILE/top.afl
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designer/top/COMPILE/top.design.afl
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designer/top/COMPILE/top.design.afl
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designer/top/COMPILE/top.design.loc
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designer/top/COMPILE/top.design.loc
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designer/top/COMPILE/top.design.seg
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designer/top/COMPILE/top.design.seg
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designer/top/COMPILE/top.loc
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designer/top/COMPILE/top.loc
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designer/top/COMPILE/top.seg
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designer/top/COMPILE/top.seg
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79918
designer/top/Design_Initialization_Data_Report.html
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79918
designer/top/Design_Initialization_Data_Report.html
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19704
designer/top/Design_Initialization_Data_Report.txt
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19704
designer/top/Design_Initialization_Data_Report.txt
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80651
designer/top/Design_Initialization_Data_Report.xml
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80651
designer/top/Design_Initialization_Data_Report.xml
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12
designer/top/RAM.cfg
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12
designer/top/RAM.cfg
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@@ -0,0 +1,12 @@
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modified_client \
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-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0} \
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-storage_type {SNVM} \
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-content_type {MEMORY_FILE} \
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-memory_file_format {Intel-Hex} \
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-memory_file {iog_cdr.hex}
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modified_client \
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-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0} \
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-storage_type {SNVM} \
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-content_type {MEMORY_FILE} \
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-memory_file_format {Intel-Hex} \
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-memory_file {iog_cdr.hex}
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23
designer/top/SNVM.cfg
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23
designer/top/SNVM.cfg
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@@ -0,0 +1,23 @@
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set_plain_text_client \
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-client_name {INIT_STAGE_1_SNVM_CLIENT} \
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-number_of_bytes 4384 \
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-content_type {MEMORY_FILE} \
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-content_file_format {Microsemi Binary 32-bit} \
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-content_file {designer\top\top_init_stage_1_snvm.mem} \
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-mem_file_base_address {0x00000000} \
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-start_page 202 \
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-use_for_simulation 0 \
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-reprogram 1 \
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-use_as_rom 1
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set_plain_text_client \
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-client_name {INIT_STAGE_2_3_SNVM_CLIENT} \
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-number_of_bytes 20616 \
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-content_type {MEMORY_FILE} \
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-content_file_format {Microsemi Binary 32-bit} \
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-content_file {designer\top\top_init_stage_2_3_snvm.mem} \
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-mem_file_base_address {0x00000000} \
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-start_page 0 \
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-use_for_simulation 0 \
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-reprogram 1 \
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-use_as_rom 1
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set_init_smk 0
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9216
designer/top/block_4.shx
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9216
designer/top/block_4.shx
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File diff suppressed because it is too large
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9216
designer/top/block_5.shx
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9216
designer/top/block_5.shx
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41
designer/top/cdc_synchronizer.csv
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41
designer/top/cdc_synchronizer.csv
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@@ -0,0 +1,41 @@
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Synchronizer SLE From,Synchronizer SLE To,Manhattan Cluster Distance
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/I1101_inst_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I0111_inst_2,0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/I0111_inst_2,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/loo01,0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.OOoIo[0],0
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/IIoIo.ii1Io[0],0
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||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.OOoIo[0],0
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||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/IIoIo.ii1Io[0],0
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||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Oool1_inst_1,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/oo0I1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/l01l1,0
|
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CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.OOoIo[0],0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/IIoIo.ii1Io[0],0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.OOoIo[0],1
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/IIoIo.ii1Io[0],1
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Io111_inst_2,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrfn_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrmc_1,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/oo111_inst_1,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Ii111,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrfn_1,1
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/lo111,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srrmc_1,1
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/io111,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtfn_1,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oo111,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/srtmc_1,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/iO111,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo,1
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/I1IIo,CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/l1IIo,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.OOoIo[0],0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.IOoIo[0],CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/IIoIo.ii1Io[0],1
|
||||
|
11
designer/top/clocklist.txt
Normal file
11
designer/top/clocklist.txt
Normal file
@@ -0,0 +1,11 @@
|
||||
"PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0",,"PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0","PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0"
|
||||
"PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK",,"PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK","PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK"
|
||||
"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0",,"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0","PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0"
|
||||
"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT1",,"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT1","PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT1"
|
||||
"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT2",,"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT2","PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT2"
|
||||
"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT3",,"PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT3","PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT3"
|
||||
"PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV",,"PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV","PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV"
|
||||
"PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q",,"PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q","PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q"
|
||||
"REFCLK_P",,"REFCLK_P","REFCLK_P"
|
||||
"REF_CLK_0",,"REF_CLK_0","REF_CLK_0"
|
||||
"TCK",,"TCK","TCK"
|
||||
1
designer/top/coverage_placeandroute
Normal file
1
designer/top/coverage_placeandroute
Normal file
@@ -0,0 +1 @@
|
||||
99.78%
|
||||
BIN
designer/top/export/top.job
Normal file
BIN
designer/top/export/top.job
Normal file
Binary file not shown.
185188
designer/top/export/top.stp
Normal file
185188
designer/top/export/top.stp
Normal file
File diff suppressed because it is too large
Load Diff
6
designer/top/export/top_job.digest
Normal file
6
designer/top/export/top_job.digest
Normal file
@@ -0,0 +1,6 @@
|
||||
Design name: top
|
||||
Checksum: 37B6
|
||||
Design version: 0
|
||||
Fabric component bitstream digest: c5715cda16a1298e3e85782534624d1c1f19f90bd47ae0021529d0ff5a7e1755
|
||||
sNVM component bitstream digest: 18e79bb157a48aea95e005784407d6839f90bad6354cb597deebaddeaa4cc0fc
|
||||
Entire bitstream digest: 86ed5db7c7172a77f8171eaa9ea5627427fa148f0c5cb64eaad5db36de49122a
|
||||
6
designer/top/export/top_stp.digest
Normal file
6
designer/top/export/top_stp.digest
Normal file
@@ -0,0 +1,6 @@
|
||||
Design name: top
|
||||
Checksum: 37B6
|
||||
Design version: 0
|
||||
Fabric component bitstream digest: c5715cda16a1298e3e85782534624d1c1f19f90bd47ae0021529d0ff5a7e1755
|
||||
sNVM component bitstream digest: 18e79bb157a48aea95e005784407d6839f90bad6354cb597deebaddeaa4cc0fc
|
||||
Entire bitstream digest: 86ed5db7c7172a77f8171eaa9ea5627427fa148f0c5cb64eaad5db36de49122a
|
||||
5539
designer/top/io_pcbit_info.ddf
Normal file
5539
designer/top/io_pcbit_info.ddf
Normal file
File diff suppressed because it is too large
Load Diff
49
designer/top/options.txt
Normal file
49
designer/top/options.txt
Normal file
@@ -0,0 +1,49 @@
|
||||
ANALYSIS_BOTTLENECK_COST_TYPE,Path Count
|
||||
ANALYSIS_BREAK_AT_ASYNC,1
|
||||
ANALYSIS_CLOCKLIST_SORT_CRITERIA,NAME
|
||||
ANALYSIS_ENABLE_INTERDOMAINS,1
|
||||
ANALYSIS_ENHANCED_MIN_TIMING,0
|
||||
ANALYSIS_EXPAND_CLOCK_NETWORK,1
|
||||
ANALYSIS_INCLUDE_ASYNC_SETS,1
|
||||
ANALYSIS_LIMIT_PATHS,1
|
||||
ANALYSIS_MAX_BOTTLENECK_INSTANCES,10
|
||||
ANALYSIS_MAX_OPCOND,slow_lv_ht
|
||||
ANALYSIS_MAX_PARALLEL_PATHS,1
|
||||
ANALYSIS_MAX_PATHS,20
|
||||
ANALYSIS_MAX_SLACK,0
|
||||
ANALYSIS_MIN_OPCOND,slow_lv_ht
|
||||
ANALYSIS_MIN_SLACK,0
|
||||
ANALYSIS_USE_LOOPBACK,0
|
||||
ANALYSIS_USE_MAX_SLACK,0
|
||||
ANALYSIS_USE_MIN_SLACK,0
|
||||
ANALYSIS_USE_SLACK_THRESHOLD,0
|
||||
BOTTLENECK_REPORT_ANALYSIS_TYPE,1
|
||||
BOTTLENECK_REPORT_MAX_PARALLEL_PATHS,1
|
||||
BOTTLENECK_REPORT_MAX_PATHS,100
|
||||
BOTTLENECK_REPORT_SLACK_THRESHOLD,0
|
||||
IS_VIOLATION_REPORT,0
|
||||
MULTI_CORNER_REPORT_FLAG,0
|
||||
PATH_TRACING_ALGORITHM,1
|
||||
REPORT_ANALYSIS_TYPE,1
|
||||
REPORT_CLOCK_DOMAINS,PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0 PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT1 PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT2 PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT3 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q REFCLK_P REF_CLK_0 TCK
|
||||
REPORT_FORMAT,TEXT
|
||||
REPORT_MAX_EXPANDED_PATHS,1
|
||||
REPORT_MAX_PARALLEL_PATHS,1
|
||||
REPORT_MAX_PATHS,5
|
||||
REPORT_SHOW_CLOCK_DOMAINS,1
|
||||
REPORT_SHOW_INOUT_SETS,1
|
||||
REPORT_SHOW_PATHS,1
|
||||
REPORT_SHOW_SUMMARY,1
|
||||
REPORT_SHOW_USER_SETS,0
|
||||
REPORT_SLACK_THRESHOLD,0
|
||||
REPORT_USE_CLOCK_DOMAINS,0
|
||||
REPORT_USE_SLACK_THRESHOLD,0
|
||||
STATS_REPORT_NUMBER_DETAILS,100
|
||||
STATS_REPORT_SLACKS,0
|
||||
VIOLATION_REPORT_ANALYSIS_TYPE,1
|
||||
VIOLATION_REPORT_LIMIT_PATHS,1
|
||||
VIOLATION_REPORT_MAX_EXPANDED_PATHS,0
|
||||
VIOLATION_REPORT_MAX_PARALLEL_PATHS,1
|
||||
VIOLATION_REPORT_MAX_PATHS,20
|
||||
VIOLATION_REPORT_SLACK_THRESHOLD,0
|
||||
VIOLATION_REPORT_USE_SLACK_THRESHOLD,1
|
||||
130484
designer/top/pinslacks.txt
Normal file
130484
designer/top/pinslacks.txt
Normal file
File diff suppressed because it is too large
Load Diff
102
designer/top/place_and_route_jitter_report.txt
Normal file
102
designer/top/place_and_route_jitter_report.txt
Normal file
@@ -0,0 +1,102 @@
|
||||
Jitter Estimation Report
|
||||
========================
|
||||
|
||||
Date : Wed Apr 15 22:52:38 2026
|
||||
Libero version : 2025.1.0.14
|
||||
Design : top
|
||||
Family : PolarFire
|
||||
Die : MPF300TS
|
||||
Speed grade : -1
|
||||
Data state : Production
|
||||
All jitter values are peak-to-peak
|
||||
|
||||
|
||||
System Jitter Calculation
|
||||
-------------------------
|
||||
|
||||
Worst aggressor based on load: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0
|
||||
System jitter (worst aggressor): 0.005 ns
|
||||
|
||||
|
||||
Jitter Calculation per Clock Domain
|
||||
-----------------------------------
|
||||
|
||||
Clock: TCK
|
||||
|
||||
(1) System jitter (worst aggressor): 0.005 ns
|
||||
(2) Input jitter: 0.000 ns
|
||||
|
||||
Resulting clock jitter (max of (1) and (2)): 0.005 ns
|
||||
|
||||
|
||||
Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV
|
||||
|
||||
(1) System jitter (worst aggressor): 0.005 ns
|
||||
(2) Master Clock jitter: 0.005 ns
|
||||
|
||||
Resulting clock jitter (max of (1) and (2)): 0.005 ns
|
||||
|
||||
|
||||
Clock: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3
|
||||
|
||||
HS_IO_CLK jitter: 0.150 ns
|
||||
|
||||
Resulting clock jitter: 0.150 ns
|
||||
|
||||
|
||||
Clock: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1
|
||||
|
||||
HS_IO_CLK jitter: 0.150 ns
|
||||
|
||||
Resulting clock jitter: 0.150 ns
|
||||
|
||||
|
||||
Clock: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0
|
||||
|
||||
System jitter (worst aggressor): 0.005 ns
|
||||
Resulting clock jitter: 0.005 ns
|
||||
|
||||
|
||||
Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0
|
||||
|
||||
(1) System jitter (worst aggressor): 0.005 ns
|
||||
(2) PLL jitter: 0.135 ns
|
||||
|
||||
Resulting clock jitter (max of (1) and (2)): 0.135 ns
|
||||
|
||||
|
||||
Clock: REFCLK_P
|
||||
|
||||
(1) System jitter (worst aggressor): 0.005 ns
|
||||
(2) Input jitter: 0.000 ns
|
||||
|
||||
Resulting clock jitter (max of (1) and (2)): 0.005 ns
|
||||
|
||||
|
||||
Clock: PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2
|
||||
|
||||
System jitter (worst aggressor): 0.005 ns
|
||||
Resulting clock jitter: 0.005 ns
|
||||
|
||||
|
||||
Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R
|
||||
|
||||
Regional jitter: 0.001 ns
|
||||
|
||||
Resulting clock jitter: 0.001 ns
|
||||
|
||||
|
||||
Clock: PHY_MDC_CLOCK
|
||||
|
||||
System jitter (worst aggressor): 0.005 ns
|
||||
Resulting clock jitter: 0.005 ns
|
||||
|
||||
|
||||
Clock: REF_CLK_0
|
||||
|
||||
(1) System jitter (worst aggressor): 0.005 ns
|
||||
(2) Input jitter: 0.000 ns
|
||||
|
||||
Resulting clock jitter (max of (1) and (2)): 0.005 ns
|
||||
|
||||
|
||||
87
designer/top/place_route.sdc
Normal file
87
designer/top/place_route.sdc
Normal file
@@ -0,0 +1,87 @@
|
||||
# Microchip Technology Inc.
|
||||
# Date: 2026-Apr-15 22:52:43
|
||||
# This file was generated based on the following SDC source files:
|
||||
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/top_derived_constraints.sdc
|
||||
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/timing_user_constraints.sdc
|
||||
#
|
||||
|
||||
create_clock -name {REF_CLK_0} -period 20 [ get_ports { REF_CLK_0 } ]
|
||||
create_clock -name {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R} -period 8 -waveform {0 3.2 } [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
create_clock -name {REFCLK_P} -period 8 [ get_ports { REFCLK_P } ]
|
||||
create_clock -name {TCK} -period 100 -waveform {0 50 } [ get_ports { TCK } ]
|
||||
create_generated_clock -name {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0} -multiply_by 8 -divide_by 5 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 90 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 180 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 270 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/A } ] [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
create_generated_clock -name {PHY_MDC_CLOCK} -divide_by 28 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -phase 0 [ get_ports { PHY_MDC } ]
|
||||
set_input_delay 0 -min -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
|
||||
set_input_delay 20 -max -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
|
||||
set_input_delay 0 -min -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_input_delay 20 -max -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay 10 -max -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay -10 -min -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/RESET } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK_PAUSE } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/SWITCH } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code*[*] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -from [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK* } ] -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_false_path -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CDR_CLK } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/dll_inst_0/CODE_UPDATE } ]
|
||||
set_false_path -from [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane* } ]
|
||||
set_clock_uncertainty 0.135 [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -rise_to [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -fall_to [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_uncertainty 0.000992228 [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -rise_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ] -fall_to [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_uncertainty 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -rise_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ] -fall_to [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { PHY_MDC_CLOCK } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { PHY_MDC_CLOCK } ] -rise_to [ get_clocks { PHY_MDC_CLOCK } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { PHY_MDC_CLOCK } ] -fall_to [ get_clocks { PHY_MDC_CLOCK } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { REFCLK_P } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REFCLK_P } ] -rise_to [ get_clocks { REFCLK_P } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REFCLK_P } ] -fall_to [ get_clocks { REFCLK_P } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { REF_CLK_0 } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { REF_CLK_0 } ] -rise_to [ get_clocks { REF_CLK_0 } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { REF_CLK_0 } ] -fall_to [ get_clocks { REF_CLK_0 } ]
|
||||
set_clock_uncertainty 0.00483062 [ get_clocks { TCK } ]
|
||||
set_clock_uncertainty -hold 0 -rise_from [ get_clocks { TCK } ] -rise_to [ get_clocks { TCK } ]
|
||||
set_clock_uncertainty -hold 0 -fall_from [ get_clocks { TCK } ] -fall_to [ get_clocks { TCK } ]
|
||||
set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_groups -name {Y_DIV_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT0_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT1_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT2_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT3_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_groups -name {PF_CCC_0_OUT0_GRP} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {JTAG_Async} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -group [ get_clocks { TCK } ]
|
||||
104
designer/top/rptstyle.xsl
Normal file
104
designer/top/rptstyle.xsl
Normal file
@@ -0,0 +1,104 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<xsl:stylesheet version="1.0" xmlns:xsl="http://www.w3.org/1999/XSL/Transform">
|
||||
<xsl:output method="html"/>
|
||||
|
||||
<xsl:template match="/">
|
||||
<html>
|
||||
<head>
|
||||
<style>
|
||||
body { font-family:arial; font-size:10pt; text-align:left; }
|
||||
h1, h2 {
|
||||
padding-top: 30px;
|
||||
}
|
||||
h3 {
|
||||
padding-top: 20px;
|
||||
}
|
||||
h4, h5, h6 {
|
||||
padding-top: 10px;
|
||||
font-size:12pt;
|
||||
}
|
||||
table {
|
||||
font-family:arial; font-size:10pt; text-align:left;
|
||||
border-color:#B0B0B0;
|
||||
border-style:solid;
|
||||
border-width:1px;
|
||||
border-collapse:collapse;
|
||||
}
|
||||
table th, table td {
|
||||
font-family:arial; font-size:10pt; text-align:left;
|
||||
border-color:#B0B0B0;
|
||||
border-style:solid;
|
||||
border-width:1px;
|
||||
padding: 4px;
|
||||
}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<xsl:apply-templates/>
|
||||
</body></html>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/doc/title">
|
||||
<h1 align="center"> <xsl:apply-templates/> </h1>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="text">
|
||||
<p> <xsl:apply-templates/> </p>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/doc/section">
|
||||
<h2> <xsl:apply-templates select="name"/> </h2>
|
||||
<xsl:apply-templates select="table|text|list|section"/>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/doc/section/section">
|
||||
<h3> <xsl:apply-templates select="name"/> </h3>
|
||||
<xsl:apply-templates select="table|text|list|section"/>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/doc/section/section/section">
|
||||
<h4> <xsl:apply-templates select="name"/> </h4>
|
||||
<xsl:apply-templates select="table|text|list|section"/>
|
||||
</xsl:template>
|
||||
<xsl:template match="/doc/section/section/section/section">
|
||||
<h5> <xsl:apply-templates select="name"/> </h5>
|
||||
<xsl:apply-templates select="table|text|list|section"/>
|
||||
</xsl:template>
|
||||
<xsl:template match="/doc/section/section/section/section/section">
|
||||
<h6> <xsl:apply-templates select="name"/> </h6>
|
||||
<xsl:apply-templates select="table|text|list"/>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="section/name">
|
||||
<xsl:apply-templates/>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="table">
|
||||
<table cellpadding="4"> <xsl:apply-templates/> </table>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="header">
|
||||
<tr> <xsl:apply-templates/> </tr>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="header/cell">
|
||||
<th> <xsl:apply-templates/> </th>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="row">
|
||||
<tr> <xsl:apply-templates/> </tr>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="row/cell">
|
||||
<td> <xsl:apply-templates/> </td>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="list">
|
||||
<ul> <xsl:apply-templates/> </ul>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="item">
|
||||
<li> <xsl:apply-templates/> </li>
|
||||
</xsl:template>
|
||||
|
||||
</xsl:stylesheet>
|
||||
73
designer/top/run_compile.tcl
Normal file
73
designer/top/run_compile.tcl
Normal file
@@ -0,0 +1,73 @@
|
||||
set_defvar -name {SPEED} -value {-1}
|
||||
set_defvar -name {VOLTAGE} -value {1.05}
|
||||
set_defvar -name {TEMPR} -value {IND}
|
||||
set_defvar -name {PART_RANGE} -value {IND}
|
||||
set_defvar -name {IO_DEFT_STD} -value {LVCMOS18}
|
||||
set_defvar -name {PACOMP_PARPT_MAX_NET} -value {10}
|
||||
set_defvar -name {PA4_GB_MAX_RCLKINT_INSERTION} -value {16}
|
||||
set_defvar -name {PA4_GB_MIN_GB_FANOUT_TO_USE_RCLKINT} -value {1000}
|
||||
set_defvar -name {PA4_GB_MAX_FANOUT_DATA_MOVE} -value {5000}
|
||||
set_defvar -name {PA4_GB_HIGH_FANOUT_THRESHOLD} -value {5000}
|
||||
set_defvar -name {PA4_GB_COUNT} -value {24}
|
||||
set_defvar -name {RESTRICTPROBEPINS} -value {0}
|
||||
set_defvar -name {RESTRICTSPIPINS} -value {0}
|
||||
set_defvar -name {PDC_IMPORT_HARDERROR} -value {1}
|
||||
set_defvar -name {PA4_IDDQ_FF_FIX} -value {1}
|
||||
set_defvar -name {BLOCK_PLACEMENT_CONFLICTS} -value {ERROR}
|
||||
set_defvar -name {BLOCK_ROUTING_CONFLICTS} -value {LOCK}
|
||||
set_defvar -name {RTG4_MITIGATION_ON} -value {0}
|
||||
set_defvar -name {USE_CONSTRAINT_FLOW} -value True
|
||||
set_defvar -name {FHB_AUTO_INSTANTIATION} -value {0}
|
||||
set_defvar -name {SYSTEM_CONTROLLER_SUSPEND_MODE} -value {0}
|
||||
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Family"} \
|
||||
-value {"PolarFire"}
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Device"} \
|
||||
-value {"MPF300TS"}
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Package"} \
|
||||
-value {"FCG1152"}
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Speed Grade"} \
|
||||
-value {"-1"}
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Core Voltage"} \
|
||||
-value {"1.05V"}
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Part Range"} \
|
||||
-value {"IND"}
|
||||
set_compile_info \
|
||||
-category {"Device Selection"} \
|
||||
-name {"Default I/O technology"} \
|
||||
-value {"LVCMOS 1.8V"}
|
||||
set_compile_info \
|
||||
-category {"Source Files"} \
|
||||
-name {"Topcell"} \
|
||||
-value {"top"}
|
||||
set_compile_info \
|
||||
-category {"Source Files"} \
|
||||
-name {"Format"} \
|
||||
-value {"Verilog"}
|
||||
set_compile_info \
|
||||
-category {"Source Files"} \
|
||||
-name {"Source"} \
|
||||
-value {"E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm"}
|
||||
set_compile_info \
|
||||
-category {"Options"} \
|
||||
-name {"Limit the number of high fanout nets to display to"} \
|
||||
-value {"10"}
|
||||
compile \
|
||||
-desdir {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top} \
|
||||
-design top \
|
||||
-fam PolarFire \
|
||||
-die PA5M300TS \
|
||||
-pkg fcg1152 \
|
||||
-merge_pdc 0
|
||||
11
designer/top/run_g5layout_dca.def
Normal file
11
designer/top/run_g5layout_dca.def
Normal file
@@ -0,0 +1,11 @@
|
||||
DESIGN=top
|
||||
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
FAM=PolarFire
|
||||
DIE=PA5M300TS
|
||||
PACKAGE=fcg1152
|
||||
NETLIST_TYPE=EDIF
|
||||
SYSTEM_CONTROLLER_SUSPEND_MODE=0
|
||||
DEV_MEM_INIT_FIRST_STAGE_MEMORY_TYPE=SNVM
|
||||
DEV_MEM_INIT_FIRST_STAGE_START_ADDRESS=000000CA
|
||||
DEV_MEM_INIT_SPI_CLOCK_DIVIDER=2
|
||||
DEV_MEM_INIT_TIMEOUT=255
|
||||
30
designer/top/run_generate_uic.tcl
Normal file
30
designer/top/run_generate_uic.tcl
Normal file
@@ -0,0 +1,30 @@
|
||||
set_device \
|
||||
-fam PolarFire \
|
||||
-die PA5M300TS \
|
||||
-pkg fcg1152
|
||||
set_proj_dir \
|
||||
-path {E:\AbhishekV\rising\ethernet_tpsram_test}
|
||||
set_impl_dir \
|
||||
-path {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top}
|
||||
set_is_relative_path \
|
||||
-value {FALSE}
|
||||
set_root_path_dir \
|
||||
-path {}
|
||||
set_first_stage \
|
||||
-address 00000000
|
||||
set_second_stage \
|
||||
-uprom_address 00000000 \
|
||||
-snvm_address 00000000 \
|
||||
-spi_address 00000400 \
|
||||
-spi_binding spi_noauth \
|
||||
-ramBroadcast 1 \
|
||||
-standalone_initialization 0 \
|
||||
-spi_ClockDivider 2
|
||||
set_override_file \
|
||||
-path {}
|
||||
set_auto_calib_timeout \
|
||||
-value {3000}
|
||||
defvar_set -name PA5_PRINT_DEVICE_SELECTION_INIT_DATA_FILE -value 1
|
||||
defvar_set -name RESTRICTPROBEPINS -value 1
|
||||
defvar_set -name SYSTEM_CONTROLLER_SUSPEND_MODE -value 0
|
||||
defvar_set -name FHB_FLOW -value 0
|
||||
23
designer/top/run_mapper.def
Normal file
23
designer/top/run_mapper.def
Normal file
@@ -0,0 +1,23 @@
|
||||
DESIGN=top
|
||||
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
FAM=PolarFire
|
||||
DIE=PA5M300TS
|
||||
PACKAGE=fcg1152
|
||||
SPEED=-1
|
||||
VOLTAGE=1.05
|
||||
TEMPR=IND
|
||||
VOLTR=IND
|
||||
VCCI_1.2_VOLTR=IND
|
||||
VCCI_1.5_VOLTR=IND
|
||||
VCCI_1.8_VOLTR=IND
|
||||
VCCI_2.5_VOLTR=IND
|
||||
VCCI_3.3_VOLTR=IND
|
||||
RESTRICTPROBEPINS=1
|
||||
RESTRICTSPIPINS=0
|
||||
DSW_VCCA_VOLTAGE_RAMP_RATE=
|
||||
PLL_SUPPLY=
|
||||
SYSTEM_CONTROLLER_SUSPEND_MODE=0
|
||||
INIT_LOCK_FILE=
|
||||
CONFIGURATION_OVERRIDE_FILE=
|
||||
MSVT_EXPORT_DATA=0
|
||||
NETLIST_TYPE=EDIF
|
||||
12
designer/top/run_pa5snvmgen.tcl
Normal file
12
designer/top/run_pa5snvmgen.tcl
Normal file
@@ -0,0 +1,12 @@
|
||||
set_device \
|
||||
-fam PolarFire \
|
||||
-die PA5M300TS \
|
||||
-pkg fcg1152
|
||||
set_input_cfg \
|
||||
-path {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\SNVM.cfg}
|
||||
set_output_efc \
|
||||
-path {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_snvm.efc}
|
||||
set_is_relative_path \
|
||||
-value {FALSE}
|
||||
set_root_path_dir \
|
||||
-path {}
|
||||
11
designer/top/run_pinrpt.tcl
Normal file
11
designer/top/run_pinrpt.tcl
Normal file
@@ -0,0 +1,11 @@
|
||||
DESIGN=top
|
||||
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
TARGET_DIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
FAM=PolarFire
|
||||
DIE=PA5M300TS
|
||||
PACKAGE=fcg1152
|
||||
PINRPT_BY_NAME=1
|
||||
PINRPT_BY_NUMBER=1
|
||||
PINRPT_BOARDLAYOUT=1
|
||||
BANK_REPORT=1
|
||||
IOREG_REPORT=1
|
||||
39
designer/top/run_placer.def
Normal file
39
designer/top/run_placer.def
Normal file
@@ -0,0 +1,39 @@
|
||||
G5PLACER_32_64_BIT_EXT=64
|
||||
DESIGN=top
|
||||
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
FAM=PolarFire
|
||||
DIE=PA5M300TS
|
||||
PACKAGE=fcg1152
|
||||
SPEED=-1
|
||||
VOLTAGE=1.05
|
||||
TEMPR=IND
|
||||
VOLTR=IND
|
||||
VCCI_1.2_VOLTR=IND
|
||||
VCCI_1.5_VOLTR=IND
|
||||
VCCI_1.8_VOLTR=IND
|
||||
VCCI_2.5_VOLTR=IND
|
||||
VCCI_3.3_VOLTR=IND
|
||||
PDC_IMPORT_HARDERROR=1
|
||||
RGB_COUNT=18
|
||||
LAYOUT_MODE=TIMING_DRIVEN
|
||||
INCREMENTAL_MODE=OFF
|
||||
PA5GDEV_IOFF_COMBINING=0
|
||||
PA5_DO_TIMING_GB_DEMOTE=1
|
||||
LAYOUTG4_POST_DRIVER_DUPLICATION=0
|
||||
PA4_LAYOUT_HIGH_EFFORT_MODE=1
|
||||
PA5_LAYOUT_HIGH_EFFORT_MODE=1
|
||||
PDPR=0
|
||||
PA4_PHYS_OPT_MODE=0
|
||||
PA5_PHYS_OPT_MODE=0
|
||||
PA4_LAYOUT_SEQ_OPT_MODE=0
|
||||
PA5_LAYOUT_SEQ_OPT_MODE=0
|
||||
RANDOM_SEED=0
|
||||
NETLIST_TYPE=EDIF
|
||||
MINDELAYG4_REPAIR=1
|
||||
MINDELAYG5_REPAIR=1
|
||||
LAYOUT_STATE=NOT_VALID
|
||||
PDC_FILE=E:\AbhishekV\rising\ethernet_tpsram_test\constraint\io\io_constraints.pdc,,
|
||||
USE_CONSTRAINT_FLOW=1
|
||||
TARGET_DEVICES_FOR_MIGRATION='PA5M300TS '
|
||||
RESTRICTPROBEPINS=1
|
||||
RESTRICTSPIPINS=0
|
||||
15
designer/top/run_placer_st_shell_cmd.tcl
Normal file
15
designer/top/run_placer_st_shell_cmd.tcl
Normal file
@@ -0,0 +1,15 @@
|
||||
read_sdc -scenario "place_and_route" -netlist "optimized" -pin_separator "/" -ignore_errors {E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/place_route.sdc}
|
||||
set_options -tdpr_scenario "place_and_route"
|
||||
save
|
||||
set_options -analysis_scenario "place_and_route"
|
||||
report -type combinational_loops -format xml {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_layout_combinational_loops.xml}
|
||||
report -type slack {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\pinslacks.txt}
|
||||
set coverage [report \
|
||||
-type constraints_coverage \
|
||||
-format xml \
|
||||
-slacks no \
|
||||
{E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_place_and_route_constraint_coverage.xml}]
|
||||
set reportfile {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\coverage_placeandroute}
|
||||
set fp [open $reportfile w]
|
||||
puts $fp $coverage
|
||||
close $fp
|
||||
20
designer/top/run_placer_st_shell_des.tcl
Normal file
20
designer/top/run_placer_st_shell_des.tcl
Normal file
@@ -0,0 +1,20 @@
|
||||
set_device \
|
||||
-family PolarFire \
|
||||
-die PA5M300TS \
|
||||
-package fcg1152 \
|
||||
-speed -1 \
|
||||
-tempr {IND} \
|
||||
-voltr {IND}
|
||||
set_def {VOLTAGE} {1.05}
|
||||
set_def {VCCI_1.2_VOLTR} {IND}
|
||||
set_def {VCCI_1.5_VOLTR} {IND}
|
||||
set_def {VCCI_1.8_VOLTR} {IND}
|
||||
set_def {VCCI_2.5_VOLTR} {IND}
|
||||
set_def {VCCI_3.3_VOLTR} {IND}
|
||||
set_def {RTG4_MITIGATION_ON} {0}
|
||||
set_def USE_CONSTRAINTS_FLOW 1
|
||||
set_def NETLIST_TYPE EDIF
|
||||
set_name top
|
||||
set_workdir {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top}
|
||||
set_log {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_sdc.log}
|
||||
set_design_state pre_layout
|
||||
9
designer/top/run_prober.tcl
Normal file
9
designer/top/run_prober.tcl
Normal file
@@ -0,0 +1,9 @@
|
||||
probe \
|
||||
-desdir {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top} \
|
||||
-design top \
|
||||
-fam PolarFire \
|
||||
-die PA5M300TS \
|
||||
-pkg fcg1152 \
|
||||
-speed -1 \
|
||||
-use_mvn_pdc 0 \
|
||||
-use_last_placement 0
|
||||
24
designer/top/run_router.def
Normal file
24
designer/top/run_router.def
Normal file
@@ -0,0 +1,24 @@
|
||||
G5ROUTER_32_64_BIT_EXT=64
|
||||
DESIGN=top
|
||||
DESDIR=E:\AbhishekV\rising\ethernet_tpsram_test\designer\top
|
||||
FAM=PolarFire
|
||||
DIE=PA5M300TS
|
||||
PACKAGE=fcg1152
|
||||
SPEED=-1
|
||||
VOLTAGE=1.05
|
||||
TEMPR=IND
|
||||
VOLTR=IND
|
||||
VCCI_1.2_VOLTR=IND
|
||||
VCCI_1.5_VOLTR=IND
|
||||
VCCI_1.8_VOLTR=IND
|
||||
VCCI_2.5_VOLTR=IND
|
||||
VCCI_3.3_VOLTR=IND
|
||||
LAYOUT_MODE=TIMING_DRIVEN
|
||||
INCREMENTAL_MODE=OFF
|
||||
LAYOUTG4_POST_DRIVER_DUPLICATION=0
|
||||
PA4_LAYOUT_HIGH_EFFORT_MODE=1
|
||||
PA5_LAYOUT_HIGH_EFFORT_MODE=1
|
||||
MINDELAYG4_REPAIR=1
|
||||
MINDELAYG5_REPAIR=1
|
||||
NETLIST_TYPE=EDIF
|
||||
LAYOUT_STATE=NOT_VALID
|
||||
77
designer/top/run_tao.tcl
Normal file
77
designer/top/run_tao.tcl
Normal file
@@ -0,0 +1,77 @@
|
||||
set_device -family {PolarFire} -die {MPF300TS} -speed {-1}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREFIFO_C0\COREFIFO_C0.v}
|
||||
read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v}
|
||||
read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v}
|
||||
read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v}
|
||||
read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v}
|
||||
read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORESPI_0\CORESPI_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CORETSE_0\CORETSE_0.v}
|
||||
read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v}
|
||||
read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
|
||||
read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreAPB3_0\CoreAPB3_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\CoreUARTapb_0\CoreUARTapb_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\Core_reset_pf\Core_reset_pf.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\MIV_RV32_C0\MIV_RV32_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_CCC_0\PF_CCC_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\hdl\SSDetect.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\hdl\fifo_to_tpsram_bridge.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\pf_init_monitor_0\pf_init_monitor_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_tpsram_test\component\work\top\top.v}
|
||||
set_top_level {top}
|
||||
map_netlist
|
||||
read_sdc {E:\AbhishekV\rising\ethernet_tpsram_test\constraint\top_derived_constraints.sdc}
|
||||
read_sdc {E:\AbhishekV\rising\ethernet_tpsram_test\constraint\timing_user_constraints.sdc}
|
||||
check_constraints {E:\AbhishekV\rising\ethernet_tpsram_test\constraint\synthesis_sdc_errors.log}
|
||||
write_fdc {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\synthesis.fdc}
|
||||
9
designer/top/run_tao_adl.tcl
Normal file
9
designer/top/run_tao_adl.tcl
Normal file
@@ -0,0 +1,9 @@
|
||||
set_device -family {PolarFire} -die {MPF300TS} -speed {-1}
|
||||
read_adl {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.adl}
|
||||
read_afl {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.afl}
|
||||
map_netlist
|
||||
read_sdc {E:\AbhishekV\rising\ethernet_tpsram_test\constraint\top_derived_constraints.sdc}
|
||||
read_sdc {E:\AbhishekV\rising\ethernet_tpsram_test\constraint\timing_user_constraints.sdc}
|
||||
check_constraints {E:\AbhishekV\rising\ethernet_tpsram_test\constraint\placer_sdc_errors.log}
|
||||
estimate_jitter -report {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\place_and_route_jitter_report.txt}
|
||||
write_sdc -mode layout {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\place_route.sdc}
|
||||
9
designer/top/run_tao_adl_vt.tcl
Normal file
9
designer/top/run_tao_adl_vt.tcl
Normal file
@@ -0,0 +1,9 @@
|
||||
set_device -family {PolarFire} -die {MPF300TS} -speed {-1}
|
||||
read_adl {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top.adl}
|
||||
read_afl {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top.afl}
|
||||
map_netlist
|
||||
read_sdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\top_derived_constraints.sdc}
|
||||
read_sdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\timing_user_constraints.sdc}
|
||||
check_constraints {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\timing_sdc_errors.log}
|
||||
estimate_jitter -report {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\timing_analysis_jitter_report.txt}
|
||||
write_sdc -mode smarttime {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\timing_analysis.sdc}
|
||||
209
designer/top/run_timrpt_st_shell_cmd.tcl
Normal file
209
designer/top/run_timrpt_st_shell_cmd.tcl
Normal file
@@ -0,0 +1,209 @@
|
||||
read_sdc -scenario "timing_analysis" -netlist "optimized" -pin_separator "/" -ignore_errors {E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/designer/top/timing_analysis.sdc}
|
||||
set_options -analysis_scenario "timing_analysis"
|
||||
save
|
||||
set has_violations {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_has_violations}
|
||||
set fp [open $has_violations w]
|
||||
set coverage [report \
|
||||
-type constraints_coverage \
|
||||
-format xml \
|
||||
-slacks no \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_timing_constraints_coverage.xml} ]
|
||||
puts $fp "_timing_constraints_coverage $coverage"
|
||||
report \
|
||||
-type combinational_loops \
|
||||
-format xml \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_timing_combinational_loops.xml}
|
||||
report_timing \
|
||||
-delay_type max \
|
||||
-max_paths 1000 \
|
||||
-file \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\max_report.json}
|
||||
report_timing \
|
||||
-delay_type min \
|
||||
-max_paths 1000 \
|
||||
-file \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\min_report.json}
|
||||
set_options -max_opcond slow_lv_lt -min_opcond slow_lv_lt
|
||||
set max_timing_violations_slow_lv_lt [report \
|
||||
-type timing_violations \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_violations_slow_lv_lt.xml} ]
|
||||
puts $fp "_max_timing_violations_slow_lv_lt $max_timing_violations_slow_lv_lt"
|
||||
set max_timing_slow_lv_lt [report \
|
||||
-type timing \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_slow_lv_lt.xml} ]
|
||||
puts $fp "_max_timing_slow_lv_lt $max_timing_slow_lv_lt"
|
||||
set min_timing_violations_slow_lv_lt [report \
|
||||
-type timing_violations \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_violations_slow_lv_lt.xml} ]
|
||||
puts $fp "_min_timing_violations_slow_lv_lt $min_timing_violations_slow_lv_lt"
|
||||
set min_timing_slow_lv_lt [report \
|
||||
-type timing \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_slow_lv_lt.xml} ]
|
||||
puts $fp "_min_timing_slow_lv_lt $min_timing_slow_lv_lt"
|
||||
set_options -max_opcond fast_hv_lt -min_opcond fast_hv_lt
|
||||
set max_timing_violations_fast_hv_lt [report \
|
||||
-type timing_violations \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_violations_fast_hv_lt.xml} ]
|
||||
puts $fp "_max_timing_violations_fast_hv_lt $max_timing_violations_fast_hv_lt"
|
||||
set max_timing_fast_hv_lt [report \
|
||||
-type timing \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_fast_hv_lt.xml} ]
|
||||
puts $fp "_max_timing_fast_hv_lt $max_timing_fast_hv_lt"
|
||||
set min_timing_violations_fast_hv_lt [report \
|
||||
-type timing_violations \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_violations_fast_hv_lt.xml} ]
|
||||
puts $fp "_min_timing_violations_fast_hv_lt $min_timing_violations_fast_hv_lt"
|
||||
set min_timing_fast_hv_lt [report \
|
||||
-type timing \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_fast_hv_lt.xml} ]
|
||||
puts $fp "_min_timing_fast_hv_lt $min_timing_fast_hv_lt"
|
||||
set_options -max_opcond slow_lv_ht -min_opcond slow_lv_ht
|
||||
set max_timing_violations_slow_lv_ht [report \
|
||||
-type timing_violations \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_violations_slow_lv_ht.xml} ]
|
||||
puts $fp "_max_timing_violations_slow_lv_ht $max_timing_violations_slow_lv_ht"
|
||||
set max_timing_slow_lv_ht [report \
|
||||
-type timing \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_slow_lv_ht.xml} ]
|
||||
puts $fp "_max_timing_slow_lv_ht $max_timing_slow_lv_ht"
|
||||
set min_timing_violations_slow_lv_ht [report \
|
||||
-type timing_violations \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_violations_slow_lv_ht.xml} ]
|
||||
puts $fp "_min_timing_violations_slow_lv_ht $min_timing_violations_slow_lv_ht"
|
||||
set min_timing_slow_lv_ht [report \
|
||||
-type timing \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_slow_lv_ht.xml} ]
|
||||
puts $fp "_min_timing_slow_lv_ht $min_timing_slow_lv_ht"
|
||||
set max_timing_violations_multi_corner [report \
|
||||
-type timing_violations \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-multi_corner yes \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_violations_multi_corner.xml} ]
|
||||
puts $fp "_max_timing_violations_multi_corner $max_timing_violations_multi_corner"
|
||||
set max_timing_multi_corner [report \
|
||||
-type timing \
|
||||
-analysis max \
|
||||
-format xml \
|
||||
-multi_corner yes \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_max_timing_multi_corner.xml} ]
|
||||
puts $fp "_max_timing_multi_corner $max_timing_multi_corner"
|
||||
set min_timing_violations_multi_corner [report \
|
||||
-type timing_violations \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-multi_corner yes \
|
||||
-use_slack_threshold yes \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 20 \
|
||||
-max_expanded_paths 0 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_violations_multi_corner.xml} ]
|
||||
puts $fp "_min_timing_violations_multi_corner $min_timing_violations_multi_corner"
|
||||
set min_timing_multi_corner [report \
|
||||
-type timing \
|
||||
-analysis min \
|
||||
-format xml \
|
||||
-multi_corner yes \
|
||||
-use_slack_threshold no \
|
||||
-slack_threshold 0.0 \
|
||||
-max_paths 5 \
|
||||
-max_expanded_paths 1 \
|
||||
-max_parallel_paths 1 \
|
||||
{E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_min_timing_multi_corner.xml} ]
|
||||
puts $fp "_min_timing_multi_corner $min_timing_multi_corner"
|
||||
close $fp
|
||||
20
designer/top/run_timrpt_st_shell_des.tcl
Normal file
20
designer/top/run_timrpt_st_shell_des.tcl
Normal file
@@ -0,0 +1,20 @@
|
||||
set_device \
|
||||
-family PolarFire \
|
||||
-die PA5M300TS \
|
||||
-package fcg1152 \
|
||||
-speed -1 \
|
||||
-tempr {IND} \
|
||||
-voltr {IND}
|
||||
set_def {VOLTAGE} {1.05}
|
||||
set_def {VCCI_1.2_VOLTR} {IND}
|
||||
set_def {VCCI_1.5_VOLTR} {IND}
|
||||
set_def {VCCI_1.8_VOLTR} {IND}
|
||||
set_def {VCCI_2.5_VOLTR} {IND}
|
||||
set_def {VCCI_3.3_VOLTR} {IND}
|
||||
set_def USE_CONSTRAINTS_FLOW 1
|
||||
set_name top
|
||||
set_workdir {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top}
|
||||
set_design_state post_layout
|
||||
set_operating_conditions -name slow_lv_lt
|
||||
set_operating_conditions -name fast_hv_lt
|
||||
set_operating_conditions -name slow_lv_ht
|
||||
54
designer/top/synthesis.fdc
Normal file
54
designer/top/synthesis.fdc
Normal file
@@ -0,0 +1,54 @@
|
||||
# Microchip Technology Inc.
|
||||
# Date: 2026-Apr-15 22:44:52
|
||||
# This file was generated based on the following SDC source files:
|
||||
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/top_derived_constraints.sdc
|
||||
# E:/AbhishekV/rising/ethernet_tpsram_test/constraint/timing_user_constraints.sdc
|
||||
#
|
||||
|
||||
create_clock -name {REF_CLK_0} -period 20 [ get_ports { REF_CLK_0 } ]
|
||||
create_clock -name {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R} -period 8 -waveform {0 3.2 } [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R } ]
|
||||
create_clock -name {REFCLK_P} -period 8 [ get_ports { REFCLK_P } ]
|
||||
create_clock -name {TCK} -period 100 -waveform {0 50 } [ get_ports { TCK } ]
|
||||
create_generated_clock -name {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0} -multiply_by 8 -divide_by 5 -source [ get_pins { PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 } ] [ get_pins { PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 } ] [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 } ] [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT1 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 } ] [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT2 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 } ] [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT3 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.A } ] [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.Y_DIV } ]
|
||||
create_generated_clock -name {PHY_MDC_CLOCK} -divide_by 28 -source [ get_pins { PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0 } ] [ get_ports { PHY_MDC } ]
|
||||
set_input_delay 0 -min -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
|
||||
set_input_delay 20 -max -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
|
||||
set_input_delay 0 -min -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_input_delay 20 -max -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay 10 -max -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay -10 -min -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.dll_90_code*[*] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST } ]
|
||||
set_false_path -from [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* } ] -through [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R } ]
|
||||
set_false_path -through [ get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE } ]
|
||||
set_false_path -from [ get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.move_lane* } ]
|
||||
set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_groups -name {Y_DIV_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT0_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT1_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT2_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT3_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_groups -name {PF_CCC_0_OUT0_GRP} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {JTAG_Async} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -group [ get_clocks { TCK } ]
|
||||
65
designer/top/timing_analysis.sdc
Normal file
65
designer/top/timing_analysis.sdc
Normal file
@@ -0,0 +1,65 @@
|
||||
# Microchip Technology Inc.
|
||||
# Date: 2026-Apr-13 22:06:32
|
||||
# This file was generated based on the following SDC source files:
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/constraint/top_derived_constraints.sdc
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/constraint/timing_user_constraints.sdc
|
||||
#
|
||||
|
||||
create_clock -name {REF_CLK_0} -period 20 [ get_ports { REF_CLK_0 } ]
|
||||
create_clock -name {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R} -period 8 -waveform {0 3.2 } [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
create_clock -name {REFCLK_P} -period 8 [ get_ports { REFCLK_P } ]
|
||||
create_clock -name {TCK} -period 100 -waveform {0 50 } [ get_ports { TCK } ]
|
||||
create_generated_clock -name {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0} -multiply_by 8 -divide_by 5 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 90 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 180 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 270 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/A } ] [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
create_generated_clock -name {PHY_MDC_CLOCK} -divide_by 28 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -phase 0 [ get_ports { PHY_MDC } ]
|
||||
set_input_delay 0 -min -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
|
||||
set_input_delay 20 -max -add_delay -clock { REF_CLK_0 } [ get_ports { RESET_N } ]
|
||||
set_input_delay 0 -min -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_input_delay 20 -max -add_delay -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay 10 -max -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay -10 -min -clock { PHY_MDC_CLOCK } [ get_ports { PHY_MDIO } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/RESET } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK_PAUSE } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/SWITCH } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code*[*] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -from [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK* } ] -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_false_path -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CDR_CLK } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/dll_inst_0/CODE_UPDATE } ]
|
||||
set_false_path -from [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane* } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { TCK } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_jitter 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_jitter 0.15 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_jitter 0.135 [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { REFCLK_P } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_jitter 0.000992228 [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { PHY_MDC_CLOCK } ]
|
||||
set_clock_jitter 0.00457968 [ get_clocks { REF_CLK_0 } ]
|
||||
set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_groups -name {Y_DIV_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT0_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT1_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT2_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT3_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
set_clock_groups -name {PF_CCC_0_OUT0_GRP} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {JTAG_Async} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -group [ get_clocks { TCK } ]
|
||||
BIN
designer/top/top.adl
Normal file
BIN
designer/top/top.adl
Normal file
Binary file not shown.
BIN
designer/top/top.afl
Normal file
BIN
designer/top/top.afl
Normal file
Binary file not shown.
BIN
designer/top/top.cfrt
Normal file
BIN
designer/top/top.cfrt
Normal file
Binary file not shown.
1
designer/top/top.dca
Normal file
1
designer/top/top.dca
Normal file
@@ -0,0 +1 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><dca xmlns="http://actel.com/sweng/afi"><format name="Design Configuration and Access" version="01.00"/><creator name="Libero" version="2025.1.0.14"/><date>Wednesday April 15 23:10:53 2026</date><project_name>top</project_name><family>PolarFire</family><device>MPF300TS</device><package>FCG1152</package><fabric_configuration><avionics_mode>0</avionics_mode><enable_uathena>1</enable_uathena><ff_clock_gate_delay>000</ff_clock_gate_delay></fabric_configuration><uic><uic_addr>000000ca</uic_addr><uic_type>3</uic_type><uic_script_timeout>fe</uic_script_timeout><uic_spiclk_div>1</uic_spiclk_div></uic></dca>
|
||||
BIN
designer/top/top.ddc
Normal file
BIN
designer/top/top.ddc
Normal file
Binary file not shown.
1
designer/top/top.hdr
Normal file
1
designer/top/top.hdr
Normal file
File diff suppressed because one or more lines are too long
BIN
designer/top/top.loc
Normal file
BIN
designer/top/top.loc
Normal file
Binary file not shown.
BIN
designer/top/top.map
Normal file
BIN
designer/top/top.map
Normal file
Binary file not shown.
58
designer/top/top.mvn.pdc
Normal file
58
designer/top/top.mvn.pdc
Normal file
@@ -0,0 +1,58 @@
|
||||
# Microchip Physical design constraints file
|
||||
|
||||
# Version: 2025.1 2025.1.0.14
|
||||
|
||||
# Design Name:
|
||||
|
||||
# Input Netlist Format: EDIF
|
||||
|
||||
# Family: PolarFire , Die: MPF300TS , Package: FCG1152 , Speed grade: -1
|
||||
|
||||
# Date generated: Wed Apr 15 22:52:34 2026
|
||||
|
||||
|
||||
#
|
||||
# IO banks setting
|
||||
#
|
||||
|
||||
set_iobank -bank_name Bank3 -vcci 3.30 -fixed true
|
||||
|
||||
#
|
||||
# Region constraints
|
||||
#
|
||||
|
||||
|
||||
#
|
||||
# I/O constraints
|
||||
#
|
||||
|
||||
set_io -port_name TCK -DIRECTION INPUT -pin_name J10
|
||||
set_io -port_name TDI -DIRECTION INPUT -pin_name K11
|
||||
set_io -port_name TDO -DIRECTION OUTPUT -pin_name K9
|
||||
set_io -port_name TMS -DIRECTION INPUT -pin_name J9
|
||||
set_io -port_name TRSTB -DIRECTION INPUT -pin_name N14
|
||||
|
||||
#
|
||||
# Ports using Dedicated Pins
|
||||
#
|
||||
|
||||
set_io -port_name TCK \
|
||||
-pin_name J10 \
|
||||
-DIRECTION INPUT
|
||||
set_io -port_name TDI \
|
||||
-pin_name K11 \
|
||||
-DIRECTION INPUT
|
||||
set_io -port_name TDO \
|
||||
-pin_name K9 \
|
||||
-DIRECTION OUTPUT
|
||||
set_io -port_name TMS \
|
||||
-pin_name J9 \
|
||||
-DIRECTION INPUT
|
||||
set_io -port_name TRSTB \
|
||||
-pin_name N14 \
|
||||
-DIRECTION INPUT
|
||||
|
||||
#
|
||||
# Core cell constraints
|
||||
#
|
||||
|
||||
23107
designer/top/top.nmatinit.pdc
Normal file
23107
designer/top/top.nmatinit.pdc
Normal file
File diff suppressed because it is too large
Load Diff
23107
designer/top/top.nmatinit.txt
Normal file
23107
designer/top/top.nmatinit.txt
Normal file
File diff suppressed because it is too large
Load Diff
BIN
designer/top/top.ppd
Normal file
BIN
designer/top/top.ppd
Normal file
Binary file not shown.
BIN
designer/top/top.seg
Normal file
BIN
designer/top/top.seg
Normal file
Binary file not shown.
BIN
designer/top/top.smat.seg
Normal file
BIN
designer/top/top.smat.seg
Normal file
Binary file not shown.
1
designer/top/top.spm
Normal file
1
designer/top/top.spm
Normal file
@@ -0,0 +1 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><SecurityPolicyManager xmlns="http://actel.com/sweng/afi"><security_key_mode>default</security_key_mode></SecurityPolicyManager>
|
||||
40
designer/top/top_RAM.cfg
Normal file
40
designer/top/top_RAM.cfg
Normal file
@@ -0,0 +1,40 @@
|
||||
set_client \
|
||||
-logical_instance_name {COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[15:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[15:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
set_client \
|
||||
-logical_instance_name {MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data[6:0]} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {INFERRED_INITIALIZED}
|
||||
set_client \
|
||||
-logical_instance_name {PF_TPSRAM_C0_0/PF_TPSRAM_C0_0} \
|
||||
-storage_type {SNVM} \
|
||||
-content_type {NO_CONTENT}
|
||||
10
designer/top/top_RAM_definition.txt
Normal file
10
designer/top/top_RAM_definition.txt
Normal file
@@ -0,0 +1,10 @@
|
||||
logical_instance_name-COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe Physical_names-[COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1/INST_RAM1K20_IP@@COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-32 Port_B_Depth-1024 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0
|
||||
logical_instance_name-CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[15:0] Physical_names-[CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-17 Port_B_Depth-32 Port_B_Width-17 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
|
||||
logical_instance_name-CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[15:0] Physical_names-[CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-17 Port_B_Depth-32 Port_B_Width-17 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
|
||||
logical_instance_name-CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io[35:0] Physical_names-[CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_6/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_5/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_7/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_1/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_3/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_2/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_4/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/oi0Io_oi0Io_0_0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-4096 Port_A_Width-36 Port_B_Depth-4096 Port_B_Width-36 RAM_type-0 RAM_Port_type-1 Memory_Source-3 ECC-0
|
||||
logical_instance_name-CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io[39:0] Physical_names-[CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_1/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_3/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_0/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/oi0Io_oi0Io_0_2/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-2048 Port_A_Width-40 Port_B_Depth-2048 Port_B_Width-40 RAM_type-0 RAM_Port_type-1 Memory_Source-3 ECC-0
|
||||
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0 Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0/INST_RAM1K20_IP@@] Cascade_type-Depth Port_A_Depth-9216 Port_A_Width-32 Port_B_Depth-9216 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0
|
||||
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
|
||||
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
|
||||
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data[6:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-2 Port_A_Width-6 Port_B_Depth-2 Port_B_Width-6 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0
|
||||
logical_instance_name-PF_TPSRAM_C0_0/PF_TPSRAM_C0_0 Physical_names-[PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM_R0C1/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-32 Port_B_Depth-1024 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0
|
||||
1
designer/top/top_SD_DFE.txt
Normal file
1
designer/top/top_SD_DFE.txt
Normal file
@@ -0,0 +1 @@
|
||||
// UIC OVERRIDE FILE GENERATED BY OPTIMIZING DFE
|
||||
71
designer/top/top_bankrpt.rpt
Normal file
71
designer/top/top_bankrpt.rpt
Normal file
@@ -0,0 +1,71 @@
|
||||
********************************************************************
|
||||
I/O Bank Report - Date: Wed Apr 15 23:06:21 2026
|
||||
Product: Designer
|
||||
Release: 2025.1
|
||||
Version: 2025.1.0.14
|
||||
Design Name: top
|
||||
Family: PolarFire
|
||||
Die: MPF300TS
|
||||
Package: FCG1152
|
||||
********************************************************************
|
||||
|
||||
|
||||
I/O Function:
|
||||
|
||||
Type | w/o register | w/ register | w/ DDR register
|
||||
--------------------------------------|---------------|--------------|----------------
|
||||
Input I/O | 4 | 0 | 0
|
||||
Output I/O | 42 | 0 | 0
|
||||
Bidirectional I/O | 1 | 0 | 0
|
||||
Differential Input I/O Pairs | 2 | 0 | 0
|
||||
Differential Output I/O Pairs | 1 | 0 | 0
|
||||
|
||||
I/O Technology:
|
||||
|
||||
| Voltages | I/Os
|
||||
--------------------------------|-------|-------|-------|--------|--------------
|
||||
I/O Standard(s) | Vddi | Vref | Input | Output | Bidirectional
|
||||
--------------------------------|-------|-------|-------|--------|--------------
|
||||
LVCMOS18 | 1.80v | N/A | 4 | 38 | 0
|
||||
LVCMOS25 | 2.50v | N/A | 0 | 4 | 1
|
||||
LVDS25 | 2.50v | N/A | 4 | 2 | 0
|
||||
|
||||
I/O Bank Resource Usage:
|
||||
|
||||
| Voltages | Single I/Os | Diff I/O Pairs | Vref I/Os | Type
|
||||
|-------|-------|------|-------|-------|--------|------|-------|----------|---------
|
||||
| Vddi | Vref | Used | Total | Used | Total | Used | Total | Vref Pins|
|
||||
------|-------|-------|------|-------|-------|--------|------|-------|----------|---------
|
||||
Bank0 | 1.80v | N/A | 32 | 72 | 0 | 36 | N/A | N/A | N/A | HSIO
|
||||
Bank1 | N/A | N/A | 0 | 60 | 0 | 30 | N/A | N/A | N/A | HSIO
|
||||
Bank2 | N/A | N/A | 0 | 96 | 0 | 48 | N/A | N/A | N/A | GPIO
|
||||
Bank3 | 3.30v | N/A | 0 | 0 | 0 | 0 | N/A | N/A | N/A | JTAG
|
||||
Bank4 | 2.50v | N/A | 5 | 92 | 3 | 46 | N/A | N/A | N/A | GPIO
|
||||
Bank5 | N/A | N/A | 0 | 48 | 0 | 24 | N/A | N/A | N/A | GPIO
|
||||
Bank6 | 1.80v | N/A | 10 | 72 | 0 | 36 | N/A | N/A | N/A | HSIO
|
||||
Bank7 | N/A | N/A | 0 | 72 | 0 | 36 | N/A | N/A | N/A | HSIO
|
||||
|
||||
|
||||
I/O Voltage Usage:
|
||||
|
||||
Voltages | I/Os
|
||||
-------|-------|------|-------
|
||||
Vddi | Vref | Used | Total
|
||||
-------|-------|------|-------
|
||||
1.80v | N/A | 42 | 144
|
||||
2.50v | N/A | 11 | 92
|
||||
3.30v | N/A | 0 | 0
|
||||
|
||||
|
||||
I/O Bank Auto Calibration:
|
||||
|
||||
| Auto Calibration | Ramp Time (ms)
|
||||
------| ---------------- | --------------
|
||||
Bank0 | ON | 50
|
||||
Bank1 | N/A | N/A
|
||||
Bank2 | N/A | N/A
|
||||
Bank3 | N/A | N/A
|
||||
Bank4 | ON | 50
|
||||
Bank5 | N/A | N/A
|
||||
Bank6 | ON | 50
|
||||
Bank7 | N/A | N/A
|
||||
8
designer/top/top_compile_ioff.rpt
Normal file
8
designer/top/top_compile_ioff.rpt
Normal file
@@ -0,0 +1,8 @@
|
||||
I/O Register Combining Report
|
||||
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
|
||||
Date: Wed Apr 15 22:52:30 2026
|
||||
|
||||
I/O Register Combining Summary
|
||||
+
|
||||
+
|
||||
|
||||
13
designer/top/top_compile_ioff.xml
Normal file
13
designer/top/top_compile_ioff.xml
Normal file
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
|
||||
<doc>
|
||||
<title>I/O Register Combining Report</title>
|
||||
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
|
||||
<text>Date: Wed Apr 15 22:52:30 2026
|
||||
</text>
|
||||
<section><name>I/O Register Combining Summary</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
</table>
|
||||
</doc>
|
||||
30
designer/top/top_compile_netlist.log
Normal file
30
designer/top/top_compile_netlist.log
Normal file
@@ -0,0 +1,30 @@
|
||||
Info: [127205813]: CMPPF_149: Added 'ADLIB:ICB_CLKINT' instance type before pin 'PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3:A'.
|
||||
|
||||
Info: [127205813]: CMPPF_149: Added 'ADLIB:ICB_CLKINT' instance type before pin 'PF_CCC_0_0/PF_CCC_0_0/clkint_0:A'.
|
||||
|
||||
Info: [127205813]: CMPPF_149: Added 'ADLIB:ICB_CLKINT' instance type before pin 'COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864:A'.
|
||||
|
||||
|
||||
|
||||
===============================================================================.
|
||||
|
||||
|
||||
|
||||
Info: Global design data:
|
||||
|
||||
Total globals: 4
|
||||
|
||||
Globals that cannot be demoted: 3
|
||||
|
||||
Globals considered for demotion: 1
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Info: List of globals that cannot be demoted:
|
||||
|
||||
CLK ASYN DATA Instance Name
|
||||
|
||||
--- ---- ---- -------------
|
||||
|
||||
221
designer/top/top_compile_netlist_hier_resources.csv
Normal file
221
designer/top/top_compile_netlist_hier_resources.csv
Normal file
@@ -0,0 +1,221 @@
|
||||
Detailed Resource Usage
|
||||
Module Name,Fabric 4LUT,Fabric DFF,Interface 4LUT,Interface DFF,Single-Ended I/O,Differential I/O Pairs,uSRAM (64x12),LSRAM (20K),Chip Globals,Row Global,PLL,DLL
|
||||
COREFIFO_C0_0/COREFIFO_C0_0/Primitives,35,35,0,0,0,0,0,0,0,0,0,0
|
||||
COREFIFO_C0_0/COREFIFO_C0_0/genblk16.fifo_corefifo_sync_scntr/Primitives,76,45,0,0,0,0,0,0,0,0,0,0
|
||||
COREFIFO_C0_0/COREFIFO_C0_0/genblk17.u_corefifo_fwft/Primitives,38,68,0,0,0,0,0,0,0,0,0,0
|
||||
COREFIFO_C0_0/COREFIFO_C0_0/genblk22.UI_ram_wrapper_1/L3_syncnonpipe/Primitives,0,0,72,72,0,0,0,2,0,0,0,0
|
||||
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/Primitives,40,0,0,0,0,0,0,0,2,0,0,0
|
||||
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk2.genblk2[0].BUFD_TRST/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
|
||||
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TDI/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
|
||||
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/Primitives,34,0,0,0,0,0,0,0,0,0,0,0
|
||||
COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/Primitives,114,17,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/UCC/Primitives,203,168,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/UCC/UCLKMUX1/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/UCON/Primitives,14,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/URF/Primitives,84,43,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/URXF/Primitives,35,18,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/Primitives,37,18,0,0,0,0,0,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/Primitives,0,14,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/Primitives,0,20,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXI_1/Primitives,195,208,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_CNVRXO_1/Primitives,22,18,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/CTSE_PEANX_SYNC_1/Primitives,2,60,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_MSGMII_PEANX_TOP_1/Primitives,262,171,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Ooio1/Primitives,164,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/Primitives,264,121,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PCS_1/loio1/Primitives,152,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PEREX_PMA_1/Primitives,307,103,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETBM_1/Primitives,181,124,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/Primitives,1,5,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/OolOo/Primitives,116,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/I0I11/Primitives,133,97,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/Primitives,1,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxi_1/Primitives,108,108,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/msgmii_convtxo_1/Primitives,20,24,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/Primitives,12,6,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_rx_sb_cnt_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/pclk_tx_sb_cnt_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/rx_ecc_cnt_rd_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tdbedc_carry_sync_1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tsbecc_carry_sync_1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/ecc_feature/tx_ecc_cnt_rd_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.rx4096x36_1/Primitives,0,0,288,288,0,0,0,8,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/lOIO1.tx2048x40_1/Primitives,0,0,144,144,0,0,0,4,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/II0I1.si_sal_U0/Primitives,115,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/Primitives,422,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_CNTRL_0/Primitives,121,65,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/Primitives,589,51,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_07/Primitives,53,25,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LADD_24/Primitives,52,25,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_00/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_01/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_02/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_03/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_04/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_05/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_06/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_08/Primitives,40,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_10/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_11/Primitives,41,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_25/Primitives,40,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_26/Primitives,40,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_LINC_27/Primitives,40,19,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SADD_35/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_29/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_30/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_31/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_32/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_33/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCHD_34/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_38/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_39/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_40/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_41/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_42/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_SINCNF_43/Primitives,27,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_09/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_12/Primitives,29,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_13/Primitives,29,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_14/Primitives,29,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_15/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_16/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_17/Primitives,29,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_18/Primitives,29,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_19/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_20/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_21/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_22/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_23/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_STORE_1/CTSE_PEMSTAT_sinc_28/Primitives,28,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U0/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/O1oIo.CTSE_SIB_SYNC_2FLP_u1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.sib_sync_pulse_U1/Primitives,2,2,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/Primitives,0,10,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_HST_1/Primitives,68,266,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_FAB_1/Primitives,209,238,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXRFIF_SYS_1/Primitives,251,303,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_FAB_1/Primitives,147,152,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_SYS_1/Primitives,211,198,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXTFIF_WTM_1/Primitives,116,90,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/OIiI1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/lIiI1/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/I11O1/Primitives,171,230,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/Primitives,4,1,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/apb_hst_cnv/l01O1/Primitives,82,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/lilI1.mmcxwol_U0/Primitives,93,52,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Primitives,5,13,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEHST_1/Primitives,71,222,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/Primitives,195,104,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/CTSE_PECRC_1/Primitives,78,32,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERFN_TOP_1/Primitives,416,191,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PERMC_TOP_1/Primitives,200,117,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/CTSE_PECRC_1/Primitives,163,32,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETFN_TOP_1/Primitives,527,292,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/CTSE_PETMC_TOP_1/Primitives,150,36,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PE_MCXMAC_CORE_1/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/Primitives,16,0,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/woldtctd_sync_U0/Primitives,0,3,0,0,0,0,0,0,0,0,0,0
|
||||
CORETSE_0_inst_0/CORETSE_0_0/i.OI/Primitives,125,104,0,0,0,0,0,0,0,0,0,0
|
||||
CoreAPB3_0_0/CoreAPB3_0_0/Primitives,4,0,0,0,0,0,0,0,0,0,0,0
|
||||
CoreAPB3_0_0/CoreAPB3_0_0/u_mux_p_to_b3/Primitives,11,0,0,0,0,0,0,0,0,0,0,0
|
||||
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/Primitives,27,24,0,0,0,0,0,0,0,0,0,0
|
||||
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/Primitives,6,9,0,0,0,0,0,0,0,0,0,0
|
||||
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_CLOCK_GEN/Primitives,24,19,0,0,0,0,0,0,0,0,0,0
|
||||
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_RX/Primitives,67,41,0,0,0,0,0,0,0,0,0,0
|
||||
CoreUARTapb_0_inst_0/CoreUARTapb_0_0/uUART/make_TX/Primitives,28,21,0,0,0,0,0,0,0,0,0,0
|
||||
Core_reset_pf_0/Core_reset_pf_0/Primitives,2,16,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/Primitives,35,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/Primitives,154,111,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_apb.u_apb_initiator_0/u_apb_req_arb/Primitives,17,4,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_mtime.u_mtime_irq/Primitives,416,176,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/MIV_subsys_debug_transport_module_jtag_0/Primitives,206,109,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_req_fifo/Primitives,53,96,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/debug_resp_fifo/Primitives,45,80,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/Primitives,68,213,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_subsys_debug.u_subsys_debug_unit_0/miv_rv32_debug_du_0/miv_rv32_debug_sba_0/Primitives,710,166,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/Primitives,0,55,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/tcm_ram_macro.u_ram_0/Primitives,1402,0,648,648,0,0,0,18,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/Primitives,66,3,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/gen_tcm0.u_subsys_TCM_0/u_TCM_req_arb/gen_pri_arb[0].u_miv_rv32_fixed_arb/Primitives,81,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/Primitives,98,283,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/Primitives,36,20,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/Primitives,4,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_1_mem_xf_1_0_2/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_1/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_xf_mem_xf_0_2/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_bcu_0/Primitives,139,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/Primitives,73,8,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_cause/Primitives,5,3,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_ebreakm/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_step/Primitives,373,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stepie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stopcount/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dcsr_stoptime/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_debug.u_csr_gpr_state_reg_dpc_pc/Primitives,66,32,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[0].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_ext_sys_irq[1].gen_ext_sys_irq_bit.u_csr_gpr_state_reg_ie_mextsysie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base/Primitives,1,30,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_execute/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata1_mcontrol_hit/Primitives,3,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[0].u_tdata2_match_data/Primitives,34,32,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data/Primitives,0,31,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_meie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_msie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_ie_mtie/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_excpt_code/Primitives,8,5,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mcause_interrupt/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mepc_epc/Primitives,32,31,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mscratch_scratch/Primitives,0,32,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_mtval_tval/Primitives,33,32,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mie/Primitives,4,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_csr_gpr_state_reg_status_mpie/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_csr_decode_0/Primitives,66,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/Primitives,11,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_sw/Primitives,3,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_csr_privarch_0/u_miv_rv32_priv_irq_0/u_miv_rv32_irq_reg_timer/Primitives,9,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_exu_0/Primitives,2023,202,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_idecode_0/Primitives,1043,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_expipe_0/u_miv_rv32_csr_decode_de_0/Primitives,38,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/Primitives,270,5,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/Primitives,213,215,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_hart_0/u_lsu_0/Primitives,202,22,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/Primitives,313,0,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_d_trx_os_buffer/Primitives,19,29,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_i_trx_os_buffer/Primitives,13,17,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/Primitives,12,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/Primitives,13,5,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_req_buffer/gen_buff_loop[0].buff_data_gen_buff_loop[0].buff_data_0_0/Primitives,0,0,12,12,0,0,1,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_gpr_ded_reset_reg/Primitives,1,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_irq_reg/Primitives,0,1,0,0,0,0,0,0,0,0,0,0
|
||||
MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/u_subsys_interconnect_0/u_subsys_regs/u_subsys_hart_soft_reset_reg/Primitives,2,1,0,0,0,0,0,0,0,0,0,0
|
||||
PF_CCC_0_0/PF_CCC_0_0/Primitives,0,0,0,0,0,0,0,0,1,0,1,0
|
||||
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/Primitives,226,59,0,0,0,0,0,0,0,0,0,0
|
||||
PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/Primitives,0,0,0,0,0,1,0,0,0,0,0,0
|
||||
PF_IOD_CDR_C0_0/PF_LANECTRL_0/Primitives,1,0,0,0,0,0,0,0,0,0,0,0
|
||||
PF_IOD_CDR_C0_0/Primitives,0,0,0,0,0,1,0,0,0,1,0,0
|
||||
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/Primitives,0,0,0,0,0,0,0,0,0,0,1,1
|
||||
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/Primitives,0,0,0,0,0,0,0,0,1,0,0,0
|
||||
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/Primitives,30,31,0,0,0,0,0,0,0,0,0,0
|
||||
PF_TPSRAM_C0_0/PF_TPSRAM_C0_0/Primitives,0,0,72,72,0,0,0,2,0,0,0,0
|
||||
Primitives/Primitives,3,0,0,0,47,1,0,0,0,0,0,0
|
||||
SSDetect_0/Primitives,6,2,0,0,0,0,0,0,0,0,0,0
|
||||
fifo_to_tpsram_bridge_0/Primitives,16,12,0,0,0,0,0,0,0,0,0,0
|
||||
|
757
designer/top/top_compile_netlist_resources.html
Normal file
757
designer/top/top_compile_netlist_resources.html
Normal file
@@ -0,0 +1,757 @@
|
||||
<html>
|
||||
<head>
|
||||
<style>
|
||||
body { font-family:arial; font-size:10pt; text-align:left; }
|
||||
h1, h2 {
|
||||
padding-top: 30px;
|
||||
}
|
||||
h3 {
|
||||
padding-top: 20px;
|
||||
}
|
||||
h4, h5, h6 {
|
||||
padding-top: 10px;
|
||||
font-size:12pt;
|
||||
}
|
||||
table {
|
||||
font-family:arial; font-size:10pt; text-align:left;
|
||||
border-color:#B0B0B0;
|
||||
border-style:solid;
|
||||
border-width:1px;
|
||||
border-collapse:collapse;
|
||||
}
|
||||
table th, table td {
|
||||
font-family:arial; font-size:10pt; text-align:left;
|
||||
border-color:#B0B0B0;
|
||||
border-style:solid;
|
||||
border-width:1px;
|
||||
padding: 4px;
|
||||
}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<h1 align="center">Compile Report</h1>
|
||||
<p>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</p>
|
||||
<p>Date: Wed Apr 15 19:37:54 2026
|
||||
</p>
|
||||
<h2>Device Selection</h2>
|
||||
<table cellpadding="4">
|
||||
<tr/>
|
||||
<tr>
|
||||
<td>Family</td>
|
||||
<td>PolarFire</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Device</td>
|
||||
<td>MPF300TS</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Package</td>
|
||||
<td>FCG1152</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Speed Grade</td>
|
||||
<td>-1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Core Voltage</td>
|
||||
<td>1.05V</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Part Range</td>
|
||||
<td>IND</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Default I/O technology</td>
|
||||
<td>LVCMOS 1.8V</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Source Files</h2>
|
||||
<table cellpadding="4">
|
||||
<tr/>
|
||||
<tr>
|
||||
<td>Topcell</td>
|
||||
<td>top</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Format</td>
|
||||
<td>Verilog</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Source</td>
|
||||
<td>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Options</h2>
|
||||
<table cellpadding="4">
|
||||
<tr/>
|
||||
<tr>
|
||||
<td>Limit the number of high fanout nets to display to</td>
|
||||
<td>10</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Resource Usage</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Type</th>
|
||||
<th>Used</th>
|
||||
<th>Total</th>
|
||||
<th>Percentage</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>4LUT</td>
|
||||
<td>18914</td>
|
||||
<td>299544</td>
|
||||
<td>6.31</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DFF</td>
|
||||
<td>8703</td>
|
||||
<td>299544</td>
|
||||
<td>2.91</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>User I/O</td>
|
||||
<td>53</td>
|
||||
<td>512</td>
|
||||
<td>10.35</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-- Single-ended I/O</td>
|
||||
<td>47</td>
|
||||
<td>512</td>
|
||||
<td>9.18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-- Differential I/O Pairs</td>
|
||||
<td>3</td>
|
||||
<td>256</td>
|
||||
<td>1.17</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-- I/Os using I/O Registers</td>
|
||||
<td>0</td>
|
||||
<td>512</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>I/O Register Flip-Flops </td>
|
||||
<td>0</td>
|
||||
<td>1536</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-- Input I/O Flip-Flops </td>
|
||||
<td>0</td>
|
||||
<td>512</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-- Output I/O Flip-Flops </td>
|
||||
<td>0</td>
|
||||
<td>512</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-- Enable I/O Flip-Flops </td>
|
||||
<td>0</td>
|
||||
<td>512</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>uSRAM</td>
|
||||
<td>11</td>
|
||||
<td>2772</td>
|
||||
<td>0.40</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>LSRAM</td>
|
||||
<td>34</td>
|
||||
<td>952</td>
|
||||
<td>3.57</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Math</td>
|
||||
<td>0</td>
|
||||
<td>924</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>H-Chip Global</td>
|
||||
<td>4</td>
|
||||
<td>48</td>
|
||||
<td>8.33</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Local Global</td>
|
||||
<td>1</td>
|
||||
<td>1008</td>
|
||||
<td>0.10</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PLL</td>
|
||||
<td>2</td>
|
||||
<td>8</td>
|
||||
<td>25.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DLL</td>
|
||||
<td>1</td>
|
||||
<td>8</td>
|
||||
<td>12.50</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>BANKEN</td>
|
||||
<td>1</td>
|
||||
<td>7</td>
|
||||
<td>14.29</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>UJTAG</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
<td>100.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>INIT</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
<td>100.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Transceiver Lanes</td>
|
||||
<td>0</td>
|
||||
<td>16</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Transceiver PCIe</td>
|
||||
<td>0</td>
|
||||
<td>2</td>
|
||||
<td>0.00</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>ICB_CLKDIV</td>
|
||||
<td>1</td>
|
||||
<td>24</td>
|
||||
<td>4.17</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>ICB_CLKINT</td>
|
||||
<td>3</td>
|
||||
<td>72</td>
|
||||
<td>4.17</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Detailed Logic Resource Usage</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Type</th>
|
||||
<th>4LUT</th>
|
||||
<th>DFF</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Fabric Logic</td>
|
||||
<td>17558</td>
|
||||
<td>7347</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>uSRAM Interface Logic</td>
|
||||
<td>132</td>
|
||||
<td>132</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>LSRAM Interface Logic</td>
|
||||
<td>1224</td>
|
||||
<td>1224</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Math Interface Logic</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Total Used</td>
|
||||
<td>18914</td>
|
||||
<td>8703</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Detailed Carry Chains Resource Usage</h2>
|
||||
<table cellpadding="4">
|
||||
<tr/>
|
||||
<tr>
|
||||
<td>Length</td>
|
||||
<td>Used</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>6</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>7</td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>8</td>
|
||||
<td>11</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>9</td>
|
||||
<td>9</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>10</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>11</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>12</td>
|
||||
<td>9</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>13</td>
|
||||
<td>32</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>14</td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>15</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>16</td>
|
||||
<td>7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>17</td>
|
||||
<td>7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>19</td>
|
||||
<td>13</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>21</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>22</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>25</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>27</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>28</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>30</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>31</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>32</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>33</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>64</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>65</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Total</td>
|
||||
<td>135</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Detailed 4LUT Groups Resource Usage</h2>
|
||||
<table cellpadding="4">
|
||||
<tr/>
|
||||
<tr>
|
||||
<td>Length</td>
|
||||
<td>Used</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2</td>
|
||||
<td>90</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>5</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>22</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Total</td>
|
||||
<td>94</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>I/O Function</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Type</th>
|
||||
<th>w/o register</th>
|
||||
<th>w/ register</th>
|
||||
<th>w/ DDR register</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Input I/O</td>
|
||||
<td>4</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Output I/O</td>
|
||||
<td>42</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Bidirectional I/O</td>
|
||||
<td>1</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Differential Input I/O Pairs</td>
|
||||
<td>2</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Differential Output I/O Pairs</td>
|
||||
<td>1</td>
|
||||
<td>0</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Nets assigned to chip global resources</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Fanout</th>
|
||||
<th>Type</th>
|
||||
<th>Name</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>4732</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : PF_CCC_0_0_OUT0_FABCLK_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Source: NETLIST</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1288</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : PF_IOD_CDR_CCC_C0_0_TX_CLK_G</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Source: NETLIST</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>205</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : COREJTAGDEBUG_C0_0_TGT_TCK_0_i</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Source: NETLIST</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>18</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Source: NETLIST</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>Nets assigned to row global resources</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Fanout</th>
|
||||
<th>Type</th>
|
||||
<th>Name</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1252</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : PF_IOD_CDR_C0_0_RX_CLK_R</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: PF_IOD_CDR_C0_0/RCLKINT_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Source: NETLIST</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>High fanout nets</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Fanout</th>
|
||||
<th>Type</th>
|
||||
<th>Name</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1649</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>939</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : Core_reset_pf_0_Core_reset_pf_0_dff</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0]</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>433</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>384</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>340</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>328</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>307</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>299</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>283</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>248</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2>High fanout nets (through buffer trees)</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th>Fanout</th>
|
||||
<th>Type</th>
|
||||
<th>Name</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1649</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>939</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : Core_reset_pf_0_Core_reset_pf_0_dff</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0]</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>433</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>384</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>340</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>328</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>307</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>299</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>283</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>248</td>
|
||||
<td>INT_NET</td>
|
||||
<td>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01</td>
|
||||
</tr>
|
||||
</table>
|
||||
</body>
|
||||
</html>
|
||||
197
designer/top/top_compile_netlist_resources.rpt
Normal file
197
designer/top/top_compile_netlist_resources.rpt
Normal file
@@ -0,0 +1,197 @@
|
||||
Compile Report
|
||||
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
|
||||
Date: Wed Apr 15 22:52:30 2026
|
||||
|
||||
Device Selection
|
||||
+------------------------+-------------+
|
||||
| Family | PolarFire |
|
||||
| Device | MPF300TS |
|
||||
| Package | FCG1152 |
|
||||
| Speed Grade | -1 |
|
||||
| Core Voltage | 1.05V |
|
||||
| Part Range | IND |
|
||||
| Default I/O technology | LVCMOS 1.8V |
|
||||
+------------------------+-------------+
|
||||
|
||||
Source Files
|
||||
+---------+-----------------------------------------------------------+
|
||||
| Topcell | top |
|
||||
| Format | Verilog |
|
||||
| Source | E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm |
|
||||
+---------+-----------------------------------------------------------+
|
||||
|
||||
Options
|
||||
+----------------------------------------------------+----+
|
||||
| Limit the number of high fanout nets to display to | 10 |
|
||||
+----------------------------------------------------+----+
|
||||
|
||||
Resource Usage
|
||||
+-----------------------------+-------+--------+------------+
|
||||
| Type | Used | Total | Percentage |
|
||||
+-----------------------------+-------+--------+------------+
|
||||
| 4LUT | 18889 | 299544 | 6.31 |
|
||||
| DFF | 8665 | 299544 | 2.89 |
|
||||
| User I/O | 53 | 512 | 10.35 |
|
||||
| -- Single-ended I/O | 47 | 512 | 9.18 |
|
||||
| -- Differential I/O Pairs | 3 | 256 | 1.17 |
|
||||
| -- I/Os using I/O Registers | 0 | 512 | 0.00 |
|
||||
| I/O Register Flip-Flops | 0 | 1536 | 0.00 |
|
||||
| -- Input I/O Flip-Flops | 0 | 512 | 0.00 |
|
||||
| -- Output I/O Flip-Flops | 0 | 512 | 0.00 |
|
||||
| -- Enable I/O Flip-Flops | 0 | 512 | 0.00 |
|
||||
| uSRAM | 11 | 2772 | 0.40 |
|
||||
| LSRAM | 34 | 952 | 3.57 |
|
||||
| Math | 0 | 924 | 0.00 |
|
||||
| H-Chip Global | 4 | 48 | 8.33 |
|
||||
| Local Global | 1 | 1008 | 0.10 |
|
||||
| PLL | 2 | 8 | 25.00 |
|
||||
| DLL | 1 | 8 | 12.50 |
|
||||
| BANKEN | 1 | 7 | 14.29 |
|
||||
| UJTAG | 1 | 1 | 100.00 |
|
||||
| INIT | 1 | 1 | 100.00 |
|
||||
| Transceiver Lanes | 0 | 16 | 0.00 |
|
||||
| Transceiver PCIe | 0 | 2 | 0.00 |
|
||||
| ICB_CLKDIV | 1 | 24 | 4.17 |
|
||||
| ICB_CLKINT | 3 | 72 | 4.17 |
|
||||
+-----------------------------+-------+--------+------------+
|
||||
|
||||
Detailed Logic Resource Usage
|
||||
+-----------------------+-------+------+
|
||||
| Type | 4LUT | DFF |
|
||||
+-----------------------+-------+------+
|
||||
| Fabric Logic | 17533 | 7309 |
|
||||
| uSRAM Interface Logic | 132 | 132 |
|
||||
| LSRAM Interface Logic | 1224 | 1224 |
|
||||
| Math Interface Logic | 0 | 0 |
|
||||
| Total Used | 18889 | 8665 |
|
||||
+-----------------------+-------+------+
|
||||
|
||||
Detailed Carry Chains Resource Usage
|
||||
+--------+------+
|
||||
| Length | Used |
|
||||
| 6 | 3 |
|
||||
| 7 | 6 |
|
||||
| 8 | 11 |
|
||||
| 9 | 9 |
|
||||
| 10 | 3 |
|
||||
| 11 | 3 |
|
||||
| 12 | 9 |
|
||||
| 13 | 32 |
|
||||
| 14 | 8 |
|
||||
| 15 | 3 |
|
||||
| 16 | 7 |
|
||||
| 17 | 7 |
|
||||
| 19 | 13 |
|
||||
| 21 | 1 |
|
||||
| 22 | 1 |
|
||||
| 25 | 2 |
|
||||
| 27 | 1 |
|
||||
| 28 | 1 |
|
||||
| 30 | 1 |
|
||||
| 31 | 3 |
|
||||
| 32 | 4 |
|
||||
| 33 | 4 |
|
||||
| 64 | 2 |
|
||||
| 65 | 1 |
|
||||
| Total | 135 |
|
||||
+--------+------+
|
||||
|
||||
Detailed 4LUT Groups Resource Usage
|
||||
+--------+------+
|
||||
| Length | Used |
|
||||
| 2 | 93 |
|
||||
| 5 | 5 |
|
||||
| 22 | 1 |
|
||||
| Total | 99 |
|
||||
+--------+------+
|
||||
|
||||
I/O Function
|
||||
+-------------------------------+--------------+-------------+-----------------+
|
||||
| Type | w/o register | w/ register | w/ DDR register |
|
||||
+-------------------------------+--------------+-------------+-----------------+
|
||||
| Input I/O | 4 | 0 | 0 |
|
||||
| Output I/O | 42 | 0 | 0 |
|
||||
| Bidirectional I/O | 1 | 0 | 0 |
|
||||
| Differential Input I/O Pairs | 2 | 0 | 0 |
|
||||
| Differential Output I/O Pairs | 1 | 0 | 0 |
|
||||
+-------------------------------+--------------+-------------+-----------------+
|
||||
|
||||
Nets assigned to chip global resources
|
||||
+--------+---------+--------------------------------------------------------------------------------------+
|
||||
| Fanout | Type | Name |
|
||||
+--------+---------+--------------------------------------------------------------------------------------+
|
||||
| 4694 | INT_NET | Net : PF_CCC_0_0_OUT0_FABCLK_0 |
|
||||
| | | Driver: PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1 |
|
||||
| | | Source: NETLIST |
|
||||
| 1288 | INT_NET | Net : PF_IOD_CDR_CCC_C0_0_TX_CLK_G |
|
||||
| | | Driver: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1 |
|
||||
| | | Source: NETLIST |
|
||||
| 205 | INT_NET | Net : COREJTAGDEBUG_C0_0_TGT_TCK_0_i |
|
||||
| | | Driver: COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1 |
|
||||
| | | Source: NETLIST |
|
||||
| 18 | INT_NET | Net : COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK |
|
||||
| | | Driver: COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1 |
|
||||
| | | Source: NETLIST |
|
||||
+--------+---------+--------------------------------------------------------------------------------------+
|
||||
|
||||
Nets assigned to row global resources
|
||||
+--------+---------+-----------------------------------+
|
||||
| Fanout | Type | Name |
|
||||
+--------+---------+-----------------------------------+
|
||||
| 1252 | INT_NET | Net : PF_IOD_CDR_C0_0_RX_CLK_R |
|
||||
| | | Driver: PF_IOD_CDR_C0_0/RCLKINT_0 |
|
||||
| | | Source: NETLIST |
|
||||
+--------+---------+-----------------------------------+
|
||||
|
||||
High fanout nets
|
||||
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
|
||||
| Fanout | Type | Name |
|
||||
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
|
||||
| 1649 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0 |
|
||||
| 939 | INT_NET | Net : Core_reset_pf_0_Core_reset_pf_0_dff |
|
||||
| | | Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0] |
|
||||
| 492 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1 |
|
||||
| 433 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo |
|
||||
| 340 | INT_NET | Net : MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z |
|
||||
| | | Driver: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn |
|
||||
| 328 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111 |
|
||||
| 307 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1 |
|
||||
| 299 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo |
|
||||
| 283 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111 |
|
||||
| 244 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01 |
|
||||
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
High fanout nets (through buffer trees)
|
||||
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
|
||||
| Fanout | Type | Name |
|
||||
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
|
||||
| 1649 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0 |
|
||||
| 939 | INT_NET | Net : Core_reset_pf_0_Core_reset_pf_0_dff |
|
||||
| | | Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0] |
|
||||
| 492 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1 |
|
||||
| 433 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo |
|
||||
| 340 | INT_NET | Net : MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z |
|
||||
| | | Driver: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn |
|
||||
| 328 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111 |
|
||||
| 307 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1 |
|
||||
| 299 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo |
|
||||
| 283 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1 |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111 |
|
||||
| 244 | INT_NET | Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z |
|
||||
| | | Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01 |
|
||||
+--------+---------+--------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
733
designer/top/top_compile_netlist_resources.xml
Normal file
733
designer/top/top_compile_netlist_resources.xml
Normal file
@@ -0,0 +1,733 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
|
||||
<doc>
|
||||
<title>Compile Report</title>
|
||||
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
|
||||
<text>Date: Wed Apr 15 22:52:29 2026
|
||||
</text>
|
||||
<section><name>Device Selection</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Family</cell>
|
||||
<cell>PolarFire</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Device</cell>
|
||||
<cell>MPF300TS</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Package</cell>
|
||||
<cell>FCG1152</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Speed Grade</cell>
|
||||
<cell>-1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Core Voltage</cell>
|
||||
<cell>1.05V</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Part Range</cell>
|
||||
<cell>IND</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Default I/O technology</cell>
|
||||
<cell>LVCMOS 1.8V</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Source Files</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Topcell</cell>
|
||||
<cell>top</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Format</cell>
|
||||
<cell>Verilog</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Source</cell>
|
||||
<cell>E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.vm</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Options</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Limit the number of high fanout nets to display to</cell>
|
||||
<cell>10</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Resource Usage</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Type</cell>
|
||||
<cell>Used</cell>
|
||||
<cell>Total</cell>
|
||||
<cell>Percentage</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>4LUT</cell>
|
||||
<cell>18889</cell>
|
||||
<cell>299544</cell>
|
||||
<cell>6.31</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>DFF</cell>
|
||||
<cell>8665</cell>
|
||||
<cell>299544</cell>
|
||||
<cell>2.89</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>User I/O</cell>
|
||||
<cell>53</cell>
|
||||
<cell>512</cell>
|
||||
<cell>10.35</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>-- Single-ended I/O</cell>
|
||||
<cell>47</cell>
|
||||
<cell>512</cell>
|
||||
<cell>9.18</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>-- Differential I/O Pairs</cell>
|
||||
<cell>3</cell>
|
||||
<cell>256</cell>
|
||||
<cell>1.17</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>-- I/Os using I/O Registers</cell>
|
||||
<cell>0</cell>
|
||||
<cell>512</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>I/O Register Flip-Flops </cell>
|
||||
<cell>0</cell>
|
||||
<cell>1536</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>-- Input I/O Flip-Flops </cell>
|
||||
<cell>0</cell>
|
||||
<cell>512</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>-- Output I/O Flip-Flops </cell>
|
||||
<cell>0</cell>
|
||||
<cell>512</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>-- Enable I/O Flip-Flops </cell>
|
||||
<cell>0</cell>
|
||||
<cell>512</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>uSRAM</cell>
|
||||
<cell>11</cell>
|
||||
<cell>2772</cell>
|
||||
<cell>0.40</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>LSRAM</cell>
|
||||
<cell>34</cell>
|
||||
<cell>952</cell>
|
||||
<cell>3.57</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Math</cell>
|
||||
<cell>0</cell>
|
||||
<cell>924</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>H-Chip Global</cell>
|
||||
<cell>4</cell>
|
||||
<cell>48</cell>
|
||||
<cell>8.33</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Local Global</cell>
|
||||
<cell>1</cell>
|
||||
<cell>1008</cell>
|
||||
<cell>0.10</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>PLL</cell>
|
||||
<cell>2</cell>
|
||||
<cell>8</cell>
|
||||
<cell>25.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>DLL</cell>
|
||||
<cell>1</cell>
|
||||
<cell>8</cell>
|
||||
<cell>12.50</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>BANKEN</cell>
|
||||
<cell>1</cell>
|
||||
<cell>7</cell>
|
||||
<cell>14.29</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>UJTAG</cell>
|
||||
<cell>1</cell>
|
||||
<cell>1</cell>
|
||||
<cell>100.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>INIT</cell>
|
||||
<cell>1</cell>
|
||||
<cell>1</cell>
|
||||
<cell>100.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Transceiver Lanes</cell>
|
||||
<cell>0</cell>
|
||||
<cell>16</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Transceiver PCIe</cell>
|
||||
<cell>0</cell>
|
||||
<cell>2</cell>
|
||||
<cell>0.00</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>ICB_CLKDIV</cell>
|
||||
<cell>1</cell>
|
||||
<cell>24</cell>
|
||||
<cell>4.17</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>ICB_CLKINT</cell>
|
||||
<cell>3</cell>
|
||||
<cell>72</cell>
|
||||
<cell>4.17</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Detailed Logic Resource Usage</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Type</cell>
|
||||
<cell>4LUT</cell>
|
||||
<cell>DFF</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Fabric Logic</cell>
|
||||
<cell>17533</cell>
|
||||
<cell>7309</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>uSRAM Interface Logic</cell>
|
||||
<cell>132</cell>
|
||||
<cell>132</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>LSRAM Interface Logic</cell>
|
||||
<cell>1224</cell>
|
||||
<cell>1224</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Math Interface Logic</cell>
|
||||
<cell>0</cell>
|
||||
<cell>0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Total Used</cell>
|
||||
<cell>18889</cell>
|
||||
<cell>8665</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Detailed Carry Chains Resource Usage</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Length</cell>
|
||||
<cell>Used</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>6</cell>
|
||||
<cell>3</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>7</cell>
|
||||
<cell>6</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>8</cell>
|
||||
<cell>11</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>9</cell>
|
||||
<cell>9</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>10</cell>
|
||||
<cell>3</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>11</cell>
|
||||
<cell>3</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>12</cell>
|
||||
<cell>9</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>13</cell>
|
||||
<cell>32</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>14</cell>
|
||||
<cell>8</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>15</cell>
|
||||
<cell>3</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>16</cell>
|
||||
<cell>7</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>17</cell>
|
||||
<cell>7</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>19</cell>
|
||||
<cell>13</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>21</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>22</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>25</cell>
|
||||
<cell>2</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>27</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>28</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>30</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>31</cell>
|
||||
<cell>3</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>32</cell>
|
||||
<cell>4</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>33</cell>
|
||||
<cell>4</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>64</cell>
|
||||
<cell>2</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>65</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Total</cell>
|
||||
<cell>135</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Detailed 4LUT Groups Resource Usage</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Length</cell>
|
||||
<cell>Used</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>2</cell>
|
||||
<cell>93</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>5</cell>
|
||||
<cell>5</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>22</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Total</cell>
|
||||
<cell>99</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>I/O Function</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Type</cell>
|
||||
<cell>w/o register</cell>
|
||||
<cell>w/ register</cell>
|
||||
<cell>w/ DDR register</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Input I/O</cell>
|
||||
<cell>4</cell>
|
||||
<cell>0</cell>
|
||||
<cell>0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Output I/O</cell>
|
||||
<cell>42</cell>
|
||||
<cell>0</cell>
|
||||
<cell>0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Bidirectional I/O</cell>
|
||||
<cell>1</cell>
|
||||
<cell>0</cell>
|
||||
<cell>0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Differential Input I/O Pairs</cell>
|
||||
<cell>2</cell>
|
||||
<cell>0</cell>
|
||||
<cell>0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Differential Output I/O Pairs</cell>
|
||||
<cell>1</cell>
|
||||
<cell>0</cell>
|
||||
<cell>0</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Nets assigned to chip global resources</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Fanout</cell>
|
||||
<cell>Type</cell>
|
||||
<cell>Name</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>4694</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : PF_CCC_0_0_OUT0_FABCLK_0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Source: NETLIST</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>1288</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : PF_IOD_CDR_CCC_C0_0_TX_CLK_G</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_RGB1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Source: NETLIST</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>205</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : COREJTAGDEBUG_C0_0_TGT_TCK_0_i</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Source: NETLIST</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>18</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_RGB1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Source: NETLIST</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>Nets assigned to row global resources</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Fanout</cell>
|
||||
<cell>Type</cell>
|
||||
<cell>Name</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1252</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : PF_IOD_CDR_C0_0_RX_CLK_R</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: PF_IOD_CDR_C0_0/RCLKINT_0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Source: NETLIST</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>High fanout nets</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Fanout</cell>
|
||||
<cell>Type</cell>
|
||||
<cell>Name</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1649</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>939</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : Core_reset_pf_0_Core_reset_pf_0_dff</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0]</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>492</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>433</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>340</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>328</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>307</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>299</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>283</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>244</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01</cell>
|
||||
</row>
|
||||
</table>
|
||||
<section><name>High fanout nets (through buffer trees)</name></section>
|
||||
<table>
|
||||
<header>
|
||||
<cell>Fanout</cell>
|
||||
<cell>Type</cell>
|
||||
<cell>Name</cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1649</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/hstrst</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/CLKRST_U/ASYNC_RESET.O0li0</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>939</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : Core_reset_pf_0_Core_reset_pf_0_dff</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: Core_reset_pf_0/Core_reset_pf_0/dff_15[0]</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>492</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/l0lo1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/STATS_INSTANCE.pemstat_U0/CTSE_PEMSTAT_EIM_2/l0lo1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>433</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/ooI01</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/llOOo</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>340</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn_Z</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: MIV_RV32_C0_0/MIV_RV32_C0_0/u_ipcore_0/subsys_resetn</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>328</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/iOlI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/Oi111</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>307</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/oilI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/amcxfif_U0/CTSE_AMCXFIF_CLKRST_1/O1iI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>299</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/oi001</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/CTSE_MSGMII_TBI_1/CTSE_PETCR_1/IlOOo</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>283</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/OIlI1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PECAR_1/li111</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>244</cell>
|
||||
<cell>INT_NET</cell>
|
||||
<cell>Net : CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01_Z</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>Driver: CORETSE_0_inst_0/CORETSE_0_0/CoreTSE_TOP_INST/SGMII_INSTANCE.msgmii_core_u0/iOl01</cell>
|
||||
</row>
|
||||
</table>
|
||||
</doc>
|
||||
25
designer/top/top_delayinstance.rpt
Normal file
25
designer/top/top_delayinstance.rpt
Normal file
@@ -0,0 +1,25 @@
|
||||
********************************************************************
|
||||
Delay Instance Report - Date: Wed Apr 15 23:06:11 2026
|
||||
Product: Designer
|
||||
Release: 2025.1
|
||||
Version: 2025.1.0.14
|
||||
Design Name: top
|
||||
Family: PolarFire
|
||||
Die: MPF300TS
|
||||
Package: FCG1152
|
||||
********************************************************************
|
||||
|
||||
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
|
||||
|
||||
|
||||
+-----------+----------------------------------------------------------+------------------+-------------+-----------------+-----------+
|
||||
| Type | Instance Name | Param Name | Delay Value | PDC Option Name | Editable? |
|
||||
+-----------+----------------------------------------------------------+------------------+-------------+-----------------+-----------+
|
||||
| LANECTRL | PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL | RX_DQS_DELAY_VAL | 16 | RX_DQS_DELAY | No |
|
||||
| LANECTRL | PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL | TX_DQS_DELAY_VAL | 1 | TX_DQS_DELAY | Yes |
|
||||
| LANECTRL | PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL | RX_DQS_DELAY_VAL | 9 | RX_DQS_DELAY | No |
|
||||
| LANECTRL | PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL | TX_DQS_DELAY_VAL | 1 | TX_DQS_DELAY | No |
|
||||
| PLL_DELAY | PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0_DELAY | CDELAY0_SEL | 0 | DELAY | No |
|
||||
| PLL_DELAY | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_DELAY | CDELAY0_SEL | 0 | DELAY | No |
|
||||
+-----------+----------------------------------------------------------+------------------+-------------+-----------------+-----------+
|
||||
|
||||
BIN
designer/top/top_fcb_block.db
Normal file
BIN
designer/top/top_fcb_block.db
Normal file
Binary file not shown.
11
designer/top/top_fp.log
Normal file
11
designer/top/top_fp.log
Normal file
@@ -0,0 +1,11 @@
|
||||
Software Version: 2025.1.0.14
|
||||
creating folder: E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_fp
|
||||
Created new project 'E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/designer/top/top_fp\top.pro'
|
||||
The 'new_project' command succeeded.
|
||||
The 'add_actel_device' command succeeded.
|
||||
The 'enable_device' command succeeded.
|
||||
Project saved.
|
||||
The 'save_project' command succeeded.
|
||||
Project closed.
|
||||
The 'close_project' command succeeded.
|
||||
The Execute Script command succeeded.
|
||||
13
designer/top/top_fp.tcl
Normal file
13
designer/top/top_fp.tcl
Normal file
@@ -0,0 +1,13 @@
|
||||
new_project \
|
||||
-name {top} \
|
||||
-location {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\designer\top\top_fp} \
|
||||
-mode {chain} \
|
||||
-connect_programmers {FALSE}
|
||||
add_actel_device \
|
||||
-device {MPF300TS} \
|
||||
-name {MPF300TS}
|
||||
enable_device \
|
||||
-name {MPF300TS} \
|
||||
-enable {TRUE}
|
||||
save_project
|
||||
close_project
|
||||
BIN
designer/top/top_fp/projectData/top.pdb
Normal file
BIN
designer/top/top_fp/projectData/top.pdb
Normal file
Binary file not shown.
BIN
designer/top/top_fp/projectData/top.ppd
Normal file
BIN
designer/top/top_fp/projectData/top.ppd
Normal file
Binary file not shown.
6
designer/top/top_fp/top.def
Normal file
6
designer/top/top_fp/top.def
Normal file
@@ -0,0 +1,6 @@
|
||||
IDE_RUNS_FLASHPRO:1
|
||||
DEFAULT_PROG_OUTPUT:stp
|
||||
GEN_EXPORT_TYPE:1
|
||||
FAM:PolarFire
|
||||
HINT_DIE:MPF300TS
|
||||
HINT_PACKAGE:FCG1152
|
||||
116
designer/top/top_fp/top.pro
Normal file
116
designer/top/top_fp/top.pro
Normal file
@@ -0,0 +1,116 @@
|
||||
<project name="top" version="1.2">
|
||||
<ProjectDirectory>
|
||||
E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp
|
||||
</ProjectDirectory>
|
||||
<View>
|
||||
ChainView
|
||||
</View>
|
||||
<LiberoTargetDevice>
|
||||
MPF300TS
|
||||
</LiberoTargetDevice>
|
||||
<LogFile>
|
||||
E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp\top.log
|
||||
</LogFile>
|
||||
<SerializationOption>
|
||||
Skip
|
||||
</SerializationOption>
|
||||
<ProgrammingInterface>
|
||||
JTAGMode
|
||||
</ProgrammingInterface>
|
||||
<programmer status="enable" type="FlashPro5" revision="UndefRev" connection="usb1.1">
|
||||
<name>
|
||||
E2008FOFN9
|
||||
</name>
|
||||
<id>
|
||||
E2008FOFN9
|
||||
</id>
|
||||
</programmer>
|
||||
<Servers>
|
||||
</Servers>
|
||||
<configuration>
|
||||
<Hardware>
|
||||
<FlashPro>
|
||||
<TCK>
|
||||
4000000
|
||||
</TCK>
|
||||
<Vpp/>
|
||||
<Vpn/>
|
||||
<Vddl/>
|
||||
<Vdd>
|
||||
2500 </Vdd>
|
||||
</FlashPro>
|
||||
<FlashProLite>
|
||||
<TCK>
|
||||
4000000
|
||||
</TCK>
|
||||
<Vpp/>
|
||||
<Vpn/>
|
||||
</FlashProLite>
|
||||
<FlashPro3>
|
||||
<TCK>
|
||||
4000000
|
||||
</TCK>
|
||||
<ClkMode>
|
||||
FreeRunningClk
|
||||
</ClkMode>
|
||||
</FlashPro3>
|
||||
<FlashPro4>
|
||||
<TCK>
|
||||
4000000
|
||||
</TCK>
|
||||
<ClkMode>
|
||||
FreeRunningClk
|
||||
</ClkMode>
|
||||
</FlashPro4>
|
||||
<FlashPro5>
|
||||
<TCK>
|
||||
4000000
|
||||
</TCK>
|
||||
<ClkMode>
|
||||
DiscreteClk
|
||||
</ClkMode>
|
||||
</FlashPro5>
|
||||
<FlashPro6>
|
||||
<TCK>
|
||||
4000000
|
||||
</TCK>
|
||||
<SCK>
|
||||
20000000
|
||||
</SCK>
|
||||
<ClkMode>
|
||||
DiscreteClk
|
||||
</ClkMode>
|
||||
</FlashPro6>
|
||||
</Hardware>
|
||||
<Device type="ACTEL">
|
||||
<Name>
|
||||
MPF300TS
|
||||
</Name>
|
||||
<Custom>
|
||||
MPF300TS
|
||||
</Custom>
|
||||
<SpiFlashFile>
|
||||
|
||||
</SpiFlashFile>
|
||||
<SpiFlashSelectedAction>
|
||||
|
||||
</SpiFlashSelectedAction>
|
||||
<Algo type="unknown">
|
||||
<irlength>
|
||||
8
|
||||
</irlength>
|
||||
<MaxTCK>
|
||||
25000000
|
||||
</MaxTCK>
|
||||
</Algo>
|
||||
</Device>
|
||||
<Algo type="unknown">
|
||||
<irlength>
|
||||
0
|
||||
</irlength>
|
||||
<MaxTCK>
|
||||
0
|
||||
</MaxTCK>
|
||||
</Algo>
|
||||
</configuration>
|
||||
</project>
|
||||
7
designer/top/top_fp/top.tcl
Normal file
7
designer/top/top_fp/top.tcl
Normal file
@@ -0,0 +1,7 @@
|
||||
open_project -project {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp\top.pro}
|
||||
enable_device -name {MPF300TS} -enable 1
|
||||
set_programming_file -name {MPF300TS} -file {E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.ppd}
|
||||
set_programming_action -action {PROGRAM} -name {MPF300TS}
|
||||
run_selected_actions
|
||||
save_project
|
||||
close_project
|
||||
58
designer/top/top_fp/top_PROGRAM.log
Normal file
58
designer/top/top_fp/top_PROGRAM.log
Normal file
@@ -0,0 +1,58 @@
|
||||
Software Version: 2025.1.0.14
|
||||
Programmer 'E2008FOFN9' : JTAG TCK / SPI SCK frequency = 1 MHz
|
||||
programmer 'E2008FOFN9' : FlashPro5
|
||||
Opened 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp\top.pro'
|
||||
The 'open_project' command succeeded.
|
||||
Info: Programming is already enabled for device 'MPF300TS'.
|
||||
The 'enable_device' command succeeded.
|
||||
PPD file 'E:/AbhishekV/rising/ethernet_tpsram_test/designer/top/top.ppd' has been loaded successfully.
|
||||
DESIGN : top; CHECKSUM : 332E; PDB_VERSION : 1.0
|
||||
The 'set_programming_file' command succeeded.
|
||||
The 'set_programming_action' command succeeded.
|
||||
programmer 'E2008FOFN9' : Scan Chain...
|
||||
Programmer 'E2008FOFN9' : JTAG TCK / SPI SCK frequency = 1 MHz
|
||||
programmer 'E2008FOFN9' : Check Chain...
|
||||
programmer 'E2008FOFN9' : Scan and Check Chain PASSED.
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Executing action PROGRAM
|
||||
Programmer 'E2008FOFN9' : JTAG TCK / SPI SCK frequency = 4 MHz
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Algo_version[16] = 0002
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT IDCODE[32] = 5f8131cf
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT ISC_ENABLE_RESULT[32] = 00000000
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CRCERR[1] = 0
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Programming Mode: JTAG
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Programming FPGA Array and sNVM...
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Calculating component bitstream digests using programming file...
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Fabric component bitstream digest[256] = 3536c84cd7ebd4e18d3b8d737acb9bfbf214a36a0468b786bee6e80299ff4529
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT sNVM component bitstream digest[256] = b3e37a02195dfac353265b684794c7104a80cdf5c7be9a90e72c2dd2b1333ec6
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT Entire bitstream digest[256] = 11f02c1686e51e570863d2f5a10232076078baa292ec867fc6e23c051fcd1c22
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Reading digests for all the segments from the device...
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CHECK FABRIC digest[256] = 525bdeb65dfa527647dd8e87641760aa9eb22b3b433b56be9ee5a7d6f65bb379
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT CC digest[256] = b0a959be4f9a973a07f1c4c8c417d2aaddbfa5318750755490932b913ce9a300
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT SNVM digest[256] = 7c8817fbb43c33e3b14f758e14bc23828035d0a9c8652bb2c0dd9db573b8ed58
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UL digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST0 digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST1 digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST2 digest[256] = d45264ac8021c51b0e1a01764b865b74ccf1bec3d20c40078063d19891aba92e
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST3 digest[256] = 4bfb5927a93198eae8f0d920233d00439b9709d36eef982730206ad142fda5f5
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST4 digest[256] = 0000000000000000000000000000000000000000000000000000000000000000
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST5 digest[256] = d45264ac8021c51b0e1a01764b865b74ccf1bec3d20c40078063d19891aba92e
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UKDIGEST6 digest[256] = 4bfb5927a93198eae8f0d920233d00439b9709d36eef982730206ad142fda5f5
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT UPERM digest[256] = 49a5818c4fff9561dff202eddf5d7b9dca9189afe8e0c6eb76de64f6726abb93
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT SYS digest[256] = e87f5b88b61dcd531c615070e1cb60cc09b0e35936501734f45a03f6ecc1931c
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Please refer to System Services User Guide for more details about different digests.
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : ===================================================================================
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : EXPORT DSN[128] = b6b0660d60864c5c632795558d6e2c8f
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : ===================================================================================
|
||||
programmer 'E2008FOFN9' : Finished: Wed Apr 15 23:23:12 2026 (Elapsed time 00:01:40)
|
||||
programmer 'E2008FOFN9' : device 'MPF300TS' : Executing action PROGRAM PASSED.
|
||||
programmer 'E2008FOFN9' : Chain programming PASSED.
|
||||
Chain Programming Finished: Wed Apr 15 23:23:12 2026 (Elapsed time 00:01:40)
|
||||
|
||||
o - o - o - o - o - o
|
||||
|
||||
The 'run_selected_actions' command succeeded.
|
||||
Project saved.
|
||||
The 'save_project' command succeeded.
|
||||
Project closed.
|
||||
The 'close_project' command succeeded.
|
||||
The Execute Script command succeeded.
|
||||
15
designer/top/top_fp/top_generateBitstream.log
Normal file
15
designer/top/top_fp/top_generateBitstream.log
Normal file
@@ -0,0 +1,15 @@
|
||||
Software Version: 2025.1.0.14
|
||||
Opened 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top_fp\top.pro'
|
||||
PDB file 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.pdb' has been loaded successfully.
|
||||
DESIGN : top; CHECKSUM : 332E; PDB_VERSION : 1.9
|
||||
Info: Programming Interface selected is JTAG.
|
||||
Info: Design version: 0
|
||||
File/Folder 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.ppd' will be overwritten.
|
||||
Successfully exported PPD file for currently secured device: 'E:\AbhishekV\rising\ethernet_tpsram_test\designer\top\top.ppd'; file programs Fabric and sNVM.
|
||||
Fabric component bitstream digest: 3536c84cd7ebd4e18d3b8d737acb9bfbf214a36a0468b786bee6e80299ff4529
|
||||
sNVM component bitstream digest: b3e37a02195dfac353265b684794c7104a80cdf5c7be9a90e72c2dd2b1333ec6
|
||||
Entire bitstream digest: 11f02c1686e51e570863d2f5a10232076078baa292ec867fc6e23c051fcd1c22
|
||||
Finished: Wed Apr 15 23:12:26 2026 (Elapsed time 00:01:25)
|
||||
|
||||
Project saved.
|
||||
Project closed.
|
||||
462
designer/top/top_glb_net_report.html
Normal file
462
designer/top/top_glb_net_report.html
Normal file
@@ -0,0 +1,462 @@
|
||||
<html>
|
||||
<head>
|
||||
<style>
|
||||
body { font-family:arial; font-size:10pt; text-align:left; }
|
||||
h1, h2 {
|
||||
padding-top: 30px;
|
||||
}
|
||||
h3 {
|
||||
padding-top: 20px;
|
||||
}
|
||||
h4, h5, h6 {
|
||||
padding-top: 10px;
|
||||
font-size:12pt;
|
||||
}
|
||||
table {
|
||||
font-family:arial; font-size:10pt; text-align:left;
|
||||
border-color:#B0B0B0;
|
||||
border-style:solid;
|
||||
border-width:1px;
|
||||
border-collapse:collapse;
|
||||
}
|
||||
table th, table td {
|
||||
font-family:arial; font-size:10pt; text-align:left;
|
||||
border-color:#B0B0B0;
|
||||
border-style:solid;
|
||||
border-width:1px;
|
||||
padding: 4px;
|
||||
}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<h1 align="center">Global Net Report</h1>
|
||||
<p>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</p>
|
||||
<p>Date: Wed Apr 15 23:03:20 2026
|
||||
</p>
|
||||
<h2>Global Nets Information</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th/>
|
||||
<th> From </th>
|
||||
<th> GB Location </th>
|
||||
<th> Net Name </th>
|
||||
<th> Fanout </th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</td>
|
||||
<td>(1154, 162)</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</td>
|
||||
<td>4694</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</td>
|
||||
<td>(1153, 162)</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</td>
|
||||
<td>1288</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>3</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</td>
|
||||
<td>(1155, 162)</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y</td>
|
||||
<td>205</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>4</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0</td>
|
||||
<td>(1152, 162)</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_Y</td>
|
||||
<td>18</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
<h2>I/O to GB Connections</h2>
|
||||
<p>(none)</p>
|
||||
<h2>Fabric to GB Connections</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th/>
|
||||
<th> From </th>
|
||||
<th> From Location </th>
|
||||
<th> To </th>
|
||||
<th> Net Name </th>
|
||||
<th> Net Type </th>
|
||||
<th> Fanout </th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK:Y</td>
|
||||
<td>(561, 114)</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/un1_DUT_TCK</td>
|
||||
<td>ROUTED</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst:UDRCK</td>
|
||||
<td>(504, 2)</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_0</td>
|
||||
<td>HARDWIRED</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
<h2>CCC to GB Connections</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th/>
|
||||
<th> From </th>
|
||||
<th> From Location </th>
|
||||
<th> To </th>
|
||||
<th> Net Name </th>
|
||||
<th> Net Type </th>
|
||||
<th> Fanout </th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0</td>
|
||||
<td>(2460, 5)</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0</td>
|
||||
<td>HARDWIRED</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0</td>
|
||||
<td>(0, 377)</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CCC_0_OUT0_0</td>
|
||||
<td>HARDWIRED</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
<h2>CCC Input Connections</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th/>
|
||||
<th> Port Name </th>
|
||||
<th> Pin Number </th>
|
||||
<th> I/O Function </th>
|
||||
<th> From </th>
|
||||
<th> From Location </th>
|
||||
<th> To </th>
|
||||
<th> CCC Location </th>
|
||||
<th> Net Name </th>
|
||||
<th> Net Type </th>
|
||||
<th> Fanout </th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1</td>
|
||||
<td>REF_CLK_0</td>
|
||||
<td>E25</td>
|
||||
<td>HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0</td>
|
||||
<td>REF_CLK_0_ibuf/U_IOPAD:Y</td>
|
||||
<td>(2256, 1)</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:REF_CLK_0</td>
|
||||
<td>(2460, 5)</td>
|
||||
<td>REF_CLK_0_c</td>
|
||||
<td>HARDWIRED</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2</td>
|
||||
<td>REFCLK_P</td>
|
||||
<td>U4</td>
|
||||
<td>GPIO215PB4/CLKIN_W_5/CCC_NW_CLKIN_W_5</td>
|
||||
<td>INBUF_DIFF_0/U_IOPADP:Y</td>
|
||||
<td>(0, 187)</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:REF_CLK_0</td>
|
||||
<td>(0, 377)</td>
|
||||
<td>INBUF_DIFF_0_Y</td>
|
||||
<td>HARDWIRED</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
<h2>Local Nets to RGB Connections</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th/>
|
||||
<th> From </th>
|
||||
<th> From Location </th>
|
||||
<th> Net Name </th>
|
||||
<th> Net Type </th>
|
||||
<th> Fanout </th>
|
||||
<th> RGB Location </th>
|
||||
<th> Local Fanout </th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1</td>
|
||||
<td>PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R</td>
|
||||
<td>(11, 201)</td>
|
||||
<td>PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R</td>
|
||||
<td>HARDWIRED</td>
|
||||
<td>1252</td>
|
||||
<td>(580, 178)</td>
|
||||
<td>466</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>(580, 205)</td>
|
||||
<td>780</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>(580, 232)</td>
|
||||
<td>6</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
<h2>Global Nets to RGB Connections</h2>
|
||||
<table cellpadding="4">
|
||||
<tr>
|
||||
<th/>
|
||||
<th> From </th>
|
||||
<th> From Location </th>
|
||||
<th> Net Name </th>
|
||||
<th> Fanout </th>
|
||||
<th/>
|
||||
<th> RGB Location </th>
|
||||
<th> Local Fanout </th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>1</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</td>
|
||||
<td>(1154, 162)</td>
|
||||
<td>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</td>
|
||||
<td>4694</td>
|
||||
<td>1</td>
|
||||
<td>(577, 149)</td>
|
||||
<td>711</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>2</td>
|
||||
<td>(577, 179)</td>
|
||||
<td>1015</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>3</td>
|
||||
<td>(577, 206)</td>
|
||||
<td>989</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>4</td>
|
||||
<td>(577, 233)</td>
|
||||
<td>169</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>5</td>
|
||||
<td>(577, 260)</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>6</td>
|
||||
<td>(583, 14)</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>7</td>
|
||||
<td>(583, 41)</td>
|
||||
<td>12</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>8</td>
|
||||
<td>(583, 95)</td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>9</td>
|
||||
<td>(583, 122)</td>
|
||||
<td>517</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>10</td>
|
||||
<td>(583, 149)</td>
|
||||
<td>713</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>11</td>
|
||||
<td>(583, 179)</td>
|
||||
<td>498</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>12</td>
|
||||
<td>(583, 206)</td>
|
||||
<td>44</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>2</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</td>
|
||||
<td>(1153, 162)</td>
|
||||
<td>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</td>
|
||||
<td>1288</td>
|
||||
<td>1</td>
|
||||
<td>(579, 147)</td>
|
||||
<td>302</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>2</td>
|
||||
<td>(579, 177)</td>
|
||||
<td>287</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>3</td>
|
||||
<td>(579, 204)</td>
|
||||
<td>538</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>4</td>
|
||||
<td>(579, 231)</td>
|
||||
<td>161</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>3</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</td>
|
||||
<td>(1155, 162)</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y</td>
|
||||
<td>205</td>
|
||||
<td>1</td>
|
||||
<td>(580, 122)</td>
|
||||
<td>29</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>2</td>
|
||||
<td>(586, 122)</td>
|
||||
<td>176</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>4</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0</td>
|
||||
<td>(1152, 162)</td>
|
||||
<td>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_Y</td>
|
||||
<td>18</td>
|
||||
<td>1</td>
|
||||
<td>(576, 93)</td>
|
||||
<td>15</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td/>
|
||||
<td>2</td>
|
||||
<td>(576, 120)</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
<h2>Clock Signals Summary</h2>
|
||||
<table cellpadding="4">
|
||||
<tr/>
|
||||
<tr>
|
||||
<td>The number of clock signals through H-Chip Global resources</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>The number of clock signals through Row Global resources</td>
|
||||
<td>23</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>The number of clock signals through Sector Global resources</td>
|
||||
<td>94</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>The number of clock signals through Cluster Global resources</td>
|
||||
<td>1075</td>
|
||||
</tr>
|
||||
</table>
|
||||
<p/>
|
||||
</body>
|
||||
</html>
|
||||
450
designer/top/top_glb_net_report.xml
Normal file
450
designer/top/top_glb_net_report.xml
Normal file
@@ -0,0 +1,450 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
|
||||
<doc>
|
||||
<title>Global Net Report</title>
|
||||
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
|
||||
<text>Date: Wed Apr 15 23:03:20 2026
|
||||
</text>
|
||||
<section>
|
||||
<name>Global Nets Information</name>
|
||||
<table>
|
||||
<header>
|
||||
<cell/>
|
||||
<cell> From </cell>
|
||||
<cell> GB Location </cell>
|
||||
<cell> Net Name </cell>
|
||||
<cell> Fanout </cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</cell>
|
||||
<cell>(1154, 162)</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</cell>
|
||||
<cell>4694</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>2</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</cell>
|
||||
<cell>(1153, 162)</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</cell>
|
||||
<cell>1288</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>3</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</cell>
|
||||
<cell>(1155, 162)</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y</cell>
|
||||
<cell>205</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>4</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0</cell>
|
||||
<cell>(1152, 162)</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_Y</cell>
|
||||
<cell>18</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
<section>
|
||||
<name>I/O to GB Connections</name>
|
||||
<text>(none)</text>
|
||||
</section>
|
||||
<section>
|
||||
<name>Fabric to GB Connections</name>
|
||||
<table>
|
||||
<header>
|
||||
<cell/>
|
||||
<cell> From </cell>
|
||||
<cell> From Location </cell>
|
||||
<cell> To </cell>
|
||||
<cell> Net Name </cell>
|
||||
<cell> Net Type </cell>
|
||||
<cell> Fanout </cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK:Y</cell>
|
||||
<cell>(561, 114)</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/un1_DUT_TCK</cell>
|
||||
<cell>ROUTED</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>2</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk1.genblk1.genblk1.UJTAG_inst:UDRCK</cell>
|
||||
<cell>(504, 2)</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_0</cell>
|
||||
<cell>HARDWIRED</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
<section>
|
||||
<name>CCC to GB Connections</name>
|
||||
<table>
|
||||
<header>
|
||||
<cell/>
|
||||
<cell> From </cell>
|
||||
<cell> From Location </cell>
|
||||
<cell> To </cell>
|
||||
<cell> Net Name </cell>
|
||||
<cell> Net Type </cell>
|
||||
<cell> Fanout </cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0</cell>
|
||||
<cell>(2460, 5)</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0</cell>
|
||||
<cell>HARDWIRED</cell>
|
||||
<cell>1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>2</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0</cell>
|
||||
<cell>(0, 377)</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CCC_0_OUT0_0</cell>
|
||||
<cell>HARDWIRED</cell>
|
||||
<cell>2</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
<section>
|
||||
<name>CCC Input Connections</name>
|
||||
<table>
|
||||
<header>
|
||||
<cell/>
|
||||
<cell> Port Name </cell>
|
||||
<cell> Pin Number </cell>
|
||||
<cell> I/O Function </cell>
|
||||
<cell> From </cell>
|
||||
<cell> From Location </cell>
|
||||
<cell> To </cell>
|
||||
<cell> CCC Location </cell>
|
||||
<cell> Net Name </cell>
|
||||
<cell> Net Type </cell>
|
||||
<cell> Fanout </cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1</cell>
|
||||
<cell>REF_CLK_0</cell>
|
||||
<cell>E25</cell>
|
||||
<cell>HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0</cell>
|
||||
<cell>REF_CLK_0_ibuf/U_IOPAD:Y</cell>
|
||||
<cell>(2256, 1)</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:REF_CLK_0</cell>
|
||||
<cell>(2460, 5)</cell>
|
||||
<cell>REF_CLK_0_c</cell>
|
||||
<cell>HARDWIRED</cell>
|
||||
<cell>2</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>2</cell>
|
||||
<cell>REFCLK_P</cell>
|
||||
<cell>U4</cell>
|
||||
<cell>GPIO215PB4/CLKIN_W_5/CCC_NW_CLKIN_W_5</cell>
|
||||
<cell>INBUF_DIFF_0/U_IOPADP:Y</cell>
|
||||
<cell>(0, 187)</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:REF_CLK_0</cell>
|
||||
<cell>(0, 377)</cell>
|
||||
<cell>INBUF_DIFF_0_Y</cell>
|
||||
<cell>HARDWIRED</cell>
|
||||
<cell>2</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
<section>
|
||||
<name>Local Nets to RGB Connections</name>
|
||||
<table>
|
||||
<header>
|
||||
<cell/>
|
||||
<cell> From </cell>
|
||||
<cell> From Location </cell>
|
||||
<cell> Net Name </cell>
|
||||
<cell> Net Type </cell>
|
||||
<cell> Fanout </cell>
|
||||
<cell> RGB Location </cell>
|
||||
<cell> Local Fanout </cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1</cell>
|
||||
<cell>PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R</cell>
|
||||
<cell>(11, 201)</cell>
|
||||
<cell>PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R</cell>
|
||||
<cell>HARDWIRED</cell>
|
||||
<cell>1252</cell>
|
||||
<cell>(580, 178)</cell>
|
||||
<cell>466</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell>(580, 205)</cell>
|
||||
<cell>780</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell> </cell>
|
||||
<cell>(580, 232)</cell>
|
||||
<cell>6</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
<section>
|
||||
<name>Global Nets to RGB Connections</name>
|
||||
<table>
|
||||
<header>
|
||||
<cell/>
|
||||
<cell> From </cell>
|
||||
<cell> From Location </cell>
|
||||
<cell> Net Name </cell>
|
||||
<cell> Fanout </cell>
|
||||
<cell> </cell>
|
||||
<cell> RGB Location </cell>
|
||||
<cell> Local Fanout </cell>
|
||||
</header>
|
||||
<row>
|
||||
<cell>1</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0</cell>
|
||||
<cell>(1154, 162)</cell>
|
||||
<cell>PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y</cell>
|
||||
<cell>4694</cell>
|
||||
<cell>1</cell>
|
||||
<cell>(577, 149)</cell>
|
||||
<cell>711</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>2</cell>
|
||||
<cell>(577, 179)</cell>
|
||||
<cell>1015</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>3</cell>
|
||||
<cell>(577, 206)</cell>
|
||||
<cell>989</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>4</cell>
|
||||
<cell>(577, 233)</cell>
|
||||
<cell>169</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>5</cell>
|
||||
<cell>(577, 260)</cell>
|
||||
<cell>14</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>6</cell>
|
||||
<cell>(583, 14)</cell>
|
||||
<cell>4</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>7</cell>
|
||||
<cell>(583, 41)</cell>
|
||||
<cell>12</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>8</cell>
|
||||
<cell>(583, 95)</cell>
|
||||
<cell>8</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>9</cell>
|
||||
<cell>(583, 122)</cell>
|
||||
<cell>517</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>10</cell>
|
||||
<cell>(583, 149)</cell>
|
||||
<cell>713</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>11</cell>
|
||||
<cell>(583, 179)</cell>
|
||||
<cell>498</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>12</cell>
|
||||
<cell>(583, 206)</cell>
|
||||
<cell>44</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>2</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0</cell>
|
||||
<cell>(1153, 162)</cell>
|
||||
<cell>PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD_RNITH9N3/U0_Y</cell>
|
||||
<cell>1288</cell>
|
||||
<cell>1</cell>
|
||||
<cell>(579, 147)</cell>
|
||||
<cell>302</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>2</cell>
|
||||
<cell>(579, 177)</cell>
|
||||
<cell>287</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>3</cell>
|
||||
<cell>(579, 204)</cell>
|
||||
<cell>538</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>4</cell>
|
||||
<cell>(579, 231)</cell>
|
||||
<cell>161</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>3</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0</cell>
|
||||
<cell>(1155, 162)</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y</cell>
|
||||
<cell>205</cell>
|
||||
<cell>1</cell>
|
||||
<cell>(580, 122)</cell>
|
||||
<cell>29</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>2</cell>
|
||||
<cell>(586, 122)</cell>
|
||||
<cell>176</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>4</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0</cell>
|
||||
<cell>(1152, 162)</cell>
|
||||
<cell>COREJTAGDEBUG_C0_0/COREJTAGDEBUG_C0_0/iUDRCK_inferred_clock_RNI5J864/U0_Y</cell>
|
||||
<cell>18</cell>
|
||||
<cell>1</cell>
|
||||
<cell>(576, 93)</cell>
|
||||
<cell>15</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell> </cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell></cell>
|
||||
<cell>2</cell>
|
||||
<cell>(576, 120)</cell>
|
||||
<cell>3</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
<section>
|
||||
<name>Clock Signals Summary</name>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>The number of clock signals through H-Chip Global resources</cell>
|
||||
<cell>4</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>The number of clock signals through Row Global resources</cell>
|
||||
<cell>23</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>The number of clock signals through Sector Global resources</cell>
|
||||
<cell>94</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>The number of clock signals through Cluster Global resources</cell>
|
||||
<cell>1075</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
</section>
|
||||
</doc>
|
||||
1
designer/top/top_has_io_constraints
Normal file
1
designer/top/top_has_io_constraints
Normal file
@@ -0,0 +1 @@
|
||||
NO_IO_CONSTRAINT_PRESENT
|
||||
17
designer/top/top_has_violations
Normal file
17
designer/top/top_has_violations
Normal file
@@ -0,0 +1,17 @@
|
||||
_timing_constraints_coverage 99.88%
|
||||
_max_timing_violations_slow_lv_lt met
|
||||
_max_timing_slow_lv_lt met
|
||||
_min_timing_violations_slow_lv_lt met
|
||||
_min_timing_slow_lv_lt met
|
||||
_max_timing_violations_fast_hv_lt met
|
||||
_max_timing_fast_hv_lt met
|
||||
_min_timing_violations_fast_hv_lt met
|
||||
_min_timing_fast_hv_lt met
|
||||
_max_timing_violations_slow_lv_ht met
|
||||
_max_timing_slow_lv_ht met
|
||||
_min_timing_violations_slow_lv_ht met
|
||||
_min_timing_slow_lv_ht met
|
||||
_max_timing_violations_multi_corner met
|
||||
_max_timing_multi_corner met
|
||||
_min_timing_violations_multi_corner met
|
||||
_min_timing_multi_corner met
|
||||
6246
designer/top/top_init_all_stages.mem
Normal file
6246
designer/top/top_init_all_stages.mem
Normal file
File diff suppressed because it is too large
Load Diff
6348
designer/top/top_init_all_stages_assembly.txt
Normal file
6348
designer/top/top_init_all_stages_assembly.txt
Normal file
File diff suppressed because it is too large
Load Diff
669
designer/top/top_init_config_lock_bits.txt
Normal file
669
designer/top/top_init_config_lock_bits.txt
Normal file
@@ -0,0 +1,669 @@
|
||||
;----------------------------------------------------------------------------------
|
||||
; Register Lock Bits Configuration File for peripheral blocks
|
||||
; Date: Wed Apr 15 23:06:44 2026
|
||||
; Version: 2025.1 2025.1.0.14
|
||||
; Design: top
|
||||
; Family: PolarFire
|
||||
; Die: MPF300TS
|
||||
; Package: FCG1152
|
||||
; Format: <Name of the peripheral block or register within peripheral block> <Locked/Unlocked value>
|
||||
; Peripheral block or register within peripheral block is:
|
||||
; Locked when value is 0
|
||||
; Unlocked when value is 1
|
||||
;----------------------------------------------------------------------------------
|
||||
Q1_TXPLL0_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q1_TXPLL0_EXTPLL_CLKBUF_LOCK 1
|
||||
Q1_TXPLL0_EXTPLL_CTRL_LOCK 1
|
||||
Q1_TXPLL0_EXTPLL_DIV_1_LOCK 1
|
||||
Q1_TXPLL0_EXTPLL_DIV_2_LOCK 1
|
||||
Q1_TXPLL0_SOFT_RESET_LOCK 1
|
||||
Q2_TXPLL1_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q2_TXPLL1_EXTPLL_CLKBUF_LOCK 1
|
||||
Q2_TXPLL1_EXTPLL_CTRL_LOCK 1
|
||||
Q2_TXPLL1_EXTPLL_DIV_1_LOCK 1
|
||||
Q2_TXPLL1_EXTPLL_DIV_2_LOCK 1
|
||||
Q2_TXPLL1_SOFT_RESET_LOCK 1
|
||||
Q1_TXPLL1_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q1_TXPLL1_EXTPLL_CLKBUF_LOCK 1
|
||||
Q1_TXPLL1_EXTPLL_CTRL_LOCK 1
|
||||
Q1_TXPLL1_EXTPLL_DIV_1_LOCK 1
|
||||
Q1_TXPLL1_EXTPLL_DIV_2_LOCK 1
|
||||
Q1_TXPLL1_SOFT_RESET_LOCK 1
|
||||
Q2_TXPLL0_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q2_TXPLL0_EXTPLL_CLKBUF_LOCK 1
|
||||
Q2_TXPLL0_EXTPLL_CTRL_LOCK 1
|
||||
Q2_TXPLL0_EXTPLL_DIV_1_LOCK 1
|
||||
Q2_TXPLL0_EXTPLL_DIV_2_LOCK 1
|
||||
Q2_TXPLL0_SOFT_RESET_LOCK 1
|
||||
Q3_TXPLL_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q3_TXPLL_EXTPLL_CLKBUF_LOCK 1
|
||||
Q3_TXPLL_EXTPLL_CTRL_LOCK 1
|
||||
Q3_TXPLL_EXTPLL_DIV_1_LOCK 1
|
||||
Q3_TXPLL_EXTPLL_DIV_2_LOCK 1
|
||||
Q3_TXPLL_SOFT_RESET_LOCK 1
|
||||
Q1_MAIN_SOFT_RESET_LOCK 1
|
||||
Q1_PCS_LANE0_L8_R0_LOCK 1
|
||||
Q1_PCS_LANE0_LCLK_R0_LOCK 1
|
||||
Q1_PCS_LANE0_LCLK_R1_LOCK 1
|
||||
Q1_PCS_LANE0_LFWF_R0_LOCK 1
|
||||
Q1_PCS_LANE0_LNTV_R0_LOCK 1
|
||||
Q1_PCS_LANE0_LOVR_R0_LOCK 1
|
||||
Q1_PCS_LANE0_LPIP_R0_LOCK 1
|
||||
Q1_PCS_LANE0_PMA_CTRL_R0_LOCK 1
|
||||
Q1_PCS_LANE1_L8_R0_LOCK 1
|
||||
Q1_PCS_LANE1_LCLK_R0_LOCK 1
|
||||
Q1_PCS_LANE1_LCLK_R1_LOCK 1
|
||||
Q1_PCS_LANE1_LFWF_R0_LOCK 1
|
||||
Q1_PCS_LANE1_LNTV_R0_LOCK 1
|
||||
Q1_PCS_LANE1_LOVR_R0_LOCK 1
|
||||
Q1_PCS_LANE1_LPIP_R0_LOCK 1
|
||||
Q1_PCS_LANE1_PMA_CTRL_R0_LOCK 1
|
||||
Q1_PCS_LANE2_L8_R0_LOCK 1
|
||||
Q1_PCS_LANE2_LCLK_R0_LOCK 1
|
||||
Q1_PCS_LANE2_LCLK_R1_LOCK 1
|
||||
Q1_PCS_LANE2_LFWF_R0_LOCK 1
|
||||
Q1_PCS_LANE2_LNTV_R0_LOCK 1
|
||||
Q1_PCS_LANE2_LOVR_R0_LOCK 1
|
||||
Q1_PCS_LANE2_LPIP_R0_LOCK 1
|
||||
Q1_PCS_LANE2_PMA_CTRL_R0_LOCK 1
|
||||
Q1_PCS_LANE3_L8_R0_LOCK 1
|
||||
Q1_PCS_LANE3_LCLK_R0_LOCK 1
|
||||
Q1_PCS_LANE3_LCLK_R1_LOCK 1
|
||||
Q1_PCS_LANE3_LFWF_R0_LOCK 1
|
||||
Q1_PCS_LANE3_LNTV_R0_LOCK 1
|
||||
Q1_PCS_LANE3_LOVR_R0_LOCK 1
|
||||
Q1_PCS_LANE3_LPIP_R0_LOCK 1
|
||||
Q1_PCS_LANE3_PMA_CTRL_R0_LOCK 1
|
||||
Q1_PCSCMN_GSSCLK_CTRL_LOCK 1
|
||||
Q1_PCSCMN_QDBG_R0_LOCK 1
|
||||
Q1_PCSCMN_QRST_R0_LOCK 1
|
||||
Q1_PCSCMN_SOFT_RESET_LOCK 1
|
||||
Q1_PMA_CMN_SOFT_RESET_LOCK 1
|
||||
Q1_PMA_CMN_TXPLL_CLK_SEL_LOCK 1
|
||||
Q1_PMA_CMN_TXPLL_CLKBUF_LOCK 1
|
||||
Q1_PMA_CMN_TXPLL_CTRL_LOCK 1
|
||||
Q1_PMA_CMN_TXPLL_DIV_1_LOCK 1
|
||||
Q1_PMA_CMN_TXPLL_DIV_2_LOCK 1
|
||||
Q1_PMA_LANE0_DES_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_DES_DFE_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE0_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q1_PMA_LANE0_DES_EM_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE0_DES_IN_TERM_LOCK 1
|
||||
Q1_PMA_LANE0_DES_PKDET_LOCK 1
|
||||
Q1_PMA_LANE0_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_DES_RXPLL_DIV_LOCK 1
|
||||
Q1_PMA_LANE0_DES_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE0_SER_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_DRV_BYP_LOCK 1
|
||||
Q1_PMA_LANE0_SER_DRV_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_RXDET_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_TERM_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SER_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE0_SERDES_RTL_CTRL_LOCK 1
|
||||
Q1_PMA_LANE0_SOFT_RESET_LOCK 1
|
||||
Q1_PMA_LANE1_DES_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_DES_DFE_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE1_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q1_PMA_LANE1_DES_EM_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE1_DES_IN_TERM_LOCK 1
|
||||
Q1_PMA_LANE1_DES_PKDET_LOCK 1
|
||||
Q1_PMA_LANE1_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_DES_RXPLL_DIV_LOCK 1
|
||||
Q1_PMA_LANE1_DES_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE1_SER_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_DRV_BYP_LOCK 1
|
||||
Q1_PMA_LANE1_SER_DRV_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_RXDET_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_TERM_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SER_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE1_SERDES_RTL_CTRL_LOCK 1
|
||||
Q1_PMA_LANE1_SOFT_RESET_LOCK 1
|
||||
Q1_PMA_LANE2_DES_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_DES_DFE_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE2_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q1_PMA_LANE2_DES_EM_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE2_DES_IN_TERM_LOCK 1
|
||||
Q1_PMA_LANE2_DES_PKDET_LOCK 1
|
||||
Q1_PMA_LANE2_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_DES_RXPLL_DIV_LOCK 1
|
||||
Q1_PMA_LANE2_DES_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE2_SER_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_DRV_BYP_LOCK 1
|
||||
Q1_PMA_LANE2_SER_DRV_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_RXDET_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_TERM_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SER_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE2_SERDES_RTL_CTRL_LOCK 1
|
||||
Q1_PMA_LANE2_SOFT_RESET_LOCK 1
|
||||
Q1_PMA_LANE3_DES_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_DES_DFE_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE3_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q1_PMA_LANE3_DES_EM_CTRL_2_LOCK 1
|
||||
Q1_PMA_LANE3_DES_IN_TERM_LOCK 1
|
||||
Q1_PMA_LANE3_DES_PKDET_LOCK 1
|
||||
Q1_PMA_LANE3_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_DES_RXPLL_DIV_LOCK 1
|
||||
Q1_PMA_LANE3_DES_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE3_SER_CLK_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_DRV_BYP_LOCK 1
|
||||
Q1_PMA_LANE3_SER_DRV_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_RXDET_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_TERM_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SER_TEST_BUS_LOCK 1
|
||||
Q1_PMA_LANE3_SERDES_RTL_CTRL_LOCK 1
|
||||
Q1_PMA_LANE3_SOFT_RESET_LOCK 1
|
||||
Q2_MAIN_SOFT_RESET_LOCK 1
|
||||
Q2_PCS_LANE0_L8_R0_LOCK 1
|
||||
Q2_PCS_LANE0_LCLK_R0_LOCK 1
|
||||
Q2_PCS_LANE0_LCLK_R1_LOCK 1
|
||||
Q2_PCS_LANE0_LFWF_R0_LOCK 1
|
||||
Q2_PCS_LANE0_LNTV_R0_LOCK 1
|
||||
Q2_PCS_LANE0_LOVR_R0_LOCK 1
|
||||
Q2_PCS_LANE0_LPIP_R0_LOCK 1
|
||||
Q2_PCS_LANE0_PMA_CTRL_R0_LOCK 1
|
||||
Q2_PCS_LANE1_L8_R0_LOCK 1
|
||||
Q2_PCS_LANE1_LCLK_R0_LOCK 1
|
||||
Q2_PCS_LANE1_LCLK_R1_LOCK 1
|
||||
Q2_PCS_LANE1_LFWF_R0_LOCK 1
|
||||
Q2_PCS_LANE1_LNTV_R0_LOCK 1
|
||||
Q2_PCS_LANE1_LOVR_R0_LOCK 1
|
||||
Q2_PCS_LANE1_LPIP_R0_LOCK 1
|
||||
Q2_PCS_LANE1_PMA_CTRL_R0_LOCK 1
|
||||
Q2_PCS_LANE2_L8_R0_LOCK 1
|
||||
Q2_PCS_LANE2_LCLK_R0_LOCK 1
|
||||
Q2_PCS_LANE2_LCLK_R1_LOCK 1
|
||||
Q2_PCS_LANE2_LFWF_R0_LOCK 1
|
||||
Q2_PCS_LANE2_LNTV_R0_LOCK 1
|
||||
Q2_PCS_LANE2_LOVR_R0_LOCK 1
|
||||
Q2_PCS_LANE2_LPIP_R0_LOCK 1
|
||||
Q2_PCS_LANE2_PMA_CTRL_R0_LOCK 1
|
||||
Q2_PCS_LANE3_L8_R0_LOCK 1
|
||||
Q2_PCS_LANE3_LCLK_R0_LOCK 1
|
||||
Q2_PCS_LANE3_LCLK_R1_LOCK 1
|
||||
Q2_PCS_LANE3_LFWF_R0_LOCK 1
|
||||
Q2_PCS_LANE3_LNTV_R0_LOCK 1
|
||||
Q2_PCS_LANE3_LOVR_R0_LOCK 1
|
||||
Q2_PCS_LANE3_LPIP_R0_LOCK 1
|
||||
Q2_PCS_LANE3_PMA_CTRL_R0_LOCK 1
|
||||
Q2_PCSCMN_GSSCLK_CTRL_LOCK 1
|
||||
Q2_PCSCMN_QDBG_R0_LOCK 1
|
||||
Q2_PCSCMN_QRST_R0_LOCK 1
|
||||
Q2_PCSCMN_SOFT_RESET_LOCK 1
|
||||
Q2_PMA_CMN_SOFT_RESET_LOCK 1
|
||||
Q2_PMA_CMN_TXPLL_CLK_SEL_LOCK 1
|
||||
Q2_PMA_CMN_TXPLL_CLKBUF_LOCK 1
|
||||
Q2_PMA_CMN_TXPLL_CTRL_LOCK 1
|
||||
Q2_PMA_CMN_TXPLL_DIV_1_LOCK 1
|
||||
Q2_PMA_CMN_TXPLL_DIV_2_LOCK 1
|
||||
Q2_PMA_LANE0_DES_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_DES_DFE_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE0_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q2_PMA_LANE0_DES_EM_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE0_DES_IN_TERM_LOCK 1
|
||||
Q2_PMA_LANE0_DES_PKDET_LOCK 1
|
||||
Q2_PMA_LANE0_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_DES_RXPLL_DIV_LOCK 1
|
||||
Q2_PMA_LANE0_DES_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE0_SER_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_DRV_BYP_LOCK 1
|
||||
Q2_PMA_LANE0_SER_DRV_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_RXDET_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_TERM_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SER_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE0_SERDES_RTL_CTRL_LOCK 1
|
||||
Q2_PMA_LANE0_SOFT_RESET_LOCK 1
|
||||
Q2_PMA_LANE1_DES_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_DES_DFE_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE1_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q2_PMA_LANE1_DES_EM_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE1_DES_IN_TERM_LOCK 1
|
||||
Q2_PMA_LANE1_DES_PKDET_LOCK 1
|
||||
Q2_PMA_LANE1_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_DES_RXPLL_DIV_LOCK 1
|
||||
Q2_PMA_LANE1_DES_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE1_SER_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_DRV_BYP_LOCK 1
|
||||
Q2_PMA_LANE1_SER_DRV_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_RXDET_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_TERM_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SER_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE1_SERDES_RTL_CTRL_LOCK 1
|
||||
Q2_PMA_LANE1_SOFT_RESET_LOCK 1
|
||||
Q2_PMA_LANE2_DES_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_DES_DFE_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE2_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q2_PMA_LANE2_DES_EM_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE2_DES_IN_TERM_LOCK 1
|
||||
Q2_PMA_LANE2_DES_PKDET_LOCK 1
|
||||
Q2_PMA_LANE2_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_DES_RXPLL_DIV_LOCK 1
|
||||
Q2_PMA_LANE2_DES_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE2_SER_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_DRV_BYP_LOCK 1
|
||||
Q2_PMA_LANE2_SER_DRV_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_RXDET_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_TERM_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SER_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE2_SERDES_RTL_CTRL_LOCK 1
|
||||
Q2_PMA_LANE2_SOFT_RESET_LOCK 1
|
||||
Q2_PMA_LANE3_DES_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_DES_DFE_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE3_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q2_PMA_LANE3_DES_EM_CTRL_2_LOCK 1
|
||||
Q2_PMA_LANE3_DES_IN_TERM_LOCK 1
|
||||
Q2_PMA_LANE3_DES_PKDET_LOCK 1
|
||||
Q2_PMA_LANE3_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_DES_RXPLL_DIV_LOCK 1
|
||||
Q2_PMA_LANE3_DES_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE3_SER_CLK_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_DRV_BYP_LOCK 1
|
||||
Q2_PMA_LANE3_SER_DRV_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_RXDET_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_TERM_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SER_TEST_BUS_LOCK 1
|
||||
Q2_PMA_LANE3_SERDES_RTL_CTRL_LOCK 1
|
||||
Q2_PMA_LANE3_SOFT_RESET_LOCK 1
|
||||
Q3_MAIN_SOFT_RESET_LOCK 1
|
||||
Q3_PCS_LANE0_L8_R0_LOCK 1
|
||||
Q3_PCS_LANE0_LCLK_R0_LOCK 1
|
||||
Q3_PCS_LANE0_LCLK_R1_LOCK 1
|
||||
Q3_PCS_LANE0_LFWF_R0_LOCK 1
|
||||
Q3_PCS_LANE0_LNTV_R0_LOCK 1
|
||||
Q3_PCS_LANE0_LOVR_R0_LOCK 1
|
||||
Q3_PCS_LANE0_LPIP_R0_LOCK 1
|
||||
Q3_PCS_LANE0_PMA_CTRL_R0_LOCK 1
|
||||
Q3_PCS_LANE1_L8_R0_LOCK 1
|
||||
Q3_PCS_LANE1_LCLK_R0_LOCK 1
|
||||
Q3_PCS_LANE1_LCLK_R1_LOCK 1
|
||||
Q3_PCS_LANE1_LFWF_R0_LOCK 1
|
||||
Q3_PCS_LANE1_LNTV_R0_LOCK 1
|
||||
Q3_PCS_LANE1_LOVR_R0_LOCK 1
|
||||
Q3_PCS_LANE1_LPIP_R0_LOCK 1
|
||||
Q3_PCS_LANE1_PMA_CTRL_R0_LOCK 1
|
||||
Q3_PCS_LANE2_L8_R0_LOCK 1
|
||||
Q3_PCS_LANE2_LCLK_R0_LOCK 1
|
||||
Q3_PCS_LANE2_LCLK_R1_LOCK 1
|
||||
Q3_PCS_LANE2_LFWF_R0_LOCK 1
|
||||
Q3_PCS_LANE2_LNTV_R0_LOCK 1
|
||||
Q3_PCS_LANE2_LOVR_R0_LOCK 1
|
||||
Q3_PCS_LANE2_LPIP_R0_LOCK 1
|
||||
Q3_PCS_LANE2_PMA_CTRL_R0_LOCK 1
|
||||
Q3_PCS_LANE3_L8_R0_LOCK 1
|
||||
Q3_PCS_LANE3_LCLK_R0_LOCK 1
|
||||
Q3_PCS_LANE3_LCLK_R1_LOCK 1
|
||||
Q3_PCS_LANE3_LFWF_R0_LOCK 1
|
||||
Q3_PCS_LANE3_LNTV_R0_LOCK 1
|
||||
Q3_PCS_LANE3_LOVR_R0_LOCK 1
|
||||
Q3_PCS_LANE3_LPIP_R0_LOCK 1
|
||||
Q3_PCS_LANE3_PMA_CTRL_R0_LOCK 1
|
||||
Q3_PCSCMN_GSSCLK_CTRL_LOCK 1
|
||||
Q3_PCSCMN_QDBG_R0_LOCK 1
|
||||
Q3_PCSCMN_QRST_R0_LOCK 1
|
||||
Q3_PCSCMN_SOFT_RESET_LOCK 1
|
||||
Q3_PMA_CMN_SOFT_RESET_LOCK 1
|
||||
Q3_PMA_CMN_TXPLL_CLK_SEL_LOCK 1
|
||||
Q3_PMA_CMN_TXPLL_CLKBUF_LOCK 1
|
||||
Q3_PMA_CMN_TXPLL_CTRL_LOCK 1
|
||||
Q3_PMA_CMN_TXPLL_DIV_1_LOCK 1
|
||||
Q3_PMA_CMN_TXPLL_DIV_2_LOCK 1
|
||||
Q3_PMA_LANE0_DES_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_DES_DFE_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE0_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q3_PMA_LANE0_DES_EM_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE0_DES_IN_TERM_LOCK 1
|
||||
Q3_PMA_LANE0_DES_PKDET_LOCK 1
|
||||
Q3_PMA_LANE0_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_DES_RXPLL_DIV_LOCK 1
|
||||
Q3_PMA_LANE0_DES_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE0_SER_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_DRV_BYP_LOCK 1
|
||||
Q3_PMA_LANE0_SER_DRV_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_RXDET_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_TERM_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SER_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE0_SERDES_RTL_CTRL_LOCK 1
|
||||
Q3_PMA_LANE0_SOFT_RESET_LOCK 1
|
||||
Q3_PMA_LANE1_DES_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_DES_DFE_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE1_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q3_PMA_LANE1_DES_EM_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE1_DES_IN_TERM_LOCK 1
|
||||
Q3_PMA_LANE1_DES_PKDET_LOCK 1
|
||||
Q3_PMA_LANE1_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_DES_RXPLL_DIV_LOCK 1
|
||||
Q3_PMA_LANE1_DES_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE1_SER_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_DRV_BYP_LOCK 1
|
||||
Q3_PMA_LANE1_SER_DRV_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_RXDET_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_TERM_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SER_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE1_SERDES_RTL_CTRL_LOCK 1
|
||||
Q3_PMA_LANE1_SOFT_RESET_LOCK 1
|
||||
Q3_PMA_LANE2_DES_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_DES_DFE_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE2_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q3_PMA_LANE2_DES_EM_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE2_DES_IN_TERM_LOCK 1
|
||||
Q3_PMA_LANE2_DES_PKDET_LOCK 1
|
||||
Q3_PMA_LANE2_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_DES_RXPLL_DIV_LOCK 1
|
||||
Q3_PMA_LANE2_DES_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE2_SER_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_DRV_BYP_LOCK 1
|
||||
Q3_PMA_LANE2_SER_DRV_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_RXDET_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_TERM_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SER_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE2_SERDES_RTL_CTRL_LOCK 1
|
||||
Q3_PMA_LANE2_SOFT_RESET_LOCK 1
|
||||
Q3_PMA_LANE3_DES_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_DES_DFE_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE3_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q3_PMA_LANE3_DES_EM_CTRL_2_LOCK 1
|
||||
Q3_PMA_LANE3_DES_IN_TERM_LOCK 1
|
||||
Q3_PMA_LANE3_DES_PKDET_LOCK 1
|
||||
Q3_PMA_LANE3_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_DES_RXPLL_DIV_LOCK 1
|
||||
Q3_PMA_LANE3_DES_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE3_SER_CLK_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_DRV_BYP_LOCK 1
|
||||
Q3_PMA_LANE3_SER_DRV_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_RXDET_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_TERM_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SER_TEST_BUS_LOCK 1
|
||||
Q3_PMA_LANE3_SERDES_RTL_CTRL_LOCK 1
|
||||
Q3_PMA_LANE3_SOFT_RESET_LOCK 1
|
||||
PCIE0_PCIE_CTRL_AXI_SLAVE_PCIE_ATR_CFG0_LOCK 1
|
||||
PCIE0_PCIE_CTRL_AXI_SLAVE_PCIE_ATR_CFG1_LOCK 1
|
||||
PCIE0_PCIE_CTRL_CLOCK_CONTROL_LOCK 1
|
||||
PCIE0_PCIE_CTRL_DEV_CONTROL_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCICONF_PCI_IDS_31_0_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCICONF_PCI_IDS_63_32_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCICONF_PCI_IDS_95_64_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCICONF_PCI_IDS_OVERRIDE_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCIE_AXI_MASTER_ATR_CFG0_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCIE_AXI_MASTER_ATR_CFG1_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCIE_AXI_MASTER_ATR_CFG2_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCIE_BAR_WIN_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCIE_PEX_DEV_LINK_SPC2_LOCK 1
|
||||
PCIE0_PCIE_CTRL_PCIE_PEX_SPC_LOCK 1
|
||||
PCIE0_PCIE_CTRL_SOFT_RESET_LOCK 1
|
||||
PCIE1_PCIE_CTRL_AXI_SLAVE_PCIE_ATR_CFG0_LOCK 1
|
||||
PCIE1_PCIE_CTRL_AXI_SLAVE_PCIE_ATR_CFG1_LOCK 1
|
||||
PCIE1_PCIE_CTRL_CLOCK_CONTROL_LOCK 1
|
||||
PCIE1_PCIE_CTRL_DEV_CONTROL_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCICONF_PCI_IDS_31_0_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCICONF_PCI_IDS_63_32_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCICONF_PCI_IDS_95_64_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCICONF_PCI_IDS_OVERRIDE_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCIE_AXI_MASTER_ATR_CFG0_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCIE_AXI_MASTER_ATR_CFG1_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCIE_AXI_MASTER_ATR_CFG2_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCIE_BAR_WIN_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCIE_PEX_DEV_LINK_SPC2_LOCK 1
|
||||
PCIE1_PCIE_CTRL_PCIE_PEX_SPC_LOCK 1
|
||||
PCIE1_PCIE_CTRL_SOFT_RESET_LOCK 1
|
||||
Q0_TXPLL0_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q0_TXPLL0_EXTPLL_CLKBUF_LOCK 1
|
||||
Q0_TXPLL0_EXTPLL_CTRL_LOCK 1
|
||||
Q0_TXPLL0_EXTPLL_DIV_1_LOCK 1
|
||||
Q0_TXPLL0_EXTPLL_DIV_2_LOCK 1
|
||||
Q0_TXPLL0_SOFT_RESET_LOCK 1
|
||||
Q0_TXPLL1_EXTPLL_CLK_SEL_LOCK 1
|
||||
Q0_TXPLL1_EXTPLL_CLKBUF_LOCK 1
|
||||
Q0_TXPLL1_EXTPLL_CTRL_LOCK 1
|
||||
Q0_TXPLL1_EXTPLL_DIV_1_LOCK 1
|
||||
Q0_TXPLL1_EXTPLL_DIV_2_LOCK 1
|
||||
Q0_TXPLL1_SOFT_RESET_LOCK 1
|
||||
G5_CONTROL_TVS_SOFT_RESET_LOCK 1
|
||||
G5_CONTROL_TVS_TVS_CONTROL_LOCK 1
|
||||
G5_CONTROL_TVS_TVS_TRIGGER_LOCK 1
|
||||
G5_CONTROL_VOLTAGEDETECT_VDETECTOR_LOCK 1
|
||||
CRYPTO_CONTROL_USER_LOCK 1
|
||||
CRYPTO_DLL_CTRL0_LOCK 1
|
||||
CRYPTO_DLL_CTRL1_LOCK 1
|
||||
CRYPTO_DLL_STAT0_LOCK 1
|
||||
CRYPTO_INTERRUPT_ENABLE_LOCK 1
|
||||
CRYPTO_MARGIN_LOCK 1
|
||||
CRYPTO_SOFT_RESET_LOCK 1
|
||||
Q0_MAIN_CLK_CTRL_LOCK 1
|
||||
Q0_MAIN_DLL_CTRL0_LOCK 1
|
||||
Q0_MAIN_DLL_CTRL1_LOCK 1
|
||||
Q0_MAIN_DLL_STAT0_LOCK 1
|
||||
Q0_MAIN_EXT_PIPE_CLK_CTRL_LOCK 1
|
||||
Q0_MAIN_INT_PIPE_CLK_CTRL_LOCK 1
|
||||
Q0_MAIN_MAJOR_LOCK 1
|
||||
Q0_MAIN_OVRLY_LOCK 1
|
||||
Q0_MAIN_QMUX_R0_LOCK 1
|
||||
Q0_MAIN_SOFT_RESET_LOCK 1
|
||||
Q0_PCS_LANE0_L8_R0_LOCK 1
|
||||
Q0_PCS_LANE0_LCLK_R0_LOCK 1
|
||||
Q0_PCS_LANE0_LCLK_R1_LOCK 1
|
||||
Q0_PCS_LANE0_LFWF_R0_LOCK 1
|
||||
Q0_PCS_LANE0_LNTV_R0_LOCK 1
|
||||
Q0_PCS_LANE0_LOVR_R0_LOCK 1
|
||||
Q0_PCS_LANE0_LPIP_R0_LOCK 1
|
||||
Q0_PCS_LANE0_PMA_CTRL_R0_LOCK 1
|
||||
Q0_PCS_LANE1_L8_R0_LOCK 1
|
||||
Q0_PCS_LANE1_LCLK_R0_LOCK 1
|
||||
Q0_PCS_LANE1_LCLK_R1_LOCK 1
|
||||
Q0_PCS_LANE1_LFWF_R0_LOCK 1
|
||||
Q0_PCS_LANE1_LNTV_R0_LOCK 1
|
||||
Q0_PCS_LANE1_LOVR_R0_LOCK 1
|
||||
Q0_PCS_LANE1_LPIP_R0_LOCK 1
|
||||
Q0_PCS_LANE1_PMA_CTRL_R0_LOCK 1
|
||||
Q0_PCS_LANE2_L8_R0_LOCK 1
|
||||
Q0_PCS_LANE2_LCLK_R0_LOCK 1
|
||||
Q0_PCS_LANE2_LCLK_R1_LOCK 1
|
||||
Q0_PCS_LANE2_LFWF_R0_LOCK 1
|
||||
Q0_PCS_LANE2_LNTV_R0_LOCK 1
|
||||
Q0_PCS_LANE2_LOVR_R0_LOCK 1
|
||||
Q0_PCS_LANE2_LPIP_R0_LOCK 1
|
||||
Q0_PCS_LANE2_PMA_CTRL_R0_LOCK 1
|
||||
Q0_PCS_LANE3_L8_R0_LOCK 1
|
||||
Q0_PCS_LANE3_LCLK_R0_LOCK 1
|
||||
Q0_PCS_LANE3_LCLK_R1_LOCK 1
|
||||
Q0_PCS_LANE3_LFWF_R0_LOCK 1
|
||||
Q0_PCS_LANE3_LNTV_R0_LOCK 1
|
||||
Q0_PCS_LANE3_LOVR_R0_LOCK 1
|
||||
Q0_PCS_LANE3_LPIP_R0_LOCK 1
|
||||
Q0_PCS_LANE3_PMA_CTRL_R0_LOCK 1
|
||||
Q0_PCSCMN_GSSCLK_CTRL_LOCK 1
|
||||
Q0_PCSCMN_QDBG_R0_LOCK 1
|
||||
Q0_PCSCMN_QRST_R0_LOCK 1
|
||||
Q0_PCSCMN_SOFT_RESET_LOCK 1
|
||||
Q0_PMA_CMN_SOFT_RESET_LOCK 1
|
||||
Q0_PMA_CMN_TXPLL_CLK_SEL_LOCK 1
|
||||
Q0_PMA_CMN_TXPLL_CLKBUF_LOCK 1
|
||||
Q0_PMA_CMN_TXPLL_CTRL_LOCK 1
|
||||
Q0_PMA_CMN_TXPLL_DIV_1_LOCK 1
|
||||
Q0_PMA_CMN_TXPLL_DIV_2_LOCK 1
|
||||
Q0_PMA_LANE0_DES_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_DES_DFE_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE0_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q0_PMA_LANE0_DES_EM_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE0_DES_IN_TERM_LOCK 1
|
||||
Q0_PMA_LANE0_DES_PKDET_LOCK 1
|
||||
Q0_PMA_LANE0_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_DES_RXPLL_DIV_LOCK 1
|
||||
Q0_PMA_LANE0_DES_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE0_SER_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_DRV_BYP_LOCK 1
|
||||
Q0_PMA_LANE0_SER_DRV_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_RXDET_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_TERM_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SER_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE0_SERDES_RTL_CTRL_LOCK 1
|
||||
Q0_PMA_LANE0_SOFT_RESET_LOCK 1
|
||||
Q0_PMA_LANE1_DES_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_DES_DFE_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE1_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q0_PMA_LANE1_DES_EM_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE1_DES_IN_TERM_LOCK 1
|
||||
Q0_PMA_LANE1_DES_PKDET_LOCK 1
|
||||
Q0_PMA_LANE1_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_DES_RXPLL_DIV_LOCK 1
|
||||
Q0_PMA_LANE1_DES_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE1_SER_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_DRV_BYP_LOCK 1
|
||||
Q0_PMA_LANE1_SER_DRV_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_RXDET_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_TERM_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SER_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE1_SERDES_RTL_CTRL_LOCK 1
|
||||
Q0_PMA_LANE1_SOFT_RESET_LOCK 1
|
||||
Q0_PMA_LANE2_DES_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_DES_DFE_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE2_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q0_PMA_LANE2_DES_EM_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE2_DES_IN_TERM_LOCK 1
|
||||
Q0_PMA_LANE2_DES_PKDET_LOCK 1
|
||||
Q0_PMA_LANE2_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_DES_RXPLL_DIV_LOCK 1
|
||||
Q0_PMA_LANE2_DES_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE2_SER_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_DRV_BYP_LOCK 1
|
||||
Q0_PMA_LANE2_SER_DRV_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_RXDET_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_TERM_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SER_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE2_SERDES_RTL_CTRL_LOCK 1
|
||||
Q0_PMA_LANE2_SOFT_RESET_LOCK 1
|
||||
Q0_PMA_LANE3_DES_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_DES_DFE_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE3_DES_DFEEM_CTRL_3_LOCK 1
|
||||
Q0_PMA_LANE3_DES_EM_CTRL_2_LOCK 1
|
||||
Q0_PMA_LANE3_DES_IN_TERM_LOCK 1
|
||||
Q0_PMA_LANE3_DES_PKDET_LOCK 1
|
||||
Q0_PMA_LANE3_DES_RTL_LOCK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_DES_RXPLL_DIV_LOCK 1
|
||||
Q0_PMA_LANE3_DES_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE3_SER_CLK_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_DRV_BYP_LOCK 1
|
||||
Q0_PMA_LANE3_SER_DRV_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_DRV_CTRL_SEL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_DRV_DATA_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_RXDET_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_TERM_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SER_TEST_BUS_LOCK 1
|
||||
Q0_PMA_LANE3_SERDES_RTL_CTRL_LOCK 1
|
||||
Q0_PMA_LANE3_SOFT_RESET_LOCK 1
|
||||
LANECTRL_S_0_LOCK 1
|
||||
LANECTRL_S_1_LOCK 1
|
||||
LANECTRL_S_2_LOCK 1
|
||||
LANECTRL_S_3_LOCK 1
|
||||
LANECTRL_S_4_LOCK 1
|
||||
LANECTRL_S_5_LOCK 1
|
||||
LANECTRL_S_6_LOCK 1
|
||||
LANECTRL_S_7_LOCK 1
|
||||
LANECTRL_S_8_LOCK 1
|
||||
LANECTRL_S_9_LOCK 1
|
||||
LANECTRL_S_10_LOCK 1
|
||||
LANECTRL_S_11_LOCK 1
|
||||
LANECTRL_S_12_LOCK 1
|
||||
LANECTRL_S_13_LOCK 1
|
||||
ICBMUXINGPC_SW_0_LOCK 1
|
||||
ICBMUXINGPC_SE_0_LOCK 1
|
||||
PLL_SW_0_LOCK 1
|
||||
PLL_SW_1_LOCK 1
|
||||
DLL_SW_0_LOCK 1
|
||||
DLL_SW_1_LOCK 1
|
||||
CRNCOMMON_SW_LOCK 1
|
||||
VREFBANKDYNPC_SW_H_LOCK 1
|
||||
PLL_SE_0_LOCK 1
|
||||
PLL_SE_1_LOCK 1
|
||||
DLL_SE_0_LOCK 1
|
||||
DLL_SE_1_LOCK 1
|
||||
CRNCOMMON_SE_LOCK 1
|
||||
LANECTRL_W_0_LOCK 0
|
||||
LANECTRL_W_1_LOCK 1
|
||||
LANECTRL_W_2_LOCK 1
|
||||
LANECTRL_W_3_LOCK 1
|
||||
ICBMUXINGPC_W_0_LOCK 1
|
||||
ICBMUXINGPC_E_0_LOCK 1
|
||||
LANECTRL_W_4_LOCK 1
|
||||
LANECTRL_W_5_LOCK 0
|
||||
LANECTRL_W_6_LOCK 1
|
||||
LANECTRL_W_7_LOCK 1
|
||||
LANECTRL_W_8_LOCK 1
|
||||
LANECTRL_W_9_LOCK 1
|
||||
LANECTRL_W_10_LOCK 1
|
||||
LANECTRL_W_11_LOCK 1
|
||||
PLL_NW_0_LOCK 1
|
||||
PLL_NW_1_LOCK 1
|
||||
DLL_NW_0_LOCK 1
|
||||
DLL_NW_1_LOCK 1
|
||||
CRNCOMMON_NW_LOCK 1
|
||||
VREFBANKDYNPC_NW_V_LOCK 1
|
||||
PLL_NE_0_LOCK 1
|
||||
PLL_NE_1_LOCK 1
|
||||
DLL_NE_0_LOCK 1
|
||||
DLL_NE_1_LOCK 1
|
||||
CRNCOMMON_NE_LOCK 1
|
||||
VREFBANKDYNPC_NE_H_LOCK 1
|
||||
LANECTRL_N_0_LOCK 1
|
||||
LANECTRL_N_1_LOCK 1
|
||||
LANECTRL_N_2_LOCK 1
|
||||
LANECTRL_N_3_LOCK 1
|
||||
LANECTRL_N_4_LOCK 1
|
||||
LANECTRL_N_5_LOCK 1
|
||||
LANECTRL_N_6_LOCK 1
|
||||
LANECTRL_N_7_LOCK 1
|
||||
LANECTRL_N_8_LOCK 1
|
||||
LANECTRL_N_9_LOCK 1
|
||||
LANECTRL_N_10_LOCK 1
|
||||
LANECTRL_N_11_LOCK 1
|
||||
LANECTRL_N_12_LOCK 1
|
||||
LANECTRL_N_13_LOCK 1
|
||||
LANECTRL_N_14_LOCK 1
|
||||
LANECTRL_N_15_LOCK 1
|
||||
LANECTRL_N_16_LOCK 1
|
||||
ICBMUXINGPC_NW_0_LOCK 1
|
||||
ICBMUXINGPC_NE_0_LOCK 1
|
||||
1146
designer/top/top_init_stage_1_assembly.txt
Normal file
1146
designer/top/top_init_stage_1_assembly.txt
Normal file
File diff suppressed because it is too large
Load Diff
1096
designer/top/top_init_stage_1_snvm.mem
Normal file
1096
designer/top/top_init_stage_1_snvm.mem
Normal file
File diff suppressed because it is too large
Load Diff
5210
designer/top/top_init_stage_2_3_assembly.txt
Normal file
5210
designer/top/top_init_stage_2_3_assembly.txt
Normal file
File diff suppressed because it is too large
Load Diff
5154
designer/top/top_init_stage_2_3_snvm.mem
Normal file
5154
designer/top/top_init_stage_2_3_snvm.mem
Normal file
File diff suppressed because it is too large
Load Diff
BIN
designer/top/top_inst.db
Normal file
BIN
designer/top/top_inst.db
Normal file
Binary file not shown.
0
designer/top/top_iod_cdr_inst.txt
Normal file
0
designer/top/top_iod_cdr_inst.txt
Normal file
792
designer/top/top_ios.cfg
Normal file
792
designer/top/top_ios.cfg
Normal file
@@ -0,0 +1,792 @@
|
||||
# Version: 1.0
|
||||
# pin_name pad_name function_name pin_type port_name macro_cell
|
||||
n18adp0b423 AJ1 HSIO164PB0 REG R_DATA[6] ADLIB:OUTBUF
|
||||
s150adp6b134 E25 HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 REG REF_CLK_0 ADLIB:INBUF
|
||||
s164adp6b148 D25 HSIO70PB6/CCC_SE_PLL1_OUT1 REG LINK_OK ADLIB:OUTBUF
|
||||
s96adp6b80 J20 HSIO36PB6 REG SPISS ADLIB:OUTBUF
|
||||
w78amp4b503 Y12 GPIO204PB4 REG PHY_MDC ADLIB:OUTBUF
|
||||
n34adp0b407 AE8 HSIO156PB0 REG R_DATA[19] ADLIB:OUTBUF
|
||||
s134adp6b118 K22 HSIO55PB6 REG RESET_N ADLIB:INBUF
|
||||
s105adn6b88 L20 HSIO40NB6 REG SPISDI ADLIB:INBUF
|
||||
s99adn6b82 G17 HSIO37NB6 REG TX ADLIB:OUTBUF
|
||||
n32adp0b409 AE7 HSIO157PB0 REG R_DATA[23] ADLIB:OUTBUF
|
||||
s153adn6b136 F22 HSIO64NB6 REG RD_BC_ERROR ADLIB:OUTBUF
|
||||
s98adp6b82 H18 HSIO37PB6 REG RX ADLIB:INBUF
|
||||
s104adp6b88 K20 HSIO40PB6 REG SPISDO ADLIB:OUTBUF
|
||||
w75amn4b507 U11 GPIO206NB4 REG PHY_RST ADLIB:OUTBUF
|
||||
n28adp0b413 AG7 HSIO159PB0/DQS REG R_DATA[11] ADLIB:OUTBUF
|
||||
n20adp0b421 AH4 HSIO163PB0 REG R_DATA[7] ADLIB:OUTBUF
|
||||
n46adp0b395 AE11 HSIO150PB0 REG R_DATA[24] ADLIB:OUTBUF
|
||||
n31adn0b411 AG9 HSIO158NB0 REG R_DATA[12] ADLIB:OUTBUF
|
||||
n15adn0b427 AH2 HSIO166NB0 REG R_DATA[10] ADLIB:OUTBUF
|
||||
n23adn0b419 AL2 HSIO162NB0 REG R_DATA[2] ADLIB:OUTBUF
|
||||
w74amp4b507 U12 GPIO206PB4 REG coma_mode ADLIB:OUTBUF
|
||||
w108amp4b473 AA10 GPIO189PB4 REG REF_CLK_SEL ADLIB:OUTBUF
|
||||
w62amp4b519 U2 GPIO212PB4 REG RX_P ADLIB:INBUF_DIFF
|
||||
w63amn4b519 U1 GPIO212NB4 REG RX_N ADLIB:INBUF_DIFF
|
||||
n40adp0b401 AE13 HSIO153PB0/DQS REG R_DATA[29] ADLIB:OUTBUF
|
||||
n26adp0b415 AD6 HSIO160PB0 REG R_DATA[4] ADLIB:OUTBUF
|
||||
n21adn0b421 AJ4 HSIO163NB0 REG R_DATA[15] ADLIB:OUTBUF
|
||||
n30adp0b411 AF9 HSIO158PB0 REG R_DATA[0] ADLIB:OUTBUF
|
||||
n38adp0b403 AG10 HSIO154PB0 REG R_DATA[18] ADLIB:OUTBUF
|
||||
n24adp0b417 AD9 HSIO161PB0 REG R_DATA[9] ADLIB:OUTBUF
|
||||
w67amn4b515 V2 GPIO210NB4 REG TX_N ADLIB:OUTBUF_DIFF
|
||||
w66amp4b515 V1 GPIO210PB4 REG TX_P ADLIB:OUTBUF_DIFF
|
||||
n33adn0b409 AF7 HSIO157NB0 REG R_DATA[16] ADLIB:OUTBUF
|
||||
n47adn0b395 AD11 HSIO150NB0 REG R_DATA[21] ADLIB:OUTBUF
|
||||
n44adp0b397 AD13 HSIO151PB0 REG R_DATA[17] ADLIB:OUTBUF
|
||||
w57amn4b525 U5 GPIO215NB4 REG REFCLK_N ADLIB:INBUF_DIFF
|
||||
w56amp4b525 U4 GPIO215PB4/CLKIN_W_5/CCC_NW_CLKIN_W_5 REG REFCLK_P ADLIB:INBUF_DIFF
|
||||
w79amn4b503 Y13 GPIO204NB4 REG PHY_MDIO ADLIB:BIBUF
|
||||
n41adn0b401 AF13 HSIO153NB0/DQS REG R_DATA[22] ADLIB:OUTBUF
|
||||
n43adn0b399 AE10 HSIO152NB0 REG R_DATA[20] ADLIB:OUTBUF
|
||||
n16adp0b425 AK3 HSIO165PB0/DQS REG R_DATA[8] ADLIB:OUTBUF
|
||||
n25adn0b417 AD8 HSIO161NB0 REG R_DATA[5] ADLIB:OUTBUF
|
||||
n19adn0b423 AK1 HSIO164NB0 REG R_DATA[3] ADLIB:OUTBUF
|
||||
s101adn6b84 K21 HSIO38NB6/DQS REG SPISCLKO ADLIB:OUTBUF
|
||||
n29adn0b413 AG6 HSIO159NB0/DQS REG R_DATA[13] ADLIB:OUTBUF
|
||||
n39adn0b403 AF10 HSIO154NB0 REG R_DATA[25] ADLIB:OUTBUF
|
||||
n35adn0b407 AF8 HSIO156NB0 REG R_DATA[28] ADLIB:OUTBUF
|
||||
n45adn0b397 AD14 HSIO151NB0 REG R_DATA[31] ADLIB:OUTBUF
|
||||
n27adn0b415 AE6 HSIO160NB0 REG R_DATA[1] ADLIB:OUTBUF
|
||||
n22adp0b419 AK2 HSIO162PB0 REG R_DATA[14] ADLIB:OUTBUF
|
||||
n37adn0b405 AF12 HSIO155NB0 REG R_DATA[26] ADLIB:OUTBUF
|
||||
n42adp0b399 AD10 HSIO152PB0 REG R_DATA[27] ADLIB:OUTBUF
|
||||
n36adp0b405 AE12 HSIO155PB0 REG R_DATA[30] ADLIB:OUTBUF
|
||||
jtag_tck J10 TCK RES TCK NULL
|
||||
jtag_trstb N14 TRSTB RES TRSTB NULL
|
||||
jtag_tdi K11 TDI RES TDI NULL
|
||||
jtag_tdo K9 TDO RES TDO NULL
|
||||
jtag_tms J9 TMS RES TMS NULL
|
||||
io_bg_v1p2_nw NC io_bg_v1p2_nw RES NULL NULL
|
||||
io_bg_v1p2_se NC io_bg_v1p2_se RES NULL NULL
|
||||
io_bg_rp_nw NC io_bg_rp_nw RES NULL NULL
|
||||
io_bg_rn_nw NC io_bg_rn_nw RES NULL NULL
|
||||
io_bg_rp_se NC io_bg_rp_se RES NULL NULL
|
||||
io_bg_rn_se NC io_bg_rn_se RES NULL NULL
|
||||
probe_pnvm_0 NC probe_pnvm_0 RES NULL NULL
|
||||
probe_pnvm_1 NC probe_pnvm_1 RES NULL NULL
|
||||
x_ana_tvs_ipad NC x_ana_tvs_ipad RES NULL NULL
|
||||
por_vdetect_override NC por_vdetect_override RES NULL NULL
|
||||
x_ana_vref NC x_ana_vref RES NULL NULL
|
||||
x_pad_sw_atest_probe NC x_pad_sw_atest_probe RES NULL NULL
|
||||
efuse_por33 NC efuse_por33 RES NULL NULL
|
||||
x_pad_analog_probe NC x_pad_analog_probe RES NULL NULL
|
||||
x_pad_vpbl_probe NC x_pad_vpbl_probe RES NULL NULL
|
||||
x_pad_vneg_probe NC x_pad_vneg_probe RES NULL NULL
|
||||
x_pad_vpmv_probe NC x_pad_vpmv_probe RES NULL NULL
|
||||
x_pad_vphv_probe NC x_pad_vphv_probe RES NULL NULL
|
||||
vddq NC vddq RES NULL NULL
|
||||
vddq NC vddq RES NULL NULL
|
||||
x_vddi3 NC x_vddi3 RES NULL NULL
|
||||
x_vddi3 NC x_vddi3 RES NULL NULL
|
||||
x_vddi3 NC x_vddi3 RES NULL NULL
|
||||
devrst_n L15 DEVRST_N RES NULL NULL
|
||||
sc_spi_sck_s_b1 L14 SCK RES NULL NULL
|
||||
sc_spi_ss_s_b2 M14 SS RES NULL NULL
|
||||
sc_spi_sdo_s_b3 K10 SDO RES NULL NULL
|
||||
sc_spi_sdi_s_b4 K12 SDI RES NULL NULL
|
||||
sc_io_cfg_interface_s_b5 L12 IO_CFG_INTF RES NULL NULL
|
||||
sc_exit_flash_freeze_b_s_b6 K13 RESERVED RES NULL NULL
|
||||
sc_spi_enable_s_b7 L13 SPI_EN RES NULL NULL
|
||||
s24amp2b8 K15 GPIO0PB2 REG NULL NULL
|
||||
s25amn2b8 J15 GPIO0NB2 REG NULL NULL
|
||||
s26amp2b10 H13 GPIO1PB2 REG NULL NULL
|
||||
s27amn2b10 H12 GPIO1NB2 REG NULL NULL
|
||||
s28amp2b12 J14 GPIO2PB2/DQS REG NULL NULL
|
||||
s29amn2b12 J13 GPIO2NB2/DQS REG NULL NULL
|
||||
s30amp2b14 H14 GPIO3PB2 REG NULL NULL
|
||||
s31amn2b14 G14 GPIO3NB2 REG NULL NULL
|
||||
s32amp2b16 J11 GPIO4PB2 REG NULL NULL
|
||||
s33amn2b16 H11 GPIO4NB2 REG NULL NULL
|
||||
s34amp2b18 G15 GPIO5PB2 REG NULL NULL
|
||||
s35amn2b18 G16 GPIO5NB2 REG NULL NULL
|
||||
s36amp2b20 G9 GPIO6PB2/CLKIN_S_4 REG NULL NULL
|
||||
s37amn2b20 F9 GPIO6NB2 REG NULL NULL
|
||||
s38amp2b22 H9 GPIO7PB2/CLKIN_S_5 REG NULL NULL
|
||||
s39amn2b22 H8 GPIO7NB2 REG NULL NULL
|
||||
s40amp2b24 H7 GPIO8PB2/DQS REG NULL NULL
|
||||
s41amn2b24 G7 GPIO8NB2/DQS REG NULL NULL
|
||||
s42amp2b26 F8 GPIO9PB2/CLKIN_S_6 REG NULL NULL
|
||||
s43amn2b26 F7 GPIO9NB2 REG NULL NULL
|
||||
s44amp2b28 H6 GPIO10PB2/LPRB_A REG NULL NULL
|
||||
s45amn2b28 G6 GPIO10NB2/LPRB_B REG NULL NULL
|
||||
s46amp2b30 G5 GPIO11PB2/CLKIN_S_7 REG NULL NULL
|
||||
s47amn2b30 F5 GPIO11NB2 REG NULL NULL
|
||||
s48amp2b32 C7 GPIO12PB2 REG NULL NULL
|
||||
s49amn2b32 B7 GPIO12NB2 REG NULL NULL
|
||||
s50amp2b34 E6 GPIO13PB2 REG NULL NULL
|
||||
s51amn2b34 D6 GPIO13NB2 REG NULL NULL
|
||||
s52amp2b36 D8 GPIO14PB2/DQS REG NULL NULL
|
||||
s53amn2b36 C8 GPIO14NB2/DQS REG NULL NULL
|
||||
s54amp2b38 E7 GPIO15PB2 REG NULL NULL
|
||||
s55amn2b38 E8 GPIO15NB2 REG NULL NULL
|
||||
s56amp2b40 A7 GPIO16PB2 REG NULL NULL
|
||||
s57amn2b40 A8 GPIO16NB2 REG NULL NULL
|
||||
s58amp2b42 C6 GPIO17PB2 REG NULL NULL
|
||||
s59amn2b42 B6 GPIO17NB2 REG NULL NULL
|
||||
s60amp2b44 G12 GPIO18PB2 REG NULL NULL
|
||||
s61amn2b44 G11 GPIO18NB2 REG NULL NULL
|
||||
s62amp2b46 F14 GPIO19PB2 REG NULL NULL
|
||||
s63amn2b46 F15 GPIO19NB2 REG NULL NULL
|
||||
s64amp2b48 E10 GPIO20PB2/DQS REG NULL NULL
|
||||
s65amn2b48 E11 GPIO20NB2/DQS REG NULL NULL
|
||||
s66amp2b50 G10 GPIO21PB2 REG NULL NULL
|
||||
s67amn2b50 F10 GPIO21NB2 REG NULL NULL
|
||||
s68amp2b52 F13 GPIO22PB2 REG NULL NULL
|
||||
s69amn2b52 E13 GPIO22NB2 REG NULL NULL
|
||||
s70amp2b54 F12 GPIO23PB2 REG NULL NULL
|
||||
s71amn2b54 E12 GPIO23NB2 REG NULL NULL
|
||||
s72amp2b56 D9 GPIO24PB2 REG NULL NULL
|
||||
s73amn2b56 C9 GPIO24NB2 REG NULL NULL
|
||||
s74amp2b58 B9 GPIO25PB2 REG NULL NULL
|
||||
s75amn2b58 A9 GPIO25NB2 REG NULL NULL
|
||||
s76amp2b60 D10 GPIO26PB2/DQS REG NULL NULL
|
||||
s77amn2b60 D11 GPIO26NB2/DQS REG NULL NULL
|
||||
s78amp2b62 D13 GPIO27PB2/CLKIN_S_8/CCC_SE_CLKIN_S_8 REG NULL NULL
|
||||
s79amn2b62 C12 GPIO27NB2 REG NULL NULL
|
||||
s80amp2b64 B10 GPIO28PB2 REG NULL NULL
|
||||
s81amn2b64 A10 GPIO28NB2 REG NULL NULL
|
||||
s82amp2b66 C11 GPIO29PB2/CLKIN_S_9/CCC_SE_CLKIN_S_9 REG NULL NULL
|
||||
s83amn2b66 B11 GPIO29NB2 REG NULL NULL
|
||||
s84amp2b68 L17 GPIO30PB2 REG NULL NULL
|
||||
s85amn2b68 M17 GPIO30NB2 REG NULL NULL
|
||||
s86amp2b70 J16 GPIO31PB2 REG NULL NULL
|
||||
s87amn2b70 K16 GPIO31NB2 REG NULL NULL
|
||||
s88amp2b72 H16 GPIO32PB2/DQS REG NULL NULL
|
||||
s89amn2b72 H17 GPIO32NB2/DQS REG NULL NULL
|
||||
s90amp2b74 J18 GPIO33PB2/CCC_SE_CLKIN_S_10 REG NULL NULL
|
||||
s91amn2b74 J19 GPIO33NB2 REG NULL NULL
|
||||
s92amp2b76 L19 GPIO34PB2 REG NULL NULL
|
||||
s93amn2b76 L18 GPIO34NB2 REG NULL NULL
|
||||
s94amp2b78 K18 GPIO35PB2/CCC_SE_CLKIN_S_11 REG NULL NULL
|
||||
s95amn2b78 K17 GPIO35NB2 REG NULL NULL
|
||||
s97adn6b80 H21 HSIO36NB6 REG NULL NULL
|
||||
s100adp6b84 J21 HSIO38PB6/DQS REG NULL NULL
|
||||
s102adp6b86 H19 HSIO39PB6 REG NULL NULL
|
||||
s103adn6b86 G19 HSIO39NB6 REG NULL NULL
|
||||
s106adp6b90 G20 HSIO41PB6 REG NULL NULL
|
||||
s107adn6b90 G21 HSIO41NB6 REG NULL NULL
|
||||
s108adp6b92 D19 HSIO42PB6 REG NULL NULL
|
||||
s109adn6b92 D20 HSIO42NB6 REG NULL NULL
|
||||
s110adp6b94 C17 HSIO43PB6 REG NULL NULL
|
||||
s111adn6b94 B17 HSIO43NB6 REG NULL NULL
|
||||
s112adp6b96 A17 HSIO44PB6/DQS REG NULL NULL
|
||||
s113adn6b96 A18 HSIO44NB6/DQS REG NULL NULL
|
||||
s114adp6b98 C18 HSIO45PB6 REG NULL NULL
|
||||
s115adn6b98 C19 HSIO45NB6 REG NULL NULL
|
||||
s116adp6b100 B19 HSIO46PB6 REG NULL NULL
|
||||
s117adn6b100 A19 HSIO46NB6 REG NULL NULL
|
||||
s118adp6b102 B20 HSIO47PB6 REG NULL NULL
|
||||
s119adn6b102 A20 HSIO47NB6 REG NULL NULL
|
||||
s120adp6b104 E21 HSIO48PB6 REG NULL NULL
|
||||
s121adn6b104 D21 HSIO48NB6 REG NULL NULL
|
||||
s122adp6b106 C21 HSIO49PB6 REG NULL NULL
|
||||
s123adn6b106 B21 HSIO49NB6 REG NULL NULL
|
||||
s124adp6b108 C22 HSIO50PB6/DQS REG NULL NULL
|
||||
s125adn6b108 B22 HSIO50NB6/DQS REG NULL NULL
|
||||
s126adp6b110 E22 HSIO51PB6 REG NULL NULL
|
||||
s127adn6b110 E23 HSIO51NB6 REG NULL NULL
|
||||
s128adp6b112 D23 HSIO52PB6 REG NULL NULL
|
||||
s129adn6b112 C23 HSIO52NB6 REG NULL NULL
|
||||
s130adp6b114 A22 HSIO53PB6 REG NULL NULL
|
||||
s131adn6b114 A23 HSIO53NB6 REG NULL NULL
|
||||
s132adp6b116 K23 HSIO54PB6 REG NULL NULL
|
||||
s133adn6b116 L23 HSIO54NB6 REG NULL NULL
|
||||
s135adn6b118 L22 HSIO55NB6 REG NULL NULL
|
||||
s136adp6b120 M22 HSIO56PB6/DQS REG NULL NULL
|
||||
s137adn6b120 M23 HSIO56NB6/DQS REG NULL NULL
|
||||
s138adp6b122 J23 HSIO57PB6 REG NULL NULL
|
||||
s139adn6b122 J24 HSIO57NB6 REG NULL NULL
|
||||
s140adp6b124 L25 HSIO58PB6 REG NULL NULL
|
||||
s141adn6b124 L24 HSIO58NB6 REG NULL NULL
|
||||
s142adp6b126 J25 HSIO59PB6 REG NULL NULL
|
||||
s143adn6b126 K25 HSIO59NB6 REG NULL NULL
|
||||
s144adp6b128 H23 HSIO60PB6 REG NULL NULL
|
||||
s145adn6b128 H22 HSIO60NB6 REG NULL NULL
|
||||
s146adp6b130 G24 HSIO61PB6 REG NULL NULL
|
||||
s147adn6b130 H24 HSIO61NB6 REG NULL NULL
|
||||
s148adp6b132 F23 HSIO62PB6/DQS/CCC_SE_PLL0_OUT0 REG NULL NULL
|
||||
s149adn6b132 F24 HSIO62NB6/DQS REG NULL NULL
|
||||
s151adn6b134 F25 HSIO63NB6 REG NULL NULL
|
||||
s152adp6b136 G22 HSIO64PB6/CCC_SE_PLL0_OUT1 REG NULL NULL
|
||||
s154adp6b138 H25 HSIO65PB6/CLKIN_S_13/CCC_SE_CLKIN_S_13 REG NULL NULL
|
||||
s155adn6b138 G25 HSIO65NB6 REG NULL NULL
|
||||
s156adp6b140 B24 HSIO66PB6 REG NULL NULL
|
||||
s157adn6b140 A24 HSIO66NB6 REG NULL NULL
|
||||
s158adp6b142 D24 HSIO67PB6 REG NULL NULL
|
||||
s159adn6b142 C24 HSIO67NB6 REG NULL NULL
|
||||
s160adp6b144 A25 HSIO68PB6/DQS/CCC_SE_PLL1_OUT0 REG NULL NULL
|
||||
s161adn6b144 B25 HSIO68NB6/DQS REG NULL NULL
|
||||
s162adp6b146 A27 HSIO69PB6/CCC_SE_CLKIN_S_14/CCC_SE_PLL1_OUT0 REG NULL NULL
|
||||
s163adn6b146 B27 HSIO69NB6 REG NULL NULL
|
||||
s165adn6b148 C26 HSIO70NB6 REG NULL NULL
|
||||
s166adp6b150 C27 HSIO71PB6/CCC_SE_CLKIN_S_15 REG NULL NULL
|
||||
s167adn6b150 B26 HSIO71NB6 REG NULL NULL
|
||||
n203adn1b239 AL27 HSIO72NB1 REG NULL NULL
|
||||
n202adp1b239 AL26 HSIO72PB1/CCC_NE_CLKIN_N_11 REG NULL NULL
|
||||
n201adn1b241 AM27 HSIO73NB1 REG NULL NULL
|
||||
n200adp1b241 AN27 HSIO73PB1/CCC_NE_PLL0_OUT1 REG NULL NULL
|
||||
n199adn1b243 AM26 HSIO74NB1 REG NULL NULL
|
||||
n198adp1b243 AM25 HSIO74PB1/CCC_NE_CLKIN_N_10/CCC_NE_PLL0_OUT0 REG NULL NULL
|
||||
n197adn1b245 AP27 HSIO75NB1/DQS REG NULL NULL
|
||||
n196adp1b245 AP26 HSIO75PB1/DQS/CCC_NE_PLL0_OUT0 REG NULL NULL
|
||||
n195adn1b247 AN26 HSIO76NB1 REG NULL NULL
|
||||
n194adp1b247 AP25 HSIO76PB1 REG NULL NULL
|
||||
n193adn1b249 AL25 HSIO77NB1 REG NULL NULL
|
||||
n192adp1b249 AK25 HSIO77PB1 REG NULL NULL
|
||||
n191adn1b251 AG25 HSIO78NB1 REG NULL NULL
|
||||
n190adp1b251 AG24 HSIO78PB1/CLKIN_N_9/CCC_NE_CLKIN_N_9 REG NULL NULL
|
||||
n189adn1b253 AJ23 HSIO79NB1 REG NULL NULL
|
||||
n188adp1b253 AH23 HSIO79PB1/CCC_NE_PLL1_OUT1 REG NULL NULL
|
||||
n187adn1b255 AH25 HSIO80NB1 REG NULL NULL
|
||||
n186adp1b255 AH24 HSIO80PB1/CLKIN_N_8/CCC_NE_CLKIN_N_8/CCC_NE_PLL1_OUT0 REG NULL NULL
|
||||
n185adn1b257 AJ25 HSIO81NB1/DQS REG NULL NULL
|
||||
n184adp1b257 AJ24 HSIO81PB1/DQS/CCC_NE_PLL1_OUT0 REG NULL NULL
|
||||
n183adn1b259 AL22 HSIO82NB1 REG NULL NULL
|
||||
n182adp1b259 AK23 HSIO82PB1 REG NULL NULL
|
||||
n181adn1b261 AL24 HSIO83NB1 REG NULL NULL
|
||||
n180adp1b261 AL23 HSIO83PB1 REG NULL NULL
|
||||
n179adn1b263 AD25 HSIO84NB1 REG NULL NULL
|
||||
n178adp1b263 AE25 HSIO84PB1 REG NULL NULL
|
||||
n177adn1b265 AD23 HSIO85NB1 REG NULL NULL
|
||||
n176adp1b265 AE23 HSIO85PB1 REG NULL NULL
|
||||
n175adn1b267 AF25 HSIO86NB1 REG NULL NULL
|
||||
n174adp1b267 AF24 HSIO86PB1 REG NULL NULL
|
||||
n173adn1b269 AE22 HSIO87NB1/DQS REG NULL NULL
|
||||
n172adp1b269 AF22 HSIO87PB1/DQS REG NULL NULL
|
||||
n171adn1b271 AF23 HSIO88NB1 REG NULL NULL
|
||||
n170adp1b271 AG22 HSIO88PB1 REG NULL NULL
|
||||
n169adn1b273 AC23 HSIO89NB1 REG NULL NULL
|
||||
n168adp1b273 AD24 HSIO89PB1 REG NULL NULL
|
||||
n167adn1b275 AN22 HSIO90NB1 REG NULL NULL
|
||||
n166adp1b275 AN21 HSIO90PB1 REG NULL NULL
|
||||
n165adn1b277 AM24 HSIO91NB1 REG NULL NULL
|
||||
n164adp1b277 AN24 HSIO91PB1 REG NULL NULL
|
||||
n163adn1b279 AP21 HSIO92NB1 REG NULL NULL
|
||||
n162adp1b279 AP20 HSIO92PB1 REG NULL NULL
|
||||
n161adn1b281 AP24 HSIO93NB1/DQS REG NULL NULL
|
||||
n160adp1b281 AP23 HSIO93PB1/DQS REG NULL NULL
|
||||
n159adn1b283 AP19 HSIO94NB1 REG NULL NULL
|
||||
n158adp1b283 AN19 HSIO94PB1 REG NULL NULL
|
||||
n157adn1b285 AN23 HSIO95NB1 REG NULL NULL
|
||||
n156adp1b285 AM22 HSIO95PB1 REG NULL NULL
|
||||
n155adn1b287 AM21 HSIO96NB1 REG NULL NULL
|
||||
n154adp1b287 AM20 HSIO96PB1/CLKIN_N_7 REG NULL NULL
|
||||
n153adn1b289 AK22 HSIO97NB1 REG NULL NULL
|
||||
n152adp1b289 AK21 HSIO97PB1 REG NULL NULL
|
||||
n151adn1b291 AK20 HSIO98NB1 REG NULL NULL
|
||||
n150adp1b291 AJ20 HSIO98PB1/CLKIN_N_6 REG NULL NULL
|
||||
n149adn1b293 AJ21 HSIO99NB1/DQS REG NULL NULL
|
||||
n148adp1b293 AH22 HSIO99PB1/DQS REG NULL NULL
|
||||
n147adn1b295 AH21 HSIO100NB1 REG NULL NULL
|
||||
n146adp1b295 AG21 HSIO100PB1 REG NULL NULL
|
||||
n145adn1b297 AM19 HSIO101NB1 REG NULL NULL
|
||||
n144adp1b297 AL20 HSIO101PB1 REG NULL NULL
|
||||
n143adn7b299 AP18 HSIO102NB7 REG NULL NULL
|
||||
n142adp7b299 AN18 HSIO102PB7 REG NULL NULL
|
||||
n141adn7b301 AM16 HSIO103NB7 REG NULL NULL
|
||||
n140adp7b301 AL17 HSIO103PB7 REG NULL NULL
|
||||
n139adn7b303 AP16 HSIO104NB7 REG NULL NULL
|
||||
n138adp7b303 AN16 HSIO104PB7 REG NULL NULL
|
||||
n137adn7b305 AL19 HSIO105NB7/DQS REG NULL NULL
|
||||
n136adp7b305 AL18 HSIO105PB7/DQS REG NULL NULL
|
||||
n135adn7b307 AN17 HSIO106NB7 REG NULL NULL
|
||||
n134adp7b307 AM17 HSIO106PB7 REG NULL NULL
|
||||
n133adn7b309 AK18 HSIO107NB7 REG NULL NULL
|
||||
n132adp7b309 AK17 HSIO107PB7 REG NULL NULL
|
||||
n131adn7b311 AP15 HSIO108NB7 REG NULL NULL
|
||||
n130adp7b311 AN14 HSIO108PB7 REG NULL NULL
|
||||
n129adn7b313 AP14 HSIO109NB7 REG NULL NULL
|
||||
n128adp7b313 AP13 HSIO109PB7 REG NULL NULL
|
||||
n127adn7b315 AM15 HSIO110NB7 REG NULL NULL
|
||||
n126adp7b315 AM14 HSIO110PB7 REG NULL NULL
|
||||
n125adn7b317 AN13 HSIO111NB7/DQS REG NULL NULL
|
||||
n124adp7b317 AN12 HSIO111PB7/DQS REG NULL NULL
|
||||
n123adn7b319 AM12 HSIO112NB7 REG NULL NULL
|
||||
n122adp7b319 AL13 HSIO112PB7 REG NULL NULL
|
||||
n121adn7b321 AL14 HSIO113NB7 REG NULL NULL
|
||||
n120adp7b321 AL15 HSIO113PB7 REG NULL NULL
|
||||
n119adn7b323 AE21 HSIO114NB7 REG NULL NULL
|
||||
n118adp7b323 AD21 HSIO114PB7 REG NULL NULL
|
||||
n117adn7b325 AF18 HSIO115NB7 REG NULL NULL
|
||||
n116adp7b325 AF19 HSIO115PB7 REG NULL NULL
|
||||
n115adn7b327 AD20 HSIO116NB7 REG NULL NULL
|
||||
n114adp7b327 AE20 HSIO116PB7 REG NULL NULL
|
||||
n113adn7b329 AE18 HSIO117NB7/DQS REG NULL NULL
|
||||
n112adp7b329 AD18 HSIO117PB7/DQS REG NULL NULL
|
||||
n111adn7b331 AG20 HSIO118NB7 REG NULL NULL
|
||||
n110adp7b331 AF20 HSIO118PB7 REG NULL NULL
|
||||
n109adn7b333 AD19 HSIO119NB7 REG NULL NULL
|
||||
n108adp7b333 AC18 HSIO119PB7 REG NULL NULL
|
||||
n107adn7b335 AP11 HSIO120NB7 REG NULL NULL
|
||||
n106adp7b335 AP10 HSIO120PB7 REG NULL NULL
|
||||
n105adn7b337 AP9 HSIO121NB7 REG NULL NULL
|
||||
n104adp7b337 AN9 HSIO121PB7 REG NULL NULL
|
||||
n103adn7b339 AL12 HSIO122NB7 REG NULL NULL
|
||||
n102adp7b339 AK11 HSIO122PB7 REG NULL NULL
|
||||
n101adn7b341 AN11 HSIO123NB7/DQS REG NULL NULL
|
||||
n100adp7b341 AM11 HSIO123PB7/DQS REG NULL NULL
|
||||
n99adn7b343 AM10 HSIO124NB7 REG NULL NULL
|
||||
n98adp7b343 AM9 HSIO124PB7 REG NULL NULL
|
||||
n97adn7b345 AL10 HSIO125NB7 REG NULL NULL
|
||||
n96adp7b345 AK10 HSIO125PB7 REG NULL NULL
|
||||
n95adn7b347 AG16 HSIO126NB7 REG NULL NULL
|
||||
n94adp7b347 AF17 HSIO126PB7 REG NULL NULL
|
||||
n93adn7b349 AE17 HSIO127NB7 REG NULL NULL
|
||||
n92adp7b349 AD17 HSIO127PB7 REG NULL NULL
|
||||
n91adn7b351 AG15 HSIO128NB7 REG NULL NULL
|
||||
n90adp7b351 AF15 HSIO128PB7 REG NULL NULL
|
||||
n89adn7b353 AD16 HSIO129NB7/DQS REG NULL NULL
|
||||
n88adp7b353 AE16 HSIO129PB7/DQS REG NULL NULL
|
||||
n87adn7b355 AG14 HSIO130NB7 REG NULL NULL
|
||||
n86adp7b355 AF14 HSIO130PB7 REG NULL NULL
|
||||
n85adn7b357 AE15 HSIO131NB7 REG NULL NULL
|
||||
n84adp7b357 AD15 HSIO131PB7 REG NULL NULL
|
||||
n83adn7b359 AK12 HSIO132NB7 REG NULL NULL
|
||||
n82adp7b359 AK13 HSIO132PB7 REG NULL NULL
|
||||
n81adn7b361 AJ13 HSIO133NB7 REG NULL NULL
|
||||
n80adp7b361 AJ14 HSIO133PB7 REG NULL NULL
|
||||
n79adn7b363 AJ11 HSIO134NB7 REG NULL NULL
|
||||
n78adp7b363 AJ10 HSIO134PB7 REG NULL NULL
|
||||
n77adn7b365 AH13 HSIO135NB7/DQS REG NULL NULL
|
||||
n76adp7b365 AH14 HSIO135PB7/DQS REG NULL NULL
|
||||
n75adn7b367 AH12 HSIO136NB7 REG NULL NULL
|
||||
n74adp7b367 AG12 HSIO136PB7 REG NULL NULL
|
||||
n73adn7b369 AH11 HSIO137NB7 REG NULL NULL
|
||||
n72adp7b369 AG11 HSIO137PB7 REG NULL NULL
|
||||
n71adn0b371 AN4 HSIO138NB0 REG NULL NULL
|
||||
n70adp0b371 AN3 HSIO138PB0 REG NULL NULL
|
||||
n69adn0b373 AM5 HSIO139NB0 REG NULL NULL
|
||||
n68adp0b373 AL5 HSIO139PB0 REG NULL NULL
|
||||
n67adn0b375 AP3 HSIO140NB0 REG NULL NULL
|
||||
n66adp0b375 AP2 HSIO140PB0 REG NULL NULL
|
||||
n65adn0b377 AM4 HSIO141NB0/DQS REG NULL NULL
|
||||
n64adp0b377 AL4 HSIO141PB0/DQS REG NULL NULL
|
||||
n63adn0b379 AN2 HSIO142NB0 REG NULL NULL
|
||||
n62adp0b379 AN1 HSIO142PB0 REG NULL NULL
|
||||
n61adn0b381 AM2 HSIO143NB0 REG NULL NULL
|
||||
n60adp0b381 AM1 HSIO143PB0 REG NULL NULL
|
||||
n59adn0b383 AK8 HSIO144NB0 REG NULL NULL
|
||||
n58adp0b383 AK7 HSIO144PB0/CLKIN_N_5 REG NULL NULL
|
||||
n57adn0b385 AK6 HSIO145NB0 REG NULL NULL
|
||||
n56adp0b385 AK5 HSIO145PB0 REG NULL NULL
|
||||
n55adn0b387 AH9 HSIO146NB0 REG NULL NULL
|
||||
n54adp0b387 AH8 HSIO146PB0/CLKIN_N_4 REG NULL NULL
|
||||
n53adn0b389 AJ6 HSIO147NB0/DQS REG NULL NULL
|
||||
n52adp0b389 AJ5 HSIO147PB0/DQS REG NULL NULL
|
||||
n51adn0b391 AJ8 HSIO148NB0 REG NULL NULL
|
||||
n50adp0b391 AJ9 HSIO148PB0 REG NULL NULL
|
||||
n49adn0b393 AH7 HSIO149NB0 REG NULL NULL
|
||||
n48adp0b393 AH6 HSIO149PB0 REG NULL NULL
|
||||
n17adn0b425 AL3 HSIO165NB0/DQS REG NULL NULL
|
||||
n14adp0b427 AH1 HSIO166PB0 REG NULL NULL
|
||||
n13adn0b429 AJ3 HSIO167NB0 REG NULL NULL
|
||||
n12adp0b429 AH3 HSIO167PB0 REG NULL NULL
|
||||
n11adn0b431 AG2 HSIO168NB0 REG NULL NULL
|
||||
n10adp0b431 AG1 HSIO168PB0/CLKIN_N_3/CCC_NW_CLKIN_N_3 REG NULL NULL
|
||||
n9adn0b433 AF3 HSIO169NB0 REG NULL NULL
|
||||
n8adp0b433 AF2 HSIO169PB0/CCC_NW_PLL1_OUT1 REG NULL NULL
|
||||
n7adn0b435 AG5 HSIO170NB0 REG NULL NULL
|
||||
n6adp0b435 AG4 HSIO170PB0/CLKIN_N_2/CCC_NW_CLKIN_N_2/CCC_NW_PLL1_OUT0 REG NULL NULL
|
||||
n5adn0b437 AE1 HSIO171NB0/DQS REG NULL NULL
|
||||
n4adp0b437 AE2 HSIO171PB0/DQS/CCC_NW_PLL1_OUT0 REG NULL NULL
|
||||
n3adn0b439 AF4 HSIO172NB0 REG NULL NULL
|
||||
n2adp0b439 AE3 HSIO172PB0/CCC_NW_CLKIN_N_1 REG NULL NULL
|
||||
n1adn0b441 AF5 HSIO173NB0 REG NULL NULL
|
||||
n0adp0b441 AE5 HSIO173PB0/CCC_NW_CLKIN_N_0 REG NULL NULL
|
||||
w139amn4b443 AD3 GPIO174NB4 REG NULL NULL
|
||||
w138amp4b443 AC2 GPIO174PB4/CLKIN_W_7/CCC_NW_CLKIN_W_7/CCC_NW_PLL0_OUT0 REG NULL NULL
|
||||
w137amn4b445 AD1 GPIO175NB4/DQS REG NULL NULL
|
||||
w136amp4b445 AC1 GPIO175PB4/DQS REG NULL NULL
|
||||
w135amn4b447 AB1 GPIO176NB4 REG NULL NULL
|
||||
w134amp4b447 AB2 GPIO176PB4 REG NULL NULL
|
||||
w133amn4b449 AC3 GPIO177NB4 REG NULL NULL
|
||||
w132amp4b449 AB4 GPIO177PB4 REG NULL NULL
|
||||
w131amn4b451 AC6 GPIO178NB4 REG NULL NULL
|
||||
w130amp4b451 AC7 GPIO178PB4 REG NULL NULL
|
||||
w129amn4b453 AB6 GPIO179NB4 REG NULL NULL
|
||||
w128amp4b453 AB7 GPIO179PB4 REG NULL NULL
|
||||
w127amn4b455 AD5 GPIO180NB4 REG NULL NULL
|
||||
w126amp4b455 AD4 GPIO180PB4/CLKIN_W_6/CCC_NW_CLKIN_W_6/CCC_NW_PLL0_OUT1 REG NULL NULL
|
||||
w125amn4b457 AC8 GPIO181NB4/DQS REG NULL NULL
|
||||
w124amp4b457 AC9 GPIO181PB4/DQS/CCC_NW_PLL0_OUT0 REG NULL NULL
|
||||
w123amn4b459 AC4 GPIO182NB4 REG NULL NULL
|
||||
w122amp4b459 AB5 GPIO182PB4 REG NULL NULL
|
||||
w121amn4b461 AA8 GPIO183NB4 REG NULL NULL
|
||||
w120amp4b461 AB9 GPIO183PB4 REG NULL NULL
|
||||
w119amn4b463 AC12 GPIO184NB4 REG NULL NULL
|
||||
w118amp4b463 AC11 GPIO184PB4 REG NULL NULL
|
||||
w117amn4b465 AC13 GPIO185NB4 REG NULL NULL
|
||||
w116amp4b465 AB14 GPIO185PB4 REG NULL NULL
|
||||
w115amn4b467 AB10 GPIO186NB4 REG NULL NULL
|
||||
w114amp4b467 AB11 GPIO186PB4 REG NULL NULL
|
||||
w113amn4b469 AA12 GPIO187NB4/DQS REG NULL NULL
|
||||
w112amp4b469 AB12 GPIO187PB4/DQS REG NULL NULL
|
||||
w111amn4b471 AA13 GPIO188NB4 REG NULL NULL
|
||||
w110amp4b471 AA14 GPIO188PB4 REG NULL NULL
|
||||
w109amn4b473 AA9 GPIO189NB4 REG NULL NULL
|
||||
w107amn4b475 AA2 GPIO190NB4 REG NULL NULL
|
||||
w106amp4b475 AA3 GPIO190PB4 REG NULL NULL
|
||||
w105amn4b477 AA5 GPIO191NB4 REG NULL NULL
|
||||
w104amp4b477 AA4 GPIO191PB4 REG NULL NULL
|
||||
w103amn4b479 Y2 GPIO192NB4 REG NULL NULL
|
||||
w102amp4b479 Y3 GPIO192PB4 REG NULL NULL
|
||||
w101amn4b481 W3 GPIO193NB4/DQS REG NULL NULL
|
||||
w100amp4b481 W4 GPIO193PB4/DQS REG NULL NULL
|
||||
w99amn4b483 Y1 GPIO194NB4 REG NULL NULL
|
||||
w98amp4b483 W1 GPIO194PB4 REG NULL NULL
|
||||
w97amn4b485 Y5 GPIO195NB4 REG NULL NULL
|
||||
w96amp4b485 W5 GPIO195PB4 REG NULL NULL
|
||||
w95amn4b487 AA7 GPIO196NB4 REG NULL NULL
|
||||
w94amp4b487 Y7 GPIO196PB4 REG NULL NULL
|
||||
w93amn4b489 Y6 GPIO197NB4 REG NULL NULL
|
||||
w92amp4b489 W6 GPIO197PB4 REG NULL NULL
|
||||
w91amn4b491 V7 GPIO198NB4 REG NULL NULL
|
||||
w90amp4b491 V8 GPIO198PB4 REG NULL NULL
|
||||
w89amn4b493 Y8 GPIO199NB4/DQS REG NULL NULL
|
||||
w88amp4b493 W8 GPIO199PB4/DQS REG NULL NULL
|
||||
w87amn4b495 Y10 GPIO200NB4 REG NULL NULL
|
||||
w86amp4b495 W10 GPIO200PB4 REG NULL NULL
|
||||
w85amn4b497 W9 GPIO201NB4 REG NULL NULL
|
||||
w84amp4b497 V9 GPIO201PB4 REG NULL NULL
|
||||
w83amn4b499 Y11 GPIO202NB4 REG NULL NULL
|
||||
w82amp4b499 W11 GPIO202PB4 REG NULL NULL
|
||||
w81amn4b501 W13 GPIO203NB4 REG NULL NULL
|
||||
w80amp4b501 V13 GPIO203PB4 REG NULL NULL
|
||||
w77amn4b505 V11 GPIO205NB4/DQS REG NULL NULL
|
||||
w76amp4b505 V12 GPIO205PB4/DQS REG NULL NULL
|
||||
w73amn4b509 W14 GPIO207NB4 REG NULL NULL
|
||||
w72amp4b509 V14 GPIO207PB4 REG NULL NULL
|
||||
w71amn4b511 V4 GPIO208NB4 REG NULL NULL
|
||||
w70amp4b511 V3 GPIO208PB4 REG NULL NULL
|
||||
w69amn4b513 T2 GPIO209NB4 REG NULL NULL
|
||||
w68amp4b513 T3 GPIO209PB4 REG NULL NULL
|
||||
w65amn4b517 R1 GPIO211NB4/DQS REG NULL NULL
|
||||
w64amp4b517 P1 GPIO211PB4/DQS REG NULL NULL
|
||||
w61amn4b521 R2 GPIO213NB4 REG NULL NULL
|
||||
w60amp4b521 R3 GPIO213PB4 REG NULL NULL
|
||||
w59amn4b523 V6 GPIO214NB4 REG NULL NULL
|
||||
w58amp4b523 U6 GPIO214PB4 REG NULL NULL
|
||||
w55amn4b527 U9 GPIO216NB4 REG NULL NULL
|
||||
w54amp4b527 U10 GPIO216PB4/CLKIN_W_4/CCC_NW_CLKIN_W_4 REG NULL NULL
|
||||
w53amn4b529 T4 GPIO217NB4/DQS REG NULL NULL
|
||||
w52amp4b529 T5 GPIO217PB4/DQS REG NULL NULL
|
||||
w51amn4b531 U7 GPIO218NB4 REG NULL NULL
|
||||
w50amp4b531 T7 GPIO218PB4 REG NULL NULL
|
||||
w49amn4b533 T8 GPIO219NB4 REG NULL NULL
|
||||
w48amp4b533 T9 GPIO219PB4/CLKIN_W_3/CCC_SW_CLKIN_W_3 REG NULL NULL
|
||||
w47amn5b535 N1 GPIO220NB5 REG NULL NULL
|
||||
w46amp5b535 N2 GPIO220PB5 REG NULL NULL
|
||||
w45amn5b537 M1 GPIO221NB5 REG NULL NULL
|
||||
w44amp5b537 M2 GPIO221PB5 REG NULL NULL
|
||||
w43amn5b539 P3 GPIO222NB5 REG NULL NULL
|
||||
w42amp5b539 P4 GPIO222PB5 REG NULL NULL
|
||||
w41amn5b541 L2 GPIO223NB5/DQS REG NULL NULL
|
||||
w40amp5b541 L3 GPIO223PB5/DQS REG NULL NULL
|
||||
w39amn5b543 N3 GPIO224NB5 REG NULL NULL
|
||||
w38amp5b543 N4 GPIO224PB5 REG NULL NULL
|
||||
w37amn5b545 M4 GPIO225NB5 REG NULL NULL
|
||||
w36amp5b545 L4 GPIO225PB5 REG NULL NULL
|
||||
w35amn5b547 R8 GPIO226NB5 REG NULL NULL
|
||||
w34amp5b547 R7 GPIO226PB5 REG NULL NULL
|
||||
w33amn5b549 R6 GPIO227NB5 REG NULL NULL
|
||||
w32amp5b549 R5 GPIO227PB5 REG NULL NULL
|
||||
w31amn5b551 N6 GPIO228NB5 REG NULL NULL
|
||||
w30amp5b551 N7 GPIO228PB5 REG NULL NULL
|
||||
w29amn5b553 P5 GPIO229NB5/DQS REG NULL NULL
|
||||
w28amp5b553 P6 GPIO229PB5/DQS REG NULL NULL
|
||||
w27amn5b555 P8 GPIO230NB5 REG NULL NULL
|
||||
w26amp5b555 P9 GPIO230PB5 REG NULL NULL
|
||||
w25amn5b557 M7 GPIO231NB5 REG NULL NULL
|
||||
w24amp5b557 N8 GPIO231PB5 REG NULL NULL
|
||||
w23amn5b559 L5 GPIO232NB5 REG NULL NULL
|
||||
w22amp5b559 K5 GPIO232PB5 REG NULL NULL
|
||||
w21amn5b561 K6 GPIO233NB5 REG NULL NULL
|
||||
w20amp5b561 K7 GPIO233PB5 REG NULL NULL
|
||||
w19amn5b563 M5 GPIO234NB5 REG NULL NULL
|
||||
w18amp5b563 M6 GPIO234PB5 REG NULL NULL
|
||||
w17amn5b565 J5 GPIO235NB5/DQS REG NULL NULL
|
||||
w16amp5b565 J6 GPIO235PB5/DQS REG NULL NULL
|
||||
w15amn5b567 L7 GPIO236NB5 REG NULL NULL
|
||||
w14amp5b567 L8 GPIO236PB5 REG NULL NULL
|
||||
w13amn5b569 K8 GPIO237NB5 REG NULL NULL
|
||||
w12amp5b569 J8 GPIO237PB5 REG NULL NULL
|
||||
w11amn5b571 K3 GPIO238NB5 REG NULL NULL
|
||||
w10amp5b571 K2 GPIO238PB5/CCC_SW_PLL0_OUT1 REG NULL NULL
|
||||
w9amn5b573 K1 GPIO239NB5 REG NULL NULL
|
||||
w8amp5b573 J1 GPIO239PB5/CLKIN_W_2/CCC_SW_CLKIN_W_2/CCC_SW_PLL0_OUT0 REG NULL NULL
|
||||
w7amn5b575 H1 GPIO240NB5 REG NULL NULL
|
||||
w6amp5b575 H2 GPIO240PB5/CLKIN_W_1/CCC_SW_CLKIN_W_1 REG NULL NULL
|
||||
w5amn5b577 J3 GPIO241NB5/DQS REG NULL NULL
|
||||
w4amp5b577 J4 GPIO241PB5/DQS/CCC_SW_PLL0_OUT0 REG NULL NULL
|
||||
w3amn5b579 H3 GPIO242NB5 REG NULL NULL
|
||||
w2amp5b579 H4 GPIO242PB5 REG NULL NULL
|
||||
w1amn5b581 G1 GPIO243NB5 REG NULL NULL
|
||||
w0amp5b581 G2 GPIO243PB5/CLKIN_W_0/CCC_SW_CLKIN_W_0 REG NULL NULL
|
||||
s0amp2b582 G4 GPIO244PB2/CCC_SW_CLKIN_S_0 REG NULL NULL
|
||||
s1amn2b582 F4 GPIO244NB2 REG NULL NULL
|
||||
s2amp2b584 E1 GPIO245PB2/CCC_SW_CLKIN_S_1 REG NULL NULL
|
||||
s3amn2b584 D1 GPIO245NB2 REG NULL NULL
|
||||
s4amp2b586 F2 GPIO246PB2/DQS/CCC_SW_PLL1_OUT0 REG NULL NULL
|
||||
s5amn2b586 E2 GPIO246NB2/DQS REG NULL NULL
|
||||
s6amp2b588 F3 GPIO247PB2/CLKIN_S_2/CCC_SW_CLKIN_S_2/CCC_SW_PLL1_OUT0 REG NULL NULL
|
||||
s7amn2b588 E3 GPIO247NB2 REG NULL NULL
|
||||
s8amp2b590 D3 GPIO248PB2/CCC_SW_PLL1_OUT1 REG NULL NULL
|
||||
s9amn2b590 D4 GPIO248NB2 REG NULL NULL
|
||||
s10amp2b592 D5 GPIO249PB2/CLKIN_S_3/CCC_SW_CLKIN_S_3 REG NULL NULL
|
||||
s11amn2b592 E5 GPIO249NB2 REG NULL NULL
|
||||
s12amp2b594 C1 GPIO250PB2 REG NULL NULL
|
||||
s13amn2b594 B1 GPIO250NB2 REG NULL NULL
|
||||
s14amp2b596 A2 GPIO251PB2 REG NULL NULL
|
||||
s15amn2b596 A3 GPIO251NB2 REG NULL NULL
|
||||
s16amp2b598 C2 GPIO252PB2/DQS REG NULL NULL
|
||||
s17amn2b598 B2 GPIO252NB2/DQS REG NULL NULL
|
||||
s18amp2b600 B4 GPIO253PB2 REG NULL NULL
|
||||
s19amn2b600 A4 GPIO253NB2 REG NULL NULL
|
||||
s20amp2b602 C3 GPIO254PB2 REG NULL NULL
|
||||
s21amn2b602 C4 GPIO254NB2 REG NULL NULL
|
||||
s22amp2b604 B5 GPIO255PB2 REG NULL NULL
|
||||
s23amn2b604 A5 GPIO255NB2 REG NULL NULL
|
||||
serdes_24_ext_refclk_p_e_b237 AF29 XCVR_2B_REFCLK_P RES NULL NULL
|
||||
serdes_24_ext_refclk_n_e_b236 AF30 XCVR_2B_REFCLK_N RES NULL NULL
|
||||
serdes_2_tx3_p_e_b235 AH33 XCVR_2_TX3_P RES NULL NULL
|
||||
serdes_2_tx3_n_e_b234 AH34 XCVR_2_TX3_N RES NULL NULL
|
||||
serdes_2_vddatx3 NC serdes_2_vddatx3 RES NULL NULL
|
||||
serdes_2_rx3_p_e_b233 AH29 XCVR_2_RX3_P RES NULL NULL
|
||||
serdes_2_rx3_n_e_b232 AH30 XCVR_2_RX3_N RES NULL NULL
|
||||
serdes_2_rx2_p_e_b231 AG31 XCVR_2_RX2_P RES NULL NULL
|
||||
serdes_2_rx2_n_e_b230 AG32 XCVR_2_RX2_N RES NULL NULL
|
||||
serdes_2_vddatx2 NC serdes_2_vddatx2 RES NULL NULL
|
||||
serdes_2_tx2_p_e_b229 AF33 XCVR_2_TX2_P RES NULL NULL
|
||||
serdes_2_tx2_n_e_b228 AF34 XCVR_2_TX2_N RES NULL NULL
|
||||
serdes_2_int_refclk_p_e_b227 AE27 XCVR_2A_REFCLK_P RES NULL NULL
|
||||
serdes_2_int_refclk_n_e_b226 AE28 XCVR_2A_REFCLK_N RES NULL NULL
|
||||
serdes_2_tx1_p_e_b225 AE31 XCVR_2_TX1_P RES NULL NULL
|
||||
serdes_2_tx1_n_e_b224 AE32 XCVR_2_TX1_N RES NULL NULL
|
||||
serdes_2_vddatx1 NC serdes_2_vddatx1 RES NULL NULL
|
||||
serdes_2_rx1_p_e_b223 AD29 XCVR_2_RX1_P RES NULL NULL
|
||||
serdes_2_rx1_n_e_b222 AD30 XCVR_2_RX1_N RES NULL NULL
|
||||
serdes_2_rx0_p_e_b221 AC31 XCVR_2_RX0_P RES NULL NULL
|
||||
serdes_2_rx0_n_e_b220 AC32 XCVR_2_RX0_N RES NULL NULL
|
||||
serdes_2_vddatx0 NC serdes_2_vddatx0 RES NULL NULL
|
||||
serdes_2_tx0_p_e_b219 AD33 XCVR_2_TX0_P RES NULL NULL
|
||||
serdes_2_tx0_n_e_b218 AD34 XCVR_2_TX0_N RES NULL NULL
|
||||
serdes_02_ext_refclk_p_e_b217 AC27 XCVR_2C_REFCLK_P RES NULL NULL
|
||||
serdes_02_ext_refclk_n_e_b216 AC28 XCVR_2C_REFCLK_N RES NULL NULL
|
||||
serdes_0n_ext_refclk_p_e_b215 AA27 XCVR_0B_REFCLK_P RES NULL NULL
|
||||
serdes_0n_ext_refclk_n_e_b214 AA28 XCVR_0B_REFCLK_N RES NULL NULL
|
||||
serdes_0_tx3_p_e_b213 AB33 XCVR_0_TX3_P RES NULL NULL
|
||||
serdes_0_tx3_n_e_b212 AB34 XCVR_0_TX3_N RES NULL NULL
|
||||
serdes_0_vddatx3 NC serdes_0_vddatx3 RES NULL NULL
|
||||
serdes_0_rx3_p_e_b211 AB29 XCVR_0_RX3_P RES NULL NULL
|
||||
serdes_0_rx3_n_e_b210 AB30 XCVR_0_RX3_N RES NULL NULL
|
||||
serdes_0_rx2_p_e_b209 Y29 XCVR_0_RX2_P RES NULL NULL
|
||||
serdes_0_rx2_n_e_b208 Y30 XCVR_0_RX2_N RES NULL NULL
|
||||
serdes_0_vddatx2 NC serdes_0_vddatx2 RES NULL NULL
|
||||
serdes_0_tx2_p_e_b207 AA31 XCVR_0_TX2_P RES NULL NULL
|
||||
serdes_0_tx2_n_e_b206 AA32 XCVR_0_TX2_N RES NULL NULL
|
||||
serdes_0_int_refclk_p_e_b205 W27 XCVR_0A_REFCLK_P RES NULL NULL
|
||||
serdes_0_int_refclk_n_e_b204 W28 XCVR_0A_REFCLK_N RES NULL NULL
|
||||
serdes_0_tx1_p_e_b203 Y33 XCVR_0_TX1_P RES NULL NULL
|
||||
serdes_0_tx1_n_e_b202 Y34 XCVR_0_TX1_N RES NULL NULL
|
||||
serdes_0_vddatx1 NC serdes_0_vddatx1 RES NULL NULL
|
||||
serdes_0_rx1_p_e_b201 W31 XCVR_0_RX1_P RES NULL NULL
|
||||
serdes_0_rx1_n_e_b200 W32 XCVR_0_RX1_N RES NULL NULL
|
||||
serdes_0_rx0_p_e_b199 V29 XCVR_0_RX0_P RES NULL NULL
|
||||
serdes_0_rx0_n_e_b198 V30 XCVR_0_RX0_N RES NULL NULL
|
||||
serdes_0_vddatx0 NC serdes_0_vddatx0 RES NULL NULL
|
||||
serdes_0_tx0_p_e_b197 V33 XCVR_0_TX0_P RES NULL NULL
|
||||
serdes_0_tx0_n_e_b196 V34 XCVR_0_TX0_N RES NULL NULL
|
||||
serdes_0s_ext_refclk_p_e_b195 U27 XCVR_0C_REFCLK_P RES NULL NULL
|
||||
serdes_0s_ext_refclk_n_e_b194 U28 XCVR_0C_REFCLK_N RES NULL NULL
|
||||
serdes_01_ext_refclk_p_e_b193 R27 XCVR_1B_REFCLK_P RES NULL NULL
|
||||
serdes_01_ext_refclk_n_e_b192 R28 XCVR_1B_REFCLK_N RES NULL NULL
|
||||
serdes_1_tx3_p_e_b191 U31 XCVR_1_TX3_P RES NULL NULL
|
||||
serdes_1_tx3_n_e_b190 U32 XCVR_1_TX3_N RES NULL NULL
|
||||
serdes_1_vddatx3 NC serdes_1_vddatx3 RES NULL NULL
|
||||
serdes_1_rx3_p_e_b189 T29 XCVR_1_RX3_P RES NULL NULL
|
||||
serdes_1_rx3_n_e_b188 T30 XCVR_1_RX3_N RES NULL NULL
|
||||
serdes_1_rx2_p_e_b187 R31 XCVR_1_RX2_P RES NULL NULL
|
||||
serdes_1_rx2_n_e_b186 R32 XCVR_1_RX2_N RES NULL NULL
|
||||
serdes_1_vddatx2 NC serdes_1_vddatx2 RES NULL NULL
|
||||
serdes_1_tx2_p_e_b185 T33 XCVR_1_TX2_P RES NULL NULL
|
||||
serdes_1_tx2_n_e_b184 T34 XCVR_1_TX2_N RES NULL NULL
|
||||
serdes_1_int_refclk_p_e_b183 N27 XCVR_1A_REFCLK_P RES NULL NULL
|
||||
serdes_1_int_refclk_n_e_b182 N28 XCVR_1A_REFCLK_N RES NULL NULL
|
||||
serdes_1_tx1_p_e_b181 P33 XCVR_1_TX1_P RES NULL NULL
|
||||
serdes_1_tx1_n_e_b180 P34 XCVR_1_TX1_N RES NULL NULL
|
||||
serdes_1_vddatx1 NC serdes_1_vddatx1 RES NULL NULL
|
||||
serdes_1_rx1_p_e_b179 P29 XCVR_1_RX1_P RES NULL NULL
|
||||
serdes_1_rx1_n_e_b178 P30 XCVR_1_RX1_N RES NULL NULL
|
||||
serdes_1_rx0_p_e_b177 M29 XCVR_1_RX0_P RES NULL NULL
|
||||
serdes_1_rx0_n_e_b176 M30 XCVR_1_RX0_N RES NULL NULL
|
||||
serdes_1_vddatx0 NC serdes_1_vddatx0 RES NULL NULL
|
||||
serdes_1_tx0_p_e_b175 N31 XCVR_1_TX0_P RES NULL NULL
|
||||
serdes_1_tx0_n_e_b174 N32 XCVR_1_TX0_N RES NULL NULL
|
||||
serdes_13_ext_refclk_p_e_b173 L27 XCVR_1C_REFCLK_P RES NULL NULL
|
||||
serdes_13_ext_refclk_n_e_b172 L28 XCVR_1C_REFCLK_N RES NULL NULL
|
||||
serdes_3_tx3_p_e_b171 M33 XCVR_3_TX3_P RES NULL NULL
|
||||
serdes_3_tx3_n_e_b170 M34 XCVR_3_TX3_N RES NULL NULL
|
||||
serdes_3_vddatx3 NC serdes_3_vddatx3 RES NULL NULL
|
||||
serdes_3_rx3_p_e_b169 L31 XCVR_3_RX3_P RES NULL NULL
|
||||
serdes_3_rx3_n_e_b168 L32 XCVR_3_RX3_N RES NULL NULL
|
||||
serdes_3_rx2_p_e_b167 K29 XCVR_3_RX2_P RES NULL NULL
|
||||
serdes_3_rx2_n_e_b166 K30 XCVR_3_RX2_N RES NULL NULL
|
||||
serdes_3_vddatx2 NC serdes_3_vddatx2 RES NULL NULL
|
||||
serdes_3_tx2_p_e_b165 K33 XCVR_3_TX2_P RES NULL NULL
|
||||
serdes_3_tx2_n_e_b164 K34 XCVR_3_TX2_N RES NULL NULL
|
||||
serdes_3_int_refclk_p_e_b163 J27 XCVR_3A_REFCLK_P RES NULL NULL
|
||||
serdes_3_int_refclk_n_e_b162 J28 XCVR_3A_REFCLK_N RES NULL NULL
|
||||
serdes_3_tx1_p_e_b161 H33 XCVR_3_TX1_P RES NULL NULL
|
||||
serdes_3_tx1_n_e_b160 H34 XCVR_3_TX1_N RES NULL NULL
|
||||
serdes_3_vddatx1 NC serdes_3_vddatx1 RES NULL NULL
|
||||
serdes_3_rx1_p_e_b159 J31 XCVR_3_RX1_P RES NULL NULL
|
||||
serdes_3_rx1_n_e_b158 J32 XCVR_3_RX1_N RES NULL NULL
|
||||
serdes_3_rx0_p_e_b157 G31 XCVR_3_RX0_P RES NULL NULL
|
||||
serdes_3_rx0_n_e_b156 G32 XCVR_3_RX0_N RES NULL NULL
|
||||
serdes_3_vddatx0 NC serdes_3_vddatx0 RES NULL NULL
|
||||
serdes_3_tx0_p_e_b155 F33 XCVR_3_TX0_P RES NULL NULL
|
||||
serdes_3_tx0_n_e_b154 F34 XCVR_3_TX0_N RES NULL NULL
|
||||
serdes_35_ext_refclk_p_e_b153 H29 XCVR_3C_REFCLK_P RES NULL NULL
|
||||
serdes_35_ext_refclk_n_e_b152 H30 XCVR_3C_REFCLK_N RES NULL NULL
|
||||
serdes_vref NC serdes_vref RES NULL NULL
|
||||
x_vdd25pll0_sw NC x_vdd25pll0_sw RES NULL NULL
|
||||
x_vdd25pll0_sw NC x_vdd25pll0_sw RES NULL NULL
|
||||
x_vdd25pll1_sw NC x_vdd25pll1_sw RES NULL NULL
|
||||
x_vdd25pll1_sw NC x_vdd25pll1_sw RES NULL NULL
|
||||
x_vdd25pll0_se NC x_vdd25pll0_se RES NULL NULL
|
||||
x_vdd25pll0_se NC x_vdd25pll0_se RES NULL NULL
|
||||
x_vdd25pll1_se NC x_vdd25pll1_se RES NULL NULL
|
||||
x_vdd25pll1_se NC x_vdd25pll1_se RES NULL NULL
|
||||
x_vdd25pll0_nw NC x_vdd25pll0_nw RES NULL NULL
|
||||
x_vdd25pll0_nw NC x_vdd25pll0_nw RES NULL NULL
|
||||
x_vdd25pll1_nw NC x_vdd25pll1_nw RES NULL NULL
|
||||
x_vdd25pll1_nw NC x_vdd25pll1_nw RES NULL NULL
|
||||
x_vdd25pll0_ne NC x_vdd25pll0_ne RES NULL NULL
|
||||
x_vdd25pll0_ne NC x_vdd25pll0_ne RES NULL NULL
|
||||
x_vdd25pll1_ne NC x_vdd25pll1_ne RES NULL NULL
|
||||
x_vdd25pll1_ne NC x_vdd25pll1_ne RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
nc NC nc RES NULL NULL
|
||||
serdes_vref NC serdes_vref RES NULL NULL
|
||||
serdes_vref NC serdes_vref RES NULL NULL
|
||||
vddsref NC vddsref RES NULL NULL
|
||||
vddsref NC vddsref RES NULL NULL
|
||||
vddsref NC vddsref RES NULL NULL
|
||||
vdda25 NC vdda25 RES NULL NULL
|
||||
vdda25 NC vdda25 RES NULL NULL
|
||||
vdda25 NC vdda25 RES NULL NULL
|
||||
vdda25 NC vdda25 RES NULL NULL
|
||||
vdda NC vdda RES NULL NULL
|
||||
vdda NC vdda RES NULL NULL
|
||||
49
designer/top/top_layout_combinational_loops.xml
Normal file
49
designer/top/top_layout_combinational_loops.xml
Normal file
@@ -0,0 +1,49 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
|
||||
<doc>
|
||||
<title>Combinational Loop Report</title>
|
||||
<text>SmartTime Version 2025.1.0.14</text>
|
||||
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
|
||||
<text>Date: Wed Apr 15 22:53:22 2026
|
||||
</text>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
<row>
|
||||
<cell>Design</cell>
|
||||
<cell>top</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Family</cell>
|
||||
<cell>PolarFire</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Die</cell>
|
||||
<cell>MPF300TS</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Package</cell>
|
||||
<cell>FCG1152</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Temperature Range</cell>
|
||||
<cell>-40 - 100 C</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Voltage Range</cell>
|
||||
<cell>1.0185 - 1.0815 V</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Speed Grade</cell>
|
||||
<cell>-1</cell>
|
||||
</row>
|
||||
<row>
|
||||
<cell>Design State</cell>
|
||||
<cell>Pre-Layout</cell>
|
||||
</row>
|
||||
</table>
|
||||
<text></text>
|
||||
<text></text>
|
||||
<text></text>
|
||||
<text>No combinational loops were detected in the design.</text>
|
||||
</doc>
|
||||
8
designer/top/top_layout_ioff.rpt
Normal file
8
designer/top/top_layout_ioff.rpt
Normal file
@@ -0,0 +1,8 @@
|
||||
I/O Register Combining Report
|
||||
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
|
||||
Date: Wed Apr 15 23:06:21 2026
|
||||
|
||||
I/O Register Combining Summary
|
||||
+
|
||||
+
|
||||
|
||||
13
designer/top/top_layout_ioff.xml
Normal file
13
designer/top/top_layout_ioff.xml
Normal file
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
|
||||
<doc>
|
||||
<title>I/O Register Combining Report</title>
|
||||
<text>Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)</text>
|
||||
<text>Date: Wed Apr 15 23:06:21 2026
|
||||
</text>
|
||||
<section><name>I/O Register Combining Summary</name></section>
|
||||
<table>
|
||||
<header>
|
||||
</header>
|
||||
</table>
|
||||
</doc>
|
||||
100
designer/top/top_layout_log.log
Normal file
100
designer/top/top_layout_log.log
Normal file
@@ -0,0 +1,100 @@
|
||||
INFO: Reading User SDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\top_derived_constraints.sdc.
|
||||
INFO: Reading User SDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\timing_user_constraints.sdc.
|
||||
INFO: The option "Abort flow if errors are found in SDC" is turned ON in Project Settings> Design flow page. The Place & Route tool will fail if errors are found in associated SDC files. Please uncheck the option to ignore the errors and continue running the tool.
|
||||
|
||||
No errors or warnings found.
|
||||
INFO: The option "Abort flow if errors are found in PDC" is turned ON in Project Settings> Design flow page. The Place & Route tool will fail if errors are found in associated PDC files. Please uncheck the option to ignore the errors and continue running the tool
|
||||
***** Place and Route Configurations *****
|
||||
|
||||
Timing-driven : ON
|
||||
|
||||
Power-driven : OFF
|
||||
|
||||
I/O Register Combining : OFF
|
||||
|
||||
Global Pins Demotion : ON
|
||||
|
||||
Driver Replication : OFF
|
||||
|
||||
High-effort : ON
|
||||
|
||||
Repair min-delay : ON
|
||||
|
||||
Incremental : OFF
|
||||
|
||||
Inter-clock optimization : ON
|
||||
|
||||
|
||||
|
||||
INFO: Reading User PDC file E:\AbhishekV\rising\ethernet_tpsram_test\constraint\io\io_constraints.pdc. 0 error(s) and 0 warning(s)
|
||||
|
||||
|
||||
|
||||
Running Timing based Global Demotion.
|
||||
|
||||
Demoted 0 global pins.
|
||||
|
||||
|
||||
|
||||
Timing based Global Demotion completed successfully.
|
||||
|
||||
|
||||
|
||||
Running the I/O Bank and Globals Assigner.
|
||||
|
||||
Info: I/O Bank and Globals Assigner identified 18 fixed I/O macros, 32 unfixed I/O macros
|
||||
|
||||
Info: I/O Bank and Globals Assigner identified bank 'Bank4' as being fixed at VCCI:2.50V VCCR:n/a
|
||||
|
||||
Info: I/O Bank and Globals Assigner detected (1) out of (7) I/O Bank(s) with locked I/O technologies.
|
||||
|
||||
|
||||
|
||||
I/O Bank and Globals Assigner completed successfully.
|
||||
|
||||
Total time spent in I/O Bank and Globals Assigner: 7 seconds
|
||||
|
||||
|
||||
|
||||
|
||||
Placer V5.0 - 2025.1.0
|
||||
|
||||
|
||||
Design: top Started: Wed Apr 15 22:53:55 2026
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
Initializing High-Effort Timing-Driven Placement ...
|
||||
|
||||
|
||||
Clustering ...
|
||||
|
||||
|
||||
Placing ...
|
||||
|
||||
|
||||
Improving placement ...
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
CDC Report:
|
||||
|
||||
|
||||
Total number of CDC synchronizer driver/sink pairs : 40
|
||||
|
||||
|
||||
Maximum distance between CDC synchronizer driver & sink: 1 cluster(s)
|
||||
|
||||
|
||||
Generated the list of CDC synchronizer pairs in cdc_synchronizer.csv.
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
End of placement.
|
||||
|
||||
1
designer/top/top_live_probe_status.txt
Normal file
1
designer/top/top_live_probe_status.txt
Normal file
@@ -0,0 +1 @@
|
||||
LIVEPROBE: Status=ENABLED
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user