working FIFO and TPSRAM without packet flter

constraint/io/io_constraints.pdc

@@ -0,0 +1,210 @@
+# Microsemi I/O Physical Design Constraints file
+
+# User I/O Constraints file 
+
+
+# Family: PolarFire , Die: MPF300T_ES , Package: FCG1152
+
+# Date generated: Wed Nov 15 13:02:44 2017 
+
+
+
+# 
+# User Locked I/O Bank Settings
+# 
+
+set_iobank -bank_name Bank4  \
+    -vcci 2.50               \
+    -fixed true
+
+
+# 
+# Unlocked I/O Bank Settings
+# The I/O Bank Settings can be locked by directly editing this file
+# or by making changes in the I/O Attribute Editor
+# 
+
+
+# 
+# User Locked I/O settings
+# 
+
+set_io -port_name LINK_OK  \
+    -pin_name D25          \
+    -fixed true            \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name PHY_MDC  \
+    -pin_name Y12          \
+    -fixed true            \
+    -io_std LVCMOS25       \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name PHY_MDIO  \
+    -pin_name Y13           \
+    -fixed true             \
+    -io_std LVCMOS25        \
+    -DIRECTION INOUT
+
+
+set_io -port_name PHY_RST  \
+    -pin_name U11          \
+    -fixed true            \
+    -io_std LVCMOS25       \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name RD_BC_ERROR  \
+    -pin_name F22              \
+    -fixed true                \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name REFCLK_N  \
+    -pin_name U5            \
+    -fixed true             \
+    -io_std LVDS25          \
+    -DIRECTION INPUT
+
+
+set_io -port_name REFCLK_P  \
+    -pin_name U4            \
+    -fixed true             \
+    -io_std LVDS25          \
+    -DIRECTION INPUT
+
+
+set_io -port_name REF_CLK_0  \
+    -pin_name E25            \
+    -fixed true              \
+    -DIRECTION INPUT
+
+
+set_io -port_name REF_CLK_SEL  \
+    -pin_name AA10             \
+    -fixed true                \
+    -io_std LVCMOS25           \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name RESET_N  \
+    -pin_name K22          \
+    -fixed true            \
+    -DIRECTION INPUT
+
+
+set_io -port_name RX  \
+    -pin_name H18     \
+    -fixed true       \
+    -DIRECTION INPUT
+
+
+set_io -port_name RX_N  \
+    -pin_name U1        \
+    -fixed true         \
+    -io_std LVDS25      \
+    -DIRECTION INPUT
+
+
+set_io -port_name RX_P  \
+    -pin_name U2        \
+    -fixed true         \
+    -io_std LVDS25      \
+    -DIRECTION INPUT
+
+
+set_io -port_name SPISCLKO  \
+    -pin_name K21           \
+    -fixed true             \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name SPISDI  \
+    -pin_name L20         \
+    -fixed true           \
+    -DIRECTION INPUT
+
+
+set_io -port_name SPISDO  \
+    -pin_name K20         \
+    -fixed true           \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name SPISS  \
+    -pin_name J20        \
+    -fixed true          \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name TX   \
+    -pin_name G17      \
+    -fixed true        \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name TX_N  \
+    -pin_name V2        \
+    -fixed true         \
+    -io_std LVDS25      \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name TX_P  \
+    -pin_name V1        \
+    -fixed true         \
+    -io_std LVDS25      \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name coma_mode  \
+    -pin_name U12            \
+    -fixed true              \
+    -io_std LVCMOS25         \
+    -DIRECTION OUTPUT
+
+
+# 
+# Dedicated Peripheral I/O Settings
+# 
+
+
+# 
+# Unlocked I/O settings
+# The I/Os in this section are unplaced or placed but are not locked
+# the other listed attributes have been applied
+# 
+
+
+#
+#Ports using Dedicated Pins
+
+#
+
+set_io -port_name TCK  \
+    -pin_name J10      \
+    -DIRECTION INPUT
+
+
+set_io -port_name TDI  \
+    -pin_name K11      \
+    -DIRECTION INPUT
+
+
+set_io -port_name TDO  \
+    -pin_name K9       \
+    -DIRECTION OUTPUT
+
+
+set_io -port_name TMS  \
+    -pin_name J9       \
+    -DIRECTION INPUT
+
+
+set_io -port_name TRSTB  \
+    -pin_name N14        \
+    -DIRECTION INPUT
+
+