working FIFO and TPSRAM without packet flter
This commit is contained in:
210
constraint/io/io_constraints.pdc
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210
constraint/io/io_constraints.pdc
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# Microsemi I/O Physical Design Constraints file
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# User I/O Constraints file
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# Family: PolarFire , Die: MPF300T_ES , Package: FCG1152
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# Date generated: Wed Nov 15 13:02:44 2017
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#
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# User Locked I/O Bank Settings
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#
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set_iobank -bank_name Bank4 \
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-vcci 2.50 \
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-fixed true
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#
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# Unlocked I/O Bank Settings
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# The I/O Bank Settings can be locked by directly editing this file
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# or by making changes in the I/O Attribute Editor
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#
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#
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# User Locked I/O settings
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#
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set_io -port_name LINK_OK \
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-pin_name D25 \
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-fixed true \
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-DIRECTION OUTPUT
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set_io -port_name PHY_MDC \
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-pin_name Y12 \
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-fixed true \
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-io_std LVCMOS25 \
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-DIRECTION OUTPUT
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set_io -port_name PHY_MDIO \
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-pin_name Y13 \
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-fixed true \
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-io_std LVCMOS25 \
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-DIRECTION INOUT
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set_io -port_name PHY_RST \
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-pin_name U11 \
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-fixed true \
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-io_std LVCMOS25 \
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-DIRECTION OUTPUT
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set_io -port_name RD_BC_ERROR \
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-pin_name F22 \
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-fixed true \
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-DIRECTION OUTPUT
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set_io -port_name REFCLK_N \
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-pin_name U5 \
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-fixed true \
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-io_std LVDS25 \
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-DIRECTION INPUT
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set_io -port_name REFCLK_P \
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-pin_name U4 \
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-fixed true \
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-io_std LVDS25 \
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-DIRECTION INPUT
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set_io -port_name REF_CLK_0 \
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-pin_name E25 \
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-fixed true \
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-DIRECTION INPUT
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set_io -port_name REF_CLK_SEL \
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-pin_name AA10 \
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-fixed true \
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-io_std LVCMOS25 \
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-DIRECTION OUTPUT
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set_io -port_name RESET_N \
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-pin_name K22 \
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-fixed true \
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-DIRECTION INPUT
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set_io -port_name RX \
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-pin_name H18 \
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-fixed true \
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-DIRECTION INPUT
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set_io -port_name RX_N \
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-pin_name U1 \
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-fixed true \
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-io_std LVDS25 \
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-DIRECTION INPUT
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set_io -port_name RX_P \
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-pin_name U2 \
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-fixed true \
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-io_std LVDS25 \
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-DIRECTION INPUT
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set_io -port_name SPISCLKO \
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-pin_name K21 \
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-fixed true \
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-DIRECTION OUTPUT
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set_io -port_name SPISDI \
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-pin_name L20 \
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-fixed true \
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-DIRECTION INPUT
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set_io -port_name SPISDO \
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-pin_name K20 \
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-fixed true \
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-DIRECTION OUTPUT
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set_io -port_name SPISS \
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-pin_name J20 \
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-fixed true \
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-DIRECTION OUTPUT
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set_io -port_name TX \
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-pin_name G17 \
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-fixed true \
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-DIRECTION OUTPUT
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set_io -port_name TX_N \
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-pin_name V2 \
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-fixed true \
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-io_std LVDS25 \
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-DIRECTION OUTPUT
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set_io -port_name TX_P \
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-pin_name V1 \
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-fixed true \
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-io_std LVDS25 \
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-DIRECTION OUTPUT
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set_io -port_name coma_mode \
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-pin_name U12 \
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-fixed true \
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-io_std LVCMOS25 \
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-DIRECTION OUTPUT
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#
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# Dedicated Peripheral I/O Settings
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#
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#
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# Unlocked I/O settings
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# The I/Os in this section are unplaced or placed but are not locked
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# the other listed attributes have been applied
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#
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#
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#Ports using Dedicated Pins
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#
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set_io -port_name TCK \
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-pin_name J10 \
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-DIRECTION INPUT
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set_io -port_name TDI \
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-pin_name K11 \
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-DIRECTION INPUT
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set_io -port_name TDO \
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-pin_name K9 \
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-DIRECTION OUTPUT
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set_io -port_name TMS \
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-pin_name J9 \
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-DIRECTION INPUT
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set_io -port_name TRSTB \
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-pin_name N14 \
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-DIRECTION INPUT
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1
constraint/placer_sdc_errors.log
Normal file
1
constraint/placer_sdc_errors.log
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@@ -0,0 +1 @@
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No errors or warnings found.
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69
constraint/run_tao_ag.tcl
Normal file
69
constraint/run_tao_ag.tcl
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@@ -0,0 +1,69 @@
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set_device -family {PolarFire} -die {MPF300TS} -speed {-1} -range {IND}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_bufd.v}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_uj_jtag.v}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug_ujtag_wrapper.v}
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read_verilog -mode system_verilog -lib COREJTAGDEBUG_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v}
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read_verilog -mode system_verilog -lib CORESPI_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CORESPI_0\CORESPI_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CORETSE_0\CORETSE_0.v}
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read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v}
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read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
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read_verilog -mode system_verilog -lib COREAPB3_LIB {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreAPB3_0\CoreAPB3_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\fifo_256x8_g5.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\Core_reset_pf\Core_reset_pf.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_hart_cfg_pkg.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_pkg.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\pkg\miv_rv32_subsys_pkg.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.1.200\memory\miv_rv32_ram_singleport_lp_ecc.v}
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read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\rtl\miv_rv32.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_CCC_0\PF_CCC_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v}
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||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\hdl\SSDetect.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0.v}
|
||||
read_verilog -mode system_verilog {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\top\top.v}
|
||||
set_top_level {top}
|
||||
read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc}
|
||||
read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.sdc}
|
||||
read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.sdc}
|
||||
read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.sdc}
|
||||
read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.sdc}
|
||||
read_sdc -component {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.sdc}
|
||||
derive_constraints
|
||||
write_sdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\top_derived_constraints.sdc}
|
||||
write_ndc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\top_derived_constraints.ndc}
|
||||
write_pdc {E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\constraint\fp\top_derived_constraints.pdc}
|
||||
1
constraint/synthesis_sdc_errors.log
Normal file
1
constraint/synthesis_sdc_errors.log
Normal file
@@ -0,0 +1 @@
|
||||
No errors or warnings found.
|
||||
1
constraint/timing_sdc_errors.log
Normal file
1
constraint/timing_sdc_errors.log
Normal file
@@ -0,0 +1 @@
|
||||
No errors or warnings found.
|
||||
28
constraint/timing_user_constraints.sdc
Normal file
28
constraint/timing_user_constraints.sdc
Normal file
@@ -0,0 +1,28 @@
|
||||
#Constraining the JTAG clock to 10 Mhz
|
||||
create_clock -name {TCK} -period 100 -waveform {0 50 } [ get_ports { TCK } ]
|
||||
|
||||
#Create PHY_MDC clock with clk/20 factor
|
||||
create_generated_clock -name {PHY_MDC_CLOCK} -divide_by 28 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -phase 0 [ get_ports { PHY_MDC } ]
|
||||
|
||||
##Input Delay Constraint on the Reset_n pin
|
||||
set_input_delay 0 -min -add_delay -clock {REF_CLK_0} [ get_ports { RESET_N } ]
|
||||
set_input_delay 20 -max -add_delay -clock {REF_CLK_0} [ get_ports { RESET_N } ]
|
||||
|
||||
###Out delay constraint on the PHY_MDC and PHY_MDIO
|
||||
set_output_delay 10 -max -clock {PHY_MDC_CLOCK} [ get_ports { PHY_MDIO } ]
|
||||
set_output_delay -10 -min -clock {PHY_MDC_CLOCK} [ get_ports { PHY_MDIO } ]
|
||||
set_input_delay 0 -min -add_delay -clock {PHY_MDC_CLOCK} [ get_ports { PHY_MDIO } ]
|
||||
set_input_delay 20 -max -add_delay -clock {PHY_MDC_CLOCK} [ get_ports { PHY_MDIO } ]
|
||||
|
||||
#The below paths are asynchronous and CDC is taken care inside the IP
|
||||
#The Below paths are set to asynchronous to aid the timing Tool not check the Async to Reg paths
|
||||
#CDC analysis is run on the design and the report is analysed and it is CDC Clean
|
||||
set_clock_groups -name {SGMII_CDR_0_0_CLK_OUT_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_clock_groups -name {Y_DIV_GRP} -asynchronous -group [ get_clocks {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT0_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT1_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT2_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
set_clock_groups -name {NWC_PLL_OUT3_GRP} -asynchronous -group [ get_clocks { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} ]
|
||||
set_clock_groups -name {PF_CCC_0_OUT0_GRP} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
set_clock_groups -name {JTAG_Async} -asynchronous -group [ get_clocks { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ] -group [ get_clocks { TCK } ]
|
||||
#set_false_path -from { SGMII_CDR_0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK* } -through { SGMII_CDR_0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R }
|
||||
43
constraint/top_derived_constraints.sdc
Normal file
43
constraint/top_derived_constraints.sdc
Normal file
@@ -0,0 +1,43 @@
|
||||
# Microchip Technology Inc.
|
||||
# Date: 2026-Apr-13 21:43:45
|
||||
# This file was generated based on the following SDC source files:
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.sdc
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.sdc
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_IOD_CDR_CCC_C0.sdc
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_CCC_0/PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.sdc
|
||||
# E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_CLK_DIV_0/PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.sdc
|
||||
# *** Any modifications to this file will be lost if derived constraints is re-run. ***
|
||||
#
|
||||
|
||||
create_clock -name {REF_CLK_0} -period 20 [ get_ports { REF_CLK_0 } ]
|
||||
create_clock -name {PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R} -period 8 -waveform {0 3.2 } [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
create_clock -name {REFCLK_P} -period 8 [ get_ports { REFCLK_P } ]
|
||||
create_generated_clock -name {PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0} -multiply_by 8 -divide_by 5 -source [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 90 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 180 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3} -multiply_by 5 -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/REF_CLK_0 } ] -phase 270 [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 } ]
|
||||
create_generated_clock -name {PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV} -edges {1 7 11} -source [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/A } ] [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/RESET } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK_PAUSE } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/SWITCH } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/dll_90_code*[*] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/valid_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/late_flag*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/ARST_N } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/RX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0/TX_SYNC_RST } ]
|
||||
set_false_path -from [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK* } ] -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
|
||||
set_false_path -through [ get_pins { PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CDR_CLK } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/lock_sync*[1] } ]
|
||||
set_false_path -to [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/diff_sync*[1] } ]
|
||||
set_false_path -to [ get_pins { PF_IOD_CDR_CCC_C0_0/PF_CCC_0/dll_inst_0/CODE_UPDATE } ]
|
||||
set_false_path -from [ get_cells { PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane* } ]
|
||||
Reference in New Issue
Block a user