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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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component/work/PF_CCC_0/PF_CCC_0.cxf Normal file
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component/work/PF_CCC_0/PF_CCC_0.sdb Normal file
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component/work/PF_CCC_0/PF_CCC_0.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:54 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of PF_CCC_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CCC_0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.220} -component_name {PF_CCC_0} -params {\
"DLL_CLK_0_BANKCLK_EN:false" \
"DLL_CLK_0_DEDICATED_EN:false" \
"DLL_CLK_0_FABCLK_EN:false" \
"DLL_CLK_1_BANKCLK_EN:false" \
"DLL_CLK_1_DEDICATED_EN:false" \
"DLL_CLK_1_FABCLK_EN:false" \
"DLL_CLK_P_EN:false" \
"DLL_CLK_P_OPTIONS_EN:false" \
"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
"DLL_CLK_REF_OPTIONS_EN:false" \
"DLL_CLK_S_EN:false" \
"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
"DLL_CLK_S_OPTIONS_EN:false" \
"DLL_DELAY4:0" \
"DLL_DYNAMIC_CODE_EN:false" \
"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
"DLL_EXPORT_PWRDWN:false" \
"DLL_FB_CLK:Primary" \
"DLL_FB_EN:false" \
"DLL_FINE_PHASE_CODE:0" \
"DLL_IN:1" \
"DLL_JITTER:0" \
"DLL_MODE:PHASE_REF_MODE" \
"DLL_ONLY_EN:false" \
"DLL_OUT_0:1" \
"DLL_OUT_1:1" \
"DLL_PRIM_PHASE:90" \
"DLL_PRIM_PHASE_CODE:0" \
"DLL_SEC_PHASE:90" \
"DLL_SEC_PHASE_CODE:0" \
"DLL_SELECTED_IN:Output2" \
"FF_REQUIRES_LOCK_EN_0:0" \
"GL0_0_BANKCLK_USED:false" \
"GL0_0_BYPASS:0" \
"GL0_0_BYPASS_EN:false" \
"GL0_0_DEDICATED_USED:false" \
"GL0_0_DIV:15" \
"GL0_0_DIVSTART:0" \
"GL0_0_DYNAMIC_PH:false" \
"GL0_0_EXPOSE_EN:false" \
"GL0_0_FABCLK_GATED_USED:false" \
"GL0_0_FABCLK_USED:true" \
"GL0_0_FREQ_SEL:false" \
"GL0_0_IS_USED:true" \
"GL0_0_OUT_FREQ:80" \
"GL0_0_PHASE_INDEX:0" \
"GL0_0_PHASE_SEL:false" \
"GL0_0_PLL_PHASE:0" \
"GL0_1_BANKCLK_USED:false" \
"GL0_1_BYPASS:0" \
"GL0_1_BYPASS_EN:false" \
"GL0_1_DEDICATED_USED:false" \
"GL0_1_DIV:1" \
"GL0_1_DIVSTART:0" \
"GL0_1_DYNAMIC_PH:false" \
"GL0_1_EXPOSE_EN:false" \
"GL0_1_FABCLK_USED:false" \
"GL0_1_FREQ_SEL:false" \
"GL0_1_IS_USED:true" \
"GL0_1_OUT_FREQ:100" \
"GL0_1_PHASE_INDEX:0" \
"GL0_1_PHASE_SEL:false" \
"GL0_1_PLL_PHASE:0" \
"GL1_0_BANKCLK_USED:false" \
"GL1_0_BYPASS:0" \
"GL1_0_BYPASS_EN:false" \
"GL1_0_DEDICATED_USED:false" \
"GL1_0_DIV:1" \
"GL1_0_DIVSTART:0" \
"GL1_0_DYNAMIC_PH:false" \
"GL1_0_EXPOSE_EN:false" \
"GL1_0_FABCLK_GATED_USED:false" \
"GL1_0_FABCLK_USED:true" \
"GL1_0_FREQ_SEL:false" \
"GL1_0_IS_USED:false" \
"GL1_0_OUT_FREQ:100" \
"GL1_0_PHASE_INDEX:0" \
"GL1_0_PHASE_SEL:false" \
"GL1_0_PLL_PHASE:0" \
"GL1_1_BANKCLK_USED:false" \
"GL1_1_BYPASS:0" \
"GL1_1_BYPASS_EN:false" \
"GL1_1_DEDICATED_USED:false" \
"GL1_1_DIV:1" \
"GL1_1_DIVSTART:0" \
"GL1_1_DYNAMIC_PH:false" \
"GL1_1_EXPOSE_EN:false" \
"GL1_1_FABCLK_USED:false" \
"GL1_1_FREQ_SEL:false" \
"GL1_1_IS_USED:false" \
"GL1_1_OUT_FREQ:0" \
"GL1_1_PHASE_INDEX:0" \
"GL1_1_PHASE_SEL:false" \
"GL1_1_PLL_PHASE:0" \
"GL2_0_BANKCLK_USED:false" \
"GL2_0_BYPASS:0" \
"GL2_0_BYPASS_EN:false" \
"GL2_0_DEDICATED_USED:false" \
"GL2_0_DIV:1" \
"GL2_0_DIVSTART:0" \
"GL2_0_DYNAMIC_PH:false" \
"GL2_0_EXPOSE_EN:false" \
"GL2_0_FABCLK_GATED_USED:false" \
"GL2_0_FABCLK_USED:true" \
"GL2_0_FREQ_SEL:false" \
"GL2_0_IS_USED:false" \
"GL2_0_OUT_FREQ:100" \
"GL2_0_PHASE_INDEX:0" \
"GL2_0_PHASE_SEL:false" \
"GL2_0_PLL_PHASE:0" \
"GL2_1_BANKCLK_USED:false" \
"GL2_1_BYPASS:0" \
"GL2_1_BYPASS_EN:false" \
"GL2_1_DEDICATED_USED:false" \
"GL2_1_DIV:1" \
"GL2_1_DIVSTART:0" \
"GL2_1_DYNAMIC_PH:false" \
"GL2_1_EXPOSE_EN:false" \
"GL2_1_FABCLK_USED:false" \
"GL2_1_FREQ_SEL:false" \
"GL2_1_IS_USED:false" \
"GL2_1_OUT_FREQ:0" \
"GL2_1_PHASE_INDEX:0" \
"GL2_1_PHASE_SEL:false" \
"GL2_1_PLL_PHASE:0" \
"GL3_0_BANKCLK_USED:false" \
"GL3_0_BYPASS:0" \
"GL3_0_BYPASS_EN:false" \
"GL3_0_DEDICATED_USED:false" \
"GL3_0_DIV:1" \
"GL3_0_DIVSTART:0" \
"GL3_0_DYNAMIC_PH:false" \
"GL3_0_EXPOSE_EN:false" \
"GL3_0_FABCLK_GATED_USED:false" \
"GL3_0_FABCLK_USED:true" \
"GL3_0_FREQ_SEL:false" \
"GL3_0_IS_USED:false" \
"GL3_0_OUT_FREQ:100" \
"GL3_0_PHASE_INDEX:0" \
"GL3_0_PHASE_SEL:false" \
"GL3_0_PLL_PHASE:0" \
"GL3_1_BANKCLK_USED:false" \
"GL3_1_BYPASS:0" \
"GL3_1_BYPASS_EN:false" \
"GL3_1_DEDICATED_USED:false" \
"GL3_1_DIV:1" \
"GL3_1_DIVSTART:0" \
"GL3_1_DYNAMIC_PH:false" \
"GL3_1_EXPOSE_EN:false" \
"GL3_1_FABCLK_USED:false" \
"GL3_1_FREQ_SEL:false" \
"GL3_1_IS_USED:false" \
"GL3_1_OUT_FREQ:0" \
"GL3_1_PHASE_INDEX:0" \
"GL3_1_PHASE_SEL:false" \
"GL3_1_PLL_PHASE:0" \
"PLL_ALLOW_CCC_EXT_FB:false" \
"PLL_BANDWIDTH_0:0" \
"PLL_BANDWIDTH_1:1" \
"PLL_BYPASS_GO_B_0:false" \
"PLL_BYPASS_GO_B_1:false" \
"PLL_BYPASS_POST_0:0" \
"PLL_BYPASS_POST_0_0:false" \
"PLL_BYPASS_POST_0_1:false" \
"PLL_BYPASS_POST_0_2:false" \
"PLL_BYPASS_POST_0_3:false" \
"PLL_BYPASS_POST_1:0" \
"PLL_BYPASS_POST_1_0:false" \
"PLL_BYPASS_POST_1_1:false" \
"PLL_BYPASS_POST_1_2:false" \
"PLL_BYPASS_POST_1_3:false" \
"PLL_BYPASS_PRE_0:0" \
"PLL_BYPASS_PRE_0_0:false" \
"PLL_BYPASS_PRE_0_1:false" \
"PLL_BYPASS_PRE_0_2:false" \
"PLL_BYPASS_PRE_0_3:false" \
"PLL_BYPASS_PRE_1:0" \
"PLL_BYPASS_PRE_1_0:false" \
"PLL_BYPASS_PRE_1_1:false" \
"PLL_BYPASS_PRE_1_2:false" \
"PLL_BYPASS_PRE_1_3:false" \
"PLL_BYPASS_SEL_0:0" \
"PLL_BYPASS_SEL_0_0:false" \
"PLL_BYPASS_SEL_0_1:false" \
"PLL_BYPASS_SEL_0_2:false" \
"PLL_BYPASS_SEL_0_3:false" \
"PLL_BYPASS_SEL_1:0" \
"PLL_BYPASS_SEL_1_0:false" \
"PLL_BYPASS_SEL_1_1:false" \
"PLL_BYPASS_SEL_1_2:false" \
"PLL_BYPASS_SEL_1_3:false" \
"PLL_DELAY_LINE_REF_FB_0:false" \
"PLL_DELAY_LINE_REF_FB_1:false" \
"PLL_DELAY_LINE_USED_0:false" \
"PLL_DELAY_LINE_USED_1:false" \
"PLL_DELAY_STEPS_0:1" \
"PLL_DELAY_STEPS_1:1" \
"PLL_DLL_CASCADED_EN:false" \
"PLL_DYNAMIC_CONTROL_EN_0:true" \
"PLL_DYNAMIC_CONTROL_EN_1:false" \
"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
"PLL_EXPORT_PWRDWN:true" \
"PLL_EXT_MAX_ADDR_0:128" \
"PLL_EXT_MAX_ADDR_1:128" \
"PLL_EXT_WAVE_SEL_0:0" \
"PLL_EXT_WAVE_SEL_1:0" \
"PLL_FB_CLK_0:GL0_0" \
"PLL_FB_CLK_1:GL0_1" \
"PLL_FEEDBACK_MODE_0:Post-VCO" \
"PLL_FEEDBACK_MODE_1:Post-VCO" \
"PLL_IN_FREQ_0:50" \
"PLL_IN_FREQ_1:100" \
"PLL_INT_MODE_EN_0:false" \
"PLL_INT_MODE_EN_1:false" \
"PLL_LOCK_COUNT_0:8" \
"PLL_LOCK_COUNT_1:8" \
"PLL_LP_REQUIRES_LOCK_EN_0:false" \
"PLL_LP_REQUIRES_LOCK_EN_1:false" \
"PLL_PLL_CASCADED_EN:false" \
"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
"PLL_REF_CLK_SEL_0:false" \
"PLL_REF_CLK_SEL_1:false" \
"PLL_REFDIV_0:1" \
"PLL_REFDIV_1:1" \
"PLL_RESET_ON_LOCK_0:true" \
"PLL_SPREAD_MODE_0:false" \
"PLL_SPREAD_MODE_1:false" \
"PLL_SSM_DEPTH_0:5" \
"PLL_SSM_DEPTH_1:5" \
"PLL_SSM_DIVVAL_0:1" \
"PLL_SSM_DIVVAL_1:1" \
"PLL_SSM_FREQ_0:32" \
"PLL_SSM_FREQ_1:32" \
"PLL_SSM_RAND_PATTERN_0:2" \
"PLL_SSM_RAND_PATTERN_1:2" \
"PLL_SSMD_EN_0:false" \
"PLL_SSMD_EN_1:false" \
"PLL_SYNC_CORNER_PLL:false" \
"PLL_SYNC_EN:false" \
"PLL_VCO_MODE_0:MIN_JITTER" \
"PLL_VCO_MODE_1:MIN_JITTER" }
# Exporting Component Description of PF_CCC_0 to TCL done
*/
// PF_CCC_0
module PF_CCC_0(
// Inputs
PLL_POWERDOWN_N_0,
REF_CLK_0,
// Outputs
OUT0_FABCLK_0,
PLL_LOCK_0
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input PLL_POWERDOWN_N_0;
input REF_CLK_0;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output OUT0_FABCLK_0;
output PLL_LOCK_0;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire OUT0_FABCLK_0_net_0;
wire PLL_LOCK_0_net_0;
wire PLL_POWERDOWN_N_0;
wire REF_CLK_0;
wire OUT0_FABCLK_0_net_1;
wire PLL_LOCK_0_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [10:0]DRI_CTRL_0_const_net_0;
wire [32:0]DRI_WDATA_0_const_net_0;
wire [10:0]DRI_CTRL_1_const_net_0;
wire [32:0]DRI_WDATA_1_const_net_0;
wire [10:0]DLL_DRI_CTRL_const_net_0;
wire [32:0]DLL_DRI_WDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign DRI_CTRL_0_const_net_0 = 11'h000;
assign DRI_WDATA_0_const_net_0 = 33'h000000000;
assign DRI_CTRL_1_const_net_0 = 11'h000;
assign DRI_WDATA_1_const_net_0 = 33'h000000000;
assign DLL_DRI_CTRL_const_net_0 = 11'h000;
assign DLL_DRI_WDATA_const_net_0 = 33'h000000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign OUT0_FABCLK_0_net_1 = OUT0_FABCLK_0_net_0;
assign OUT0_FABCLK_0 = OUT0_FABCLK_0_net_1;
assign PLL_LOCK_0_net_1 = PLL_LOCK_0_net_0;
assign PLL_LOCK_0 = PLL_LOCK_0_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------PF_CCC_0_PF_CCC_0_0_PF_CCC - Actel:SgCore:PF_CCC:2.2.220
PF_CCC_0_PF_CCC_0_0_PF_CCC PF_CCC_0_0(
// Inputs
.REF_CLK_0 ( REF_CLK_0 ),
.PLL_POWERDOWN_N_0 ( PLL_POWERDOWN_N_0 ),
// Outputs
.OUT0_FABCLK_0 ( OUT0_FABCLK_0_net_0 ),
.PLL_LOCK_0 ( PLL_LOCK_0_net_0 )
);
endmodule

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component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_CCC_0_PF_CCC_0_0_PF_CCC</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_CCC_0_PF_CCC_0_0_PF_CCC.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
</fileSets>
</component>

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component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc Normal file
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set_component PF_CCC_0_PF_CCC_0_0_PF_CCC
# Microchip Technology Inc.
# Date: 2026-Apr-13 21:41:54
#
# Base clock for PLL #0
create_clock -period 20 [ get_pins { pll_inst_0/REF_CLK_0 } ]
create_generated_clock -multiply_by 8 -divide_by 5 -source [ get_pins { pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { pll_inst_0/OUT0 } ]

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component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_CCC_0_PF_CCC_0_0_PF_CCC(
OUT0_FABCLK_0,
PLL_LOCK_0,
REF_CLK_0,
PLL_POWERDOWN_N_0
);
output OUT0_FABCLK_0;
output PLL_LOCK_0;
input REF_CLK_0;
input PLL_POWERDOWN_N_0;
wire gnd_net, vcc_net, pll_inst_0_clkint_0;
CLKINT clkint_0 (.A(pll_inst_0_clkint_0), .Y(OUT0_FABCLK_0));
PLL #( .VCOFREQUENCY(4800), .DELAY_LINE_SIMULATION_MODE(""), .DATA_RATE(0.0)
, .FORMAL_NAME(""), .INTERFACE_NAME(""), .INTERFACE_LEVEL(3'b0)
, .SOFTRESET(1'b0), .SOFT_POWERDOWN_N(1'b1), .RFDIV_EN(1'b1), .OUT0_DIV_EN(1'b1)
, .OUT1_DIV_EN(1'b0), .OUT2_DIV_EN(1'b0), .OUT3_DIV_EN(1'b0), .SOFT_REF_CLK_SEL(1'b0)
, .RESET_ON_LOCK(1'b1), .BYPASS_CLK_SEL(4'b0), .BYPASS_GO_EN_N(1'b1)
, .BYPASS_PLL(4'b0), .BYPASS_OUT_DIVIDER(4'b0), .FF_REQUIRES_LOCK(1'b0)
, .FSE_N(1'b0), .FB_CLK_SEL_0(2'b00), .FB_CLK_SEL_1(1'b0), .RFDIV(6'b000001)
, .FRAC_EN(1'b0), .FRAC_DAC_EN(1'b0), .DIV0_RST_DELAY(3'b000)
, .DIV0_VAL(7'b0001111), .DIV1_RST_DELAY(3'b0), .DIV1_VAL(7'b1)
, .DIV2_RST_DELAY(3'b0), .DIV2_VAL(7'b1), .DIV3_RST_DELAY(3'b0)
, .DIV3_VAL(7'b1), .DIV3_CLK_SEL(1'b0), .BW_INT_CTRL(2'b0), .BW_PROP_CTRL(2'b11)
, .IREF_EN(1'b1), .IREF_TOGGLE(1'b0), .LOCK_CNT(4'b1000), .DESKEW_CAL_CNT(3'b110)
, .DESKEW_CAL_EN(1'b1), .DESKEW_CAL_BYPASS(1'b0), .SYNC_REF_DIV_EN(1'b0)
, .SYNC_REF_DIV_EN_2(1'b0), .OUT0_PHASE_SEL(3'b000), .OUT1_PHASE_SEL(3'b0)
, .OUT2_PHASE_SEL(3'b0), .OUT3_PHASE_SEL(3'b0), .SOFT_LOAD_PHASE_N(1'b1)
, .SSM_DIV_VAL(6'b1), .FB_FRAC_VAL(24'b0), .SSM_SPREAD_MODE(1'b0)
, .SSM_MODULATION(5'b00101), .FB_INT_VAL(12'b000001100000), .SSM_EN_N(1'b1)
, .SSM_EXT_WAVE_EN(2'b0), .SSM_EXT_WAVE_MAX_ADDR(8'b0), .SSM_RANDOM_EN(1'b0)
, .SSM_RANDOM_PATTERN_SEL(3'b0), .CDMUX0_SEL(2'b0), .CDMUX1_SEL(1'b1)
, .CDMUX2_SEL(1'b0), .CDELAY0_SEL(8'b0), .CDELAY0_EN(1'b0), .DRI_EN(1'b1)
) pll_inst_0 (.LOCK(PLL_LOCK_0), .SSCG_WAVE_TABLE_ADDR({nc0,
nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .DELAY_LINE_OUT_OF_RANGE()
, .POWERDOWN_N(PLL_POWERDOWN_N_0), .OUT0_EN(vcc_net), .OUT1_EN(
gnd_net), .OUT2_EN(gnd_net), .OUT3_EN(gnd_net), .REF_CLK_SEL(
gnd_net), .BYPASS_EN_N(vcc_net), .LOAD_PHASE_N(vcc_net),
.SSCG_WAVE_TABLE({gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net}), .PHASE_DIRECTION(gnd_net),
.PHASE_ROTATE(gnd_net), .PHASE_OUT0_SEL(gnd_net),
.PHASE_OUT1_SEL(gnd_net), .PHASE_OUT2_SEL(gnd_net),
.PHASE_OUT3_SEL(gnd_net), .DELAY_LINE_MOVE(gnd_net),
.DELAY_LINE_DIRECTION(gnd_net), .DELAY_LINE_WIDE(gnd_net),
.DELAY_LINE_LOAD(vcc_net), .REFCLK_SYNC_EN(gnd_net),
.REF_CLK_0(REF_CLK_0), .REF_CLK_1(gnd_net), .FB_CLK(gnd_net),
.OUT0(pll_inst_0_clkint_0), .OUT1(), .OUT2(), .OUT3(),
.DRI_CLK(gnd_net), .DRI_CTRL({gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net}), .DRI_WDATA({gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net}), .DRI_ARST_N(vcc_net), .DRI_RDATA({nc8, nc9, nc10,
nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20,
nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40}),
.DRI_INTERRUPT());
VCC vcc_inst (.Y(vcc_net));
GND gnd_inst (.Y(gnd_net));
endmodule

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component/work/PF_CCC_0/PF_CCC_0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:54 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : PF_CCC_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0/PF_CCC_0.v
Constraint files:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc