working FIFO and TPSRAM without packet flter
This commit is contained in:
1
component/work/COREFIFO_C0/COREFIFO_C0.cxf
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1
component/work/COREFIFO_C0/COREFIFO_C0.cxf
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./COREFIFO_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./COREFIFO_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./COREFIFO_C0_0/COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/DirectCore/COREFIFO/3.1.101/COREFIFO.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./COREFIFO_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="DirectCore" name="COREFIFO" vendor="Actel" version="3.1.101"/><configuration><configurableElement referenceId="AE_STATIC_EN" value="false"/><configurableElement referenceId="AEVAL" value="4"/><configurableElement referenceId="AF_STATIC_EN" value="false"/><configurableElement referenceId="AFVAL" value="1020"/><configurableElement referenceId="CTRL_TYPE" value="2"/><configurableElement referenceId="DIE_SIZE" value="15"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="ESTOP" value="true"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="FSTOP" value="true"/><configurableElement referenceId="FWFT" value="true"/><configurableElement referenceId="NUM_STAGES" value="2"/><configurableElement referenceId="OVERFLOW_EN" value="false"/><configurableElement referenceId="PIPE" value="1"/><configurableElement referenceId="PREFETCH" value="false"/><configurableElement referenceId="RAM_OPT" value="0"/><configurableElement referenceId="RDCNT_EN" value="false"/><configurableElement referenceId="RDEPTH" value="1024"/><configurableElement referenceId="RE_POLARITY" value="0"/><configurableElement referenceId="READ_DVALID" value="false"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SYNC" value="1"/><configurableElement referenceId="SYNC_RESET" value="0"/><configurableElement referenceId="testbench" value="User"/><configurableElement referenceId="UNDERFLOW_EN" value="false"/><configurableElement referenceId="WDEPTH" value="1024"/><configurableElement referenceId="WE_POLARITY" value="0"/><configurableElement referenceId="WRCNT_EN" value="false"/><configurableElement referenceId="WRITE_ACK" value="false"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RESET_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FULL</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>EMPTY</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Q</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>
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BIN
component/work/COREFIFO_C0/COREFIFO_C0.sdb
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BIN
component/work/COREFIFO_C0/COREFIFO_C0.sdb
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component/work/COREFIFO_C0/COREFIFO_C0.v
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component/work/COREFIFO_C0/COREFIFO_C0.v
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//////////////////////////////////////////////////////////////////////
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// Created by SmartDesign Wed Apr 15 18:21:52 2026
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// Version: 2025.1 2025.1.0.14
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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//////////////////////////////////////////////////////////////////////
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// Component Description (Tcl)
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//////////////////////////////////////////////////////////////////////
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/*
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# Exporting Component Description of COREFIFO_C0 to TCL
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# Family: PolarFire
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# Part Number: MPF300TS-1FCG1152I
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# Create and Configure the core component COREFIFO_C0
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create_and_configure_core -core_vlnv {Actel:DirectCore:COREFIFO:3.1.101} -component_name {COREFIFO_C0} -params {\
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"AE_STATIC_EN:false" \
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"AEVAL:4" \
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"AF_STATIC_EN:false" \
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"AFVAL:1020" \
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"CTRL_TYPE:2" \
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"DIE_SIZE:15" \
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"ECC:0" \
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"ESTOP:true" \
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"FSTOP:true" \
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"FWFT:true" \
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"NUM_STAGES:2" \
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"OVERFLOW_EN:false" \
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"PIPE:1" \
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"PREFETCH:false" \
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"RAM_OPT:0" \
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"RDCNT_EN:false" \
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"RDEPTH:1024" \
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"RE_POLARITY:0" \
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"READ_DVALID:false" \
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"RWIDTH:32" \
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"SYNC:1" \
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"SYNC_RESET:0" \
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"UNDERFLOW_EN:false" \
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"WDEPTH:1024" \
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"WE_POLARITY:0" \
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"WRCNT_EN:false" \
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"WRITE_ACK:false" \
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"WWIDTH:32" }
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# Exporting Component Description of COREFIFO_C0 to TCL done
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*/
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// COREFIFO_C0
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module COREFIFO_C0(
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// Inputs
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CLK,
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DATA,
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RE,
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RESET_N,
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WE,
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// Outputs
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EMPTY,
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FULL,
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Q
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);
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//--------------------------------------------------------------------
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// Input
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//--------------------------------------------------------------------
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input CLK;
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input [31:0] DATA;
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input RE;
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input RESET_N;
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input WE;
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//--------------------------------------------------------------------
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// Output
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//--------------------------------------------------------------------
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output EMPTY;
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output FULL;
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output [31:0] Q;
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//--------------------------------------------------------------------
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// Nets
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//--------------------------------------------------------------------
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wire CLK;
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wire [31:0] DATA;
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wire EMPTY_net_0;
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wire FULL_net_0;
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wire [31:0] Q_net_0;
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wire RE;
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wire RESET_N;
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wire WE;
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wire FULL_net_1;
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wire EMPTY_net_1;
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wire [31:0] Q_net_1;
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//--------------------------------------------------------------------
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// TiedOff Nets
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//--------------------------------------------------------------------
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wire GND_net;
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wire [31:0] MEMRD_const_net_0;
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//--------------------------------------------------------------------
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// Constant assignments
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//--------------------------------------------------------------------
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assign GND_net = 1'b0;
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assign MEMRD_const_net_0 = 32'h00000000;
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//--------------------------------------------------------------------
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// Top level output port assignments
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//--------------------------------------------------------------------
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assign FULL_net_1 = FULL_net_0;
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assign FULL = FULL_net_1;
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assign EMPTY_net_1 = EMPTY_net_0;
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assign EMPTY = EMPTY_net_1;
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assign Q_net_1 = Q_net_0;
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assign Q[31:0] = Q_net_1;
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//--------------------------------------------------------------------
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// Component instances
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//--------------------------------------------------------------------
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//--------COREFIFO_C0_COREFIFO_C0_0_COREFIFO - Actel:DirectCore:COREFIFO:3.1.101
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COREFIFO_C0_COREFIFO_C0_0_COREFIFO #(
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.AE_STATIC_EN ( 0 ),
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.AEVAL ( 4 ),
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.AF_STATIC_EN ( 0 ),
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.AFVAL ( 1020 ),
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.CTRL_TYPE ( 2 ),
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.DIE_SIZE ( 15 ),
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.ECC ( 0 ),
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.ESTOP ( 1 ),
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.FAMILY ( 26 ),
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.FSTOP ( 1 ),
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.FWFT ( 1 ),
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.NUM_STAGES ( 2 ),
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.OVERFLOW_EN ( 0 ),
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.PIPE ( 1 ),
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.PREFETCH ( 0 ),
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.RAM_OPT ( 0 ),
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.RDCNT_EN ( 0 ),
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.RDEPTH ( 1024 ),
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.RE_POLARITY ( 0 ),
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.READ_DVALID ( 0 ),
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.RWIDTH ( 32 ),
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.SYNC ( 1 ),
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.SYNC_RESET ( 0 ),
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.UNDERFLOW_EN ( 0 ),
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.WDEPTH ( 1024 ),
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.WE_POLARITY ( 0 ),
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.WRCNT_EN ( 0 ),
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.WRITE_ACK ( 0 ),
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.WWIDTH ( 32 ) )
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COREFIFO_C0_0(
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// Inputs
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.CLK ( CLK ),
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.WCLOCK ( GND_net ), // tied to 1'b0 from definition
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.RCLOCK ( GND_net ), // tied to 1'b0 from definition
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.RESET_N ( RESET_N ),
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.WRESET_N ( GND_net ), // tied to 1'b0 from definition
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.RRESET_N ( GND_net ), // tied to 1'b0 from definition
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.WE ( WE ),
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.RE ( RE ),
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.DATA ( DATA ),
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.MEMRD ( MEMRD_const_net_0 ), // tied to 32'h00000000 from definition
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// Outputs
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.FULL ( FULL_net_0 ),
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.EMPTY ( EMPTY_net_0 ),
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.AFULL ( ),
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.AEMPTY ( ),
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.OVERFLOW ( ),
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.UNDERFLOW ( ),
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.WACK ( ),
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.DVLD ( ),
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.MEMWE ( ),
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.MEMRE ( ),
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.SB_CORRECT ( ),
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.DB_DETECT ( ),
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.Q ( Q_net_0 ),
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.WRCNT ( ),
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.RDCNT ( ),
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.MEMWADDR ( ),
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.MEMRADDR ( ),
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.MEMWD ( )
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);
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endmodule
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0_COREFIFO_C0_0_COREFIFO</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\core\COREFIFO.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="3"><name>rtl\vlog\core\corefifo_sync.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="4"><name>rtl\vlog\core\corefifo_sync_scntr.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="5"><name>rtl\vlog\core\corefifo_async.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="6"><name>rtl\vlog\core\corefifo_nstagessync.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="7"><name>rtl\vlog\core\corefifo_graytobinconv.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="8"><name>rtl\vlog\core\corefifo_fwft.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="9"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="10"><name>rtl\vlog\test\user\top_define.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="11"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v</name><fileType>verilogSource</fileType></file><file fileid="12"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v</name><fileType>verilogSource</fileType></file><file fileid="13"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v</name><fileType>verilogSource</fileType></file><file fileid="14"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v</name><fileType>verilogSource</fileType></file><file fileid="15"><name>rtl\vlog\test\user\testbench.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime> -all</SimulationTime><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="16"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v</name><fileType>verilogSource</fileType></file><file fileid="17"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v</name><fileType>verilogSource</fileType></file><file fileid="18"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="19"><name>mti\scripts\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="20"><name>mti\scripts\runall.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel></Component>
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set_component COREFIFO_C0_COREFIFO_C0_0_COREFIFO
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set_false_path -to [ get_cells { genblk*.U_corefifo_async/*/shift_reg* } ]
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36
component/work/COREFIFO_C0/COREFIFO_C0_0/coreparameters.v
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component/work/COREFIFO_C0/COREFIFO_C0_0/coreparameters.v
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//--------------------------------------------------------------------
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// Created by Microsemi SmartDesign Wed Apr 15 18:21:52 2026
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// Parameters for COREFIFO
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//--------------------------------------------------------------------
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parameter AE_STATIC_EN = 0;
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parameter AEVAL = 4;
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parameter AF_STATIC_EN = 0;
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parameter AFVAL = 1020;
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parameter CTRL_TYPE = 2;
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parameter DIE_SIZE = 15;
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parameter ECC = 0;
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parameter ESTOP = 1;
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parameter FAMILY = 26;
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parameter FSTOP = 1;
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parameter FWFT = 1;
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parameter NUM_STAGES = 2;
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parameter OVERFLOW_EN = 0;
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parameter PIPE = 1;
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parameter PREFETCH = 0;
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parameter RAM_OPT = 0;
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parameter RDCNT_EN = 0;
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parameter RDEPTH = 1024;
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parameter RE_POLARITY = 0;
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parameter READ_DVALID = 0;
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parameter RWIDTH = 32;
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parameter SYNC = 1;
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parameter SYNC_RESET = 0;
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parameter testbench = "User";
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parameter UNDERFLOW_EN = 0;
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parameter WDEPTH = 1024;
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parameter WE_POLARITY = 0;
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parameter WRCNT_EN = 0;
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parameter WRITE_ACK = 0;
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parameter WWIDTH = 32;
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@@ -0,0 +1,2 @@
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run 700000ns
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radix h
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82
component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/wave.do
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component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/wave.do
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@@ -0,0 +1,82 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/uut_fifo/RESET_N
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add wave -noupdate /testbench/uut_fifo/WCLOCK
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add wave -noupdate /testbench/uut_fifo/WE
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add wave -noupdate /testbench/uut_fifo/DATA
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add wave -noupdate /testbench/uut_fifo/FULL
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add wave -noupdate /testbench/uut_fifo/AFULL
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add wave -noupdate /testbench/uut_fifo/WACK
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add wave -noupdate /testbench/uut_fifo/OVERFLOW
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add wave -noupdate /testbench/uut_fifo/RCLOCK
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add wave -noupdate /testbench/uut_fifo/RE
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add wave -noupdate /testbench/uut_fifo/Q
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add wave -noupdate /testbench/uut_fifo/DVLD
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add wave -noupdate /testbench/uut_fifo/EMPTY
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add wave -noupdate /testbench/uut_fifo/AEMPTY
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add wave -noupdate /testbench/uut_fifo/RDCNT
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add wave -noupdate /testbench/uut_fifo/UNDERFLOW
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add wave -noupdate /testbench/uut_fifo/MEMWE
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add wave -noupdate /testbench/uut_fifo/MEMWD
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add wave -noupdate /testbench/uut_fifo/MEMWADDR
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add wave -noupdate /testbench/uut_fifo/MEMRE
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add wave -noupdate /testbench/uut_fifo/MEMRD
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add wave -noupdate /testbench/uut_fifo/MEMRADDR
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/wclk
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add wave -noupdate /testbench/we
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add wave -noupdate /testbench/wdata
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add wave -noupdate /testbench/full
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add wave -noupdate /testbench/afull
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add wave -noupdate /testbench/overflow
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add wave -noupdate /testbench/wrcount
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add wave -noupdate /testbench/rclk
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add wave -noupdate /testbench/re
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add wave -noupdate /testbench/rdata
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add wave -noupdate /testbench/empty
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add wave -noupdate /testbench/aempty
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add wave -noupdate /testbench/dvld
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add wave -noupdate /testbench/rdcount
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/err_cnt
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add wave -noupdate /testbench/ext_waddr
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add wave -noupdate /testbench/ext_raddr
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add wave -noupdate /testbench/ext_data
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add wave -noupdate /testbench/ext_rd
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add wave -noupdate /testbench/ext_we
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add wave -noupdate /testbench/ext_re
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add wave -noupdate /testbench/int_waddr
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add wave -noupdate /testbench/int_raddr
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add wave -noupdate /testbench/int_data
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add wave -noupdate /testbench/int_rd
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add wave -noupdate /testbench/int_we
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add wave -noupdate /testbench/int_re
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add wave -noupdate /testbench/monitor/wack_r
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add wave -noupdate /testbench/monitor/tb_wcnt
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add wave -noupdate /testbench/monitor/tb_wack
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add wave -noupdate /testbench/monitor/tb_underflow
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add wave -noupdate /testbench/monitor/tb_rcnt
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add wave -noupdate /testbench/monitor/tb_overflow
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add wave -noupdate /testbench/monitor/tb_empty
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add wave -noupdate /testbench/monitor/tb_dvld
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add wave -noupdate /testbench/monitor/tb_full
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||||
add wave -noupdate /testbench/monitor/tb_afull
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||||
add wave -noupdate /testbench/monitor/tb_aempty
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {32473187607 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 524
|
||||
configure wave -valuecolwidth 60
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits fs
|
||||
update
|
||||
WaveRestoreZoom {30291784830 fs} {35134349071 fs}
|
||||
1479
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v
Normal file
1479
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,44 @@
|
||||
DESIGN:COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
|
||||
FAM:PolarFire
|
||||
DEVICE:300
|
||||
OUTFORMAT:Verilog
|
||||
LPMTYPE:LPM_RAM
|
||||
CLKS:1
|
||||
PTYPE:1
|
||||
BATCH:T
|
||||
MGNTIMER:F
|
||||
MGNCMPL:F
|
||||
GEN_BEHV_MODULE:F
|
||||
WWIDTH:32
|
||||
RWIDTH:32
|
||||
WDEPTH:1024
|
||||
RDEPTH:1024
|
||||
WE_POLARITY:1
|
||||
RE_POLARITY:1
|
||||
RCLK_EDGE:RISE
|
||||
WCLK_EDGE:RISE
|
||||
CLK_EDGE:RISE
|
||||
INIT_RAM:F
|
||||
LPM_HINT:0
|
||||
ECC:0
|
||||
PMODE2:0
|
||||
BUSY_FLAG:0
|
||||
BYTEENABLES:0
|
||||
DATA_IN_PN:W_DATA
|
||||
DATA_OUT_PN:R_DATA
|
||||
WADDRESS_PN:W_ADDR
|
||||
RADDRESS_PN:R_ADDR
|
||||
WE_PN:W_EN
|
||||
RE_PN:R_EN
|
||||
WCLOCK_PN:W_CLK
|
||||
RCLOCK_PN:R_CLK
|
||||
CLOCK_PN:CLK
|
||||
SII_LOCK:0
|
||||
SD_EXPORT_HIDDEN_PORTS:false
|
||||
CASCADE:0
|
||||
A_DOUT_EN_POLARITY:2
|
||||
A_DOUT_EN_PN:R_DATA_EN
|
||||
A_DOUT_SRST_POLARITY:2
|
||||
A_DOUT_SRST_PN:R_DATA_SRST_N
|
||||
RESET_POLARITY:2
|
||||
RESET_PN:R_DATA_ARST_N
|
||||
@@ -0,0 +1,80 @@
|
||||
|
||||
****************
|
||||
Macro Parameters
|
||||
****************
|
||||
|
||||
Name : COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
|
||||
Family : PolarFire
|
||||
Output Format : VERILOG
|
||||
Type : RAM
|
||||
Write Block Enable Polarity : Active High
|
||||
Read Block Enable Polarity : Active High
|
||||
A_DOUT Enable Polarity : None
|
||||
B_DOUT Enable Polarity : None
|
||||
A_DOUT Sync-reset Polarity : None
|
||||
B_DOUT Sync-reset Polarity : None
|
||||
A_DOUT Async-reset Polarity : None
|
||||
B_DOUT Async-reset Polarity : None
|
||||
Reset Polarity : None
|
||||
Read Clock Edge : Rising
|
||||
Write Clock Edge : Rising
|
||||
A_REN Polarity : None
|
||||
B_REN Polarity : None
|
||||
Write Depth : 1024
|
||||
Write Width : 32
|
||||
Read Depth : 1024
|
||||
Read Width : 32
|
||||
Portname DataIn : W_DATA
|
||||
Portname DataOut : R_DATA
|
||||
Portname WClock : W_CLK
|
||||
Portname RClock : R_CLK
|
||||
Portname WAddress : W_ADDR
|
||||
Portname RAddress : R_ADDR
|
||||
Portname Single Clock : CLK
|
||||
Portname Single Async-reset : R_DATA_ARST_N
|
||||
Portname DataAIn :
|
||||
Portname DataBIn :
|
||||
Portname DataAOut :
|
||||
Portname DataBOut :
|
||||
Portname AddressA :
|
||||
Portname AddressB :
|
||||
Portname CLKA :
|
||||
Portname CLKB :
|
||||
Portname RWA :
|
||||
Portname RWB :
|
||||
Portname BLKA :
|
||||
Portname BLKB :
|
||||
Portname A_DOUT_EN : R_DATA_EN
|
||||
Portname B_DOUT_EN :
|
||||
Portname A_DOUT_SRST_N : R_DATA_SRST_N
|
||||
Portname B_DOUT_SRST_N :
|
||||
Portname A_DOUT_ARST_N :
|
||||
Portname B_DOUT_ARST_N :
|
||||
Portname Write Enable : W_EN
|
||||
Portname Read Enable : R_EN
|
||||
Portname A_WBYTE_EN :
|
||||
Portname B_WBYTE_EN :
|
||||
Portname A_REN :
|
||||
Portname B_REN :
|
||||
LPM_HINT : 0
|
||||
Device : 300
|
||||
RAM Type : Two Port
|
||||
Optimized for : Speed
|
||||
Initialize RAM : False
|
||||
Clocks : Single Read/Write Clock
|
||||
Byte Enables : No
|
||||
Read Pipeline A : No
|
||||
Read Pipeline B : No
|
||||
Write Mode A : Hold Data
|
||||
Write Mode B : Hold Data
|
||||
ECC Type : Disabled
|
||||
Lock access : Off
|
||||
ACCESS_BUSY : Disabled
|
||||
|
||||
Cascade Configuration:
|
||||
Write Port configuration : 1024x20
|
||||
Read Port configuration : 1024x20
|
||||
Number of blocks depth wise: 1
|
||||
Number of blocks width wise: 2
|
||||
|
||||
Wrote Verilog netlist to E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v.
|
||||
@@ -0,0 +1,86 @@
|
||||
`timescale 1 ns/100 ps
|
||||
// Version: 2025.1 2025.1.0.14
|
||||
|
||||
|
||||
module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top(
|
||||
W_DATA,
|
||||
R_DATA,
|
||||
W_ADDR,
|
||||
R_ADDR,
|
||||
W_EN,
|
||||
R_EN,
|
||||
CLK
|
||||
);
|
||||
input [31:0] W_DATA;
|
||||
output [31:0] R_DATA;
|
||||
input [9:0] W_ADDR;
|
||||
input [9:0] R_ADDR;
|
||||
input W_EN;
|
||||
input R_EN;
|
||||
input CLK;
|
||||
|
||||
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , VCC, GND, ADLIB_VCC;
|
||||
wire GND_power_net1;
|
||||
wire VCC_power_net1;
|
||||
assign GND = GND_power_net1;
|
||||
assign VCC = VCC_power_net1;
|
||||
assign ADLIB_VCC = VCC_power_net1;
|
||||
|
||||
RAM1K20 #( .RAMINDEX("core%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
|
||||
) COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 (.A_DOUT({nc0,
|
||||
nc1, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
|
||||
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24], nc2, nc3,
|
||||
R_DATA[23], R_DATA[22], R_DATA[21], R_DATA[20], R_DATA[19],
|
||||
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc4, nc5, nc6,
|
||||
nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17,
|
||||
nc18, nc19, nc20, nc21, nc22, nc23}), .DB_DETECT(),
|
||||
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ), .A_ADDR({
|
||||
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
|
||||
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
|
||||
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
|
||||
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
|
||||
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(R_EN),
|
||||
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
|
||||
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
|
||||
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
|
||||
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
|
||||
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[31],
|
||||
W_DATA[30], W_DATA[29], W_DATA[28], W_DATA[27], W_DATA[26],
|
||||
W_DATA[25], W_DATA[24], GND, GND, W_DATA[23], W_DATA[22],
|
||||
W_DATA[21], W_DATA[20], W_DATA[19], W_DATA[18], W_DATA[17],
|
||||
W_DATA[16]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
|
||||
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
|
||||
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
|
||||
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
|
||||
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
|
||||
RAM1K20 #( .RAMINDEX("core%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
|
||||
) COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 (.A_DOUT({nc24,
|
||||
nc25, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
|
||||
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8], nc26, nc27,
|
||||
R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
|
||||
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc28, nc29, nc30,
|
||||
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
|
||||
nc41, nc42, nc43, nc44, nc45, nc46, nc47}), .DB_DETECT(),
|
||||
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][0] ), .A_ADDR({
|
||||
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
|
||||
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
|
||||
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
|
||||
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
|
||||
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(R_EN),
|
||||
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
|
||||
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
|
||||
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
|
||||
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
|
||||
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[15],
|
||||
W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11], W_DATA[10],
|
||||
W_DATA[9], W_DATA[8], GND, GND, W_DATA[7], W_DATA[6],
|
||||
W_DATA[5], W_DATA[4], W_DATA[3], W_DATA[2], W_DATA[1],
|
||||
W_DATA[0]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
|
||||
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
|
||||
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
|
||||
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
|
||||
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
|
||||
GND GND_power_inst1 (.Y(GND_power_net1));
|
||||
VCC VCC_power_inst1 (.Y(VCC_power_net1));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,64 @@
|
||||
// This is automatically generated file
|
||||
|
||||
`timescale 1 ns/100 ps
|
||||
module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper(
|
||||
WDATA,
|
||||
WADDR,
|
||||
WEN,
|
||||
REN,
|
||||
RDATA,
|
||||
RADDR,
|
||||
RESET_N,
|
||||
CLOCK,
|
||||
WCLOCK,
|
||||
A_SB_CORRECT,
|
||||
B_SB_CORRECT,
|
||||
A_DB_DETECT,
|
||||
B_DB_DETECT,
|
||||
RCLOCK
|
||||
);
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// PARAMETER Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
parameter RWIDTH = 32; // Read port Data Width
|
||||
parameter WWIDTH = 32; // Write port Data Width
|
||||
parameter RDEPTH = 128; // Read port Data Depth
|
||||
parameter WDEPTH = 128; // Write port Data Depth
|
||||
parameter SYNC = 0; // Synchronous or Asynchronous operation | 1 - Single Clock, 0 - Dual clock
|
||||
parameter PIPE = 1; // Pipeline read data out
|
||||
parameter CTRL_TYPE = 1; // Controller only options | 1 - Controller Only, 2 - RAM1Kx18, 3 - RAM64x18
|
||||
parameter SYNC_RESET = 0; // Synchronous or Asynchronous RESET | 1 - Synchronous reset, 0 - Asynchronous reset
|
||||
parameter RAM_OPT = 0; // | 0 -High Speed , 1 - Low Power
|
||||
// --------------------------------------------------------------------------
|
||||
// I/O Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
input [WWIDTH - 1 : 0] WDATA;
|
||||
input [(WDEPTH - 1) : 0] WADDR;
|
||||
input WEN;
|
||||
input REN;
|
||||
output [RWIDTH - 1 : 0] RDATA;
|
||||
input [(RDEPTH - 1) : 0] RADDR;
|
||||
input RESET_N;
|
||||
input WCLOCK;
|
||||
input RCLOCK;
|
||||
output A_SB_CORRECT;
|
||||
output B_SB_CORRECT;
|
||||
output A_DB_DETECT;
|
||||
output B_DB_DETECT;
|
||||
input CLOCK;
|
||||
|
||||
|
||||
COREFIFO_C0_COREFIFO_C0_0_LSRAM_top L3_syncnonpipe (
|
||||
.W_DATA (WDATA ),
|
||||
.W_ADDR (WADDR ),
|
||||
.W_EN (WEN ),
|
||||
.R_DATA (RDATA ),
|
||||
.R_ADDR (RADDR ),
|
||||
.R_EN (REN ),
|
||||
.CLK (CLOCK )
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,371 @@
|
||||
// ********************************************************************/
|
||||
// Microchip Corporation Proprietary and Confidential
|
||||
// Copyright 2023 Microchip Corporation. All rights reserved.
|
||||
//
|
||||
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
|
||||
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
|
||||
// IN ADVANCE IN WRITING.
|
||||
//
|
||||
// IP Core: COREFIFO
|
||||
//
|
||||
// SVN Revision Information:
|
||||
// SVN $Revision: $
|
||||
// SVN $Date: $
|
||||
//
|
||||
//
|
||||
// *********************************************************************/
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
module COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft (
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
clk,
|
||||
//reset_rclk_top,
|
||||
//reset_wclk_top,
|
||||
aresetn_wclk,
|
||||
aresetn_rclk,
|
||||
sresetn_wclk,
|
||||
sresetn_rclk,
|
||||
empty,
|
||||
aempty,
|
||||
rd_en,
|
||||
fifo_rd_en,
|
||||
fifo_empty,
|
||||
fifo_aempty,
|
||||
fifo_dout,
|
||||
wr_en,
|
||||
din,
|
||||
fwft_dvld,
|
||||
reg_valid,
|
||||
dout,
|
||||
fifo_MEMRADDR,
|
||||
fwft_MEMRADDR
|
||||
);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// PARAMETER Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
parameter RDEPTH = 10;
|
||||
parameter WWIDTH = 10;
|
||||
parameter RWIDTH = 10;
|
||||
parameter WCLK_HIGH = 1;
|
||||
parameter RCLK_HIGH = 1;
|
||||
parameter RESET_LOW = 1;
|
||||
parameter WRITE_LOW = 1;
|
||||
parameter READ_LOW = 1;
|
||||
parameter PREFETCH = 0;
|
||||
parameter FWFT = 0;
|
||||
parameter SYNC = 1;
|
||||
parameter SYNC_RESET = 0;//uncommented in v3.0
|
||||
|
||||
localparam RDEPTH_CAL = (RDEPTH == 0) ? RDEPTH : (RDEPTH-1);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// I/O Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
//--------
|
||||
// Inputs
|
||||
//--------
|
||||
|
||||
// Clocks and Reset
|
||||
input wr_clk;
|
||||
input rd_clk;
|
||||
input clk;
|
||||
//input reset_rclk_top;
|
||||
//input reset_wclk_top;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output fifo_rd_en;
|
||||
input [RWIDTH-1 : 0] fifo_dout;
|
||||
input fifo_empty;
|
||||
input fifo_aempty;
|
||||
input [WWIDTH - 1 : 0] din;
|
||||
input [RDEPTH_CAL : 0] fifo_MEMRADDR;
|
||||
|
||||
input aresetn_rclk; //added in v3.0
|
||||
input aresetn_wclk;//added in v3.0
|
||||
input sresetn_rclk;//added in v3.0
|
||||
input sresetn_wclk;//added in v3.0
|
||||
//---------
|
||||
// Outputs
|
||||
//---------
|
||||
output empty;
|
||||
output aempty;
|
||||
output [RWIDTH-1 : 0] dout;
|
||||
output fwft_dvld;
|
||||
output reg_valid;
|
||||
output [RDEPTH_CAL : 0] fwft_MEMRADDR;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal signals
|
||||
// --------------------------------------------------------------------------
|
||||
reg fifo_valid, dout_valid, middle_valid ;
|
||||
reg [RWIDTH - 1 : 0] middle_dout;
|
||||
|
||||
reg [RWIDTH - 1 : 0] dout;
|
||||
//wire [RWIDTH - 1 : 0] dout; //added by mahesh
|
||||
|
||||
wire [RWIDTH - 1 : 0] fifo_dout;
|
||||
wire fifo_rd_en, fifo_empty;
|
||||
wire update_dout, update_middle;
|
||||
|
||||
wire [RDEPTH_CAL : 0] fwft_MEMRADDR;
|
||||
//reg [RDEPTH_CAL : 0] fwft_MEMRADDR;
|
||||
|
||||
reg fifo_empty_r;
|
||||
wire fwft_dvld;
|
||||
reg wr_p_r;
|
||||
reg reg_valid;
|
||||
wire we_p;
|
||||
reg we_p_r;
|
||||
wire re_p;
|
||||
reg re_p_d;
|
||||
wire aresetn;
|
||||
//wire sresetn;
|
||||
wire pos_rclk;
|
||||
wire pos_wclk;
|
||||
|
||||
reg empty_r;
|
||||
reg reg_valid_r;
|
||||
wire empty1;
|
||||
reg empty;
|
||||
reg update_dout_r;
|
||||
|
||||
wire fifo_empty_pulse;
|
||||
reg fifo_empty_pulse_d;
|
||||
wire fifo_init_pulse;
|
||||
|
||||
wire reset_wclk;
|
||||
wire reset_rclk;
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||
// || ||
|
||||
// || Start - of - Code ||
|
||||
// || ||
|
||||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Clocks, resets and enables
|
||||
// --------------------------------------------------------------------------
|
||||
generate
|
||||
if(SYNC == 1) begin
|
||||
assign pos_rclk = RCLK_HIGH ? clk : ~clk;
|
||||
assign pos_wclk = WCLK_HIGH ? clk : ~clk;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if(SYNC == 0) begin
|
||||
assign pos_rclk = RCLK_HIGH ? rd_clk : ~rd_clk;
|
||||
assign pos_wclk = WCLK_HIGH ? wr_clk : ~wr_clk;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign we_p = WRITE_LOW ? (~wr_en) : (wr_en);
|
||||
assign re_p = READ_LOW ? (~rd_en) : (rd_en);
|
||||
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate addresses to the memory
|
||||
// --------------------------------------------------------------------------
|
||||
assign fwft_MEMRADDR = fifo_MEMRADDR ;
|
||||
|
||||
assign update_middle = fifo_valid & (middle_valid == update_dout);
|
||||
assign update_dout = (fifo_valid || middle_valid) && (re_p || !dout_valid);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generates the read enable to be given to the FIFO controller
|
||||
// fifo_rd_en: It is different from the top-level read enable
|
||||
// --------------------------------------------------------------------------
|
||||
assign fifo_rd_en = !(fifo_empty) && !(middle_valid && dout_valid && fifo_valid);
|
||||
//assign fifo_rd_en = fifo_init_pulse | re_p;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate empty/almost empty signal
|
||||
// --------------------------------------------------------------------------
|
||||
//assign empty = !dout_valid | (!fifo_valid && !middle_valid && dout_valid & !update_dout & re_p);
|
||||
//assign empty = fifo_empty_r; //!dout_valid ; // change by mahesh
|
||||
// assign empty = !dout_valid ; // SAR no
|
||||
|
||||
assign aempty = fifo_aempty | empty;
|
||||
|
||||
always @(posedge pos_rclk or negedge aresetn_rclk) begin
|
||||
if(!aresetn_rclk | !sresetn_rclk)
|
||||
empty <= 1'b1;
|
||||
else if(update_dout)
|
||||
empty <= 1'b0;
|
||||
else if(re_p)
|
||||
empty <= 1'b1;
|
||||
|
||||
end
|
||||
|
||||
//assign reset_rclk = reset_rclk_top;commented in v3.0
|
||||
//assign reset_wclk = reset_wclk_top;commented in v3.0
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Register empty signal
|
||||
// --------------------------------------------------------------------------
|
||||
always @(posedge pos_rclk or negedge aresetn_rclk) begin
|
||||
if(!aresetn_rclk | !sresetn_rclk) begin
|
||||
fifo_empty_r <= 1'b0;
|
||||
//fifo_empty_r <= fifo_empty;
|
||||
update_dout_r <= 'h0;
|
||||
end
|
||||
else begin
|
||||
fifo_empty_r <= fifo_empty;
|
||||
update_dout_r <= update_dout;
|
||||
end
|
||||
end
|
||||
|
||||
assign fifo_empty_pulse = fifo_empty_r & !fifo_empty;
|
||||
|
||||
assign fifo_init_pulse = !fifo_empty_pulse_d & fifo_empty_pulse;
|
||||
|
||||
//-----------------------------------------------------------------
|
||||
// Register re_p signal
|
||||
//-----------------------------------------------------------------
|
||||
always @(posedge pos_rclk or negedge aresetn_rclk) begin
|
||||
if(!aresetn_rclk | !sresetn_rclk) begin
|
||||
re_p_d <= 1'b0;
|
||||
end else begin
|
||||
re_p_d <= re_p;
|
||||
end
|
||||
end
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// delayed empty pulse for the genration of fifo read enable
|
||||
//--------------------------------------------------------------------------
|
||||
always @(posedge pos_rclk or negedge aresetn_rclk) begin
|
||||
if(!aresetn_rclk | !sresetn_rclk) begin
|
||||
fifo_empty_pulse_d <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (fifo_empty_pulse == 1'b1) begin
|
||||
fifo_empty_pulse_d <= 1'b1;
|
||||
end else if (fifo_empty == 1'b0 && fifo_empty_r == 1'b0) begin
|
||||
fifo_empty_pulse_d <= 1'b0;
|
||||
end else begin
|
||||
fifo_empty_pulse_d <= fifo_empty_pulse_d;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// FWFT logic
|
||||
// --------------------------------------------------------------------------
|
||||
//assign dout = fifo_dout;
|
||||
|
||||
//always @(posedge pos_rclk or negedge aresetn) begin
|
||||
// if((!aresetn) || (!sresetn)) begin
|
||||
// dout <= 'h0;
|
||||
// end else begin
|
||||
// dout <= fifo_dout;
|
||||
// end
|
||||
//end
|
||||
|
||||
always @(posedge pos_rclk or negedge aresetn_rclk) begin
|
||||
if(!aresetn_rclk | !sresetn_rclk) begin
|
||||
fifo_valid <= 1'b0;
|
||||
middle_valid <= 1'b0;
|
||||
dout_valid <= 1'b0;
|
||||
dout <= 'h0;
|
||||
middle_dout <= 'h0;
|
||||
end
|
||||
else begin
|
||||
if(update_middle) begin
|
||||
middle_dout <= fifo_dout;
|
||||
end
|
||||
if(update_dout) begin
|
||||
dout <= middle_valid ? middle_dout : fifo_dout;
|
||||
end
|
||||
|
||||
if(fifo_rd_en) begin
|
||||
fifo_valid <= 1'b1;
|
||||
end
|
||||
else if(update_middle || update_dout) begin
|
||||
fifo_valid <= 1'b0;
|
||||
end
|
||||
|
||||
if(update_middle) begin
|
||||
middle_valid <= 1'b1;
|
||||
end
|
||||
else if(update_dout) begin
|
||||
middle_valid <= 1'b0;
|
||||
end
|
||||
|
||||
if(update_dout) begin
|
||||
dout_valid <= 1'b1;
|
||||
end
|
||||
else if(re_p) begin
|
||||
dout_valid <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate the data valid signal
|
||||
// --------------------------------------------------------------------------
|
||||
generate
|
||||
if(FWFT == 1) begin
|
||||
// assign fwft_dvld = reg_valid | (re_p & !empty_r); SAR
|
||||
assign fwft_dvld = dout_valid;
|
||||
//assign fwft_dvld = (re_p & !empty_r);
|
||||
//assign fwft_dvld = reg_valid | re_p;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if(PREFETCH == 1) begin
|
||||
// assign fwft_dvld = (re_p) & !empty_r; SAR no
|
||||
assign fwft_dvld = (re_p) & dout_valid; // SAR no
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate the qualifying signal to sample the read data. It is also used
|
||||
// to generate the read data valid signal
|
||||
// --------------------------------------------------------------------------
|
||||
always @(*) begin
|
||||
if(re_p == 1'b1) begin
|
||||
reg_valid = 1'b0;
|
||||
end
|
||||
else if(empty == 1'b0 && empty_r == 1'b1) begin
|
||||
reg_valid = 1'b1;
|
||||
end
|
||||
else begin
|
||||
reg_valid = reg_valid_r;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_rclk or negedge aresetn_rclk) begin
|
||||
if(!aresetn_rclk | !sresetn_rclk) begin
|
||||
empty_r <= 1'b0;
|
||||
reg_valid_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
empty_r <= empty;
|
||||
reg_valid_r <= reg_valid;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_wclk or negedge aresetn_wclk) begin
|
||||
if(!aresetn_wclk | !sresetn_wclk) begin
|
||||
we_p_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
we_p_r <= we_p;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // corefifo_fwft
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// End - of - Code
|
||||
// --------------------------------------------------------------------------
|
||||
@@ -0,0 +1,74 @@
|
||||
// ********************************************************************/
|
||||
// Microchip Corporation Proprietary and Confidential
|
||||
// Copyright 2023 Microchip Corporation. All rights reserved.
|
||||
//
|
||||
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
|
||||
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
|
||||
// IN ADVANCE IN WRITING.
|
||||
//
|
||||
// IP Core: COREFIFO
|
||||
//
|
||||
// SVN Revision Information:
|
||||
// SVN $Revision: $
|
||||
// SVN $Date: $
|
||||
//
|
||||
//
|
||||
// *********************************************************************/
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
module COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv(
|
||||
gray_in,
|
||||
bin_out
|
||||
);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Parameter Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
parameter ADDRWIDTH = 3;
|
||||
// parameter SYNC_RESET = 0;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// I/O Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
//--------
|
||||
// Inputs
|
||||
//--------
|
||||
input [ADDRWIDTH:0] gray_in;
|
||||
|
||||
//---------
|
||||
// Outputs
|
||||
//---------
|
||||
output [ADDRWIDTH:0] bin_out;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal signals
|
||||
// --------------------------------------------------------------------------
|
||||
reg [ADDRWIDTH:0] bin_out;
|
||||
integer i;
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Start - of - Code
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Logic to Convert the Gray code to Binary
|
||||
// --------------------------------------------------------------------------
|
||||
always @(*) begin
|
||||
|
||||
bin_out[ADDRWIDTH] = gray_in[ADDRWIDTH];
|
||||
|
||||
for(i=ADDRWIDTH;i>0;i = i-1) begin
|
||||
bin_out[i-1] = (bin_out[i] ^ gray_in[i-1]);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule // corefifo_grayToBinConv
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// End - of - Code
|
||||
// --------------------------------------------------------------------------
|
||||
@@ -0,0 +1,92 @@
|
||||
// ********************************************************************/
|
||||
// Microchip Corporation Proprietary and Confidential
|
||||
// Copyright 2023 Microchip Corporation. All rights reserved.
|
||||
//
|
||||
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
|
||||
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
|
||||
// IN ADVANCE IN WRITING.
|
||||
//
|
||||
// IP Core: COREFIFO
|
||||
//
|
||||
// SVN Revision Information:
|
||||
// SVN $Revision: $
|
||||
// SVN $Date: $
|
||||
//
|
||||
//
|
||||
// *********************************************************************/
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
module COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync(
|
||||
clk,
|
||||
//rstn,
|
||||
arstn,//added in v3.0
|
||||
srstn,//added in v3.0
|
||||
inp,
|
||||
sync_out
|
||||
);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// PARAMETER Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
parameter NUM_STAGES = 2;
|
||||
parameter ADDRWIDTH = 3;
|
||||
|
||||
input clk;
|
||||
//input rstn;commented in v3.0
|
||||
input arstn;//added in v3.0
|
||||
input srstn;//added in v3.0
|
||||
input [ADDRWIDTH : 0 ] inp;
|
||||
output [ADDRWIDTH : 0 ] sync_out;
|
||||
|
||||
//reg [WIDTH -1:0] signal_out;
|
||||
|
||||
reg [ADDRWIDTH : 0 ] shift_reg ;
|
||||
reg [ADDRWIDTH : 0 ] shift_mem_reg [NUM_STAGES-1:0] ;
|
||||
|
||||
|
||||
always @ ( posedge clk or negedge arstn)
|
||||
begin
|
||||
if (!arstn | !srstn)
|
||||
shift_reg <= 'h0;
|
||||
else
|
||||
shift_reg <= inp;
|
||||
|
||||
end
|
||||
|
||||
|
||||
always @ (*)
|
||||
shift_mem_reg[0] = shift_reg;
|
||||
|
||||
integer i;
|
||||
always @ ( posedge clk or negedge arstn)
|
||||
begin
|
||||
if (!arstn | !srstn)
|
||||
begin
|
||||
for(i = NUM_STAGES-1; i >0 ; i = i-1)
|
||||
begin
|
||||
shift_mem_reg[i] <= 'h0;
|
||||
end
|
||||
end
|
||||
/// signal_out <= 'h0;
|
||||
else
|
||||
begin
|
||||
|
||||
for(i = NUM_STAGES-1; i > 0; i = i-1)
|
||||
shift_mem_reg[i] <= shift_mem_reg[i-1];
|
||||
|
||||
|
||||
//end
|
||||
//signal_out <= shift_reg[NUM_STAGES-1];
|
||||
end
|
||||
end
|
||||
|
||||
assign sync_out = shift_mem_reg[NUM_STAGES-1];
|
||||
|
||||
|
||||
|
||||
endmodule // corefifo_doubleSync
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// End - of - Code
|
||||
// --------------------------------------------------------------------------
|
||||
@@ -0,0 +1,860 @@
|
||||
// ********************************************************************/
|
||||
// Microchip Corporation Proprietary and Confidential
|
||||
// Copyright 2023 Microchip Corporation. All rights reserved.
|
||||
//
|
||||
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
|
||||
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
|
||||
// IN ADVANCE IN WRITING.
|
||||
//
|
||||
// IP Core: COREFIFO
|
||||
//
|
||||
// SVN Revision Information:
|
||||
// SVN $Revision: $
|
||||
// SVN $Date: $
|
||||
//
|
||||
//
|
||||
// *********************************************************************/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync (
|
||||
clk,
|
||||
//reset,
|
||||
aresetn,
|
||||
sresetn,
|
||||
we,
|
||||
re,
|
||||
full,
|
||||
afull,
|
||||
wrcnt,
|
||||
empty,
|
||||
aempty,
|
||||
rdcnt,
|
||||
underflow,
|
||||
overflow,
|
||||
dvld,
|
||||
wack,
|
||||
memwaddr,
|
||||
memwe,
|
||||
memraddr,
|
||||
memre
|
||||
);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// PARAMETER Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
parameter WRITE_WIDTH = 32;
|
||||
parameter WRITE_DEPTH = 10;
|
||||
parameter FULL_WRITE_DEPTH = 1024;
|
||||
parameter READ_WIDTH = 32;
|
||||
parameter READ_DEPTH = 10;
|
||||
parameter VAR_ASPECT_WRDEPTH = 10;
|
||||
parameter VAR_ASPECT_RDDEPTH = 10;
|
||||
parameter FULL_READ_DEPTH = 1024;
|
||||
parameter PREFETCH = 0;
|
||||
parameter FWFT = 0;
|
||||
parameter WCLK_HIGH = 1;
|
||||
parameter RESET_LOW = 1;
|
||||
parameter WRITE_LOW = 1;
|
||||
parameter READ_LOW = 1;
|
||||
parameter AF_FLAG_STATIC = 1;
|
||||
parameter AE_FLAG_STATIC = 1;
|
||||
parameter AFULL_VAL = 1020;
|
||||
parameter AEMPTY_VAL = 4;
|
||||
parameter ESTOP = 1;
|
||||
parameter FSTOP = 1;
|
||||
parameter PIPE = 1;
|
||||
parameter REGISTER_RADDR = 1;
|
||||
parameter READ_DVALID = 32;
|
||||
parameter WRITE_ACK = 32;
|
||||
parameter OVERFLOW_EN = 1;
|
||||
parameter UNDERFLOW_EN = 1;
|
||||
parameter WRCNT_EN = 1;
|
||||
parameter RDCNT_EN = 1;
|
||||
parameter SYNC_RESET = 0;//uncommented in v3.0
|
||||
localparam WDEPTH_CAL = (WRITE_DEPTH == 0) ? WRITE_DEPTH : (WRITE_DEPTH-1);
|
||||
localparam RDEPTH_CAL = (READ_DEPTH == 0) ? READ_DEPTH : (READ_DEPTH-1);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// I/O Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
//--------
|
||||
// Inputs
|
||||
//--------
|
||||
input clk; // fifo clock
|
||||
//input reset; // reset
|
||||
input aresetn;
|
||||
input sresetn;
|
||||
input we; // write enable to fifo
|
||||
input re; // read enable to fifo
|
||||
|
||||
//---------
|
||||
// Outputs
|
||||
//---------
|
||||
output full; // full status flag
|
||||
output afull; // almost full status flag
|
||||
output [WRITE_DEPTH:0] wrcnt; // number of elements remaining in write domain
|
||||
|
||||
output empty; // empty status flag
|
||||
output aempty; // almost empty status flag
|
||||
output [READ_DEPTH:0] rdcnt; // number of elements remaining in read domain
|
||||
|
||||
output underflow; // underflow status flag
|
||||
output overflow; // overflow status flag
|
||||
output dvld; // dvld status flag
|
||||
output wack; // wack status flag
|
||||
|
||||
output [WDEPTH_CAL:0] memwaddr; // memory write address
|
||||
output memwe; // memory write enable
|
||||
output [RDEPTH_CAL:0] memraddr; // memory read address
|
||||
output memre; // memory read enable
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal signals
|
||||
// --------------------------------------------------------------------------
|
||||
wire full;
|
||||
wire afull;
|
||||
wire [WRITE_DEPTH:0] wrcnt;
|
||||
wire empty;
|
||||
wire aempty;
|
||||
wire [READ_DEPTH:0] rdcnt;
|
||||
wire [WDEPTH_CAL:0] memwaddr;
|
||||
wire memwe;
|
||||
wire [RDEPTH_CAL:0] memraddr;
|
||||
wire memre;
|
||||
|
||||
reg full_r;
|
||||
// reg full_reg;
|
||||
reg afull_r;
|
||||
reg [WRITE_DEPTH:0] wrcnt_r;
|
||||
reg empty_r;
|
||||
reg aempty_r;
|
||||
reg [READ_DEPTH:0] rdcnt_r;
|
||||
reg [WDEPTH_CAL:0] memwaddr_r;
|
||||
reg [RDEPTH_CAL:0] memraddr_r;
|
||||
reg dvld_r;
|
||||
reg dvld_r2;
|
||||
reg underflow_r;
|
||||
reg wack_r;
|
||||
reg overflow_r;
|
||||
//reg [READ_DEPTH:0] rptr;
|
||||
reg [READ_DEPTH:0] rptr_nxt;
|
||||
// reg [WRITE_DEPTH:0] wptr;
|
||||
reg [WRITE_DEPTH:0] wptr_nxt;
|
||||
reg [VAR_ASPECT_WRDEPTH:0] wptrsync_shift;
|
||||
reg [VAR_ASPECT_RDDEPTH:0] rptrsync_shift;
|
||||
// reg re_p_d1;
|
||||
|
||||
wire [WRITE_DEPTH:0] afthreshi, wdiff_bus;
|
||||
wire [READ_DEPTH:0] aethreshi, rdiff_bus;
|
||||
wire fulli;
|
||||
wire almostfulli;
|
||||
wire almostfulli_assert;
|
||||
wire almostfulli_deassert;
|
||||
wire emptyi;
|
||||
wire almostemptyi;
|
||||
wire almostemptyi_assert;
|
||||
wire almostemptyi_deassert;
|
||||
wire we_p;
|
||||
wire re_p;
|
||||
wire we_i;
|
||||
wire re_i;
|
||||
wire pos_clk;
|
||||
wire neg_reset;
|
||||
wire fulli_fstop;
|
||||
wire emptyi_estop;
|
||||
wire aresetn;
|
||||
wire sresetn;//uncommented in v3.0
|
||||
|
||||
wire [WRITE_DEPTH : 0] wptr_cmb;
|
||||
wire [READ_DEPTH : 0] rptr_cmb;
|
||||
// --------------------------------------------------------------------------
|
||||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||
// || ||
|
||||
// || Start - of - Code ||
|
||||
// || ||
|
||||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Top-level outputs
|
||||
// --------------------------------------------------------------------------
|
||||
assign full = full_r;
|
||||
assign afull = afull_r;
|
||||
assign empty = empty_r;
|
||||
assign aempty = aempty_r;
|
||||
assign underflow = underflow_r;
|
||||
assign wack = wack_r;
|
||||
assign overflow = overflow_r;
|
||||
assign memwaddr = memwaddr_r;
|
||||
assign memraddr = memraddr_r;
|
||||
|
||||
assign wrcnt = wrcnt_r;
|
||||
assign rdcnt = rdcnt_r;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// threshold values
|
||||
// --------------------------------------------------------------------------
|
||||
assign afthreshi = AF_FLAG_STATIC ? AFULL_VAL-1 : FULL_WRITE_DEPTH;
|
||||
//***HARI***assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL+1 : 0;
|
||||
assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL : 2;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// clocks and enables
|
||||
// --------------------------------------------------------------------------
|
||||
assign pos_clk = WCLK_HIGH ? clk : ~clk;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// resets
|
||||
// --------------------------------------------------------------------------
|
||||
/* // assign neg_reset = RESET_LOW ? ~reset : reset;----------------------commented by anurag
|
||||
assign aresetn = RESET_LOW ? ~reset : reset;//----------------------updated by anurag
|
||||
// assign aresetn = (SYNC_RESET == 1) ? 1'b1 : neg_reset;-----------commented by anurag
|
||||
// assign sresetn = (SYNC_RESET == 1) ? neg_reset : 1'b1;------------commented by anurag */
|
||||
|
||||
//assign neg_reset = RESET_LOW ? ~reset : reset;//uncommented in v3.0
|
||||
//
|
||||
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : neg_reset;//uncommented in v3.0
|
||||
//assign sresetn = (SYNC_RESET == 1) ? neg_reset : 1'b1;//uncommented in v3.0
|
||||
// --------------------------------------------------------------------------
|
||||
// Status flags
|
||||
// --------------------------------------------------------------------------
|
||||
assign we_p = WRITE_LOW ? (~we) : (we);
|
||||
assign re_p = READ_LOW ? (~re) : (re);
|
||||
assign we_i = we_p & !full_r;
|
||||
assign re_i = re_p & !empty_r;
|
||||
//assign wdiff_bus = wptr_nxt - rptrsync_shift;
|
||||
assign wdiff_bus = wptr_cmb - rptrsync_shift;
|
||||
//assign rdiff_bus = wptrsync_shift - rptr_nxt;
|
||||
assign rdiff_bus = wptrsync_shift - rptr_cmb;
|
||||
assign dvld = (REGISTER_RADDR==2) ? dvld_r2 :
|
||||
((REGISTER_RADDR == 1 && PREFETCH == 0) ? dvld_r : re_i);
|
||||
|
||||
/* always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
full_reg <= 0;
|
||||
end
|
||||
else begin
|
||||
full_reg <= full_r;
|
||||
end
|
||||
end
|
||||
*/
|
||||
// --------------------------------------------------------------------------
|
||||
// Read pointer binary counter
|
||||
// --------------------------------------------------------------------------
|
||||
/* always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
rptr <= 0;
|
||||
end
|
||||
else begin
|
||||
rptr <= rptr_nxt;
|
||||
end
|
||||
end */
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Write pointer binary counter
|
||||
// --------------------------------------------------------------------------
|
||||
/* always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
wptr <= 0;
|
||||
end
|
||||
else begin
|
||||
wptr <= wptr_nxt;
|
||||
end
|
||||
end */
|
||||
|
||||
/* always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if(!aresetn | !sresetn ) begin
|
||||
re_p_d1 <= 'h0;
|
||||
end
|
||||
else begin
|
||||
re_p_d1 <= re_p;
|
||||
end
|
||||
end */
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// For variable aspect ratios
|
||||
// The variable aspect logic is handled by shifting the required bits of the
|
||||
// read/write pointer so that they are of the same width.
|
||||
// --------------------------------------------------------------------------
|
||||
always @(rptr_nxt or wptr_nxt)
|
||||
begin
|
||||
if (WRITE_DEPTH > READ_DEPTH) begin
|
||||
rptrsync_shift = rptr_nxt<<(WRITE_DEPTH - READ_DEPTH);
|
||||
wptrsync_shift = wptr_nxt>>(WRITE_DEPTH - READ_DEPTH);
|
||||
end
|
||||
else if (READ_DEPTH > WRITE_DEPTH) begin
|
||||
rptrsync_shift = rptr_nxt>>(READ_DEPTH - WRITE_DEPTH);
|
||||
wptrsync_shift = wptr_nxt<<(READ_DEPTH - WRITE_DEPTH);
|
||||
end
|
||||
else begin
|
||||
rptrsync_shift = rptr_nxt;
|
||||
wptrsync_shift = wptr_nxt;
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Flag generation logic
|
||||
// --------------------------------------------------------------------------
|
||||
//***HARI***assign almostfulli = wdiff_bus >= afthreshi;
|
||||
assign almostfulli_assert = we_p & (wdiff_bus >= afthreshi);
|
||||
assign almostfulli_deassert = (wdiff_bus <= afthreshi);
|
||||
assign almostfulli = almostfulli_assert ? 1'b1 : (almostfulli_deassert? 1'b0 : afull );
|
||||
|
||||
//***HARI***assign almostemptyi = aethreshi >= rdiff_bus;
|
||||
assign almostemptyi_assert = re_p & (aethreshi >= rdiff_bus);
|
||||
assign almostemptyi_deassert = (aethreshi <= rdiff_bus) & aempty;
|
||||
assign almostemptyi = almostemptyi_deassert ? 1'b0 : (almostemptyi_assert ? 1'b1 : aempty);
|
||||
|
||||
//assign fulli = we_p ? (wdiff_bus >= (FULL_WRITE_DEPTH-1)) : (wdiff_bus >= (FULL_WRITE_DEPTH));
|
||||
assign fulli = we_p ? (wdiff_bus > (FULL_WRITE_DEPTH-1)) : (wdiff_bus >= (FULL_WRITE_DEPTH));
|
||||
//assign fulli_fstop = (we_p & !full_r) ? (wdiff_bus[WRITE_DEPTH - 1:0] == (FULL_WRITE_DEPTH-1)) :(((we_p ^ re_p) & full_r)? 1'b0 : full_r);
|
||||
assign fulli_fstop = (we_p & !full_r) ? (wdiff_bus > (FULL_WRITE_DEPTH -1)) :(((we_p ^ re_p) & full_r)? 1'b0 : full_r);
|
||||
|
||||
//assign emptyi = (rdiff_bus <= 1);
|
||||
assign emptyi = (rdiff_bus < 1);
|
||||
//assign emptyi_estop = re_p ? (rdiff_bus == 1) : (rdiff_bus <= 0);
|
||||
assign emptyi_estop = re_p ? (rdiff_bus == 0) : (rdiff_bus <= 0);
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
dvld_r2 <= 0;
|
||||
end
|
||||
else begin
|
||||
dvld_r2 <= dvld_r;
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Update the pointer values based in ESTOP and FSTOP parameters.
|
||||
// Generate the status flags - Empty/Full/Almost Empty/ Almost Full
|
||||
// Generate the data handshaking flags - DVLD/WACK
|
||||
// Generate error count flags - Underflow/Overflow
|
||||
// Generate write and read address signals to the external memory
|
||||
// --------------------------------------------------------------------------
|
||||
genvar k;
|
||||
generate
|
||||
|
||||
if (ESTOP == 1 && FSTOP == 1) begin
|
||||
/* ESTOP and FSTOP both are true */
|
||||
/* write pointer */
|
||||
|
||||
assign wptr_cmb = wptr_nxt + we_i;///////////////////////////added
|
||||
assign rptr_cmb = rptr_nxt + re_i;//////////////////////////added
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
wptr_nxt <= 0;
|
||||
end
|
||||
else if(we_i == 1'b1) begin
|
||||
//wptr_nxt <= wptr_nxt + 1;
|
||||
wptr_nxt <= wptr_cmb;/////////////added
|
||||
end
|
||||
end
|
||||
|
||||
/* read pointer */
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
rptr_nxt <= 0;
|
||||
end
|
||||
else if(re_i == 1'b1) begin
|
||||
//rptr_nxt <= rptr_nxt + 1;
|
||||
rptr_nxt <= rptr_cmb;/////////////added
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
empty_r <= 1;
|
||||
aempty_r <= 1;
|
||||
dvld_r <= 0;
|
||||
underflow_r <= 0;
|
||||
rdcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
//if((re_p & (rdiff_bus == 1))) begin
|
||||
if((re_i & (rdiff_bus == 0))) begin
|
||||
empty_r <= 1'b1;
|
||||
end
|
||||
else if((!re_p & (rdiff_bus == 1))) begin
|
||||
empty_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
empty_r <= emptyi;
|
||||
end
|
||||
|
||||
aempty_r <= almostemptyi;
|
||||
if(RDCNT_EN == 1) begin
|
||||
rdcnt_r <= rdiff_bus;
|
||||
end
|
||||
|
||||
if (re_i == 1'b1 && READ_DVALID == 1)
|
||||
dvld_r <= 1'b1;
|
||||
else
|
||||
dvld_r <= 1'b0;
|
||||
|
||||
if (re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
|
||||
underflow_r <= 1'b1;
|
||||
else
|
||||
underflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
full_r <= 0;
|
||||
afull_r <= 0;
|
||||
wack_r <= 0;
|
||||
overflow_r <= 0;
|
||||
wrcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
full_r <= FSTOP ? fulli : fulli_fstop;
|
||||
afull_r <= almostfulli;
|
||||
|
||||
//if (full_r == 1'b0 && WRCNT_EN == 1) begin
|
||||
if ( WRCNT_EN == 1) begin
|
||||
wrcnt_r <= wdiff_bus;
|
||||
end
|
||||
|
||||
if (we_i == 1'b1 && WRITE_ACK == 1)
|
||||
wack_r <= 1'b1;
|
||||
else
|
||||
wack_r <= 1'b0;
|
||||
|
||||
if (we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
|
||||
overflow_r <= 1'b1;
|
||||
else
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn )
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memwaddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if (we_i == 1'b1) begin
|
||||
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
|
||||
memwaddr_r <= 'h0;
|
||||
end else begin
|
||||
memwaddr_r <= memwaddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memraddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if (re_i == 1'b1) begin
|
||||
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
|
||||
memraddr_r <= 'h0;
|
||||
end else begin
|
||||
memraddr_r <= memraddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign memwe = we_i;
|
||||
assign memre = re_i;
|
||||
|
||||
|
||||
end
|
||||
else if (ESTOP == 1 && FSTOP == 0) begin
|
||||
/* ESTOP is true and FSTOP is false */
|
||||
|
||||
/* write pointer */
|
||||
assign wptr_cmb = wptr_nxt + we_p;
|
||||
assign rptr_cmb = rptr_nxt + re_i;
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
wptr_nxt <= 0;
|
||||
end
|
||||
else if(we_p == 1'b1) begin
|
||||
//wptr_nxt <= wptr_nxt + 1;
|
||||
wptr_nxt <= wptr_cmb;
|
||||
end
|
||||
end
|
||||
|
||||
/* read pointer */
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
rptr_nxt <= 0;
|
||||
end
|
||||
else if(re_i == 1'b1) begin
|
||||
//rptr_nxt <= rptr_nxt + 1;
|
||||
rptr_nxt <= wptr_cmb;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
empty_r <= 1;
|
||||
aempty_r <= 1;
|
||||
dvld_r <= 0;
|
||||
underflow_r <= 0;
|
||||
rdcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
//if((re_p & (rdiff_bus == 1))) begin
|
||||
if(((rdiff_bus == 0))) begin
|
||||
empty_r <= 1'b1;
|
||||
end
|
||||
else if((!re_p & (rdiff_bus == 1))) begin
|
||||
empty_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
empty_r <= emptyi;
|
||||
end
|
||||
|
||||
aempty_r <= almostemptyi;
|
||||
if(RDCNT_EN == 1) begin
|
||||
rdcnt_r <= rdiff_bus;
|
||||
end
|
||||
|
||||
if (re_i == 1'b1 && READ_DVALID == 1'b1)
|
||||
dvld_r <= 1'b1;
|
||||
else
|
||||
dvld_r <= 1'b0;
|
||||
|
||||
if (re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
|
||||
underflow_r <= 1'b1;
|
||||
else
|
||||
underflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
full_r <= 0;
|
||||
afull_r <= 0;
|
||||
wack_r <= 0;
|
||||
overflow_r <= 0;
|
||||
wrcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
full_r <= fulli_fstop;
|
||||
afull_r <= almostfulli;
|
||||
if(WRCNT_EN == 1) begin
|
||||
wrcnt_r <= wdiff_bus;
|
||||
end
|
||||
|
||||
if (we_p == 1'b1 && WRITE_ACK == 1'b1)
|
||||
wack_r <= 1'b1;
|
||||
else
|
||||
wack_r <= 1'b0;
|
||||
|
||||
if (we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
|
||||
overflow_r <= 1'b1;
|
||||
else
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn )
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
memwaddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if (we_p == 1'b1) begin
|
||||
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
|
||||
memwaddr_r <= 'h0;
|
||||
end else begin
|
||||
memwaddr_r <= memwaddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
memraddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if (re_i == 1'b1) begin
|
||||
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
|
||||
memraddr_r <= 'h0;
|
||||
end else begin
|
||||
memraddr_r <= memraddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign memwe = we_p;
|
||||
assign memre = re_i;
|
||||
|
||||
end
|
||||
else if (ESTOP == 0 && FSTOP == 1) begin
|
||||
/* FSTOP is true and ESTOP is false */
|
||||
|
||||
/* write pointer */
|
||||
assign wptr_cmb = wptr_nxt + we_i;
|
||||
assign rptr_cmb = rptr_nxt + re_p;
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
wptr_nxt <= 0;
|
||||
end
|
||||
else if(we_i == 1'b1) begin
|
||||
wptr_nxt <= wptr_cmb;
|
||||
end
|
||||
end
|
||||
|
||||
/* read pointer */
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
rptr_nxt <= 0;
|
||||
end
|
||||
else if(re_p == 1'b1) begin
|
||||
//rptr_nxt <= rptr_nxt + 1;
|
||||
rptr_nxt <= rptr_cmb;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
empty_r <= 1;
|
||||
aempty_r <= 1;
|
||||
dvld_r <= 0;
|
||||
underflow_r <= 0;
|
||||
rdcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
empty_r <= emptyi;
|
||||
aempty_r <= almostemptyi;
|
||||
if(RDCNT_EN == 1) begin
|
||||
rdcnt_r <= rdiff_bus;
|
||||
end
|
||||
|
||||
if (re_p == 1'b1 && READ_DVALID == 1'b1)
|
||||
dvld_r <= 1'b1;
|
||||
else
|
||||
dvld_r <= 1'b0;
|
||||
|
||||
if ( re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
|
||||
underflow_r <= 1'b1;
|
||||
else
|
||||
underflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
full_r <= 0;
|
||||
afull_r <= 0;
|
||||
wack_r <= 0;
|
||||
overflow_r <= 0;
|
||||
wrcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
full_r <= fulli;
|
||||
afull_r <= almostfulli;
|
||||
|
||||
//if (full_r == 1'b0 && WRCNT_EN == 1) begin
|
||||
if ( WRCNT_EN == 1) begin
|
||||
wrcnt_r <= wdiff_bus;
|
||||
end
|
||||
|
||||
if (we_i ==1'b1 && WRITE_ACK == 1'b1)
|
||||
wack_r <= 1'b1;
|
||||
else
|
||||
wack_r <= 1'b0;
|
||||
|
||||
if (we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
|
||||
overflow_r <= 1'b1;
|
||||
else
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn )
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memwaddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if ( we_i == 1'b1) begin
|
||||
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
|
||||
memwaddr_r <= 'h0;
|
||||
end else begin
|
||||
memwaddr_r <= memwaddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memraddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if ( re_p == 1'b1) begin
|
||||
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
|
||||
memraddr_r <= 'h0;
|
||||
end else begin
|
||||
memraddr_r <= memraddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign memwe = we_i;
|
||||
assign memre = re_p;
|
||||
|
||||
end
|
||||
else if (ESTOP == 0 && FSTOP == 0) begin
|
||||
/* ESTOP and FSTOP are false */
|
||||
|
||||
/* write pointer */
|
||||
assign wptr_cmb = wptr_nxt + we_p;
|
||||
assign rptr_cmb = rptr_nxt + re_p;
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
wptr_nxt <= 0;
|
||||
end
|
||||
else if(we_p == 1'b1) begin
|
||||
//wptr_nxt <= wptr_nxt + 1;
|
||||
wptr_nxt <= wptr_cmb;
|
||||
end
|
||||
end
|
||||
|
||||
/* read pointer */
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
rptr_nxt <= 0;
|
||||
end
|
||||
else if(re_p == 1'b1) begin
|
||||
//rptr_nxt <= rptr_nxt + 1;
|
||||
rptr_nxt <= rptr_cmb;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
empty_r <= 1;
|
||||
aempty_r <= 1;
|
||||
dvld_r <= 0;
|
||||
underflow_r <= 0;
|
||||
rdcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
empty_r <= emptyi_estop;
|
||||
aempty_r <= almostemptyi;
|
||||
if(RDCNT_EN == 1) begin
|
||||
rdcnt_r <= rdiff_bus;
|
||||
end
|
||||
|
||||
if (re_p == 1'b1 && READ_DVALID == 1'b1)
|
||||
dvld_r <= 1'b1;
|
||||
else
|
||||
dvld_r <= 1'b0;
|
||||
|
||||
if ( re_p ==1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
|
||||
underflow_r <= 1'b1;
|
||||
else
|
||||
underflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
full_r <= 0;
|
||||
afull_r <= 0;
|
||||
wack_r <= 0;
|
||||
overflow_r <= 0;
|
||||
wrcnt_r <= 0;
|
||||
end
|
||||
else begin
|
||||
full_r <= fulli_fstop;
|
||||
afull_r <= almostfulli;
|
||||
if(WRCNT_EN == 1) begin
|
||||
wrcnt_r <= wdiff_bus;
|
||||
end
|
||||
|
||||
if (we_p == 1'b1 && WRITE_ACK == 1'b1)
|
||||
wack_r <= 1'b1;
|
||||
else
|
||||
wack_r <= 1'b0;
|
||||
|
||||
if ( we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
|
||||
overflow_r <= 1'b1;
|
||||
else
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn )
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memwaddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if ( we_p == 1'b1) begin
|
||||
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
|
||||
memwaddr_r <= 'h0;
|
||||
end else begin
|
||||
memwaddr_r <= memwaddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memraddr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
if ( re_p == 1'b1) begin
|
||||
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
|
||||
memraddr_r <= 'h0;
|
||||
end else begin
|
||||
memraddr_r <= memraddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign memwe = we_p;
|
||||
assign memre = re_p;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule // corefifo_sync
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// End - of - Code
|
||||
// --------------------------------------------------------------------------
|
||||
@@ -0,0 +1,656 @@
|
||||
// ********************************************************************/
|
||||
// Microchip Corporation Proprietary and Confidential
|
||||
// Copyright 2023 Microchip Corporation. All rights reserved.
|
||||
//
|
||||
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
|
||||
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
|
||||
// IN ADVANCE IN WRITING.
|
||||
//
|
||||
// IP Core: COREFIFO
|
||||
//
|
||||
// SVN Revision Information:
|
||||
// SVN $Revision: $
|
||||
// SVN $Date: $
|
||||
//
|
||||
//
|
||||
// *********************************************************************/
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr (
|
||||
clk,
|
||||
//reset,
|
||||
aresetn,
|
||||
sresetn,
|
||||
we,
|
||||
re,
|
||||
re_top,
|
||||
full,
|
||||
afull,
|
||||
wrcnt,
|
||||
empty,
|
||||
aempty,
|
||||
rdcnt,
|
||||
underflow,
|
||||
overflow,
|
||||
dvld,
|
||||
wack,
|
||||
memwaddr,
|
||||
memwe,
|
||||
memraddr,
|
||||
memre,
|
||||
empty_top_fwft
|
||||
|
||||
);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// PARAMETER Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
parameter WRITE_WIDTH = 18;
|
||||
parameter WRITE_DEPTH = 10;
|
||||
parameter FULL_WRITE_DEPTH = 1024;
|
||||
parameter READ_WIDTH = 18;
|
||||
parameter READ_DEPTH = WRITE_DEPTH;
|
||||
parameter FULL_READ_DEPTH = 1024;
|
||||
parameter PREFETCH = 1;
|
||||
parameter FWFT = 0;
|
||||
parameter WCLK_HIGH = 1;
|
||||
parameter RESET_LOW = 1;
|
||||
parameter WRITE_LOW = 1;
|
||||
parameter READ_LOW = 1;
|
||||
parameter AF_FLAG_STATIC = 1;
|
||||
parameter AE_FLAG_STATIC = 1;
|
||||
parameter AFULL_VAL = 1020;
|
||||
parameter AEMPTY_VAL = 4;
|
||||
parameter ESTOP = 1;
|
||||
parameter FSTOP = 1;
|
||||
parameter PIPE = 1;
|
||||
parameter REGISTER_RADDR = 1;
|
||||
parameter READ_DVALID = 1;
|
||||
parameter WRITE_ACK = 1;
|
||||
parameter OVERFLOW_EN = 1;
|
||||
parameter UNDERFLOW_EN = 1;
|
||||
parameter WRCNT_EN = 1;
|
||||
parameter RDCNT_EN = 1;
|
||||
parameter ECC = 1;
|
||||
parameter SYNC_RESET = 0;//uncommented in v3.0
|
||||
parameter FAMILY = 25;
|
||||
localparam WDEPTH_CAL = (WRITE_DEPTH == 0) ? WRITE_DEPTH : (WRITE_DEPTH-1);
|
||||
localparam RDEPTH_CAL = (READ_DEPTH == 0) ? READ_DEPTH : (READ_DEPTH-1);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// I/O Declaration
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
//--------
|
||||
// Inputs
|
||||
//--------
|
||||
input clk; // fifo clock
|
||||
//input reset; // reset
|
||||
input aresetn;
|
||||
input sresetn;
|
||||
input we; // write enable to fifo
|
||||
input re; // read enable to fifo
|
||||
input re_top; // read enable to fifo
|
||||
input empty_top_fwft;
|
||||
|
||||
//---------
|
||||
// Outputs
|
||||
//---------
|
||||
output full; // full status flag
|
||||
output afull; // almost full status flag
|
||||
output [WRITE_DEPTH:0] wrcnt; // number of elements remaining in write domain
|
||||
|
||||
output empty; // empty status flag
|
||||
output aempty; // almost empty status flag
|
||||
output [READ_DEPTH:0] rdcnt; // number of elements remaining in read domain
|
||||
|
||||
output underflow; // underflow status flag
|
||||
output overflow; // overflow status flag
|
||||
output dvld; // dvld status flag
|
||||
output wack; // wack status flag
|
||||
|
||||
output [WDEPTH_CAL:0] memwaddr; // memory write address
|
||||
output memwe; // memory write enable
|
||||
output [RDEPTH_CAL:0] memraddr; // memory read address
|
||||
output memre; // memory read enable
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal signals
|
||||
// --------------------------------------------------------------------------
|
||||
wire full;
|
||||
wire afull;
|
||||
reg [WRITE_DEPTH:0] wrcnt;
|
||||
wire empty;
|
||||
wire aempty;
|
||||
wire aempty_fwft;
|
||||
reg [READ_DEPTH:0] rdcnt;
|
||||
wire [WDEPTH_CAL:0] memwaddr;
|
||||
wire memwe;
|
||||
wire [RDEPTH_CAL:0] memraddr;
|
||||
wire memre;
|
||||
|
||||
reg full_r;
|
||||
reg full_reg;
|
||||
reg afull_r;
|
||||
reg empty_r;
|
||||
reg empty_r_fwft;
|
||||
reg empty_top_fwft_r;
|
||||
reg aempty_r;
|
||||
reg aempty_r_fwft;
|
||||
reg [WDEPTH_CAL:0] memwaddr_r;
|
||||
reg [RDEPTH_CAL:0] memraddr_r;
|
||||
reg dvld_r;
|
||||
reg dvld_r2;
|
||||
reg underflow_r;
|
||||
reg wack_r;
|
||||
reg overflow_r;
|
||||
reg [READ_DEPTH:0] sc_r;
|
||||
reg [WRITE_DEPTH:0] sc_w;
|
||||
wire [READ_DEPTH:0] sc_r_cmb;//added in v3.0
|
||||
wire [WRITE_DEPTH:0] sc_w_cmb;//added in v3.0
|
||||
reg [READ_DEPTH:0] sc_r_fwft;
|
||||
wire [READ_DEPTH:0] sc_r_fwft_cmb;//added in v3.0
|
||||
reg almostemptyi;
|
||||
reg re_p_d1;
|
||||
reg we_f_i;
|
||||
|
||||
wire [WRITE_DEPTH:0] afthreshi;
|
||||
wire [READ_DEPTH:0] aethreshi;
|
||||
wire fulli;
|
||||
wire almostfulli;
|
||||
wire almostfulli_assert;
|
||||
wire almostfulli_deassert;
|
||||
wire fulli_assert;
|
||||
wire fulli_deassert;
|
||||
wire emptyi;
|
||||
wire emptyi_fwft;
|
||||
wire we_p;
|
||||
wire re_p;
|
||||
wire we_i;
|
||||
wire re_i;
|
||||
wire pos_clk;
|
||||
wire neg_reset;
|
||||
wire re_top_p;
|
||||
wire aresetn;
|
||||
wire sresetn;//uncommented in v3.0
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||
// || ||
|
||||
// || Start - of - Code ||
|
||||
// || ||
|
||||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||
// --------------------------------------------------------------------------
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// clocks and enables
|
||||
// --------------------------------------------------------------------------
|
||||
assign pos_clk = WCLK_HIGH ? clk : ~clk;
|
||||
|
||||
|
||||
//assign resetn = RESET_LOW ? ~reset : reset;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// resets
|
||||
// --------------------------------------------------------------------------
|
||||
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : neg_reset;
|
||||
//assign sresetn = (SYNC_RESET == 1) ? neg_reset : 1'b1;
|
||||
|
||||
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : resetn;
|
||||
//assign sresetn = (SYNC_RESET == 1) ? resetn : 1'b1;
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Read and Write enables
|
||||
// --------------------------------------------------------------------------
|
||||
generate
|
||||
if (FWFT == 0 && PREFETCH == 0) begin
|
||||
assign re_p = READ_LOW ? (~re) : (re);
|
||||
assign we_p = WRITE_LOW ? (~we) : (we);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if ((FWFT == 1 || PREFETCH == 1) && PIPE == 1) begin
|
||||
assign re_p = re;
|
||||
assign re_top_p = READ_LOW ? (~re_top) : (re_top);
|
||||
assign we_p = WRITE_LOW ? (~we) : (we);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign we_i = we_p & !full_r ;
|
||||
assign re_i = re_p & !empty_r;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Top-level outputs
|
||||
// --------------------------------------------------------------------------
|
||||
assign full = full_r;
|
||||
assign afull = afull_r;
|
||||
assign empty = empty_r;
|
||||
assign aempty = aempty_r;
|
||||
assign aempty_fwft = aempty_r;
|
||||
assign underflow = underflow_r;
|
||||
assign wack = wack_r;
|
||||
assign dvld = (REGISTER_RADDR==2) ? dvld_r2 :
|
||||
((REGISTER_RADDR == 1 && PREFETCH == 0) ? dvld_r : re_i);
|
||||
assign overflow = overflow_r;
|
||||
assign memwaddr = memwaddr_r;
|
||||
assign memraddr = memraddr_r;
|
||||
assign memwe = we_i;
|
||||
assign memre = re_i;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate top-level read data output
|
||||
// wrcnt: write count is the number of elements remaining in the Wr clock
|
||||
// domain
|
||||
// --------------------------------------------------------------------------
|
||||
always @(negedge aresetn or posedge pos_clk)
|
||||
begin
|
||||
if (!aresetn | !sresetn ) begin
|
||||
wrcnt <= {WRITE_DEPTH{1'b0}};
|
||||
end
|
||||
else if (WRCNT_EN && PREFETCH == 0 && FWFT == 0 && ECC == 1 && FAMILY == 25) begin
|
||||
//wrcnt <= sc_r;
|
||||
wrcnt <= sc_w_cmb; ////added in v3.0
|
||||
end
|
||||
else if (WRCNT_EN && PREFETCH == 0 && FWFT == 0) begin
|
||||
//wrcnt <= sc_r;
|
||||
wrcnt <= sc_r_cmb; ////added in v3.0
|
||||
end
|
||||
|
||||
else if (WRCNT_EN && (PREFETCH == 1 || FWFT == 1)) begin
|
||||
//wrcnt <= sc_r_fwft;
|
||||
wrcnt <= sc_r_fwft_cmb; ////added in v3.0
|
||||
end
|
||||
else begin
|
||||
wrcnt <= {WRITE_DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// rdcnt: read count is the number of elements remaining in the Rd clock
|
||||
// domain
|
||||
// --------------------------------------------------------------------------
|
||||
always @(negedge aresetn or posedge pos_clk)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
rdcnt <= {READ_DEPTH{1'b0}};
|
||||
end
|
||||
else if (RDCNT_EN && PREFETCH == 0 && FWFT == 0) begin
|
||||
//rdcnt <= sc_r;
|
||||
rdcnt <= sc_r_cmb; ////added in v3.0
|
||||
end
|
||||
else if (RDCNT_EN && (PREFETCH == 1 || FWFT == 1)) begin
|
||||
//rdcnt <= sc_r_fwft;
|
||||
rdcnt <= sc_r_fwft_cmb; //added in v3.0
|
||||
end
|
||||
else begin
|
||||
rdcnt <= {READ_DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
|
||||
//////////////////////////////////////For ECC and pipe/////AI
|
||||
generate
|
||||
//if ( ECC == 1 && PIPE == 2 )
|
||||
if ( ECC == 1 && FAMILY == 25 )
|
||||
begin
|
||||
reg empty_f;
|
||||
|
||||
assign emptyi = (( sc_r == 1) & re_i & !we_f_i);
|
||||
|
||||
always @(negedge aresetn or posedge pos_clk)
|
||||
begin
|
||||
if (!aresetn | !sresetn)
|
||||
empty_f <= 1'b1;
|
||||
else if (re_i ^ we_i)
|
||||
empty_f <= emptyi ;
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
if (!aresetn | !sresetn) //begin
|
||||
empty_r <= 1'b1;
|
||||
else
|
||||
empty_r <= emptyi ? 1'b1 : empty_f;
|
||||
end
|
||||
else
|
||||
begin
|
||||
assign emptyi = ( sc_r == 1) & !we_i & re_i;
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
if (!aresetn | !sresetn)
|
||||
empty_r <= 1'b1;
|
||||
else if(re_i ^ we_i)
|
||||
empty_r <= emptyi;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
////////////////////////////////////////////
|
||||
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
if (!aresetn | !sresetn)
|
||||
we_f_i <= 1'b0;
|
||||
else
|
||||
we_f_i <= we_i;
|
||||
|
||||
|
||||
|
||||
|
||||
assign sc_r_cmb = ( ECC == 1 && FAMILY == 25 ) ? sc_r + we_f_i - re_i : sc_r + we_i - re_i;////added in v3.0
|
||||
generate
|
||||
if(( ECC == 1 && FAMILY == 25 ))
|
||||
assign sc_w_cmb = sc_w + we_i - re_i;////added in v3.0
|
||||
else
|
||||
assign sc_w_cmb = 0;
|
||||
endgenerate
|
||||
|
||||
assign sc_r_fwft_cmb = sc_r_fwft + we_i - re_top_p;////added in v3.0
|
||||
// --------------------------------------------------------------------------
|
||||
// Binary counter
|
||||
// The counter increments on Write and decrements on Read
|
||||
// --------------------------------------------------------------------------
|
||||
always @(negedge aresetn or posedge pos_clk)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
sc_r <= 0;
|
||||
end
|
||||
else if ( ECC == 1 && FAMILY == 25 ) begin
|
||||
if( we_f_i ^ re_i) begin
|
||||
sc_r <= sc_r_cmb;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if ( we_i ^ re_i) begin
|
||||
sc_r <= sc_r_cmb; //added in v3.0
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(negedge aresetn or posedge pos_clk)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
sc_w <= 0;
|
||||
end
|
||||
else if ( ECC == 1 && FAMILY == 25 ) begin
|
||||
if( we_i ^ re_i) begin
|
||||
sc_w <= sc_w_cmb;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(negedge aresetn or posedge pos_clk)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
sc_r_fwft <= 0;
|
||||
end
|
||||
//else if ( we_i ^ ((re_top_p & empty_top_fwft & !empty_top_fwft_r) || (re_top_p & !empty_top_fwft) )) begin ---SAR #112344
|
||||
else if ( we_i ^ (re_top_p & !empty_top_fwft)) begin
|
||||
if(we_i == 1'b1) begin
|
||||
//sc_r_fwft <= (sc_r_fwft + 1);
|
||||
sc_r_fwft <= sc_r_fwft_cmb; //added in v3.0
|
||||
end
|
||||
//else if(((re_top_p & empty_top_fwft & !empty_top_fwft_r) || (re_top_p & !empty_top_fwft) )) begin ---SAR #112344
|
||||
else if(re_top_p & !empty_top_fwft) begin
|
||||
//sc_r_fwft <= (sc_r_fwft - 1);
|
||||
sc_r_fwft <= sc_r_fwft_cmb;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign emptyi_fwft = ( sc_r_fwft == 'h0);
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate almost flags
|
||||
// --------------------------------------------------------------------------
|
||||
generate
|
||||
if (FWFT == 0 && PREFETCH == 0) begin
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// threshold values
|
||||
// --------------------------------------------------------------------------
|
||||
assign afthreshi = AF_FLAG_STATIC ? AFULL_VAL-1 : FULL_WRITE_DEPTH;
|
||||
assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL : 2; //SAR#60185
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
//***AHK almostemptyi = (( sc_r <= aethreshi) & !we_i & re_i) | ( (sc_r < aethreshi) & we_i & !re_i);
|
||||
almostemptyi = (( sc_r <= aethreshi) & !we_i & re_i) | ( (sc_r+1 < aethreshi) & we_i & !re_i);
|
||||
end
|
||||
|
||||
//***AHK assign almostfulli = ((sc_r >= (afthreshi)) & we_i & !re_i) | ( (sc_r > afthreshi) & !we_i & re_i);
|
||||
assign almostfulli = ( ECC == 1 && FAMILY == 25 ) ? ((sc_w >= (afthreshi)) & we_i & !re_i) | ( (sc_w-1 > afthreshi) & !we_i & re_i) : ((sc_r >= (afthreshi)) & we_i & !re_i) | ( (sc_r-1 > afthreshi) & !we_i & re_i);
|
||||
assign fulli = ( ECC == 1 && FAMILY == 25 ) ? ( sc_w == (FULL_WRITE_DEPTH-1)) & we_i & !re_i : ( sc_r == (FULL_WRITE_DEPTH-1)) & we_i & !re_i ;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if ((FWFT == 1 || PREFETCH == 1) && PIPE == 1) begin
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// threshold values
|
||||
// --------------------------------------------------------------------------
|
||||
assign afthreshi = AF_FLAG_STATIC ? AFULL_VAL : FULL_WRITE_DEPTH;
|
||||
assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL : 2; //SAR#60185
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
almostemptyi <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if((sc_r_fwft >= aethreshi) && we_i & !re_top_p) begin
|
||||
almostemptyi <= 1'b0;
|
||||
end
|
||||
else if((sc_r_fwft-1 <= aethreshi) && sc_r_fwft > 0 && !we_i & re_top_p) begin
|
||||
almostemptyi <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign almostfulli_assert = ((sc_r_fwft >= (afthreshi-1)) & we_i & !(re_top_p & !empty_r_fwft));
|
||||
assign almostfulli_deassert = ( (sc_r_fwft <= afthreshi) & !we_i & (re_top_p & !empty_r_fwft));
|
||||
assign almostfulli = almostfulli_assert ? 1'b1 : (almostfulli_deassert ? 1'b0 : afull_r);
|
||||
|
||||
assign fulli_assert = ( sc_r_fwft >= (FULL_WRITE_DEPTH-1)) & we_i & !(re_top_p & !empty_r_fwft);
|
||||
assign fulli_deassert = ( sc_r_fwft < (FULL_WRITE_DEPTH-1 )) & !we_i & (re_top_p & !empty_r_fwft);
|
||||
assign fulli = fulli_deassert ? 1'b0 : (fulli_assert ? 1'b1 : full_r);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
dvld_r2 <= 1'b0;
|
||||
full_reg <= 1'b0;
|
||||
re_p_d1 <= 'h0;
|
||||
empty_top_fwft_r <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
dvld_r2 <= dvld_r;
|
||||
full_reg <= full_r;
|
||||
re_p_d1 <= re_p;
|
||||
empty_top_fwft_r <= empty_top_fwft;
|
||||
end
|
||||
end
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate the status flags - Empty/Full/Almost Empty/ Almost Full
|
||||
// Generate the data handshaking flags - DVLD/WACK
|
||||
// Generate error count flags - Underflow/Overflow
|
||||
// Generate write and read address signals to the external memory
|
||||
// --------------------------------------------------------------------------
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
// empty_r <= 1'b1;
|
||||
empty_r_fwft<= 1'b1;
|
||||
aempty_r_fwft <= 1'b1;
|
||||
dvld_r <= 1'b0;
|
||||
underflow_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
|
||||
// if (we_i ^ re_i)
|
||||
// empty_r <= emptyi;
|
||||
|
||||
if (we_i ^ ((re_top_p & empty_top_fwft & !empty_top_fwft_r)|| (re_top_p & !empty_top_fwft)))
|
||||
empty_r_fwft <= emptyi_fwft;
|
||||
|
||||
if ((we_i ^ (re_top_p & !empty_r_fwft)))
|
||||
aempty_r_fwft <= almostemptyi;
|
||||
|
||||
|
||||
if (re_i == 1'b1 && READ_DVALID == 1 && (FWFT == 0 && PREFETCH == 0))
|
||||
dvld_r <= 1'b1;
|
||||
else if ((re_top_p & !empty_r_fwft) && READ_DVALID == 1 && (FWFT == 1 || PREFETCH == 1))
|
||||
dvld_r <= 1'b1;
|
||||
else
|
||||
dvld_r <= 1'b0;
|
||||
|
||||
if ( re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1 && (FWFT == 0 && PREFETCH == 0))
|
||||
underflow_r <= 1'b1;
|
||||
else if ( re_top_p == 1'b1 && empty_top_fwft == 1'b1 && UNDERFLOW_EN == 1 && (FWFT == 1 || PREFETCH == 1))
|
||||
underflow_r <= 1'b1;
|
||||
else
|
||||
underflow_r <= 1'b0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (FWFT == 0 && PREFETCH == 0) begin
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
aempty_r <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
if ((we_i ^ re_i)) begin
|
||||
aempty_r <= almostemptyi;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
full_r <= 1'b0;
|
||||
afull_r <= 1'b0;
|
||||
wack_r <= 1'b0;
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
|
||||
if(we_i ^ re_i) begin
|
||||
full_r <= fulli;
|
||||
end
|
||||
|
||||
|
||||
if ((we_i ^ re_i))
|
||||
afull_r <= almostfulli;
|
||||
|
||||
if (we_i == 1'b1 && WRITE_ACK == 1)
|
||||
wack_r <= 1'b1;
|
||||
else
|
||||
wack_r <= 1'b0;
|
||||
|
||||
if ( we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
|
||||
overflow_r <= 1'b1;
|
||||
else
|
||||
overflow_r <= 1'b0;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if ((FWFT == 1 || PREFETCH == 1) && PIPE == 1) begin
|
||||
always @(*)
|
||||
begin
|
||||
aempty_r = almostemptyi;
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if (!aresetn | !sresetn) begin
|
||||
full_r <= 1'b0;
|
||||
afull_r <= 1'b0;
|
||||
wack_r <= 1'b0;
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if ((we_i ^ (re_top_p & !empty_r_fwft)) ) begin
|
||||
if (we_i == 1'b1 && !(re_top_p & !empty_r_fwft)) begin
|
||||
full_r <= fulli;
|
||||
end
|
||||
else if (we_i == 1'b0 && (re_top_p & !empty_r_fwft)) begin
|
||||
full_r <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if ((we_i ^ (re_top_p & !empty_r_fwft)))
|
||||
afull_r <= almostfulli;
|
||||
|
||||
if (we_i == 1'b1 && WRITE_ACK == 1)
|
||||
wack_r <= 1'b1;
|
||||
else
|
||||
wack_r <= 1'b0;
|
||||
|
||||
if ( we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
|
||||
overflow_r <= 1'b1;
|
||||
else
|
||||
overflow_r <= 1'b0;
|
||||
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Generate write and read addresses to the memory
|
||||
// --------------------------------------------------------------------------
|
||||
always @(posedge pos_clk or negedge aresetn )
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memwaddr_r <= 'h0;
|
||||
end
|
||||
else begin
|
||||
if ( we_i == 1'b1) begin
|
||||
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
|
||||
memwaddr_r <= 'h0;
|
||||
end else begin
|
||||
memwaddr_r <= memwaddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge pos_clk or negedge aresetn)
|
||||
begin
|
||||
if ( !aresetn | !sresetn ) begin
|
||||
memraddr_r <= 'h0;
|
||||
end
|
||||
else begin
|
||||
if ( re_i == 1'b1) begin
|
||||
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
|
||||
memraddr_r <= 'h0;
|
||||
end else begin
|
||||
memraddr_r <= memraddr_r + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // corefifo_sync_scntr
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// End - of - Code
|
||||
// --------------------------------------------------------------------------
|
||||
@@ -0,0 +1,684 @@
|
||||
// ****************************************************************************
|
||||
// GENERIC TEST BENCH TO TEST FIFO
|
||||
// ****************************************************************************
|
||||
`timescale 1 ns / 100 ps
|
||||
|
||||
module testbench();
|
||||
|
||||
`include "../../../../coreparameters.v"
|
||||
`include "top_define.v"
|
||||
parameter CLKPERIOD = 15;
|
||||
parameter WCLKPERIOD = 15;
|
||||
parameter RCLKPERIOD = 15;
|
||||
parameter WDEPTH_TB = (CTRL_TYPE == 2 || CTRL_TYPE == 1) ? 1024 : 64;
|
||||
parameter RDEPTH_TB = (CTRL_TYPE == 2 || CTRL_TYPE == 1) ? 1024 : 64;
|
||||
parameter WWIDTH_TB = 18;
|
||||
parameter RWIDTH_TB = 18;
|
||||
parameter CTRL_TYPE_TB = 1;
|
||||
|
||||
`define DLY 1
|
||||
`define MAXDEPTH 18
|
||||
|
||||
function [31:0] logb2;
|
||||
input integer x;
|
||||
integer tmp, res;
|
||||
begin
|
||||
tmp = 1;
|
||||
res = 0;
|
||||
if(x == 1) begin
|
||||
logb2 = 1;
|
||||
end
|
||||
else begin
|
||||
while(tmp < x) begin
|
||||
tmp = tmp * 2;
|
||||
res = res + 1;
|
||||
end
|
||||
logb2 = res;
|
||||
end
|
||||
end
|
||||
endfunction // logb2
|
||||
|
||||
/******************* TESTBENCH VARIABLES FOR DRIVING THE DESIGN INSTANTIATION *****************/
|
||||
|
||||
wire [WWIDTH-1:0] wdata;
|
||||
wire we, re;
|
||||
reg err_cnt;
|
||||
wire wclk, rclk,reset;
|
||||
wire clk;
|
||||
wire [(logb2(RDEPTH)) : 0] rdcount;
|
||||
wire [(logb2(WDEPTH)) : 0] wrcount;
|
||||
wire [RWIDTH-1:0] rdata,rdata1;
|
||||
/******************* External memory ****************************************/
|
||||
|
||||
wire [(logb2(WDEPTH)-1) : 0] ext_waddr;
|
||||
wire [(logb2(RDEPTH)-1) : 0] ext_raddr;
|
||||
wire [WWIDTH-1:0] ext_data;
|
||||
wire [RWIDTH-1:0] ext_rd;
|
||||
wire ext_we, ext_re;
|
||||
|
||||
/******************* Internal memory ****************************************/
|
||||
|
||||
wire [(logb2(WDEPTH)-1) : 0] int_waddr;
|
||||
wire [(logb2(RDEPTH)-1) : 0] int_raddr;
|
||||
wire [WWIDTH-1:0] int_data;
|
||||
wire [RWIDTH-1:0] int_rd;
|
||||
wire int_we, int_re;
|
||||
|
||||
/******************* Internal memory ****************************************/
|
||||
|
||||
wire [(logb2(WDEPTH)-1) : 0] fifo_waddr;
|
||||
wire [(logb2(RDEPTH)-1) : 0] fifo_raddr;
|
||||
|
||||
integer total_error;
|
||||
wire SB_CORRECT;
|
||||
wire DB_DETECT;
|
||||
|
||||
// ****************************************************************************
|
||||
// DIFFERENCE FUNCTION
|
||||
// ****************************************************************************
|
||||
|
||||
function integer diff;
|
||||
input integer a;
|
||||
input integer b;
|
||||
input integer addrwidth;
|
||||
begin
|
||||
if ( a > 0 || b==0 )
|
||||
diff = a - b;
|
||||
else
|
||||
diff = ((2<<addrwidth)) - b;
|
||||
end
|
||||
endfunction
|
||||
initial
|
||||
begin
|
||||
err_cnt = 0;
|
||||
end
|
||||
|
||||
assign int_waddr = (CTRL_TYPE != 1) ? `DUT.fifo_MEMWADDR : 0;
|
||||
assign int_raddr = (CTRL_TYPE != 1) ? `DUT.fifo_MEMRADDR : 0;
|
||||
assign int_we = (CTRL_TYPE != 1) ? `DUT.fifo_MEMWE : 0;
|
||||
assign int_re = (CTRL_TYPE != 1) ? `DUT.fifo_MEMRE : 0;
|
||||
|
||||
assign fifo_waddr = (CTRL_TYPE != 1) ? int_waddr : ext_waddr;
|
||||
assign fifo_raddr = (CTRL_TYPE != 1) ? int_raddr : ext_raddr;
|
||||
|
||||
//`include "fifo_inst.v"
|
||||
clock_driver #(
|
||||
.CLKPERIOD(CLKPERIOD),
|
||||
.WCLKPERIOD(WCLKPERIOD),
|
||||
.RCLKPERIOD(RCLKPERIOD)
|
||||
)
|
||||
|
||||
|
||||
clk_driver (
|
||||
.clk1(clk),
|
||||
.wclk1(wclk),
|
||||
.rclk1(rclk)
|
||||
);
|
||||
|
||||
fifo_driver #( .CTRL_TYPE(CTRL_TYPE),
|
||||
.WRITE_DEPTH(WDEPTH),
|
||||
.WRITE_WIDTH(WWIDTH),
|
||||
.FULL_WRITE_DEPTH(logb2(WDEPTH)),
|
||||
.READ_DEPTH(RDEPTH),
|
||||
.READ_WIDTH(RWIDTH),
|
||||
.FULL_READ_DEPTH(logb2(RDEPTH)),
|
||||
.WE_POLARITY(0),
|
||||
.RE_POLARITY(0),
|
||||
.RESET_POLARITY(0),
|
||||
.RCLK_EDGE(1),
|
||||
.WCLK_EDGE(1),
|
||||
.PIPE(1),
|
||||
.ECC(0),
|
||||
.PREFETCH(0),
|
||||
.ESTOP(1),
|
||||
.FSTOP(1),
|
||||
.SYNC(SYNC)
|
||||
)
|
||||
|
||||
driver (
|
||||
|
||||
.clk (clk),
|
||||
.wclk(wclk),
|
||||
.rclk(rclk),
|
||||
.waddr(fifo_waddr),
|
||||
.raddr(fifo_raddr),
|
||||
.full(full),
|
||||
.empty(empty),
|
||||
.q(rdata),
|
||||
.dvld(dvld),
|
||||
.reset(reset),
|
||||
.we(we),
|
||||
.re(re),
|
||||
.wdata(wdata)
|
||||
|
||||
);
|
||||
assign rdata = (CTRL_TYPE == 1) ? ext_rd : int_rd ;
|
||||
fifo_monitor #(
|
||||
.SYNC(SYNC),
|
||||
.WRITE_WIDTH(WWIDTH),
|
||||
.WRITE_DEPTH(logb2(WDEPTH)),
|
||||
.FULL_WRITE_DEPTH(WDEPTH),
|
||||
.READ_WIDTH(RWIDTH),
|
||||
.READ_DEPTH(logb2(RDEPTH)),
|
||||
.FULL_READ_DEPTH(RDEPTH),
|
||||
.AFVAL(AFVAL),
|
||||
.AEVAL(AEVAL),
|
||||
.AE_STATIC_EN(AE_STATIC_EN),
|
||||
.AF_STATIC_EN(AF_STATIC_EN),
|
||||
.PIPE(1),
|
||||
.ESTOP(1),
|
||||
.FSTOP(1),
|
||||
.OVERFLOW_EN (OVERFLOW_EN ),
|
||||
.UNDERFLOW_EN (UNDERFLOW_EN ),
|
||||
.WRCNT_EN (WRCNT_EN ),
|
||||
.RDCNT_EN (RDCNT_EN ),
|
||||
.RCLK_EDGE(1),
|
||||
.WCLK_EDGE(1),
|
||||
.RESET_POLARITY(0),
|
||||
.READ_DVALID(READ_DVALID),
|
||||
.RE_POLARITY(0),
|
||||
.WE_POLARITY(0)
|
||||
)
|
||||
|
||||
monitor (
|
||||
.clk(clk),
|
||||
.rclk(rclk),
|
||||
.wclk(wclk),
|
||||
.reset(reset),
|
||||
.we(we),
|
||||
.re(re),
|
||||
|
||||
.wcnt(wrcount),
|
||||
.rcnt(rdcount),
|
||||
|
||||
.full(full),
|
||||
.afull(afull),
|
||||
.empty(empty),
|
||||
.aempty(aempty),
|
||||
.underflow(underflow),
|
||||
.overflow(overflow),
|
||||
.wack(wack),
|
||||
.dvld(dvld)
|
||||
);
|
||||
|
||||
|
||||
//`include "design_instance.v"
|
||||
COREFIFO_C0_COREFIFO_C0_0_COREFIFO #(
|
||||
|
||||
.FAMILY(FAMILY),
|
||||
.SYNC(SYNC),
|
||||
//.RCLK_EDGE(1),commented in v3.0
|
||||
//.WCLK_EDGE(1),commented in v3.0
|
||||
.RE_POLARITY(0),
|
||||
//.RESET_POLARITY(0),commented in v3.0
|
||||
.WE_POLARITY(0),
|
||||
.RWIDTH(RWIDTH),
|
||||
.WWIDTH(WWIDTH),
|
||||
.RDEPTH(RDEPTH),
|
||||
.WDEPTH(WDEPTH),
|
||||
.READ_DVALID(READ_DVALID),
|
||||
.WRITE_ACK(WRITE_ACK),
|
||||
.CTRL_TYPE(CTRL_TYPE),
|
||||
.ESTOP(1),
|
||||
.FSTOP(1),
|
||||
.AE_STATIC_EN(AE_STATIC_EN),
|
||||
.AF_STATIC_EN(AF_STATIC_EN),
|
||||
.AEVAL(AEVAL),
|
||||
.AFVAL(AFVAL),
|
||||
.PIPE(1),
|
||||
.ECC(0),
|
||||
.PREFETCH(0),
|
||||
.OVERFLOW_EN (OVERFLOW_EN ),
|
||||
.UNDERFLOW_EN (UNDERFLOW_EN ),
|
||||
.WRCNT_EN (WRCNT_EN ),
|
||||
.NUM_STAGES (NUM_STAGES ),
|
||||
.RDCNT_EN (RDCNT_EN )
|
||||
)
|
||||
|
||||
uut_fifo (
|
||||
|
||||
.CLK(clk )
|
||||
,.WCLOCK(wclk)
|
||||
,.RCLOCK(rclk)
|
||||
|
||||
,.RESET_N(reset)
|
||||
,.WRESET_N(reset)
|
||||
,.RRESET_N(reset)
|
||||
|
||||
,.DATA(wdata)
|
||||
,.Q(rdata1)
|
||||
,.WE(we)
|
||||
,.RE(re)
|
||||
,.FULL(full)
|
||||
,.EMPTY(empty)
|
||||
,.AFULL(afull)
|
||||
,.AEMPTY(aempty)
|
||||
,.OVERFLOW(overflow)
|
||||
,.UNDERFLOW(underflow)
|
||||
,.WACK(wack)
|
||||
,.DVLD(dvld)
|
||||
,.WRCNT(wrcount)
|
||||
,.RDCNT(rdcount)
|
||||
,.MEMWE(ext_we)
|
||||
,.MEMRE(ext_re)
|
||||
,.MEMWADDR(ext_waddr)
|
||||
,.MEMRADDR(ext_raddr)
|
||||
,.MEMWD(ext_data)
|
||||
,.MEMRD(ext_rd)
|
||||
,.SB_CORRECT(SB_CORRECT)
|
||||
,.DB_DETECT(DB_DETECT)
|
||||
|
||||
);
|
||||
|
||||
generate
|
||||
if (CTRL_TYPE == 1) begin
|
||||
|
||||
g4_dp_ext_mem #(
|
||||
.SYNC(SYNC),
|
||||
.RAM_WW(WWIDTH),
|
||||
.RAM_RW(RWIDTH),
|
||||
.RAM_WD(logb2(WDEPTH)),
|
||||
.RAM_RD(logb2(RDEPTH)),
|
||||
.READ_ADDRESS_END(RDEPTH),
|
||||
.WRITE_ADDRESS_END(WDEPTH),
|
||||
.WRITE_CLK(1),
|
||||
.READ_CLK(1),
|
||||
.WRITE_ENABLE(0),
|
||||
.READ_ENABLE(0),
|
||||
.PIPE(1),
|
||||
.RESET_POLARITY(0)
|
||||
)
|
||||
|
||||
ext_mem (
|
||||
.clk(clk),
|
||||
.wclk(wclk),
|
||||
.rclk(rclk),
|
||||
.rst_n(reset),
|
||||
.waddr(ext_waddr),
|
||||
.raddr(ext_raddr),
|
||||
.data(ext_data),
|
||||
.we(ext_we),
|
||||
.re(ext_re),
|
||||
.q(ext_rd)
|
||||
);
|
||||
end
|
||||
else begin
|
||||
|
||||
g4_dp_ext_mem #(
|
||||
.SYNC(SYNC),
|
||||
.RAM_WW(WWIDTH),
|
||||
.RAM_RW(RWIDTH),
|
||||
.RAM_WD(logb2(WDEPTH)),
|
||||
.RAM_RD(logb2(RDEPTH)),
|
||||
.READ_ADDRESS_END(RDEPTH),
|
||||
.WRITE_ADDRESS_END(WDEPTH),
|
||||
.WRITE_CLK(1),
|
||||
.READ_CLK(1),
|
||||
.WRITE_ENABLE(0),
|
||||
.READ_ENABLE(0),
|
||||
.RESET_POLARITY(0),
|
||||
.PIPE(1)
|
||||
)
|
||||
|
||||
int_mem (
|
||||
.clk(clk),
|
||||
.wclk(wclk),
|
||||
.rclk(rclk),
|
||||
.rst_n(reset),
|
||||
.waddr(int_waddr),
|
||||
.raddr(int_raddr),
|
||||
.data(wdata),
|
||||
.we(int_we),
|
||||
.re(int_re),
|
||||
.q(int_rd)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//`include "fifo_POR.v"
|
||||
task fifo_POR;
|
||||
begin
|
||||
|
||||
`RESET_ASSERTED;
|
||||
`FIFO_MONITOR.check_full_flag(1'b0);
|
||||
`FIFO_MONITOR.check_afull_flag(1'b0);
|
||||
`FIFO_MONITOR.check_empty_flag(1'b1);
|
||||
`FIFO_MONITOR.check_aempty_flag(1'b1);
|
||||
repeat(10) @(negedge `WCLK);
|
||||
|
||||
`RESET_NEGATED;
|
||||
$display ("--------------------End-POR-Testcase--------------------------------");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
//`include "fifo_basic_RW_test.v"
|
||||
task fifo_basic_RW_test;
|
||||
|
||||
begin
|
||||
|
||||
$display ("Test Seq:1: WRITE OP in FIFO ");
|
||||
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`FIFO_DRIVER.push(WDEPTH-1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat(10) @(negedge `WCLK);
|
||||
|
||||
|
||||
$display ("Test Seq:1: READ OP in FIFO ");
|
||||
|
||||
repeat(2) @(negedge `RCLK);
|
||||
|
||||
`FIFO_DRIVER.pop(RDEPTH-1);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
repeat(20) @(negedge `RCLK);
|
||||
|
||||
|
||||
repeat(20) @(negedge `RCLK);
|
||||
|
||||
$display (" RESET FIIFO ");
|
||||
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`RESET_NEGATED;
|
||||
|
||||
repeat (10)@(posedge `WCLK);
|
||||
/*$display (" Test Seq:3: All Flags check during WRITING FIFO ");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat (2)@(posedge `WCLK);
|
||||
`FIFO_DRIVER.push(1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat (2)@(posedge `WCLK);
|
||||
|
||||
$display (" Test Seq:4: All Flags check during READ FIFO ");
|
||||
|
||||
repeat(2) @(negedge `RCLK);
|
||||
`FIFO_DRIVER.pop(RDEPTH-1);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
repeat(3) @(posedge `RCLK);
|
||||
|
||||
$display (" RESET FIFO ");
|
||||
|
||||
////////////////////////////////////////////////
|
||||
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`RESET_NEGATED;
|
||||
|
||||
////////////////////////////////////////////////
|
||||
*/
|
||||
$display ("--------------------End-Basic RW-Testcase--------------------------------");
|
||||
end
|
||||
|
||||
endtask
|
||||
|
||||
task async_fifo_basic_RW_test;
|
||||
begin
|
||||
|
||||
$display ("************ RESET FIFO ************* \n\n");
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`RESET_NEGATED;
|
||||
repeat(10) @(negedge `RCLK);
|
||||
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
$display ("Test Seq:2: FULL WRITE AND READ FIFO \n");
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
|
||||
repeat(5) @(negedge `WCLK);
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
$display ("Test Seq:2.1: FULL WRITE IN FIFO \n");
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat(10) @(negedge `WCLK);
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
$display ("Test Seq:2.2:FULL READ from FIFO \n");
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
|
||||
repeat(2) @(negedge `RCLK);
|
||||
|
||||
if (PIPE == 2) begin
|
||||
`FIFO_DRIVER.pop(RDEPTH-2);
|
||||
end
|
||||
else begin
|
||||
`FIFO_DRIVER.pop(RDEPTH-2);
|
||||
end
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
repeat(10) @(negedge `RCLK);
|
||||
|
||||
$display ("***************** RESET FIFO ****************** \n\n");
|
||||
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`RESET_NEGATED;
|
||||
|
||||
/*
|
||||
if(OVERFLOW_EN == 1) begin
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:2: WRITE wdepth-1 in FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-2);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat (10)@(posedge `WCLK);
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:2.1: OVERFLOW DURING WRITE IN FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
repeat (2)@(posedge `WCLK);
|
||||
|
||||
$display ("***************** RESET FIFO ****************** \n\n");
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`RESET_NEGATED;
|
||||
end
|
||||
|
||||
|
||||
|
||||
if(UNDERFLOW_EN == 1) begin
|
||||
|
||||
$display (" Test Seq:3: FULL WRITE IN FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat (10)@(posedge `WCLK);
|
||||
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:3: FULL READ FROM FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
repeat(2) @(negedge `RCLK);
|
||||
`FIFO_DRIVER.pop(RDEPTH-2);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
|
||||
$display ("//////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:3: UNDERFLOW Flag DURING READ FROM FIFO \n");
|
||||
$display ("//////////////////////////////////////////////////// \n");
|
||||
repeat(3) @(posedge `RCLK);
|
||||
if (PIPE !==2 ) begin
|
||||
`FIFO_DRIVER.pop(2);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
repeat(3) @(posedge `RCLK);
|
||||
|
||||
end
|
||||
|
||||
$display ("***************** RESET FIFO ****************** \n\n");
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `WCLK);
|
||||
`RESET_NEGATED;
|
||||
|
||||
end
|
||||
*/
|
||||
end
|
||||
|
||||
endtask
|
||||
|
||||
|
||||
task sync_fifo_basic_RW_test;
|
||||
begin
|
||||
|
||||
$display ("************ RESET FIFO ************* \n\n");
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `CLK);
|
||||
`RESET_NEGATED;
|
||||
repeat(10) @(negedge `CLK);
|
||||
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
$display ("Test Seq:2: FULL WRITE AND READ FIFO \n");
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
|
||||
repeat(5) @(negedge `CLK);
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
$display ("Test Seq:2.1: FULL WRITE IN FIFO \n");
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat(10) @(negedge `CLK);
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
$display ("Test Seq:2.2:FULL READ from FIFO \n");
|
||||
$display ("//////////////////////////////////////////////// \n");
|
||||
|
||||
repeat(2) @(negedge `CLK);
|
||||
|
||||
`FIFO_DRIVER.pop(RDEPTH-2);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
repeat(10) @(negedge `CLK);
|
||||
|
||||
$display ("***************** RESET FIFO ****************** \n\n");
|
||||
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `CLK);
|
||||
`RESET_NEGATED;
|
||||
|
||||
/*
|
||||
if(OVERFLOW_EN == 1) begin
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:2: WRITE wdepth-1 in FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-2);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat (10)@(posedge `CLK);
|
||||
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:2.1: OVERFLOW DURING WRITE IN FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
repeat (2)@(posedge `CLK);
|
||||
|
||||
$display ("***************** RESET FIFO ****************** \n\n");
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `CLK);
|
||||
`RESET_NEGATED;
|
||||
end
|
||||
|
||||
|
||||
|
||||
if(UNDERFLOW_EN == 1) begin
|
||||
|
||||
$display (" Test Seq:3: FULL WRITE IN FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
`FIFO_DRIVER.push(WDEPTH-1);
|
||||
`FIFO_DRIVER.write_deassert;
|
||||
|
||||
repeat (10)@(posedge `CLK);
|
||||
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:3.1: All Flags check during READ FIFO \n");
|
||||
$display ("////////////////////////////////////////////////// \n");
|
||||
|
||||
repeat(2) @(negedge `CLK);
|
||||
`FIFO_DRIVER.pop(RDEPTH-1);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
|
||||
$display ("//////////////////////////////////////////////////// \n");
|
||||
$display (" Test Seq:3.2: UNDERFLOW Flag DURING READ FROM FIFO \n");
|
||||
$display ("//////////////////////////////////////////////////// \n");
|
||||
repeat(3) @(posedge `CLK);
|
||||
`FIFO_DRIVER.pop(3);
|
||||
`FIFO_DRIVER.read_deassert;
|
||||
repeat(3) @(posedge `CLK);
|
||||
*/
|
||||
$display ("***************** RESET FIFO ****************** \n\n");
|
||||
`RESET_ASSERTED;
|
||||
repeat(2) @(negedge `CLK);
|
||||
`RESET_NEGATED;
|
||||
|
||||
end
|
||||
|
||||
|
||||
endtask
|
||||
|
||||
|
||||
//`include "regression.v"
|
||||
|
||||
initial begin
|
||||
|
||||
$display (" Flag status during RESET condition \n");
|
||||
#100
|
||||
//`WCLK_ON;
|
||||
|
||||
fifo_POR;
|
||||
$display ("\n\n");
|
||||
$display ("----------------------------------------------------");
|
||||
$display (" Testcase 1 :FIFO_POR_TEST ");
|
||||
$display ("----------------------------------------------------");
|
||||
|
||||
|
||||
if(SYNC == 0) begin
|
||||
$display ("\n\n");
|
||||
$display ("----------------------------------------------------");
|
||||
$display (" Testcase 2 : ASYNC FIFO_BASIC_RW_TEST ");
|
||||
$display ("----------------------------------------------------\n");
|
||||
async_fifo_basic_RW_test;
|
||||
end
|
||||
else if(SYNC == 1) begin
|
||||
$display ("\n\n");
|
||||
$display ("----------------------------------------------------");
|
||||
$display (" Testcase 2 : SYNC FIFO_BASIC_RW_TEST ");
|
||||
$display ("----------------------------------------------------\n");
|
||||
sync_fifo_basic_RW_test;
|
||||
end
|
||||
|
||||
if (`FIFO_MONITOR.err_cnt >0 || `FIFO_DRIVER.rderr_cnt >0) begin
|
||||
total_error = (`FIFO_MONITOR.err_cnt + `FIFO_DRIVER.rderr_cnt);
|
||||
$display ("----------------------------------------------------");
|
||||
$display (" REGRESSION FAIL!! ");
|
||||
//$display (" TOTAL NUMBER OF ERROR = %d ",`FIFO_MONITOR.total_error);
|
||||
$display ("----------------------------------------------------");
|
||||
$finish;
|
||||
end
|
||||
else
|
||||
$display ("----------------------------------------------------");
|
||||
$display (" REGRESSION PASS!! ");
|
||||
$display (" All Tests PASSED!! ");
|
||||
$display ("----------------------------------------------------\n");
|
||||
repeat(10) @(negedge `WCLK);
|
||||
|
||||
$finish;
|
||||
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@@ -0,0 +1,29 @@
|
||||
|
||||
`define HIGH 1'b1
|
||||
|
||||
`define LOW 1'b0
|
||||
|
||||
`define TB testbench
|
||||
|
||||
`define DUT uut_fifo
|
||||
|
||||
`define FIFO_DRIVER driver
|
||||
|
||||
`define FIFO_MONITOR monitor
|
||||
|
||||
`define CLK_DRIVER clk_driver
|
||||
|
||||
`define WCLK_ON clk_on
|
||||
|
||||
`define WCLK_OFF clk_off
|
||||
|
||||
`define RESET_ASSERTED driver.reset_asserted
|
||||
|
||||
`define RESET_NEGATED driver.reset_negated
|
||||
|
||||
`define CLK clk
|
||||
|
||||
`define WCLK wclk
|
||||
|
||||
`define RCLK rclk
|
||||
|
||||
37
component/work/COREFIFO_C0/COREFIFO_C0_manifest.txt
Normal file
37
component/work/COREFIFO_C0/COREFIFO_C0_manifest.txt
Normal file
@@ -0,0 +1,37 @@
|
||||
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
|
||||
|
||||
Date : Wed Apr 15 18:21:54 2026
|
||||
Project : E:\AbhishekV\rising\ethernet_tpsram_test
|
||||
Component : COREFIFO_C0
|
||||
Family : PolarFire
|
||||
|
||||
|
||||
HDL source files for all Synthesis and Simulation tools:
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync_scntr.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_async.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_nstagessync.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_graytobinconv.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_fwft.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0.v
|
||||
|
||||
Stimulus files for all Simulation tools:
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/wave.do
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/runall.do
|
||||
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/coreparameters.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/test/user/top_define.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/clock_driver.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/fifo_driver.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/fifo_monitor.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/g4_dp_ext_mem.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/test/user/testbench.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WeqR.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WgtR.v
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WltR.v
|
||||
|
||||
Constraint files:
|
||||
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.sdc
|
||||
Reference in New Issue
Block a user