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working FIFO and TPSRAM without packet flter

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abhishekpythons
2026-04-15 23:54:00 +05:30
parent 77c69687d9
commit e4b91625ea
579 changed files with 1295759 additions and 0 deletions
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component/work/COREFIFO_C0/COREFIFO_C0.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0</name><vendor/><library/><version/><fileSets><fileSet fileSetId="OTHER_FILESET"><file fileid="0"><name>./COREFIFO_C0.sdb</name><userFileType>SDB</userFileType></file><file fileid="1"><name>./COREFIFO_C0_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet><fileSet fileSetId="COMPONENT_FILESET"><file fileid="2"><name>./COREFIFO_C0_0/COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf</name><userFileType>CXF</userFileType></file><file fileid="3"><name>../../Actel/DirectCore/COREFIFO/3.1.101/COREFIFO.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="4"><name>./COREFIFO_C0.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>OTHER_FILESET</fileSetRef><fileSetRef>COMPONENT_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="DirectCore" name="COREFIFO" vendor="Actel" version="3.1.101"/><configuration><configurableElement referenceId="AE_STATIC_EN" value="false"/><configurableElement referenceId="AEVAL" value="4"/><configurableElement referenceId="AF_STATIC_EN" value="false"/><configurableElement referenceId="AFVAL" value="1020"/><configurableElement referenceId="CTRL_TYPE" value="2"/><configurableElement referenceId="DIE_SIZE" value="15"/><configurableElement referenceId="ECC" value="0"/><configurableElement referenceId="ESTOP" value="true"/><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="FSTOP" value="true"/><configurableElement referenceId="FWFT" value="true"/><configurableElement referenceId="NUM_STAGES" value="2"/><configurableElement referenceId="OVERFLOW_EN" value="false"/><configurableElement referenceId="PIPE" value="1"/><configurableElement referenceId="PREFETCH" value="false"/><configurableElement referenceId="RAM_OPT" value="0"/><configurableElement referenceId="RDCNT_EN" value="false"/><configurableElement referenceId="RDEPTH" value="1024"/><configurableElement referenceId="RE_POLARITY" value="0"/><configurableElement referenceId="READ_DVALID" value="false"/><configurableElement referenceId="RWIDTH" value="32"/><configurableElement referenceId="SYNC" value="1"/><configurableElement referenceId="SYNC_RESET" value="0"/><configurableElement referenceId="testbench" value="User"/><configurableElement referenceId="UNDERFLOW_EN" value="false"/><configurableElement referenceId="WDEPTH" value="1024"/><configurableElement referenceId="WE_POLARITY" value="0"/><configurableElement referenceId="WRCNT_EN" value="false"/><configurableElement referenceId="WRITE_ACK" value="false"/><configurableElement referenceId="WWIDTH" value="32"/></configuration></vendorExtensions><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RESET_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>WE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>RE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FULL</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>EMPTY</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>DATA</name><direction>in</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>Q</name><direction>out</direction><left>31</left><right>0</right><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>

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component/work/COREFIFO_C0/COREFIFO_C0.sdb Normal file
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component/work/COREFIFO_C0/COREFIFO_C0.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 18:21:52 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of COREFIFO_C0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component COREFIFO_C0
create_and_configure_core -core_vlnv {Actel:DirectCore:COREFIFO:3.1.101} -component_name {COREFIFO_C0} -params {\
"AE_STATIC_EN:false" \
"AEVAL:4" \
"AF_STATIC_EN:false" \
"AFVAL:1020" \
"CTRL_TYPE:2" \
"DIE_SIZE:15" \
"ECC:0" \
"ESTOP:true" \
"FSTOP:true" \
"FWFT:true" \
"NUM_STAGES:2" \
"OVERFLOW_EN:false" \
"PIPE:1" \
"PREFETCH:false" \
"RAM_OPT:0" \
"RDCNT_EN:false" \
"RDEPTH:1024" \
"RE_POLARITY:0" \
"READ_DVALID:false" \
"RWIDTH:32" \
"SYNC:1" \
"SYNC_RESET:0" \
"UNDERFLOW_EN:false" \
"WDEPTH:1024" \
"WE_POLARITY:0" \
"WRCNT_EN:false" \
"WRITE_ACK:false" \
"WWIDTH:32" }
# Exporting Component Description of COREFIFO_C0 to TCL done
*/
// COREFIFO_C0
module COREFIFO_C0(
// Inputs
CLK,
DATA,
RE,
RESET_N,
WE,
// Outputs
EMPTY,
FULL,
Q
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input CLK;
input [31:0] DATA;
input RE;
input RESET_N;
input WE;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output EMPTY;
output FULL;
output [31:0] Q;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire CLK;
wire [31:0] DATA;
wire EMPTY_net_0;
wire FULL_net_0;
wire [31:0] Q_net_0;
wire RE;
wire RESET_N;
wire WE;
wire FULL_net_1;
wire EMPTY_net_1;
wire [31:0] Q_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [31:0] MEMRD_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign MEMRD_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign FULL_net_1 = FULL_net_0;
assign FULL = FULL_net_1;
assign EMPTY_net_1 = EMPTY_net_0;
assign EMPTY = EMPTY_net_1;
assign Q_net_1 = Q_net_0;
assign Q[31:0] = Q_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------COREFIFO_C0_COREFIFO_C0_0_COREFIFO - Actel:DirectCore:COREFIFO:3.1.101
COREFIFO_C0_COREFIFO_C0_0_COREFIFO #(
.AE_STATIC_EN ( 0 ),
.AEVAL ( 4 ),
.AF_STATIC_EN ( 0 ),
.AFVAL ( 1020 ),
.CTRL_TYPE ( 2 ),
.DIE_SIZE ( 15 ),
.ECC ( 0 ),
.ESTOP ( 1 ),
.FAMILY ( 26 ),
.FSTOP ( 1 ),
.FWFT ( 1 ),
.NUM_STAGES ( 2 ),
.OVERFLOW_EN ( 0 ),
.PIPE ( 1 ),
.PREFETCH ( 0 ),
.RAM_OPT ( 0 ),
.RDCNT_EN ( 0 ),
.RDEPTH ( 1024 ),
.RE_POLARITY ( 0 ),
.READ_DVALID ( 0 ),
.RWIDTH ( 32 ),
.SYNC ( 1 ),
.SYNC_RESET ( 0 ),
.UNDERFLOW_EN ( 0 ),
.WDEPTH ( 1024 ),
.WE_POLARITY ( 0 ),
.WRCNT_EN ( 0 ),
.WRITE_ACK ( 0 ),
.WWIDTH ( 32 ) )
COREFIFO_C0_0(
// Inputs
.CLK ( CLK ),
.WCLOCK ( GND_net ), // tied to 1'b0 from definition
.RCLOCK ( GND_net ), // tied to 1'b0 from definition
.RESET_N ( RESET_N ),
.WRESET_N ( GND_net ), // tied to 1'b0 from definition
.RRESET_N ( GND_net ), // tied to 1'b0 from definition
.WE ( WE ),
.RE ( RE ),
.DATA ( DATA ),
.MEMRD ( MEMRD_const_net_0 ), // tied to 32'h00000000 from definition
// Outputs
.FULL ( FULL_net_0 ),
.EMPTY ( EMPTY_net_0 ),
.AFULL ( ),
.AEMPTY ( ),
.OVERFLOW ( ),
.UNDERFLOW ( ),
.WACK ( ),
.DVLD ( ),
.MEMWE ( ),
.MEMRE ( ),
.SB_CORRECT ( ),
.DB_DETECT ( ),
.Q ( Q_net_0 ),
.WRCNT ( ),
.RDCNT ( ),
.MEMWADDR ( ),
.MEMRADDR ( ),
.MEMWD ( )
);
endmodule

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO_C0_COREFIFO_C0_0_COREFIFO</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\core\COREFIFO.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="3"><name>rtl\vlog\core\corefifo_sync.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="4"><name>rtl\vlog\core\corefifo_sync_scntr.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="5"><name>rtl\vlog\core\corefifo_async.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="6"><name>rtl\vlog\core\corefifo_nstagessync.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="7"><name>rtl\vlog\core\corefifo_graytobinconv.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="8"><name>rtl\vlog\core\corefifo_fwft.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="9"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="10"><name>rtl\vlog\test\user\top_define.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="11"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v</name><fileType>verilogSource</fileType></file><file fileid="12"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v</name><fileType>verilogSource</fileType></file><file fileid="13"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v</name><fileType>verilogSource</fileType></file><file fileid="14"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v</name><fileType>verilogSource</fileType></file><file fileid="15"><name>rtl\vlog\test\user\testbench.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime> -all</SimulationTime><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="16"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v</name><fileType>verilogSource</fileType></file><file fileid="17"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v</name><fileType>verilogSource</fileType></file><file fileid="18"><name>..\..\..\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="19"><name>mti\scripts\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="20"><name>mti\scripts\runall.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view></views></hwModel></Component>

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component/work/COREFIFO_C0/COREFIFO_C0_0/COREFIFO_C0_COREFIFO_C0_0_COREFIFO.sdc Normal file
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set_component COREFIFO_C0_COREFIFO_C0_0_COREFIFO
set_false_path -to [ get_cells { genblk*.U_corefifo_async/*/shift_reg* } ]

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component/work/COREFIFO_C0/COREFIFO_C0_0/coreparameters.v Normal file
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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Wed Apr 15 18:21:52 2026
// Parameters for COREFIFO
//--------------------------------------------------------------------
parameter AE_STATIC_EN = 0;
parameter AEVAL = 4;
parameter AF_STATIC_EN = 0;
parameter AFVAL = 1020;
parameter CTRL_TYPE = 2;
parameter DIE_SIZE = 15;
parameter ECC = 0;
parameter ESTOP = 1;
parameter FAMILY = 26;
parameter FSTOP = 1;
parameter FWFT = 1;
parameter NUM_STAGES = 2;
parameter OVERFLOW_EN = 0;
parameter PIPE = 1;
parameter PREFETCH = 0;
parameter RAM_OPT = 0;
parameter RDCNT_EN = 0;
parameter RDEPTH = 1024;
parameter RE_POLARITY = 0;
parameter READ_DVALID = 0;
parameter RWIDTH = 32;
parameter SYNC = 1;
parameter SYNC_RESET = 0;
parameter testbench = "User";
parameter UNDERFLOW_EN = 0;
parameter WDEPTH = 1024;
parameter WE_POLARITY = 0;
parameter WRCNT_EN = 0;
parameter WRITE_ACK = 0;
parameter WWIDTH = 32;

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run 700000ns
radix h

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component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/wave.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/uut_fifo/RESET_N
add wave -noupdate /testbench/uut_fifo/WCLOCK
add wave -noupdate /testbench/uut_fifo/WE
add wave -noupdate /testbench/uut_fifo/DATA
add wave -noupdate /testbench/uut_fifo/FULL
add wave -noupdate /testbench/uut_fifo/AFULL
add wave -noupdate /testbench/uut_fifo/WACK
add wave -noupdate /testbench/uut_fifo/OVERFLOW
add wave -noupdate /testbench/uut_fifo/RCLOCK
add wave -noupdate /testbench/uut_fifo/RE
add wave -noupdate /testbench/uut_fifo/Q
add wave -noupdate /testbench/uut_fifo/DVLD
add wave -noupdate /testbench/uut_fifo/EMPTY
add wave -noupdate /testbench/uut_fifo/AEMPTY
add wave -noupdate /testbench/uut_fifo/RDCNT
add wave -noupdate /testbench/uut_fifo/UNDERFLOW
add wave -noupdate /testbench/uut_fifo/MEMWE
add wave -noupdate /testbench/uut_fifo/MEMWD
add wave -noupdate /testbench/uut_fifo/MEMWADDR
add wave -noupdate /testbench/uut_fifo/MEMRE
add wave -noupdate /testbench/uut_fifo/MEMRD
add wave -noupdate /testbench/uut_fifo/MEMRADDR
add wave -noupdate /testbench/reset
add wave -noupdate /testbench/wclk
add wave -noupdate /testbench/we
add wave -noupdate /testbench/wdata
add wave -noupdate /testbench/full
add wave -noupdate /testbench/afull
add wave -noupdate /testbench/overflow
add wave -noupdate /testbench/wrcount
add wave -noupdate /testbench/rclk
add wave -noupdate /testbench/re
add wave -noupdate /testbench/rdata
add wave -noupdate /testbench/empty
add wave -noupdate /testbench/aempty
add wave -noupdate /testbench/dvld
add wave -noupdate /testbench/rdcount
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/err_cnt
add wave -noupdate /testbench/ext_waddr
add wave -noupdate /testbench/ext_raddr
add wave -noupdate /testbench/ext_data
add wave -noupdate /testbench/ext_rd
add wave -noupdate /testbench/ext_we
add wave -noupdate /testbench/ext_re
add wave -noupdate /testbench/int_waddr
add wave -noupdate /testbench/int_raddr
add wave -noupdate /testbench/int_data
add wave -noupdate /testbench/int_rd
add wave -noupdate /testbench/int_we
add wave -noupdate /testbench/int_re
add wave -noupdate /testbench/monitor/wack_r
add wave -noupdate /testbench/monitor/tb_wcnt
add wave -noupdate /testbench/monitor/tb_wack
add wave -noupdate /testbench/monitor/tb_underflow
add wave -noupdate /testbench/monitor/tb_rcnt
add wave -noupdate /testbench/monitor/tb_overflow
add wave -noupdate /testbench/monitor/tb_empty
add wave -noupdate /testbench/monitor/tb_dvld
add wave -noupdate /testbench/monitor/tb_full
add wave -noupdate /testbench/monitor/tb_afull
add wave -noupdate /testbench/monitor/tb_aempty
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {32473187607 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 524
configure wave -valuecolwidth 60
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits fs
update
WaveRestoreZoom {30291784830 fs} {35134349071 fs}

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component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v Normal file
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component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.gen Normal file
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DESIGN:COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
FAM:PolarFire
DEVICE:300
OUTFORMAT:Verilog
LPMTYPE:LPM_RAM
CLKS:1
PTYPE:1
BATCH:T
MGNTIMER:F
MGNCMPL:F
GEN_BEHV_MODULE:F
WWIDTH:32
RWIDTH:32
WDEPTH:1024
RDEPTH:1024
WE_POLARITY:1
RE_POLARITY:1
RCLK_EDGE:RISE
WCLK_EDGE:RISE
CLK_EDGE:RISE
INIT_RAM:F
LPM_HINT:0
ECC:0
PMODE2:0
BUSY_FLAG:0
BYTEENABLES:0
DATA_IN_PN:W_DATA
DATA_OUT_PN:R_DATA
WADDRESS_PN:W_ADDR
RADDRESS_PN:R_ADDR
WE_PN:W_EN
RE_PN:R_EN
WCLOCK_PN:W_CLK
RCLOCK_PN:R_CLK
CLOCK_PN:CLK
SII_LOCK:0
SD_EXPORT_HIDDEN_PORTS:false
CASCADE:0
A_DOUT_EN_POLARITY:2
A_DOUT_EN_PN:R_DATA_EN
A_DOUT_SRST_POLARITY:2
A_DOUT_SRST_PN:R_DATA_SRST_N
RESET_POLARITY:2
RESET_PN:R_DATA_ARST_N

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component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.log Normal file
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****************
Macro Parameters
****************
Name : COREFIFO_C0_COREFIFO_C0_0_LSRAM_top
Family : PolarFire
Output Format : VERILOG
Type : RAM
Write Block Enable Polarity : Active High
Read Block Enable Polarity : Active High
A_DOUT Enable Polarity : None
B_DOUT Enable Polarity : None
A_DOUT Sync-reset Polarity : None
B_DOUT Sync-reset Polarity : None
A_DOUT Async-reset Polarity : None
B_DOUT Async-reset Polarity : None
Reset Polarity : None
Read Clock Edge : Rising
Write Clock Edge : Rising
A_REN Polarity : None
B_REN Polarity : None
Write Depth : 1024
Write Width : 32
Read Depth : 1024
Read Width : 32
Portname DataIn : W_DATA
Portname DataOut : R_DATA
Portname WClock : W_CLK
Portname RClock : R_CLK
Portname WAddress : W_ADDR
Portname RAddress : R_ADDR
Portname Single Clock : CLK
Portname Single Async-reset : R_DATA_ARST_N
Portname DataAIn :
Portname DataBIn :
Portname DataAOut :
Portname DataBOut :
Portname AddressA :
Portname AddressB :
Portname CLKA :
Portname CLKB :
Portname RWA :
Portname RWB :
Portname BLKA :
Portname BLKB :
Portname A_DOUT_EN : R_DATA_EN
Portname B_DOUT_EN :
Portname A_DOUT_SRST_N : R_DATA_SRST_N
Portname B_DOUT_SRST_N :
Portname A_DOUT_ARST_N :
Portname B_DOUT_ARST_N :
Portname Write Enable : W_EN
Portname Read Enable : R_EN
Portname A_WBYTE_EN :
Portname B_WBYTE_EN :
Portname A_REN :
Portname B_REN :
LPM_HINT : 0
Device : 300
RAM Type : Two Port
Optimized for : Speed
Initialize RAM : False
Clocks : Single Read/Write Clock
Byte Enables : No
Read Pipeline A : No
Read Pipeline B : No
Write Mode A : Hold Data
Write Mode B : Hold Data
ECC Type : Disabled
Lock access : Off
ACCESS_BUSY : Disabled
Cascade Configuration:
Write Port configuration : 1024x20
Read Port configuration : 1024x20
Number of blocks depth wise: 1
Number of blocks width wise: 2
Wrote Verilog netlist to E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v.

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component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module COREFIFO_C0_COREFIFO_C0_0_LSRAM_top(
W_DATA,
R_DATA,
W_ADDR,
R_ADDR,
W_EN,
R_EN,
CLK
);
input [31:0] W_DATA;
output [31:0] R_DATA;
input [9:0] W_ADDR;
input [9:0] R_ADDR;
input W_EN;
input R_EN;
input CLK;
wire \ACCESS_BUSY[0][0] , \ACCESS_BUSY[0][1] , VCC, GND, ADLIB_VCC;
wire GND_power_net1;
wire VCC_power_net1;
assign GND = GND_power_net1;
assign VCC = VCC_power_net1;
assign ADLIB_VCC = VCC_power_net1;
RAM1K20 #( .RAMINDEX("core%1024-1024%32-32%SPEED%0%1%TWO-PORT%ECC_EN-0")
) COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C1 (.A_DOUT({nc0,
nc1, R_DATA[31], R_DATA[30], R_DATA[29], R_DATA[28],
R_DATA[27], R_DATA[26], R_DATA[25], R_DATA[24], nc2, nc3,
R_DATA[23], R_DATA[22], R_DATA[21], R_DATA[20], R_DATA[19],
R_DATA[18], R_DATA[17], R_DATA[16]}), .B_DOUT({nc4, nc5, nc6,
nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17,
nc18, nc19, nc20, nc21, nc22, nc23}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][1] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(R_EN),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[31],
W_DATA[30], W_DATA[29], W_DATA[28], W_DATA[27], W_DATA[26],
W_DATA[25], W_DATA[24], GND, GND, W_DATA[23], W_DATA[22],
W_DATA[21], W_DATA[20], W_DATA[19], W_DATA[18], W_DATA[17],
W_DATA[16]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
RAM1K20 #( .RAMINDEX("core%1024-1024%32-32%SPEED%0%0%TWO-PORT%ECC_EN-0")
) COREFIFO_C0_COREFIFO_C0_0_LSRAM_top_R0C0 (.A_DOUT({nc24,
nc25, R_DATA[15], R_DATA[14], R_DATA[13], R_DATA[12],
R_DATA[11], R_DATA[10], R_DATA[9], R_DATA[8], nc26, nc27,
R_DATA[7], R_DATA[6], R_DATA[5], R_DATA[4], R_DATA[3],
R_DATA[2], R_DATA[1], R_DATA[0]}), .B_DOUT({nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
nc41, nc42, nc43, nc44, nc45, nc46, nc47}), .DB_DETECT(),
.SB_CORRECT(), .ACCESS_BUSY(\ACCESS_BUSY[0][0] ), .A_ADDR({
R_ADDR[9], R_ADDR[8], R_ADDR[7], R_ADDR[6], R_ADDR[5],
R_ADDR[4], R_ADDR[3], R_ADDR[2], R_ADDR[1], R_ADDR[0], GND,
GND, GND, GND}), .A_BLK_EN({VCC, VCC, VCC}), .A_CLK(CLK),
.A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND,
GND, GND, GND, GND, GND, GND, GND, GND, GND}), .A_REN(R_EN),
.A_WEN({GND, GND}), .A_DOUT_EN(VCC), .A_DOUT_ARST_N(VCC),
.A_DOUT_SRST_N(VCC), .B_ADDR({W_ADDR[9], W_ADDR[8], W_ADDR[7],
W_ADDR[6], W_ADDR[5], W_ADDR[4], W_ADDR[3], W_ADDR[2],
W_ADDR[1], W_ADDR[0], GND, GND, GND, GND}), .B_BLK_EN({W_EN,
VCC, VCC}), .B_CLK(CLK), .B_DIN({GND, GND, W_DATA[15],
W_DATA[14], W_DATA[13], W_DATA[12], W_DATA[11], W_DATA[10],
W_DATA[9], W_DATA[8], GND, GND, W_DATA[7], W_DATA[6],
W_DATA[5], W_DATA[4], W_DATA[3], W_DATA[2], W_DATA[1],
W_DATA[0]}), .B_REN(VCC), .B_WEN({VCC, VCC}), .B_DOUT_EN(VCC),
.B_DOUT_ARST_N(GND), .B_DOUT_SRST_N(VCC), .ECC_EN(GND),
.BUSY_FB(GND), .A_WIDTH({VCC, GND, GND}), .A_WMODE({GND, GND}),
.A_BYPASS(VCC), .B_WIDTH({VCC, GND, GND}), .B_WMODE({GND, GND})
, .B_BYPASS(VCC), .ECC_BYPASS(GND));
GND GND_power_inst1 (.Y(GND_power_net1));
VCC VCC_power_inst1 (.Y(VCC_power_net1));
endmodule

64
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v Normal file
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// This is automatically generated file
`timescale 1 ns/100 ps
module COREFIFO_C0_COREFIFO_C0_0_ram_wrapper(
WDATA,
WADDR,
WEN,
REN,
RDATA,
RADDR,
RESET_N,
CLOCK,
WCLOCK,
A_SB_CORRECT,
B_SB_CORRECT,
A_DB_DETECT,
B_DB_DETECT,
RCLOCK
);
// --------------------------------------------------------------------------
// PARAMETER Declaration
// --------------------------------------------------------------------------
parameter RWIDTH = 32; // Read port Data Width
parameter WWIDTH = 32; // Write port Data Width
parameter RDEPTH = 128; // Read port Data Depth
parameter WDEPTH = 128; // Write port Data Depth
parameter SYNC = 0; // Synchronous or Asynchronous operation | 1 - Single Clock, 0 - Dual clock
parameter PIPE = 1; // Pipeline read data out
parameter CTRL_TYPE = 1; // Controller only options | 1 - Controller Only, 2 - RAM1Kx18, 3 - RAM64x18
parameter SYNC_RESET = 0; // Synchronous or Asynchronous RESET | 1 - Synchronous reset, 0 - Asynchronous reset
parameter RAM_OPT = 0; // | 0 -High Speed , 1 - Low Power
// --------------------------------------------------------------------------
// I/O Declaration
// --------------------------------------------------------------------------
input [WWIDTH - 1 : 0] WDATA;
input [(WDEPTH - 1) : 0] WADDR;
input WEN;
input REN;
output [RWIDTH - 1 : 0] RDATA;
input [(RDEPTH - 1) : 0] RADDR;
input RESET_N;
input WCLOCK;
input RCLOCK;
output A_SB_CORRECT;
output B_SB_CORRECT;
output A_DB_DETECT;
output B_DB_DETECT;
input CLOCK;
COREFIFO_C0_COREFIFO_C0_0_LSRAM_top L3_syncnonpipe (
.W_DATA (WDATA ),
.W_ADDR (WADDR ),
.W_EN (WEN ),
.R_DATA (RDATA ),
.R_ADDR (RADDR ),
.R_EN (REN ),
.CLK (CLOCK )
);
endmodule

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// ********************************************************************/
// Microchip Corporation Proprietary and Confidential
// Copyright 2023 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// IP Core: COREFIFO
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
//
// *********************************************************************/
`timescale 1ns / 100ps
module COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft (
wr_clk,
rd_clk,
clk,
//reset_rclk_top,
//reset_wclk_top,
aresetn_wclk,
aresetn_rclk,
sresetn_wclk,
sresetn_rclk,
empty,
aempty,
rd_en,
fifo_rd_en,
fifo_empty,
fifo_aempty,
fifo_dout,
wr_en,
din,
fwft_dvld,
reg_valid,
dout,
fifo_MEMRADDR,
fwft_MEMRADDR
);
// --------------------------------------------------------------------------
// PARAMETER Declaration
// --------------------------------------------------------------------------
parameter RDEPTH = 10;
parameter WWIDTH = 10;
parameter RWIDTH = 10;
parameter WCLK_HIGH = 1;
parameter RCLK_HIGH = 1;
parameter RESET_LOW = 1;
parameter WRITE_LOW = 1;
parameter READ_LOW = 1;
parameter PREFETCH = 0;
parameter FWFT = 0;
parameter SYNC = 1;
parameter SYNC_RESET = 0;//uncommented in v3.0
localparam RDEPTH_CAL = (RDEPTH == 0) ? RDEPTH : (RDEPTH-1);
// --------------------------------------------------------------------------
// I/O Declaration
// --------------------------------------------------------------------------
//--------
// Inputs
//--------
// Clocks and Reset
input wr_clk;
input rd_clk;
input clk;
//input reset_rclk_top;
//input reset_wclk_top;
input wr_en;
input rd_en;
output fifo_rd_en;
input [RWIDTH-1 : 0] fifo_dout;
input fifo_empty;
input fifo_aempty;
input [WWIDTH - 1 : 0] din;
input [RDEPTH_CAL : 0] fifo_MEMRADDR;
input aresetn_rclk; //added in v3.0
input aresetn_wclk;//added in v3.0
input sresetn_rclk;//added in v3.0
input sresetn_wclk;//added in v3.0
//---------
// Outputs
//---------
output empty;
output aempty;
output [RWIDTH-1 : 0] dout;
output fwft_dvld;
output reg_valid;
output [RDEPTH_CAL : 0] fwft_MEMRADDR;
// --------------------------------------------------------------------------
// Internal signals
// --------------------------------------------------------------------------
reg fifo_valid, dout_valid, middle_valid ;
reg [RWIDTH - 1 : 0] middle_dout;
reg [RWIDTH - 1 : 0] dout;
//wire [RWIDTH - 1 : 0] dout; //added by mahesh
wire [RWIDTH - 1 : 0] fifo_dout;
wire fifo_rd_en, fifo_empty;
wire update_dout, update_middle;
wire [RDEPTH_CAL : 0] fwft_MEMRADDR;
//reg [RDEPTH_CAL : 0] fwft_MEMRADDR;
reg fifo_empty_r;
wire fwft_dvld;
reg wr_p_r;
reg reg_valid;
wire we_p;
reg we_p_r;
wire re_p;
reg re_p_d;
wire aresetn;
//wire sresetn;
wire pos_rclk;
wire pos_wclk;
reg empty_r;
reg reg_valid_r;
wire empty1;
reg empty;
reg update_dout_r;
wire fifo_empty_pulse;
reg fifo_empty_pulse_d;
wire fifo_init_pulse;
wire reset_wclk;
wire reset_rclk;
// --------------------------------------------------------------------------
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
// || ||
// || Start - of - Code ||
// || ||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
// --------------------------------------------------------------------------
// --------------------------------------------------------------------------
// Clocks, resets and enables
// --------------------------------------------------------------------------
generate
if(SYNC == 1) begin
assign pos_rclk = RCLK_HIGH ? clk : ~clk;
assign pos_wclk = WCLK_HIGH ? clk : ~clk;
end
endgenerate
generate
if(SYNC == 0) begin
assign pos_rclk = RCLK_HIGH ? rd_clk : ~rd_clk;
assign pos_wclk = WCLK_HIGH ? wr_clk : ~wr_clk;
end
endgenerate
assign we_p = WRITE_LOW ? (~wr_en) : (wr_en);
assign re_p = READ_LOW ? (~rd_en) : (rd_en);
// --------------------------------------------------------------------------
// Generate addresses to the memory
// --------------------------------------------------------------------------
assign fwft_MEMRADDR = fifo_MEMRADDR ;
assign update_middle = fifo_valid & (middle_valid == update_dout);
assign update_dout = (fifo_valid || middle_valid) && (re_p || !dout_valid);
// --------------------------------------------------------------------------
// Generates the read enable to be given to the FIFO controller
// fifo_rd_en: It is different from the top-level read enable
// --------------------------------------------------------------------------
assign fifo_rd_en = !(fifo_empty) && !(middle_valid && dout_valid && fifo_valid);
//assign fifo_rd_en = fifo_init_pulse | re_p;
// --------------------------------------------------------------------------
// Generate empty/almost empty signal
// --------------------------------------------------------------------------
//assign empty = !dout_valid | (!fifo_valid && !middle_valid && dout_valid & !update_dout & re_p);
//assign empty = fifo_empty_r; //!dout_valid ; // change by mahesh
// assign empty = !dout_valid ; // SAR no
assign aempty = fifo_aempty | empty;
always @(posedge pos_rclk or negedge aresetn_rclk) begin
if(!aresetn_rclk | !sresetn_rclk)
empty <= 1'b1;
else if(update_dout)
empty <= 1'b0;
else if(re_p)
empty <= 1'b1;
end
//assign reset_rclk = reset_rclk_top;commented in v3.0
//assign reset_wclk = reset_wclk_top;commented in v3.0
// --------------------------------------------------------------------------
// Register empty signal
// --------------------------------------------------------------------------
always @(posedge pos_rclk or negedge aresetn_rclk) begin
if(!aresetn_rclk | !sresetn_rclk) begin
fifo_empty_r <= 1'b0;
//fifo_empty_r <= fifo_empty;
update_dout_r <= 'h0;
end
else begin
fifo_empty_r <= fifo_empty;
update_dout_r <= update_dout;
end
end
assign fifo_empty_pulse = fifo_empty_r & !fifo_empty;
assign fifo_init_pulse = !fifo_empty_pulse_d & fifo_empty_pulse;
//-----------------------------------------------------------------
// Register re_p signal
//-----------------------------------------------------------------
always @(posedge pos_rclk or negedge aresetn_rclk) begin
if(!aresetn_rclk | !sresetn_rclk) begin
re_p_d <= 1'b0;
end else begin
re_p_d <= re_p;
end
end
//---------------------------------------------------------------------------
// delayed empty pulse for the genration of fifo read enable
//--------------------------------------------------------------------------
always @(posedge pos_rclk or negedge aresetn_rclk) begin
if(!aresetn_rclk | !sresetn_rclk) begin
fifo_empty_pulse_d <= 1'b0;
end
else begin
if (fifo_empty_pulse == 1'b1) begin
fifo_empty_pulse_d <= 1'b1;
end else if (fifo_empty == 1'b0 && fifo_empty_r == 1'b0) begin
fifo_empty_pulse_d <= 1'b0;
end else begin
fifo_empty_pulse_d <= fifo_empty_pulse_d;
end
end
end
// --------------------------------------------------------------------------
// FWFT logic
// --------------------------------------------------------------------------
//assign dout = fifo_dout;
//always @(posedge pos_rclk or negedge aresetn) begin
// if((!aresetn) || (!sresetn)) begin
// dout <= 'h0;
// end else begin
// dout <= fifo_dout;
// end
//end
always @(posedge pos_rclk or negedge aresetn_rclk) begin
if(!aresetn_rclk | !sresetn_rclk) begin
fifo_valid <= 1'b0;
middle_valid <= 1'b0;
dout_valid <= 1'b0;
dout <= 'h0;
middle_dout <= 'h0;
end
else begin
if(update_middle) begin
middle_dout <= fifo_dout;
end
if(update_dout) begin
dout <= middle_valid ? middle_dout : fifo_dout;
end
if(fifo_rd_en) begin
fifo_valid <= 1'b1;
end
else if(update_middle || update_dout) begin
fifo_valid <= 1'b0;
end
if(update_middle) begin
middle_valid <= 1'b1;
end
else if(update_dout) begin
middle_valid <= 1'b0;
end
if(update_dout) begin
dout_valid <= 1'b1;
end
else if(re_p) begin
dout_valid <= 1'b0;
end
end
end
// --------------------------------------------------------------------------
// Generate the data valid signal
// --------------------------------------------------------------------------
generate
if(FWFT == 1) begin
// assign fwft_dvld = reg_valid | (re_p & !empty_r); SAR
assign fwft_dvld = dout_valid;
//assign fwft_dvld = (re_p & !empty_r);
//assign fwft_dvld = reg_valid | re_p;
end
endgenerate
generate
if(PREFETCH == 1) begin
// assign fwft_dvld = (re_p) & !empty_r; SAR no
assign fwft_dvld = (re_p) & dout_valid; // SAR no
end
endgenerate
// --------------------------------------------------------------------------
// Generate the qualifying signal to sample the read data. It is also used
// to generate the read data valid signal
// --------------------------------------------------------------------------
always @(*) begin
if(re_p == 1'b1) begin
reg_valid = 1'b0;
end
else if(empty == 1'b0 && empty_r == 1'b1) begin
reg_valid = 1'b1;
end
else begin
reg_valid = reg_valid_r;
end
end
always @(posedge pos_rclk or negedge aresetn_rclk) begin
if(!aresetn_rclk | !sresetn_rclk) begin
empty_r <= 1'b0;
reg_valid_r <= 1'b0;
end
else begin
empty_r <= empty;
reg_valid_r <= reg_valid;
end
end
always @(posedge pos_wclk or negedge aresetn_wclk) begin
if(!aresetn_wclk | !sresetn_wclk) begin
we_p_r <= 1'b0;
end
else begin
we_p_r <= we_p;
end
end
endmodule // corefifo_fwft
// --------------------------------------------------------------------------
// End - of - Code
// --------------------------------------------------------------------------

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// ********************************************************************/
// Microchip Corporation Proprietary and Confidential
// Copyright 2023 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// IP Core: COREFIFO
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
//
// *********************************************************************/
`timescale 1ns / 100ps
module COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv(
gray_in,
bin_out
);
// --------------------------------------------------------------------------
// Parameter Declaration
// --------------------------------------------------------------------------
parameter ADDRWIDTH = 3;
// parameter SYNC_RESET = 0;
// --------------------------------------------------------------------------
// I/O Declaration
// --------------------------------------------------------------------------
//--------
// Inputs
//--------
input [ADDRWIDTH:0] gray_in;
//---------
// Outputs
//---------
output [ADDRWIDTH:0] bin_out;
// --------------------------------------------------------------------------
// Internal signals
// --------------------------------------------------------------------------
reg [ADDRWIDTH:0] bin_out;
integer i;
// --------------------------------------------------------------------------
// Start - of - Code
// --------------------------------------------------------------------------
// --------------------------------------------------------------------------
// Logic to Convert the Gray code to Binary
// --------------------------------------------------------------------------
always @(*) begin
bin_out[ADDRWIDTH] = gray_in[ADDRWIDTH];
for(i=ADDRWIDTH;i>0;i = i-1) begin
bin_out[i-1] = (bin_out[i] ^ gray_in[i-1]);
end
end
endmodule // corefifo_grayToBinConv
// --------------------------------------------------------------------------
// End - of - Code
// --------------------------------------------------------------------------

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component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_nstagessync.v Normal file
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// ********************************************************************/
// Microchip Corporation Proprietary and Confidential
// Copyright 2023 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// IP Core: COREFIFO
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
//
// *********************************************************************/
`timescale 1ns / 100ps
module COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync(
clk,
//rstn,
arstn,//added in v3.0
srstn,//added in v3.0
inp,
sync_out
);
// --------------------------------------------------------------------------
// PARAMETER Declaration
// --------------------------------------------------------------------------
parameter NUM_STAGES = 2;
parameter ADDRWIDTH = 3;
input clk;
//input rstn;commented in v3.0
input arstn;//added in v3.0
input srstn;//added in v3.0
input [ADDRWIDTH : 0 ] inp;
output [ADDRWIDTH : 0 ] sync_out;
//reg [WIDTH -1:0] signal_out;
reg [ADDRWIDTH : 0 ] shift_reg ;
reg [ADDRWIDTH : 0 ] shift_mem_reg [NUM_STAGES-1:0] ;
always @ ( posedge clk or negedge arstn)
begin
if (!arstn | !srstn)
shift_reg <= 'h0;
else
shift_reg <= inp;
end
always @ (*)
shift_mem_reg[0] = shift_reg;
integer i;
always @ ( posedge clk or negedge arstn)
begin
if (!arstn | !srstn)
begin
for(i = NUM_STAGES-1; i >0 ; i = i-1)
begin
shift_mem_reg[i] <= 'h0;
end
end
/// signal_out <= 'h0;
else
begin
for(i = NUM_STAGES-1; i > 0; i = i-1)
shift_mem_reg[i] <= shift_mem_reg[i-1];
//end
//signal_out <= shift_reg[NUM_STAGES-1];
end
end
assign sync_out = shift_mem_reg[NUM_STAGES-1];
endmodule // corefifo_doubleSync
// --------------------------------------------------------------------------
// End - of - Code
// --------------------------------------------------------------------------

860
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync.v Normal file
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// ********************************************************************/
// Microchip Corporation Proprietary and Confidential
// Copyright 2023 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// IP Core: COREFIFO
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
//
// *********************************************************************/
`timescale 1ns/100ps
module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync (
clk,
//reset,
aresetn,
sresetn,
we,
re,
full,
afull,
wrcnt,
empty,
aempty,
rdcnt,
underflow,
overflow,
dvld,
wack,
memwaddr,
memwe,
memraddr,
memre
);
// --------------------------------------------------------------------------
// PARAMETER Declaration
// --------------------------------------------------------------------------
parameter WRITE_WIDTH = 32;
parameter WRITE_DEPTH = 10;
parameter FULL_WRITE_DEPTH = 1024;
parameter READ_WIDTH = 32;
parameter READ_DEPTH = 10;
parameter VAR_ASPECT_WRDEPTH = 10;
parameter VAR_ASPECT_RDDEPTH = 10;
parameter FULL_READ_DEPTH = 1024;
parameter PREFETCH = 0;
parameter FWFT = 0;
parameter WCLK_HIGH = 1;
parameter RESET_LOW = 1;
parameter WRITE_LOW = 1;
parameter READ_LOW = 1;
parameter AF_FLAG_STATIC = 1;
parameter AE_FLAG_STATIC = 1;
parameter AFULL_VAL = 1020;
parameter AEMPTY_VAL = 4;
parameter ESTOP = 1;
parameter FSTOP = 1;
parameter PIPE = 1;
parameter REGISTER_RADDR = 1;
parameter READ_DVALID = 32;
parameter WRITE_ACK = 32;
parameter OVERFLOW_EN = 1;
parameter UNDERFLOW_EN = 1;
parameter WRCNT_EN = 1;
parameter RDCNT_EN = 1;
parameter SYNC_RESET = 0;//uncommented in v3.0
localparam WDEPTH_CAL = (WRITE_DEPTH == 0) ? WRITE_DEPTH : (WRITE_DEPTH-1);
localparam RDEPTH_CAL = (READ_DEPTH == 0) ? READ_DEPTH : (READ_DEPTH-1);
// --------------------------------------------------------------------------
// I/O Declaration
// --------------------------------------------------------------------------
//--------
// Inputs
//--------
input clk; // fifo clock
//input reset; // reset
input aresetn;
input sresetn;
input we; // write enable to fifo
input re; // read enable to fifo
//---------
// Outputs
//---------
output full; // full status flag
output afull; // almost full status flag
output [WRITE_DEPTH:0] wrcnt; // number of elements remaining in write domain
output empty; // empty status flag
output aempty; // almost empty status flag
output [READ_DEPTH:0] rdcnt; // number of elements remaining in read domain
output underflow; // underflow status flag
output overflow; // overflow status flag
output dvld; // dvld status flag
output wack; // wack status flag
output [WDEPTH_CAL:0] memwaddr; // memory write address
output memwe; // memory write enable
output [RDEPTH_CAL:0] memraddr; // memory read address
output memre; // memory read enable
// --------------------------------------------------------------------------
// Internal signals
// --------------------------------------------------------------------------
wire full;
wire afull;
wire [WRITE_DEPTH:0] wrcnt;
wire empty;
wire aempty;
wire [READ_DEPTH:0] rdcnt;
wire [WDEPTH_CAL:0] memwaddr;
wire memwe;
wire [RDEPTH_CAL:0] memraddr;
wire memre;
reg full_r;
// reg full_reg;
reg afull_r;
reg [WRITE_DEPTH:0] wrcnt_r;
reg empty_r;
reg aempty_r;
reg [READ_DEPTH:0] rdcnt_r;
reg [WDEPTH_CAL:0] memwaddr_r;
reg [RDEPTH_CAL:0] memraddr_r;
reg dvld_r;
reg dvld_r2;
reg underflow_r;
reg wack_r;
reg overflow_r;
//reg [READ_DEPTH:0] rptr;
reg [READ_DEPTH:0] rptr_nxt;
// reg [WRITE_DEPTH:0] wptr;
reg [WRITE_DEPTH:0] wptr_nxt;
reg [VAR_ASPECT_WRDEPTH:0] wptrsync_shift;
reg [VAR_ASPECT_RDDEPTH:0] rptrsync_shift;
// reg re_p_d1;
wire [WRITE_DEPTH:0] afthreshi, wdiff_bus;
wire [READ_DEPTH:0] aethreshi, rdiff_bus;
wire fulli;
wire almostfulli;
wire almostfulli_assert;
wire almostfulli_deassert;
wire emptyi;
wire almostemptyi;
wire almostemptyi_assert;
wire almostemptyi_deassert;
wire we_p;
wire re_p;
wire we_i;
wire re_i;
wire pos_clk;
wire neg_reset;
wire fulli_fstop;
wire emptyi_estop;
wire aresetn;
wire sresetn;//uncommented in v3.0
wire [WRITE_DEPTH : 0] wptr_cmb;
wire [READ_DEPTH : 0] rptr_cmb;
// --------------------------------------------------------------------------
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
// || ||
// || Start - of - Code ||
// || ||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
// --------------------------------------------------------------------------
// --------------------------------------------------------------------------
// Top-level outputs
// --------------------------------------------------------------------------
assign full = full_r;
assign afull = afull_r;
assign empty = empty_r;
assign aempty = aempty_r;
assign underflow = underflow_r;
assign wack = wack_r;
assign overflow = overflow_r;
assign memwaddr = memwaddr_r;
assign memraddr = memraddr_r;
assign wrcnt = wrcnt_r;
assign rdcnt = rdcnt_r;
// --------------------------------------------------------------------------
// threshold values
// --------------------------------------------------------------------------
assign afthreshi = AF_FLAG_STATIC ? AFULL_VAL-1 : FULL_WRITE_DEPTH;
//***HARI***assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL+1 : 0;
assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL : 2;
// --------------------------------------------------------------------------
// clocks and enables
// --------------------------------------------------------------------------
assign pos_clk = WCLK_HIGH ? clk : ~clk;
// --------------------------------------------------------------------------
// resets
// --------------------------------------------------------------------------
/* // assign neg_reset = RESET_LOW ? ~reset : reset;----------------------commented by anurag
assign aresetn = RESET_LOW ? ~reset : reset;//----------------------updated by anurag
// assign aresetn = (SYNC_RESET == 1) ? 1'b1 : neg_reset;-----------commented by anurag
// assign sresetn = (SYNC_RESET == 1) ? neg_reset : 1'b1;------------commented by anurag */
//assign neg_reset = RESET_LOW ? ~reset : reset;//uncommented in v3.0
//
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : neg_reset;//uncommented in v3.0
//assign sresetn = (SYNC_RESET == 1) ? neg_reset : 1'b1;//uncommented in v3.0
// --------------------------------------------------------------------------
// Status flags
// --------------------------------------------------------------------------
assign we_p = WRITE_LOW ? (~we) : (we);
assign re_p = READ_LOW ? (~re) : (re);
assign we_i = we_p & !full_r;
assign re_i = re_p & !empty_r;
//assign wdiff_bus = wptr_nxt - rptrsync_shift;
assign wdiff_bus = wptr_cmb - rptrsync_shift;
//assign rdiff_bus = wptrsync_shift - rptr_nxt;
assign rdiff_bus = wptrsync_shift - rptr_cmb;
assign dvld = (REGISTER_RADDR==2) ? dvld_r2 :
((REGISTER_RADDR == 1 && PREFETCH == 0) ? dvld_r : re_i);
/* always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
full_reg <= 0;
end
else begin
full_reg <= full_r;
end
end
*/
// --------------------------------------------------------------------------
// Read pointer binary counter
// --------------------------------------------------------------------------
/* always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
rptr <= 0;
end
else begin
rptr <= rptr_nxt;
end
end */
// --------------------------------------------------------------------------
// Write pointer binary counter
// --------------------------------------------------------------------------
/* always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
wptr <= 0;
end
else begin
wptr <= wptr_nxt;
end
end */
/* always @(posedge pos_clk or negedge aresetn)
begin
if(!aresetn | !sresetn ) begin
re_p_d1 <= 'h0;
end
else begin
re_p_d1 <= re_p;
end
end */
// --------------------------------------------------------------------------
// For variable aspect ratios
// The variable aspect logic is handled by shifting the required bits of the
// read/write pointer so that they are of the same width.
// --------------------------------------------------------------------------
always @(rptr_nxt or wptr_nxt)
begin
if (WRITE_DEPTH > READ_DEPTH) begin
rptrsync_shift = rptr_nxt<<(WRITE_DEPTH - READ_DEPTH);
wptrsync_shift = wptr_nxt>>(WRITE_DEPTH - READ_DEPTH);
end
else if (READ_DEPTH > WRITE_DEPTH) begin
rptrsync_shift = rptr_nxt>>(READ_DEPTH - WRITE_DEPTH);
wptrsync_shift = wptr_nxt<<(READ_DEPTH - WRITE_DEPTH);
end
else begin
rptrsync_shift = rptr_nxt;
wptrsync_shift = wptr_nxt;
end
end
// --------------------------------------------------------------------------
// Flag generation logic
// --------------------------------------------------------------------------
//***HARI***assign almostfulli = wdiff_bus >= afthreshi;
assign almostfulli_assert = we_p & (wdiff_bus >= afthreshi);
assign almostfulli_deassert = (wdiff_bus <= afthreshi);
assign almostfulli = almostfulli_assert ? 1'b1 : (almostfulli_deassert? 1'b0 : afull );
//***HARI***assign almostemptyi = aethreshi >= rdiff_bus;
assign almostemptyi_assert = re_p & (aethreshi >= rdiff_bus);
assign almostemptyi_deassert = (aethreshi <= rdiff_bus) & aempty;
assign almostemptyi = almostemptyi_deassert ? 1'b0 : (almostemptyi_assert ? 1'b1 : aempty);
//assign fulli = we_p ? (wdiff_bus >= (FULL_WRITE_DEPTH-1)) : (wdiff_bus >= (FULL_WRITE_DEPTH));
assign fulli = we_p ? (wdiff_bus > (FULL_WRITE_DEPTH-1)) : (wdiff_bus >= (FULL_WRITE_DEPTH));
//assign fulli_fstop = (we_p & !full_r) ? (wdiff_bus[WRITE_DEPTH - 1:0] == (FULL_WRITE_DEPTH-1)) :(((we_p ^ re_p) & full_r)? 1'b0 : full_r);
assign fulli_fstop = (we_p & !full_r) ? (wdiff_bus > (FULL_WRITE_DEPTH -1)) :(((we_p ^ re_p) & full_r)? 1'b0 : full_r);
//assign emptyi = (rdiff_bus <= 1);
assign emptyi = (rdiff_bus < 1);
//assign emptyi_estop = re_p ? (rdiff_bus == 1) : (rdiff_bus <= 0);
assign emptyi_estop = re_p ? (rdiff_bus == 0) : (rdiff_bus <= 0);
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
dvld_r2 <= 0;
end
else begin
dvld_r2 <= dvld_r;
end
end
// --------------------------------------------------------------------------
// Update the pointer values based in ESTOP and FSTOP parameters.
// Generate the status flags - Empty/Full/Almost Empty/ Almost Full
// Generate the data handshaking flags - DVLD/WACK
// Generate error count flags - Underflow/Overflow
// Generate write and read address signals to the external memory
// --------------------------------------------------------------------------
genvar k;
generate
if (ESTOP == 1 && FSTOP == 1) begin
/* ESTOP and FSTOP both are true */
/* write pointer */
assign wptr_cmb = wptr_nxt + we_i;///////////////////////////added
assign rptr_cmb = rptr_nxt + re_i;//////////////////////////added
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
wptr_nxt <= 0;
end
else if(we_i == 1'b1) begin
//wptr_nxt <= wptr_nxt + 1;
wptr_nxt <= wptr_cmb;/////////////added
end
end
/* read pointer */
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
rptr_nxt <= 0;
end
else if(re_i == 1'b1) begin
//rptr_nxt <= rptr_nxt + 1;
rptr_nxt <= rptr_cmb;/////////////added
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
empty_r <= 1;
aempty_r <= 1;
dvld_r <= 0;
underflow_r <= 0;
rdcnt_r <= 0;
end
else begin
//if((re_p & (rdiff_bus == 1))) begin
if((re_i & (rdiff_bus == 0))) begin
empty_r <= 1'b1;
end
else if((!re_p & (rdiff_bus == 1))) begin
empty_r <= 1'b0;
end
else begin
empty_r <= emptyi;
end
aempty_r <= almostemptyi;
if(RDCNT_EN == 1) begin
rdcnt_r <= rdiff_bus;
end
if (re_i == 1'b1 && READ_DVALID == 1)
dvld_r <= 1'b1;
else
dvld_r <= 1'b0;
if (re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
underflow_r <= 1'b1;
else
underflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
full_r <= 0;
afull_r <= 0;
wack_r <= 0;
overflow_r <= 0;
wrcnt_r <= 0;
end
else begin
full_r <= FSTOP ? fulli : fulli_fstop;
afull_r <= almostfulli;
//if (full_r == 1'b0 && WRCNT_EN == 1) begin
if ( WRCNT_EN == 1) begin
wrcnt_r <= wdiff_bus;
end
if (we_i == 1'b1 && WRITE_ACK == 1)
wack_r <= 1'b1;
else
wack_r <= 1'b0;
if (we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
overflow_r <= 1'b1;
else
overflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn )
begin
if ( !aresetn | !sresetn ) begin
memwaddr_r <= 0;
end
else begin
if (we_i == 1'b1) begin
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
memwaddr_r <= 'h0;
end else begin
memwaddr_r <= memwaddr_r + 1;
end
end
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if ( !aresetn | !sresetn ) begin
memraddr_r <= 0;
end
else begin
if (re_i == 1'b1) begin
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
memraddr_r <= 'h0;
end else begin
memraddr_r <= memraddr_r + 1;
end
end
end
end
assign memwe = we_i;
assign memre = re_i;
end
else if (ESTOP == 1 && FSTOP == 0) begin
/* ESTOP is true and FSTOP is false */
/* write pointer */
assign wptr_cmb = wptr_nxt + we_p;
assign rptr_cmb = rptr_nxt + re_i;
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
wptr_nxt <= 0;
end
else if(we_p == 1'b1) begin
//wptr_nxt <= wptr_nxt + 1;
wptr_nxt <= wptr_cmb;
end
end
/* read pointer */
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn ) begin
rptr_nxt <= 0;
end
else if(re_i == 1'b1) begin
//rptr_nxt <= rptr_nxt + 1;
rptr_nxt <= wptr_cmb;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
empty_r <= 1;
aempty_r <= 1;
dvld_r <= 0;
underflow_r <= 0;
rdcnt_r <= 0;
end
else begin
//if((re_p & (rdiff_bus == 1))) begin
if(((rdiff_bus == 0))) begin
empty_r <= 1'b1;
end
else if((!re_p & (rdiff_bus == 1))) begin
empty_r <= 1'b0;
end
else begin
empty_r <= emptyi;
end
aempty_r <= almostemptyi;
if(RDCNT_EN == 1) begin
rdcnt_r <= rdiff_bus;
end
if (re_i == 1'b1 && READ_DVALID == 1'b1)
dvld_r <= 1'b1;
else
dvld_r <= 1'b0;
if (re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
underflow_r <= 1'b1;
else
underflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
full_r <= 0;
afull_r <= 0;
wack_r <= 0;
overflow_r <= 0;
wrcnt_r <= 0;
end
else begin
full_r <= fulli_fstop;
afull_r <= almostfulli;
if(WRCNT_EN == 1) begin
wrcnt_r <= wdiff_bus;
end
if (we_p == 1'b1 && WRITE_ACK == 1'b1)
wack_r <= 1'b1;
else
wack_r <= 1'b0;
if (we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
overflow_r <= 1'b1;
else
overflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn )
begin
if (!aresetn | !sresetn) begin
memwaddr_r <= 0;
end
else begin
if (we_p == 1'b1) begin
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
memwaddr_r <= 'h0;
end else begin
memwaddr_r <= memwaddr_r + 1;
end
end
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
memraddr_r <= 0;
end
else begin
if (re_i == 1'b1) begin
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
memraddr_r <= 'h0;
end else begin
memraddr_r <= memraddr_r + 1;
end
end
end
end
assign memwe = we_p;
assign memre = re_i;
end
else if (ESTOP == 0 && FSTOP == 1) begin
/* FSTOP is true and ESTOP is false */
/* write pointer */
assign wptr_cmb = wptr_nxt + we_i;
assign rptr_cmb = rptr_nxt + re_p;
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
wptr_nxt <= 0;
end
else if(we_i == 1'b1) begin
wptr_nxt <= wptr_cmb;
end
end
/* read pointer */
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
rptr_nxt <= 0;
end
else if(re_p == 1'b1) begin
//rptr_nxt <= rptr_nxt + 1;
rptr_nxt <= rptr_cmb;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
empty_r <= 1;
aempty_r <= 1;
dvld_r <= 0;
underflow_r <= 0;
rdcnt_r <= 0;
end
else begin
empty_r <= emptyi;
aempty_r <= almostemptyi;
if(RDCNT_EN == 1) begin
rdcnt_r <= rdiff_bus;
end
if (re_p == 1'b1 && READ_DVALID == 1'b1)
dvld_r <= 1'b1;
else
dvld_r <= 1'b0;
if ( re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
underflow_r <= 1'b1;
else
underflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
full_r <= 0;
afull_r <= 0;
wack_r <= 0;
overflow_r <= 0;
wrcnt_r <= 0;
end
else begin
full_r <= fulli;
afull_r <= almostfulli;
//if (full_r == 1'b0 && WRCNT_EN == 1) begin
if ( WRCNT_EN == 1) begin
wrcnt_r <= wdiff_bus;
end
if (we_i ==1'b1 && WRITE_ACK == 1'b1)
wack_r <= 1'b1;
else
wack_r <= 1'b0;
if (we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
overflow_r <= 1'b1;
else
overflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn )
begin
if ( !aresetn | !sresetn ) begin
memwaddr_r <= 0;
end
else begin
if ( we_i == 1'b1) begin
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
memwaddr_r <= 'h0;
end else begin
memwaddr_r <= memwaddr_r + 1;
end
end
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if ( !aresetn | !sresetn ) begin
memraddr_r <= 0;
end
else begin
if ( re_p == 1'b1) begin
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
memraddr_r <= 'h0;
end else begin
memraddr_r <= memraddr_r + 1;
end
end
end
end
assign memwe = we_i;
assign memre = re_p;
end
else if (ESTOP == 0 && FSTOP == 0) begin
/* ESTOP and FSTOP are false */
/* write pointer */
assign wptr_cmb = wptr_nxt + we_p;
assign rptr_cmb = rptr_nxt + re_p;
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
wptr_nxt <= 0;
end
else if(we_p == 1'b1) begin
//wptr_nxt <= wptr_nxt + 1;
wptr_nxt <= wptr_cmb;
end
end
/* read pointer */
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
rptr_nxt <= 0;
end
else if(re_p == 1'b1) begin
//rptr_nxt <= rptr_nxt + 1;
rptr_nxt <= rptr_cmb;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
empty_r <= 1;
aempty_r <= 1;
dvld_r <= 0;
underflow_r <= 0;
rdcnt_r <= 0;
end
else begin
empty_r <= emptyi_estop;
aempty_r <= almostemptyi;
if(RDCNT_EN == 1) begin
rdcnt_r <= rdiff_bus;
end
if (re_p == 1'b1 && READ_DVALID == 1'b1)
dvld_r <= 1'b1;
else
dvld_r <= 1'b0;
if ( re_p ==1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1)
underflow_r <= 1'b1;
else
underflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
full_r <= 0;
afull_r <= 0;
wack_r <= 0;
overflow_r <= 0;
wrcnt_r <= 0;
end
else begin
full_r <= fulli_fstop;
afull_r <= almostfulli;
if(WRCNT_EN == 1) begin
wrcnt_r <= wdiff_bus;
end
if (we_p == 1'b1 && WRITE_ACK == 1'b1)
wack_r <= 1'b1;
else
wack_r <= 1'b0;
if ( we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
overflow_r <= 1'b1;
else
overflow_r <= 1'b0;
end
end
always @(posedge pos_clk or negedge aresetn )
begin
if ( !aresetn | !sresetn ) begin
memwaddr_r <= 0;
end
else begin
if ( we_p == 1'b1) begin
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
memwaddr_r <= 'h0;
end else begin
memwaddr_r <= memwaddr_r + 1;
end
end
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if ( !aresetn | !sresetn ) begin
memraddr_r <= 0;
end
else begin
if ( re_p == 1'b1) begin
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
memraddr_r <= 'h0;
end else begin
memraddr_r <= memraddr_r + 1;
end
end
end
end
assign memwe = we_p;
assign memre = re_p;
end
endgenerate
endmodule // corefifo_sync
// --------------------------------------------------------------------------
// End - of - Code
// --------------------------------------------------------------------------

656
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync_scntr.v Normal file
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@@ -0,0 +1,656 @@
// ********************************************************************/
// Microchip Corporation Proprietary and Confidential
// Copyright 2023 Microchip Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// IP Core: COREFIFO
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
//
// *********************************************************************/
`timescale 1ns/100ps
module COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr (
clk,
//reset,
aresetn,
sresetn,
we,
re,
re_top,
full,
afull,
wrcnt,
empty,
aempty,
rdcnt,
underflow,
overflow,
dvld,
wack,
memwaddr,
memwe,
memraddr,
memre,
empty_top_fwft
);
// --------------------------------------------------------------------------
// PARAMETER Declaration
// --------------------------------------------------------------------------
parameter WRITE_WIDTH = 18;
parameter WRITE_DEPTH = 10;
parameter FULL_WRITE_DEPTH = 1024;
parameter READ_WIDTH = 18;
parameter READ_DEPTH = WRITE_DEPTH;
parameter FULL_READ_DEPTH = 1024;
parameter PREFETCH = 1;
parameter FWFT = 0;
parameter WCLK_HIGH = 1;
parameter RESET_LOW = 1;
parameter WRITE_LOW = 1;
parameter READ_LOW = 1;
parameter AF_FLAG_STATIC = 1;
parameter AE_FLAG_STATIC = 1;
parameter AFULL_VAL = 1020;
parameter AEMPTY_VAL = 4;
parameter ESTOP = 1;
parameter FSTOP = 1;
parameter PIPE = 1;
parameter REGISTER_RADDR = 1;
parameter READ_DVALID = 1;
parameter WRITE_ACK = 1;
parameter OVERFLOW_EN = 1;
parameter UNDERFLOW_EN = 1;
parameter WRCNT_EN = 1;
parameter RDCNT_EN = 1;
parameter ECC = 1;
parameter SYNC_RESET = 0;//uncommented in v3.0
parameter FAMILY = 25;
localparam WDEPTH_CAL = (WRITE_DEPTH == 0) ? WRITE_DEPTH : (WRITE_DEPTH-1);
localparam RDEPTH_CAL = (READ_DEPTH == 0) ? READ_DEPTH : (READ_DEPTH-1);
// --------------------------------------------------------------------------
// I/O Declaration
// --------------------------------------------------------------------------
//--------
// Inputs
//--------
input clk; // fifo clock
//input reset; // reset
input aresetn;
input sresetn;
input we; // write enable to fifo
input re; // read enable to fifo
input re_top; // read enable to fifo
input empty_top_fwft;
//---------
// Outputs
//---------
output full; // full status flag
output afull; // almost full status flag
output [WRITE_DEPTH:0] wrcnt; // number of elements remaining in write domain
output empty; // empty status flag
output aempty; // almost empty status flag
output [READ_DEPTH:0] rdcnt; // number of elements remaining in read domain
output underflow; // underflow status flag
output overflow; // overflow status flag
output dvld; // dvld status flag
output wack; // wack status flag
output [WDEPTH_CAL:0] memwaddr; // memory write address
output memwe; // memory write enable
output [RDEPTH_CAL:0] memraddr; // memory read address
output memre; // memory read enable
// --------------------------------------------------------------------------
// Internal signals
// --------------------------------------------------------------------------
wire full;
wire afull;
reg [WRITE_DEPTH:0] wrcnt;
wire empty;
wire aempty;
wire aempty_fwft;
reg [READ_DEPTH:0] rdcnt;
wire [WDEPTH_CAL:0] memwaddr;
wire memwe;
wire [RDEPTH_CAL:0] memraddr;
wire memre;
reg full_r;
reg full_reg;
reg afull_r;
reg empty_r;
reg empty_r_fwft;
reg empty_top_fwft_r;
reg aempty_r;
reg aempty_r_fwft;
reg [WDEPTH_CAL:0] memwaddr_r;
reg [RDEPTH_CAL:0] memraddr_r;
reg dvld_r;
reg dvld_r2;
reg underflow_r;
reg wack_r;
reg overflow_r;
reg [READ_DEPTH:0] sc_r;
reg [WRITE_DEPTH:0] sc_w;
wire [READ_DEPTH:0] sc_r_cmb;//added in v3.0
wire [WRITE_DEPTH:0] sc_w_cmb;//added in v3.0
reg [READ_DEPTH:0] sc_r_fwft;
wire [READ_DEPTH:0] sc_r_fwft_cmb;//added in v3.0
reg almostemptyi;
reg re_p_d1;
reg we_f_i;
wire [WRITE_DEPTH:0] afthreshi;
wire [READ_DEPTH:0] aethreshi;
wire fulli;
wire almostfulli;
wire almostfulli_assert;
wire almostfulli_deassert;
wire fulli_assert;
wire fulli_deassert;
wire emptyi;
wire emptyi_fwft;
wire we_p;
wire re_p;
wire we_i;
wire re_i;
wire pos_clk;
wire neg_reset;
wire re_top_p;
wire aresetn;
wire sresetn;//uncommented in v3.0
// --------------------------------------------------------------------------
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
// || ||
// || Start - of - Code ||
// || ||
// ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
// --------------------------------------------------------------------------
// --------------------------------------------------------------------------
// clocks and enables
// --------------------------------------------------------------------------
assign pos_clk = WCLK_HIGH ? clk : ~clk;
//assign resetn = RESET_LOW ? ~reset : reset;
// --------------------------------------------------------------------------
// resets
// --------------------------------------------------------------------------
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : neg_reset;
//assign sresetn = (SYNC_RESET == 1) ? neg_reset : 1'b1;
//assign aresetn = (SYNC_RESET == 1) ? 1'b1 : resetn;
//assign sresetn = (SYNC_RESET == 1) ? resetn : 1'b1;
// --------------------------------------------------------------------------
// Read and Write enables
// --------------------------------------------------------------------------
generate
if (FWFT == 0 && PREFETCH == 0) begin
assign re_p = READ_LOW ? (~re) : (re);
assign we_p = WRITE_LOW ? (~we) : (we);
end
endgenerate
generate
if ((FWFT == 1 || PREFETCH == 1) && PIPE == 1) begin
assign re_p = re;
assign re_top_p = READ_LOW ? (~re_top) : (re_top);
assign we_p = WRITE_LOW ? (~we) : (we);
end
endgenerate
assign we_i = we_p & !full_r ;
assign re_i = re_p & !empty_r;
// --------------------------------------------------------------------------
// Top-level outputs
// --------------------------------------------------------------------------
assign full = full_r;
assign afull = afull_r;
assign empty = empty_r;
assign aempty = aempty_r;
assign aempty_fwft = aempty_r;
assign underflow = underflow_r;
assign wack = wack_r;
assign dvld = (REGISTER_RADDR==2) ? dvld_r2 :
((REGISTER_RADDR == 1 && PREFETCH == 0) ? dvld_r : re_i);
assign overflow = overflow_r;
assign memwaddr = memwaddr_r;
assign memraddr = memraddr_r;
assign memwe = we_i;
assign memre = re_i;
// --------------------------------------------------------------------------
// Generate top-level read data output
// wrcnt: write count is the number of elements remaining in the Wr clock
// domain
// --------------------------------------------------------------------------
always @(negedge aresetn or posedge pos_clk)
begin
if (!aresetn | !sresetn ) begin
wrcnt <= {WRITE_DEPTH{1'b0}};
end
else if (WRCNT_EN && PREFETCH == 0 && FWFT == 0 && ECC == 1 && FAMILY == 25) begin
//wrcnt <= sc_r;
wrcnt <= sc_w_cmb; ////added in v3.0
end
else if (WRCNT_EN && PREFETCH == 0 && FWFT == 0) begin
//wrcnt <= sc_r;
wrcnt <= sc_r_cmb; ////added in v3.0
end
else if (WRCNT_EN && (PREFETCH == 1 || FWFT == 1)) begin
//wrcnt <= sc_r_fwft;
wrcnt <= sc_r_fwft_cmb; ////added in v3.0
end
else begin
wrcnt <= {WRITE_DEPTH{1'b0}};
end
end
// --------------------------------------------------------------------------
// rdcnt: read count is the number of elements remaining in the Rd clock
// domain
// --------------------------------------------------------------------------
always @(negedge aresetn or posedge pos_clk)
begin
if (!aresetn | !sresetn) begin
rdcnt <= {READ_DEPTH{1'b0}};
end
else if (RDCNT_EN && PREFETCH == 0 && FWFT == 0) begin
//rdcnt <= sc_r;
rdcnt <= sc_r_cmb; ////added in v3.0
end
else if (RDCNT_EN && (PREFETCH == 1 || FWFT == 1)) begin
//rdcnt <= sc_r_fwft;
rdcnt <= sc_r_fwft_cmb; //added in v3.0
end
else begin
rdcnt <= {READ_DEPTH{1'b0}};
end
end
//////////////////////////////////////For ECC and pipe/////AI
generate
//if ( ECC == 1 && PIPE == 2 )
if ( ECC == 1 && FAMILY == 25 )
begin
reg empty_f;
assign emptyi = (( sc_r == 1) & re_i & !we_f_i);
always @(negedge aresetn or posedge pos_clk)
begin
if (!aresetn | !sresetn)
empty_f <= 1'b1;
else if (re_i ^ we_i)
empty_f <= emptyi ;
end
always @(posedge pos_clk or negedge aresetn)
if (!aresetn | !sresetn) //begin
empty_r <= 1'b1;
else
empty_r <= emptyi ? 1'b1 : empty_f;
end
else
begin
assign emptyi = ( sc_r == 1) & !we_i & re_i;
always @(posedge pos_clk or negedge aresetn)
if (!aresetn | !sresetn)
empty_r <= 1'b1;
else if(re_i ^ we_i)
empty_r <= emptyi;
end
endgenerate
////////////////////////////////////////////
always @(posedge pos_clk or negedge aresetn)
if (!aresetn | !sresetn)
we_f_i <= 1'b0;
else
we_f_i <= we_i;
assign sc_r_cmb = ( ECC == 1 && FAMILY == 25 ) ? sc_r + we_f_i - re_i : sc_r + we_i - re_i;////added in v3.0
generate
if(( ECC == 1 && FAMILY == 25 ))
assign sc_w_cmb = sc_w + we_i - re_i;////added in v3.0
else
assign sc_w_cmb = 0;
endgenerate
assign sc_r_fwft_cmb = sc_r_fwft + we_i - re_top_p;////added in v3.0
// --------------------------------------------------------------------------
// Binary counter
// The counter increments on Write and decrements on Read
// --------------------------------------------------------------------------
always @(negedge aresetn or posedge pos_clk)
begin
if (!aresetn | !sresetn) begin
sc_r <= 0;
end
else if ( ECC == 1 && FAMILY == 25 ) begin
if( we_f_i ^ re_i) begin
sc_r <= sc_r_cmb;
end
end
else begin
if ( we_i ^ re_i) begin
sc_r <= sc_r_cmb; //added in v3.0
end
end
end
always @(negedge aresetn or posedge pos_clk)
begin
if (!aresetn | !sresetn) begin
sc_w <= 0;
end
else if ( ECC == 1 && FAMILY == 25 ) begin
if( we_i ^ re_i) begin
sc_w <= sc_w_cmb;
end
end
end
always @(negedge aresetn or posedge pos_clk)
begin
if (!aresetn | !sresetn) begin
sc_r_fwft <= 0;
end
//else if ( we_i ^ ((re_top_p & empty_top_fwft & !empty_top_fwft_r) || (re_top_p & !empty_top_fwft) )) begin ---SAR #112344
else if ( we_i ^ (re_top_p & !empty_top_fwft)) begin
if(we_i == 1'b1) begin
//sc_r_fwft <= (sc_r_fwft + 1);
sc_r_fwft <= sc_r_fwft_cmb; //added in v3.0
end
//else if(((re_top_p & empty_top_fwft & !empty_top_fwft_r) || (re_top_p & !empty_top_fwft) )) begin ---SAR #112344
else if(re_top_p & !empty_top_fwft) begin
//sc_r_fwft <= (sc_r_fwft - 1);
sc_r_fwft <= sc_r_fwft_cmb;
end
end
end
assign emptyi_fwft = ( sc_r_fwft == 'h0);
// --------------------------------------------------------------------------
// Generate almost flags
// --------------------------------------------------------------------------
generate
if (FWFT == 0 && PREFETCH == 0) begin
// --------------------------------------------------------------------------
// threshold values
// --------------------------------------------------------------------------
assign afthreshi = AF_FLAG_STATIC ? AFULL_VAL-1 : FULL_WRITE_DEPTH;
assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL : 2; //SAR#60185
always @(*)
begin
//***AHK almostemptyi = (( sc_r <= aethreshi) & !we_i & re_i) | ( (sc_r < aethreshi) & we_i & !re_i);
almostemptyi = (( sc_r <= aethreshi) & !we_i & re_i) | ( (sc_r+1 < aethreshi) & we_i & !re_i);
end
//***AHK assign almostfulli = ((sc_r >= (afthreshi)) & we_i & !re_i) | ( (sc_r > afthreshi) & !we_i & re_i);
assign almostfulli = ( ECC == 1 && FAMILY == 25 ) ? ((sc_w >= (afthreshi)) & we_i & !re_i) | ( (sc_w-1 > afthreshi) & !we_i & re_i) : ((sc_r >= (afthreshi)) & we_i & !re_i) | ( (sc_r-1 > afthreshi) & !we_i & re_i);
assign fulli = ( ECC == 1 && FAMILY == 25 ) ? ( sc_w == (FULL_WRITE_DEPTH-1)) & we_i & !re_i : ( sc_r == (FULL_WRITE_DEPTH-1)) & we_i & !re_i ;
end
endgenerate
generate
if ((FWFT == 1 || PREFETCH == 1) && PIPE == 1) begin
// --------------------------------------------------------------------------
// threshold values
// --------------------------------------------------------------------------
assign afthreshi = AF_FLAG_STATIC ? AFULL_VAL : FULL_WRITE_DEPTH;
assign aethreshi = AE_FLAG_STATIC ? AEMPTY_VAL : 2; //SAR#60185
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
almostemptyi <= 1'b1;
end
else begin
if((sc_r_fwft >= aethreshi) && we_i & !re_top_p) begin
almostemptyi <= 1'b0;
end
else if((sc_r_fwft-1 <= aethreshi) && sc_r_fwft > 0 && !we_i & re_top_p) begin
almostemptyi <= 1'b1;
end
end
end
assign almostfulli_assert = ((sc_r_fwft >= (afthreshi-1)) & we_i & !(re_top_p & !empty_r_fwft));
assign almostfulli_deassert = ( (sc_r_fwft <= afthreshi) & !we_i & (re_top_p & !empty_r_fwft));
assign almostfulli = almostfulli_assert ? 1'b1 : (almostfulli_deassert ? 1'b0 : afull_r);
assign fulli_assert = ( sc_r_fwft >= (FULL_WRITE_DEPTH-1)) & we_i & !(re_top_p & !empty_r_fwft);
assign fulli_deassert = ( sc_r_fwft < (FULL_WRITE_DEPTH-1 )) & !we_i & (re_top_p & !empty_r_fwft);
assign fulli = fulli_deassert ? 1'b0 : (fulli_assert ? 1'b1 : full_r);
end
endgenerate
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
dvld_r2 <= 1'b0;
full_reg <= 1'b0;
re_p_d1 <= 'h0;
empty_top_fwft_r <= 1'b1;
end
else begin
dvld_r2 <= dvld_r;
full_reg <= full_r;
re_p_d1 <= re_p;
empty_top_fwft_r <= empty_top_fwft;
end
end
// --------------------------------------------------------------------------
// Generate the status flags - Empty/Full/Almost Empty/ Almost Full
// Generate the data handshaking flags - DVLD/WACK
// Generate error count flags - Underflow/Overflow
// Generate write and read address signals to the external memory
// --------------------------------------------------------------------------
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
// empty_r <= 1'b1;
empty_r_fwft<= 1'b1;
aempty_r_fwft <= 1'b1;
dvld_r <= 1'b0;
underflow_r <= 1'b0;
end
else begin
// if (we_i ^ re_i)
// empty_r <= emptyi;
if (we_i ^ ((re_top_p & empty_top_fwft & !empty_top_fwft_r)|| (re_top_p & !empty_top_fwft)))
empty_r_fwft <= emptyi_fwft;
if ((we_i ^ (re_top_p & !empty_r_fwft)))
aempty_r_fwft <= almostemptyi;
if (re_i == 1'b1 && READ_DVALID == 1 && (FWFT == 0 && PREFETCH == 0))
dvld_r <= 1'b1;
else if ((re_top_p & !empty_r_fwft) && READ_DVALID == 1 && (FWFT == 1 || PREFETCH == 1))
dvld_r <= 1'b1;
else
dvld_r <= 1'b0;
if ( re_p == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1 && (FWFT == 0 && PREFETCH == 0))
underflow_r <= 1'b1;
else if ( re_top_p == 1'b1 && empty_top_fwft == 1'b1 && UNDERFLOW_EN == 1 && (FWFT == 1 || PREFETCH == 1))
underflow_r <= 1'b1;
else
underflow_r <= 1'b0;
end
end
generate
if (FWFT == 0 && PREFETCH == 0) begin
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
aempty_r <= 1'b1;
end
else begin
if ((we_i ^ re_i)) begin
aempty_r <= almostemptyi;
end
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
full_r <= 1'b0;
afull_r <= 1'b0;
wack_r <= 1'b0;
overflow_r <= 1'b0;
end
else begin
if(we_i ^ re_i) begin
full_r <= fulli;
end
if ((we_i ^ re_i))
afull_r <= almostfulli;
if (we_i == 1'b1 && WRITE_ACK == 1)
wack_r <= 1'b1;
else
wack_r <= 1'b0;
if ( we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
overflow_r <= 1'b1;
else
overflow_r <= 1'b0;
end
end
end
endgenerate
generate
if ((FWFT == 1 || PREFETCH == 1) && PIPE == 1) begin
always @(*)
begin
aempty_r = almostemptyi;
end
always @(posedge pos_clk or negedge aresetn)
begin
if (!aresetn | !sresetn) begin
full_r <= 1'b0;
afull_r <= 1'b0;
wack_r <= 1'b0;
overflow_r <= 1'b0;
end
else begin
if ((we_i ^ (re_top_p & !empty_r_fwft)) ) begin
if (we_i == 1'b1 && !(re_top_p & !empty_r_fwft)) begin
full_r <= fulli;
end
else if (we_i == 1'b0 && (re_top_p & !empty_r_fwft)) begin
full_r <= 1'b0;
end
end
if ((we_i ^ (re_top_p & !empty_r_fwft)))
afull_r <= almostfulli;
if (we_i == 1'b1 && WRITE_ACK == 1)
wack_r <= 1'b1;
else
wack_r <= 1'b0;
if ( we_p == 1'b1 && full_r == 1'b1 && OVERFLOW_EN == 1)
overflow_r <= 1'b1;
else
overflow_r <= 1'b0;
end
end
end
endgenerate
// --------------------------------------------------------------------------
// Generate write and read addresses to the memory
// --------------------------------------------------------------------------
always @(posedge pos_clk or negedge aresetn )
begin
if ( !aresetn | !sresetn ) begin
memwaddr_r <= 'h0;
end
else begin
if ( we_i == 1'b1) begin
if(memwaddr_r == (FULL_WRITE_DEPTH-1)) begin //SAR#68070
memwaddr_r <= 'h0;
end else begin
memwaddr_r <= memwaddr_r + 1;
end
end
end
end
always @(posedge pos_clk or negedge aresetn)
begin
if ( !aresetn | !sresetn ) begin
memraddr_r <= 'h0;
end
else begin
if ( re_i == 1'b1) begin
if(memraddr_r == (FULL_READ_DEPTH-1)) begin //SAR#68070
memraddr_r <= 'h0;
end else begin
memraddr_r <= memraddr_r + 1;
end
end
end
end
endmodule // corefifo_sync_scntr
// --------------------------------------------------------------------------
// End - of - Code
// --------------------------------------------------------------------------

684
component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/test/user/testbench.v Normal file
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@@ -0,0 +1,684 @@
// ****************************************************************************
// GENERIC TEST BENCH TO TEST FIFO
// ****************************************************************************
`timescale 1 ns / 100 ps
module testbench();
`include "../../../../coreparameters.v"
`include "top_define.v"
parameter CLKPERIOD = 15;
parameter WCLKPERIOD = 15;
parameter RCLKPERIOD = 15;
parameter WDEPTH_TB = (CTRL_TYPE == 2 || CTRL_TYPE == 1) ? 1024 : 64;
parameter RDEPTH_TB = (CTRL_TYPE == 2 || CTRL_TYPE == 1) ? 1024 : 64;
parameter WWIDTH_TB = 18;
parameter RWIDTH_TB = 18;
parameter CTRL_TYPE_TB = 1;
`define DLY 1
`define MAXDEPTH 18
function [31:0] logb2;
input integer x;
integer tmp, res;
begin
tmp = 1;
res = 0;
if(x == 1) begin
logb2 = 1;
end
else begin
while(tmp < x) begin
tmp = tmp * 2;
res = res + 1;
end
logb2 = res;
end
end
endfunction // logb2
/******************* TESTBENCH VARIABLES FOR DRIVING THE DESIGN INSTANTIATION *****************/
wire [WWIDTH-1:0] wdata;
wire we, re;
reg err_cnt;
wire wclk, rclk,reset;
wire clk;
wire [(logb2(RDEPTH)) : 0] rdcount;
wire [(logb2(WDEPTH)) : 0] wrcount;
wire [RWIDTH-1:0] rdata,rdata1;
/******************* External memory ****************************************/
wire [(logb2(WDEPTH)-1) : 0] ext_waddr;
wire [(logb2(RDEPTH)-1) : 0] ext_raddr;
wire [WWIDTH-1:0] ext_data;
wire [RWIDTH-1:0] ext_rd;
wire ext_we, ext_re;
/******************* Internal memory ****************************************/
wire [(logb2(WDEPTH)-1) : 0] int_waddr;
wire [(logb2(RDEPTH)-1) : 0] int_raddr;
wire [WWIDTH-1:0] int_data;
wire [RWIDTH-1:0] int_rd;
wire int_we, int_re;
/******************* Internal memory ****************************************/
wire [(logb2(WDEPTH)-1) : 0] fifo_waddr;
wire [(logb2(RDEPTH)-1) : 0] fifo_raddr;
integer total_error;
wire SB_CORRECT;
wire DB_DETECT;
// ****************************************************************************
// DIFFERENCE FUNCTION
// ****************************************************************************
function integer diff;
input integer a;
input integer b;
input integer addrwidth;
begin
if ( a > 0 || b==0 )
diff = a - b;
else
diff = ((2<<addrwidth)) - b;
end
endfunction
initial
begin
err_cnt = 0;
end
assign int_waddr = (CTRL_TYPE != 1) ? `DUT.fifo_MEMWADDR : 0;
assign int_raddr = (CTRL_TYPE != 1) ? `DUT.fifo_MEMRADDR : 0;
assign int_we = (CTRL_TYPE != 1) ? `DUT.fifo_MEMWE : 0;
assign int_re = (CTRL_TYPE != 1) ? `DUT.fifo_MEMRE : 0;
assign fifo_waddr = (CTRL_TYPE != 1) ? int_waddr : ext_waddr;
assign fifo_raddr = (CTRL_TYPE != 1) ? int_raddr : ext_raddr;
//`include "fifo_inst.v"
clock_driver #(
.CLKPERIOD(CLKPERIOD),
.WCLKPERIOD(WCLKPERIOD),
.RCLKPERIOD(RCLKPERIOD)
)
clk_driver (
.clk1(clk),
.wclk1(wclk),
.rclk1(rclk)
);
fifo_driver #( .CTRL_TYPE(CTRL_TYPE),
.WRITE_DEPTH(WDEPTH),
.WRITE_WIDTH(WWIDTH),
.FULL_WRITE_DEPTH(logb2(WDEPTH)),
.READ_DEPTH(RDEPTH),
.READ_WIDTH(RWIDTH),
.FULL_READ_DEPTH(logb2(RDEPTH)),
.WE_POLARITY(0),
.RE_POLARITY(0),
.RESET_POLARITY(0),
.RCLK_EDGE(1),
.WCLK_EDGE(1),
.PIPE(1),
.ECC(0),
.PREFETCH(0),
.ESTOP(1),
.FSTOP(1),
.SYNC(SYNC)
)
driver (
.clk (clk),
.wclk(wclk),
.rclk(rclk),
.waddr(fifo_waddr),
.raddr(fifo_raddr),
.full(full),
.empty(empty),
.q(rdata),
.dvld(dvld),
.reset(reset),
.we(we),
.re(re),
.wdata(wdata)
);
assign rdata = (CTRL_TYPE == 1) ? ext_rd : int_rd ;
fifo_monitor #(
.SYNC(SYNC),
.WRITE_WIDTH(WWIDTH),
.WRITE_DEPTH(logb2(WDEPTH)),
.FULL_WRITE_DEPTH(WDEPTH),
.READ_WIDTH(RWIDTH),
.READ_DEPTH(logb2(RDEPTH)),
.FULL_READ_DEPTH(RDEPTH),
.AFVAL(AFVAL),
.AEVAL(AEVAL),
.AE_STATIC_EN(AE_STATIC_EN),
.AF_STATIC_EN(AF_STATIC_EN),
.PIPE(1),
.ESTOP(1),
.FSTOP(1),
.OVERFLOW_EN (OVERFLOW_EN ),
.UNDERFLOW_EN (UNDERFLOW_EN ),
.WRCNT_EN (WRCNT_EN ),
.RDCNT_EN (RDCNT_EN ),
.RCLK_EDGE(1),
.WCLK_EDGE(1),
.RESET_POLARITY(0),
.READ_DVALID(READ_DVALID),
.RE_POLARITY(0),
.WE_POLARITY(0)
)
monitor (
.clk(clk),
.rclk(rclk),
.wclk(wclk),
.reset(reset),
.we(we),
.re(re),
.wcnt(wrcount),
.rcnt(rdcount),
.full(full),
.afull(afull),
.empty(empty),
.aempty(aempty),
.underflow(underflow),
.overflow(overflow),
.wack(wack),
.dvld(dvld)
);
//`include "design_instance.v"
COREFIFO_C0_COREFIFO_C0_0_COREFIFO #(
.FAMILY(FAMILY),
.SYNC(SYNC),
//.RCLK_EDGE(1),commented in v3.0
//.WCLK_EDGE(1),commented in v3.0
.RE_POLARITY(0),
//.RESET_POLARITY(0),commented in v3.0
.WE_POLARITY(0),
.RWIDTH(RWIDTH),
.WWIDTH(WWIDTH),
.RDEPTH(RDEPTH),
.WDEPTH(WDEPTH),
.READ_DVALID(READ_DVALID),
.WRITE_ACK(WRITE_ACK),
.CTRL_TYPE(CTRL_TYPE),
.ESTOP(1),
.FSTOP(1),
.AE_STATIC_EN(AE_STATIC_EN),
.AF_STATIC_EN(AF_STATIC_EN),
.AEVAL(AEVAL),
.AFVAL(AFVAL),
.PIPE(1),
.ECC(0),
.PREFETCH(0),
.OVERFLOW_EN (OVERFLOW_EN ),
.UNDERFLOW_EN (UNDERFLOW_EN ),
.WRCNT_EN (WRCNT_EN ),
.NUM_STAGES (NUM_STAGES ),
.RDCNT_EN (RDCNT_EN )
)
uut_fifo (
.CLK(clk )
,.WCLOCK(wclk)
,.RCLOCK(rclk)
,.RESET_N(reset)
,.WRESET_N(reset)
,.RRESET_N(reset)
,.DATA(wdata)
,.Q(rdata1)
,.WE(we)
,.RE(re)
,.FULL(full)
,.EMPTY(empty)
,.AFULL(afull)
,.AEMPTY(aempty)
,.OVERFLOW(overflow)
,.UNDERFLOW(underflow)
,.WACK(wack)
,.DVLD(dvld)
,.WRCNT(wrcount)
,.RDCNT(rdcount)
,.MEMWE(ext_we)
,.MEMRE(ext_re)
,.MEMWADDR(ext_waddr)
,.MEMRADDR(ext_raddr)
,.MEMWD(ext_data)
,.MEMRD(ext_rd)
,.SB_CORRECT(SB_CORRECT)
,.DB_DETECT(DB_DETECT)
);
generate
if (CTRL_TYPE == 1) begin
g4_dp_ext_mem #(
.SYNC(SYNC),
.RAM_WW(WWIDTH),
.RAM_RW(RWIDTH),
.RAM_WD(logb2(WDEPTH)),
.RAM_RD(logb2(RDEPTH)),
.READ_ADDRESS_END(RDEPTH),
.WRITE_ADDRESS_END(WDEPTH),
.WRITE_CLK(1),
.READ_CLK(1),
.WRITE_ENABLE(0),
.READ_ENABLE(0),
.PIPE(1),
.RESET_POLARITY(0)
)
ext_mem (
.clk(clk),
.wclk(wclk),
.rclk(rclk),
.rst_n(reset),
.waddr(ext_waddr),
.raddr(ext_raddr),
.data(ext_data),
.we(ext_we),
.re(ext_re),
.q(ext_rd)
);
end
else begin
g4_dp_ext_mem #(
.SYNC(SYNC),
.RAM_WW(WWIDTH),
.RAM_RW(RWIDTH),
.RAM_WD(logb2(WDEPTH)),
.RAM_RD(logb2(RDEPTH)),
.READ_ADDRESS_END(RDEPTH),
.WRITE_ADDRESS_END(WDEPTH),
.WRITE_CLK(1),
.READ_CLK(1),
.WRITE_ENABLE(0),
.READ_ENABLE(0),
.RESET_POLARITY(0),
.PIPE(1)
)
int_mem (
.clk(clk),
.wclk(wclk),
.rclk(rclk),
.rst_n(reset),
.waddr(int_waddr),
.raddr(int_raddr),
.data(wdata),
.we(int_we),
.re(int_re),
.q(int_rd)
);
end
endgenerate
//`include "fifo_POR.v"
task fifo_POR;
begin
`RESET_ASSERTED;
`FIFO_MONITOR.check_full_flag(1'b0);
`FIFO_MONITOR.check_afull_flag(1'b0);
`FIFO_MONITOR.check_empty_flag(1'b1);
`FIFO_MONITOR.check_aempty_flag(1'b1);
repeat(10) @(negedge `WCLK);
`RESET_NEGATED;
$display ("--------------------End-POR-Testcase--------------------------------");
end
endtask
//`include "fifo_basic_RW_test.v"
task fifo_basic_RW_test;
begin
$display ("Test Seq:1: WRITE OP in FIFO ");
repeat(2) @(negedge `WCLK);
`FIFO_DRIVER.push(WDEPTH-1);
`FIFO_DRIVER.write_deassert;
repeat(10) @(negedge `WCLK);
$display ("Test Seq:1: READ OP in FIFO ");
repeat(2) @(negedge `RCLK);
`FIFO_DRIVER.pop(RDEPTH-1);
`FIFO_DRIVER.read_deassert;
repeat(20) @(negedge `RCLK);
repeat(20) @(negedge `RCLK);
$display (" RESET FIIFO ");
`RESET_ASSERTED;
repeat(2) @(negedge `WCLK);
`RESET_NEGATED;
repeat (10)@(posedge `WCLK);
/*$display (" Test Seq:3: All Flags check during WRITING FIFO ");
`FIFO_DRIVER.push(WDEPTH-1);
`FIFO_DRIVER.write_deassert;
repeat (2)@(posedge `WCLK);
`FIFO_DRIVER.push(1);
`FIFO_DRIVER.write_deassert;
repeat (2)@(posedge `WCLK);
$display (" Test Seq:4: All Flags check during READ FIFO ");
repeat(2) @(negedge `RCLK);
`FIFO_DRIVER.pop(RDEPTH-1);
`FIFO_DRIVER.read_deassert;
repeat(3) @(posedge `RCLK);
$display (" RESET FIFO ");
////////////////////////////////////////////////
`RESET_ASSERTED;
repeat(2) @(negedge `WCLK);
`RESET_NEGATED;
////////////////////////////////////////////////
*/
$display ("--------------------End-Basic RW-Testcase--------------------------------");
end
endtask
task async_fifo_basic_RW_test;
begin
$display ("************ RESET FIFO ************* \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `WCLK);
`RESET_NEGATED;
repeat(10) @(negedge `RCLK);
$display ("//////////////////////////////////////////////// \n");
$display ("Test Seq:2: FULL WRITE AND READ FIFO \n");
$display ("//////////////////////////////////////////////// \n");
repeat(5) @(negedge `WCLK);
$display ("//////////////////////////////////////////////// \n");
$display ("Test Seq:2.1: FULL WRITE IN FIFO \n");
$display ("//////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(WDEPTH-1);
`FIFO_DRIVER.write_deassert;
repeat(10) @(negedge `WCLK);
$display ("//////////////////////////////////////////////// \n");
$display ("Test Seq:2.2:FULL READ from FIFO \n");
$display ("//////////////////////////////////////////////// \n");
repeat(2) @(negedge `RCLK);
if (PIPE == 2) begin
`FIFO_DRIVER.pop(RDEPTH-2);
end
else begin
`FIFO_DRIVER.pop(RDEPTH-2);
end
`FIFO_DRIVER.read_deassert;
repeat(10) @(negedge `RCLK);
$display ("***************** RESET FIFO ****************** \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `WCLK);
`RESET_NEGATED;
/*
if(OVERFLOW_EN == 1) begin
$display ("////////////////////////////////////////////////// \n");
$display (" Test Seq:2: WRITE wdepth-1 in FIFO \n");
$display ("////////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(WDEPTH-2);
`FIFO_DRIVER.write_deassert;
repeat (10)@(posedge `WCLK);
$display ("////////////////////////////////////////////////// \n");
$display (" Test Seq:2.1: OVERFLOW DURING WRITE IN FIFO \n");
$display ("////////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(1);
`FIFO_DRIVER.write_deassert;
repeat (2)@(posedge `WCLK);
$display ("***************** RESET FIFO ****************** \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `WCLK);
`RESET_NEGATED;
end
if(UNDERFLOW_EN == 1) begin
$display (" Test Seq:3: FULL WRITE IN FIFO \n");
$display ("////////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(WDEPTH-1);
`FIFO_DRIVER.write_deassert;
repeat (10)@(posedge `WCLK);
$display ("////////////////////////////////////////////////// \n");
$display (" Test Seq:3: FULL READ FROM FIFO \n");
$display ("////////////////////////////////////////////////// \n");
repeat(2) @(negedge `RCLK);
`FIFO_DRIVER.pop(RDEPTH-2);
`FIFO_DRIVER.read_deassert;
$display ("//////////////////////////////////////////////////// \n");
$display (" Test Seq:3: UNDERFLOW Flag DURING READ FROM FIFO \n");
$display ("//////////////////////////////////////////////////// \n");
repeat(3) @(posedge `RCLK);
if (PIPE !==2 ) begin
`FIFO_DRIVER.pop(2);
`FIFO_DRIVER.read_deassert;
repeat(3) @(posedge `RCLK);
end
$display ("***************** RESET FIFO ****************** \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `WCLK);
`RESET_NEGATED;
end
*/
end
endtask
task sync_fifo_basic_RW_test;
begin
$display ("************ RESET FIFO ************* \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `CLK);
`RESET_NEGATED;
repeat(10) @(negedge `CLK);
$display ("//////////////////////////////////////////////// \n");
$display ("Test Seq:2: FULL WRITE AND READ FIFO \n");
$display ("//////////////////////////////////////////////// \n");
repeat(5) @(negedge `CLK);
$display ("//////////////////////////////////////////////// \n");
$display ("Test Seq:2.1: FULL WRITE IN FIFO \n");
$display ("//////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(WDEPTH-1);
`FIFO_DRIVER.write_deassert;
repeat(10) @(negedge `CLK);
$display ("//////////////////////////////////////////////// \n");
$display ("Test Seq:2.2:FULL READ from FIFO \n");
$display ("//////////////////////////////////////////////// \n");
repeat(2) @(negedge `CLK);
`FIFO_DRIVER.pop(RDEPTH-2);
`FIFO_DRIVER.read_deassert;
repeat(10) @(negedge `CLK);
$display ("***************** RESET FIFO ****************** \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `CLK);
`RESET_NEGATED;
/*
if(OVERFLOW_EN == 1) begin
$display ("////////////////////////////////////////////////// \n");
$display (" Test Seq:2: WRITE wdepth-1 in FIFO \n");
$display ("////////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(WDEPTH-2);
`FIFO_DRIVER.write_deassert;
repeat (10)@(posedge `CLK);
$display ("////////////////////////////////////////////////// \n");
$display (" Test Seq:2.1: OVERFLOW DURING WRITE IN FIFO \n");
$display ("////////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(1);
`FIFO_DRIVER.write_deassert;
repeat (2)@(posedge `CLK);
$display ("***************** RESET FIFO ****************** \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `CLK);
`RESET_NEGATED;
end
if(UNDERFLOW_EN == 1) begin
$display (" Test Seq:3: FULL WRITE IN FIFO \n");
$display ("////////////////////////////////////////////////// \n");
`FIFO_DRIVER.push(WDEPTH-1);
`FIFO_DRIVER.write_deassert;
repeat (10)@(posedge `CLK);
$display ("////////////////////////////////////////////////// \n");
$display (" Test Seq:3.1: All Flags check during READ FIFO \n");
$display ("////////////////////////////////////////////////// \n");
repeat(2) @(negedge `CLK);
`FIFO_DRIVER.pop(RDEPTH-1);
`FIFO_DRIVER.read_deassert;
$display ("//////////////////////////////////////////////////// \n");
$display (" Test Seq:3.2: UNDERFLOW Flag DURING READ FROM FIFO \n");
$display ("//////////////////////////////////////////////////// \n");
repeat(3) @(posedge `CLK);
`FIFO_DRIVER.pop(3);
`FIFO_DRIVER.read_deassert;
repeat(3) @(posedge `CLK);
*/
$display ("***************** RESET FIFO ****************** \n\n");
`RESET_ASSERTED;
repeat(2) @(negedge `CLK);
`RESET_NEGATED;
end
endtask
//`include "regression.v"
initial begin
$display (" Flag status during RESET condition \n");
#100
//`WCLK_ON;
fifo_POR;
$display ("\n\n");
$display ("----------------------------------------------------");
$display (" Testcase 1 :FIFO_POR_TEST ");
$display ("----------------------------------------------------");
if(SYNC == 0) begin
$display ("\n\n");
$display ("----------------------------------------------------");
$display (" Testcase 2 : ASYNC FIFO_BASIC_RW_TEST ");
$display ("----------------------------------------------------\n");
async_fifo_basic_RW_test;
end
else if(SYNC == 1) begin
$display ("\n\n");
$display ("----------------------------------------------------");
$display (" Testcase 2 : SYNC FIFO_BASIC_RW_TEST ");
$display ("----------------------------------------------------\n");
sync_fifo_basic_RW_test;
end
if (`FIFO_MONITOR.err_cnt >0 || `FIFO_DRIVER.rderr_cnt >0) begin
total_error = (`FIFO_MONITOR.err_cnt + `FIFO_DRIVER.rderr_cnt);
$display ("----------------------------------------------------");
$display (" REGRESSION FAIL!! ");
//$display (" TOTAL NUMBER OF ERROR = %d ",`FIFO_MONITOR.total_error);
$display ("----------------------------------------------------");
$finish;
end
else
$display ("----------------------------------------------------");
$display (" REGRESSION PASS!! ");
$display (" All Tests PASSED!! ");
$display ("----------------------------------------------------\n");
repeat(10) @(negedge `WCLK);
$finish;
end
endmodule

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`define HIGH 1'b1
`define LOW 1'b0
`define TB testbench
`define DUT uut_fifo
`define FIFO_DRIVER driver
`define FIFO_MONITOR monitor
`define CLK_DRIVER clk_driver
`define WCLK_ON clk_on
`define WCLK_OFF clk_off
`define RESET_ASSERTED driver.reset_asserted
`define RESET_NEGATED driver.reset_negated
`define CLK clk
`define WCLK wclk
`define RCLK rclk

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component/work/COREFIFO_C0/COREFIFO_C0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Wed Apr 15 18:21:54 2026
Project : E:\AbhishekV\rising\ethernet_tpsram_test
Component : COREFIFO_C0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/COREFIFO.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_sync_scntr.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_async.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_nstagessync.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_graytobinconv.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/core/corefifo_fwft.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/wave.do
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/mti/scripts/runall.do
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/coreparameters.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/test/user/top_define.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/clock_driver.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/fifo_driver.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/fifo_monitor.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/g4_dp_ext_mem.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0/COREFIFO_C0_0/rtl/vlog/test/user/testbench.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WeqR.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WgtR.v
E:/AbhishekV/rising/ethernet_tpsram_test/component/Actel/DirectCore/COREFIFO/3.1.101/rtl/vlog/test/user/MEM_WltR.v
Constraint files:
E:/AbhishekV/rising/ethernet_tpsram_test/component/work/COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.sdc

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component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0.sdb Normal file
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component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:01 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of COREJTAGDEBUG_C0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component COREJTAGDEBUG_C0
create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -component_name {COREJTAGDEBUG_C0} -params {\
"IR_CODE_TGT_0:0x55" \
"IR_CODE_TGT_1:0x56" \
"IR_CODE_TGT_2:0x57" \
"IR_CODE_TGT_3:0x58" \
"IR_CODE_TGT_4:0x59" \
"IR_CODE_TGT_5:0x5a" \
"IR_CODE_TGT_6:0x5b" \
"IR_CODE_TGT_7:0x5c" \
"IR_CODE_TGT_8:0x5d" \
"IR_CODE_TGT_9:0x5e" \
"IR_CODE_TGT_10:0x5f" \
"IR_CODE_TGT_11:0x60" \
"IR_CODE_TGT_12:0x61" \
"IR_CODE_TGT_13:0x62" \
"IR_CODE_TGT_14:0x63" \
"IR_CODE_TGT_15:0x64" \
"NUM_DEBUG_TGTS:1" \
"TGT_ACTIVE_HIGH_RESET_0:false" \
"TGT_ACTIVE_HIGH_RESET_1:false" \
"TGT_ACTIVE_HIGH_RESET_2:false" \
"TGT_ACTIVE_HIGH_RESET_3:false" \
"TGT_ACTIVE_HIGH_RESET_4:false" \
"TGT_ACTIVE_HIGH_RESET_5:false" \
"TGT_ACTIVE_HIGH_RESET_6:false" \
"TGT_ACTIVE_HIGH_RESET_7:false" \
"TGT_ACTIVE_HIGH_RESET_8:false" \
"TGT_ACTIVE_HIGH_RESET_9:false" \
"TGT_ACTIVE_HIGH_RESET_10:false" \
"TGT_ACTIVE_HIGH_RESET_11:false" \
"TGT_ACTIVE_HIGH_RESET_12:false" \
"TGT_ACTIVE_HIGH_RESET_13:false" \
"TGT_ACTIVE_HIGH_RESET_14:false" \
"TGT_ACTIVE_HIGH_RESET_15:false" \
"UJTAG_BYPASS:false" \
"UJTAG_SEC_EN:false" }
# Exporting Component Description of COREJTAGDEBUG_C0 to TCL done
*/
// COREJTAGDEBUG_C0
module COREJTAGDEBUG_C0(
// Inputs
TCK,
TDI,
TGT_TDO_0,
TMS,
TRSTB,
// Outputs
TDO,
TGT_TCK_0,
TGT_TDI_0,
TGT_TMS_0,
TGT_TRSTN_0
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input TCK;
input TDI;
input TGT_TDO_0;
input TMS;
input TRSTB;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output TDO;
output TGT_TCK_0;
output TGT_TDI_0;
output TGT_TMS_0;
output TGT_TRSTN_0;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire TCK;
wire TDI;
wire TDO_net_0;
wire TGT_TCK_0_net_0;
wire TGT_TDI_0_net_0;
wire TGT_TDO_0;
wire TGT_TMS_0_net_0;
wire TGT_TRSTN_0_net_0;
wire TMS;
wire TRSTB;
wire TDO_net_1;
wire TGT_TCK_0_net_1;
wire TGT_TMS_0_net_1;
wire TGT_TDI_0_net_1;
wire TGT_TRSTN_0_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire VCC_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TDO_net_1 = TDO_net_0;
assign TDO = TDO_net_1;
assign TGT_TCK_0_net_1 = TGT_TCK_0_net_0;
assign TGT_TCK_0 = TGT_TCK_0_net_1;
assign TGT_TMS_0_net_1 = TGT_TMS_0_net_0;
assign TGT_TMS_0 = TGT_TMS_0_net_1;
assign TGT_TDI_0_net_1 = TGT_TDI_0_net_0;
assign TGT_TDI_0 = TGT_TDI_0_net_1;
assign TGT_TRSTN_0_net_1 = TGT_TRSTN_0_net_0;
assign TGT_TRSTN_0 = TGT_TRSTN_0_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------COREJTAGDEBUG - Actel:DirectCore:COREJTAGDEBUG:4.0.100
COREJTAGDEBUG #(
.FAMILY ( 26 ),
.IR_CODE_TGT_0 ( 'h55 ),
.IR_CODE_TGT_1 ( 'h56 ),
.IR_CODE_TGT_2 ( 'h57 ),
.IR_CODE_TGT_3 ( 'h58 ),
.IR_CODE_TGT_4 ( 'h59 ),
.IR_CODE_TGT_5 ( 'h5a ),
.IR_CODE_TGT_6 ( 'h5b ),
.IR_CODE_TGT_7 ( 'h5c ),
.IR_CODE_TGT_8 ( 'h5d ),
.IR_CODE_TGT_9 ( 'h5e ),
.IR_CODE_TGT_10 ( 'h5f ),
.IR_CODE_TGT_11 ( 'h60 ),
.IR_CODE_TGT_12 ( 'h61 ),
.IR_CODE_TGT_13 ( 'h62 ),
.IR_CODE_TGT_14 ( 'h63 ),
.IR_CODE_TGT_15 ( 'h64 ),
.NUM_DEBUG_TGTS ( 1 ),
.TGT_ACTIVE_HIGH_RESET_0 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_1 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_2 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_3 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_4 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_5 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_6 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_7 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_8 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_9 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_10 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_11 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_12 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_13 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_14 ( 0 ),
.TGT_ACTIVE_HIGH_RESET_15 ( 0 ),
.UJTAG_BYPASS ( 0 ),
.UJTAG_SEC_EN ( 0 ) )
COREJTAGDEBUG_C0_0(
// Inputs
.TRSTB ( TRSTB ),
.TCK ( TCK ),
.TMS ( TMS ),
.TDI ( TDI ),
.TGT_TDO_0 ( TGT_TDO_0 ),
.TGT_TDO_1 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_2 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_3 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_4 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_5 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_6 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_7 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_8 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_9 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_10 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_11 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_12 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_13 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_14 ( GND_net ), // tied to 1'b0 from definition
.TGT_TDO_15 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TCK_0 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TMS_0 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TDI_0 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TRSTB_0 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TCK_1 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TMS_1 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TDI_1 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TRSTB_1 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TCK_2 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TMS_2 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TDI_2 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TRSTB_2 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TCK_3 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TMS_3 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TDI_3 ( GND_net ), // tied to 1'b0 from definition
.UJTAG_BYPASS_TRSTB_3 ( GND_net ), // tied to 1'b0 from definition
.UTRSTB_SEC ( VCC_net ), // tied to 1'b1 from definition
.EN_SEC ( GND_net ), // tied to 1'b0 from definition
.TDI_SEC ( GND_net ), // tied to 1'b0 from definition
// Outputs
.TDO ( TDO_net_0 ),
.TGT_TRST_0 ( ),
.TGT_TCK_0 ( TGT_TCK_0_net_0 ),
.TGT_TMS_0 ( TGT_TMS_0_net_0 ),
.TGT_TDI_0 ( TGT_TDI_0_net_0 ),
.TGT_TRST_1 ( ),
.TGT_TCK_1 ( ),
.TGT_TMS_1 ( ),
.TGT_TDI_1 ( ),
.TGT_TRST_2 ( ),
.TGT_TCK_2 ( ),
.TGT_TMS_2 ( ),
.TGT_TDI_2 ( ),
.TGT_TRST_3 ( ),
.TGT_TCK_3 ( ),
.TGT_TMS_3 ( ),
.TGT_TDI_3 ( ),
.TGT_TRST_4 ( ),
.TGT_TCK_4 ( ),
.TGT_TMS_4 ( ),
.TGT_TDI_4 ( ),
.TGT_TRST_5 ( ),
.TGT_TCK_5 ( ),
.TGT_TMS_5 ( ),
.TGT_TDI_5 ( ),
.TGT_TRST_6 ( ),
.TGT_TCK_6 ( ),
.TGT_TMS_6 ( ),
.TGT_TDI_6 ( ),
.TGT_TRST_7 ( ),
.TGT_TCK_7 ( ),
.TGT_TMS_7 ( ),
.TGT_TDI_7 ( ),
.TGT_TRST_8 ( ),
.TGT_TCK_8 ( ),
.TGT_TMS_8 ( ),
.TGT_TDI_8 ( ),
.TGT_TRST_9 ( ),
.TGT_TCK_9 ( ),
.TGT_TMS_9 ( ),
.TGT_TDI_9 ( ),
.TGT_TRST_10 ( ),
.TGT_TCK_10 ( ),
.TGT_TMS_10 ( ),
.TGT_TDI_10 ( ),
.TGT_TRST_11 ( ),
.TGT_TCK_11 ( ),
.TGT_TMS_11 ( ),
.TGT_TDI_11 ( ),
.TGT_TRST_12 ( ),
.TGT_TCK_12 ( ),
.TGT_TMS_12 ( ),
.TGT_TDI_12 ( ),
.TGT_TRST_13 ( ),
.TGT_TCK_13 ( ),
.TGT_TMS_13 ( ),
.TGT_TDI_13 ( ),
.TGT_TRST_14 ( ),
.TGT_TCK_14 ( ),
.TGT_TMS_14 ( ),
.TGT_TDI_14 ( ),
.TGT_TRST_15 ( ),
.TGT_TCK_15 ( ),
.TGT_TMS_15 ( ),
.TGT_TDI_15 ( ),
.UJTAG_BYPASS_TDO_1 ( ),
.UJTAG_BYPASS_TDO_2 ( ),
.UJTAG_BYPASS_TDO_3 ( ),
.UJTAG_BYPASS_TDO_0 ( ),
.TGT_TRSTN_0 ( TGT_TRSTN_0_net_0 ),
.TGT_TRSTN_1 ( ),
.TGT_TRSTN_2 ( ),
.TGT_TRSTN_3 ( ),
.TGT_TRSTN_4 ( ),
.TGT_TRSTN_5 ( ),
.TGT_TRSTN_6 ( ),
.TGT_TRSTN_7 ( ),
.TGT_TRSTN_8 ( ),
.TGT_TRSTN_9 ( ),
.TGT_TRSTN_10 ( ),
.TGT_TRSTN_11 ( ),
.TGT_TRSTN_12 ( ),
.TGT_TRSTN_13 ( ),
.TGT_TRSTN_14 ( ),
.TGT_TRSTN_15 ( ),
.UTRSTB ( ),
.UTMS ( )
);
endmodule

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component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:02 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : COREJTAGDEBUG_C0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_ujtag_wrapper.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_uj_jtag.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/core/corejtagdebug_bufd.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/COREJTAGDEBUG_C0/COREJTAGDEBUG_C0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/mti/corejtagdebug_wave.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/rtl/vlog/test/corejtagdebug_host_emulator.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/rtl/vlog/test/corejtagdebug_jtag_tap.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/4.0.100/rtl/vlog/test/corejtagdebug_testbench.v

1
component/work/CORESPI_0/CORESPI_0.cxf Normal file
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component/work/CORESPI_0/CORESPI_0.sdb Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:04 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CORESPI_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CORESPI_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CORESPI:5.2.104} -component_name {CORESPI_0} -params {\
"APB_DWIDTH:32" \
"CFG_CLK:16" \
"CFG_FIFO_DEPTH:32" \
"CFG_FRAME_SIZE:16" \
"CFG_MODE:0" \
"CFG_MOT_MODE:0" \
"CFG_MOT_SSEL:true" \
"CFG_NSC_OPERATION:0" \
"CFG_TI_JMB_FRAMES:false" \
"CFG_TI_NSC_CUSTOM:0" \
"CFG_TI_NSC_FRC:false" }
# Exporting Component Description of CORESPI_0 to TCL done
*/
// CORESPI_0
module CORESPI_0(
// Inputs
PADDR,
PCLK,
PENABLE,
PRESETN,
PSEL,
PWDATA,
PWRITE,
SPICLKI,
SPISDI,
SPISSI,
// Outputs
PRDATA,
PREADY,
PSLVERR,
SPIINT,
SPIMODE,
SPIOEN,
SPIRXAVAIL,
SPISCLKO,
SPISDO,
SPISS,
SPITXRFM
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [6:0] PADDR;
input PCLK;
input PENABLE;
input PRESETN;
input PSEL;
input [31:0] PWDATA;
input PWRITE;
input SPICLKI;
input SPISDI;
input SPISSI;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] PRDATA;
output PREADY;
output PSLVERR;
output SPIINT;
output SPIMODE;
output SPIOEN;
output SPIRXAVAIL;
output SPISCLKO;
output SPISDO;
output [7:0] SPISS;
output SPITXRFM;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [6:0] PADDR;
wire PENABLE;
wire [31:0] APB_bif_PRDATA;
wire APB_bif_PREADY;
wire PSEL;
wire APB_bif_PSLVERR;
wire [31:0] PWDATA;
wire PWRITE;
wire PCLK;
wire PRESETN;
wire SPICLKI;
wire SPIINT_net_0;
wire SPIMODE_net_0;
wire SPIOEN_net_0;
wire SPIRXAVAIL_net_0;
wire SPISCLKO_net_0;
wire SPISDI;
wire SPISDO_net_0;
wire [7:0] SPISS_net_0;
wire SPISSI;
wire SPITXRFM_net_0;
wire SPIINT_net_1;
wire SPIRXAVAIL_net_1;
wire SPITXRFM_net_1;
wire [7:0] SPISS_net_1;
wire SPISCLKO_net_1;
wire SPIOEN_net_1;
wire SPISDO_net_1;
wire SPIMODE_net_1;
wire [31:0] APB_bif_PRDATA_net_0;
wire APB_bif_PREADY_net_0;
wire APB_bif_PSLVERR_net_0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign SPIINT_net_1 = SPIINT_net_0;
assign SPIINT = SPIINT_net_1;
assign SPIRXAVAIL_net_1 = SPIRXAVAIL_net_0;
assign SPIRXAVAIL = SPIRXAVAIL_net_1;
assign SPITXRFM_net_1 = SPITXRFM_net_0;
assign SPITXRFM = SPITXRFM_net_1;
assign SPISS_net_1 = SPISS_net_0;
assign SPISS[7:0] = SPISS_net_1;
assign SPISCLKO_net_1 = SPISCLKO_net_0;
assign SPISCLKO = SPISCLKO_net_1;
assign SPIOEN_net_1 = SPIOEN_net_0;
assign SPIOEN = SPIOEN_net_1;
assign SPISDO_net_1 = SPISDO_net_0;
assign SPISDO = SPISDO_net_1;
assign SPIMODE_net_1 = SPIMODE_net_0;
assign SPIMODE = SPIMODE_net_1;
assign APB_bif_PRDATA_net_0 = APB_bif_PRDATA;
assign PRDATA[31:0] = APB_bif_PRDATA_net_0;
assign APB_bif_PREADY_net_0 = APB_bif_PREADY;
assign PREADY = APB_bif_PREADY_net_0;
assign APB_bif_PSLVERR_net_0 = APB_bif_PSLVERR;
assign PSLVERR = APB_bif_PSLVERR_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CORESPI - Actel:DirectCore:CORESPI:5.2.104
CORESPI #(
.APB_DWIDTH ( 32 ),
.CFG_CLK ( 16 ),
.CFG_FIFO_DEPTH ( 32 ),
.CFG_FRAME_SIZE ( 16 ),
.CFG_MODE ( 0 ),
.CFG_MOT_MODE ( 0 ),
.CFG_MOT_SSEL ( 1 ),
.CFG_NSC_OPERATION ( 0 ),
.CFG_TI_JMB_FRAMES ( 0 ),
.CFG_TI_NSC_CUSTOM ( 0 ),
.CFG_TI_NSC_FRC ( 0 ) )
CORESPI_0_0(
// Inputs
.PCLK ( PCLK ),
.PRESETN ( PRESETN ),
.PADDR ( PADDR ),
.PSEL ( PSEL ),
.PENABLE ( PENABLE ),
.PWRITE ( PWRITE ),
.PWDATA ( PWDATA ),
.SPISSI ( SPISSI ),
.SPISDI ( SPISDI ),
.SPICLKI ( SPICLKI ),
// Outputs
.PRDATA ( APB_bif_PRDATA ),
.PREADY ( APB_bif_PREADY ),
.PSLVERR ( APB_bif_PSLVERR ),
.SPIINT ( SPIINT_net_0 ),
.SPIRXAVAIL ( SPIRXAVAIL_net_0 ),
.SPITXRFM ( SPITXRFM_net_0 ),
.SPISS ( SPISS_net_0 ),
.SPISCLKO ( SPISCLKO_net_0 ),
.SPIOEN ( SPIOEN_net_0 ),
.SPISDO ( SPISDO_net_0 ),
.SPIMODE ( SPIMODE_net_0 )
);
endmodule

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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:04 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : CORESPI_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/corespi.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_chanctrl.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_clockmux.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_control.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_fifo.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_rf.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CORESPI_0/CORESPI_0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec.exe
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec.lin
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/mti/bfmtovec_compile.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/mti/user_tb.bfm
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/mti/wave.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_ahbtoapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_apb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_main.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/amba_bfm/bfm_package.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/test/user/testbench.v

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component/work/CORETSE_0/CORETSE_0.cxf Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:12 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CORETSE_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CORETSE_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CORETSE:4.0.124} -component_name {CORETSE_0} -params {\
"ECC_ENABLE:false" \
"GMII_TBI:1" \
"HOST_INTERFACE:0" \
"MDIO_PHYID:18" \
"PACKET_SIZE:11" \
"SAL:true" \
"SLIP_ENABLE:false" \
"STATS:true" \
"TXRX_INTR_ENABLE:true" \
"WoL:true" }
# Exporting Component Description of CORETSE_0 to TCL done
*/
// CORETSE_0
module CORETSE_0(
// Inputs
MDI,
MRXACPT,
MRXCLK,
MTXBYTEVALID,
MTXCLK,
MTXDAT,
MTXEOF,
MTXRDY,
MTXSOF,
PADDR,
PCLK,
PENABLE,
PRESETN,
PSEL,
PWDATA,
PWRITE,
RCG,
RXCLK,
SIGNAL_DETECT,
TBI_RX_CLK,
TBI_TX_CLK,
TXCLK,
// Outputs
ANX_STATE,
MDC,
MDO,
MDOEN,
MRXBYTEVALID,
MRXDAT,
MRXEOF,
MRXRDY,
MRXSOF,
MTXACPT,
MTXHWM,
PRDATA,
PREADY,
PSLVERR,
RCG_ERROR,
SYNC,
TBI_TX_VALID,
TCG,
TSM_CONTROL,
TSM_RX_INTR,
TSM_TX_INTR
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input MDI;
input MRXACPT;
input MRXCLK;
input [1:0] MTXBYTEVALID;
input MTXCLK;
input [31:0] MTXDAT;
input MTXEOF;
input MTXRDY;
input MTXSOF;
input [31:0] PADDR;
input PCLK;
input PENABLE;
input PRESETN;
input PSEL;
input [31:0] PWDATA;
input PWRITE;
input [9:0] RCG;
input RXCLK;
input SIGNAL_DETECT;
input TBI_RX_CLK;
input TBI_TX_CLK;
input TXCLK;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [9:0] ANX_STATE;
output MDC;
output MDO;
output MDOEN;
output [1:0] MRXBYTEVALID;
output [31:0] MRXDAT;
output MRXEOF;
output MRXRDY;
output MRXSOF;
output MTXACPT;
output MTXHWM;
output [31:0] PRDATA;
output PREADY;
output PSLVERR;
output RCG_ERROR;
output SYNC;
output TBI_TX_VALID;
output [9:0] TCG;
output [31:0] TSM_CONTROL;
output [3:0] TSM_RX_INTR;
output [3:0] TSM_TX_INTR;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [9:0] ANX_STATE_net_0;
wire [31:0] PADDR;
wire PENABLE;
wire [31:0] APBS_PRDATA;
wire APBS_PREADY;
wire PSEL;
wire APBS_PSLVERR;
wire [31:0] PWDATA;
wire PWRITE;
wire MDC_net_0;
wire MDI;
wire MDO_net_0;
wire MDOEN_net_0;
wire MRXACPT;
wire [1:0] MRXBYTEVALID_net_0;
wire MRXCLK;
wire [31:0] MRXDAT_net_0;
wire MRXEOF_net_0;
wire MRXRDY_net_0;
wire MRXSOF_net_0;
wire MTXACPT_net_0;
wire [1:0] MTXBYTEVALID;
wire MTXCLK;
wire [31:0] MTXDAT;
wire MTXEOF;
wire MTXHWM_net_0;
wire MTXRDY;
wire MTXSOF;
wire PCLK;
wire PRESETN;
wire [9:0] RCG;
wire RCG_ERROR_net_0;
wire RXCLK;
wire SIGNAL_DETECT;
wire SYNC_net_0;
wire TBI_RX_CLK;
wire TBI_TX_CLK;
wire TBI_TX_VALID_net_0;
wire [9:0] TCG_net_0;
wire [31:0] TSM_CONTROL_net_0;
wire [3:0] TSM_RX_INTR_net_0;
wire [3:0] TSM_TX_INTR_net_0;
wire TXCLK;
wire MTXACPT_net_1;
wire MTXHWM_net_1;
wire MRXRDY_net_1;
wire MRXSOF_net_1;
wire MRXEOF_net_1;
wire [31:0] MRXDAT_net_1;
wire [1:0] MRXBYTEVALID_net_1;
wire [9:0] TCG_net_1;
wire TBI_TX_VALID_net_1;
wire SYNC_net_1;
wire [9:0] ANX_STATE_net_1;
wire RCG_ERROR_net_1;
wire MDC_net_1;
wire MDO_net_1;
wire MDOEN_net_1;
wire [31:0] TSM_CONTROL_net_1;
wire [3:0] TSM_TX_INTR_net_1;
wire [3:0] TSM_RX_INTR_net_1;
wire [31:0] APBS_PRDATA_net_0;
wire APBS_PSLVERR_net_0;
wire APBS_PREADY_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [31:0] AXI4S_TTDATA_const_net_0;
wire [3:0] AXI4S_TTKEEP_const_net_0;
wire [7:0] RXD_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign AXI4S_TTDATA_const_net_0 = 32'h00000000;
assign AXI4S_TTKEEP_const_net_0 = 4'h0;
assign RXD_const_net_0 = 8'h00;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MTXACPT_net_1 = MTXACPT_net_0;
assign MTXACPT = MTXACPT_net_1;
assign MTXHWM_net_1 = MTXHWM_net_0;
assign MTXHWM = MTXHWM_net_1;
assign MRXRDY_net_1 = MRXRDY_net_0;
assign MRXRDY = MRXRDY_net_1;
assign MRXSOF_net_1 = MRXSOF_net_0;
assign MRXSOF = MRXSOF_net_1;
assign MRXEOF_net_1 = MRXEOF_net_0;
assign MRXEOF = MRXEOF_net_1;
assign MRXDAT_net_1 = MRXDAT_net_0;
assign MRXDAT[31:0] = MRXDAT_net_1;
assign MRXBYTEVALID_net_1 = MRXBYTEVALID_net_0;
assign MRXBYTEVALID[1:0] = MRXBYTEVALID_net_1;
assign TCG_net_1 = TCG_net_0;
assign TCG[9:0] = TCG_net_1;
assign TBI_TX_VALID_net_1 = TBI_TX_VALID_net_0;
assign TBI_TX_VALID = TBI_TX_VALID_net_1;
assign SYNC_net_1 = SYNC_net_0;
assign SYNC = SYNC_net_1;
assign ANX_STATE_net_1 = ANX_STATE_net_0;
assign ANX_STATE[9:0] = ANX_STATE_net_1;
assign RCG_ERROR_net_1 = RCG_ERROR_net_0;
assign RCG_ERROR = RCG_ERROR_net_1;
assign MDC_net_1 = MDC_net_0;
assign MDC = MDC_net_1;
assign MDO_net_1 = MDO_net_0;
assign MDO = MDO_net_1;
assign MDOEN_net_1 = MDOEN_net_0;
assign MDOEN = MDOEN_net_1;
assign TSM_CONTROL_net_1 = TSM_CONTROL_net_0;
assign TSM_CONTROL[31:0] = TSM_CONTROL_net_1;
assign TSM_TX_INTR_net_1 = TSM_TX_INTR_net_0;
assign TSM_TX_INTR[3:0] = TSM_TX_INTR_net_1;
assign TSM_RX_INTR_net_1 = TSM_RX_INTR_net_0;
assign TSM_RX_INTR[3:0] = TSM_RX_INTR_net_1;
assign APBS_PRDATA_net_0 = APBS_PRDATA;
assign PRDATA[31:0] = APBS_PRDATA_net_0;
assign APBS_PSLVERR_net_0 = APBS_PSLVERR;
assign PSLVERR = APBS_PSLVERR_net_0;
assign APBS_PREADY_net_0 = APBS_PREADY;
assign PREADY = APBS_PREADY_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CORETSE - Actel:DirectCore:CORETSE:4.0.124
CORETSE #(
.ECC_ENABLE ( 0 ),
.FAMILY ( 26 ),
.GMII_TBI ( 1 ),
.HOST_INTERFACE ( 0 ),
.MDIO_PHYID ( 18 ),
.PACKET_SIZE ( 11 ),
.SAL ( 1 ),
.SLIP_ENABLE ( 0 ),
.STATS ( 1 ),
.TXRX_INTR_ENABLE ( 1 ),
.WoL ( 1 ) )
CORETSE_0_0(
// Inputs
.MTXCLK ( MTXCLK ),
.MTXRDY ( MTXRDY ),
.MTXSOF ( MTXSOF ),
.MTXEOF ( MTXEOF ),
.MTXDAT ( MTXDAT ),
.MTXBYTEVALID ( MTXBYTEVALID ),
.MRXCLK ( MRXCLK ),
.MRXACPT ( MRXACPT ),
.AXI4S_TCLK ( GND_net ), // tied to 1'b0 from definition
.AXI4S_TTVALID ( GND_net ), // tied to 1'b0 from definition
.AXI4S_TTDATA ( AXI4S_TTDATA_const_net_0 ), // tied to 32'h00000000 from definition
.AXI4S_TTKEEP ( AXI4S_TTKEEP_const_net_0 ), // tied to 4'h0 from definition
.AXI4S_TTLAST ( GND_net ), // tied to 1'b0 from definition
.AXI4S_ICLK ( GND_net ), // tied to 1'b0 from definition
.AXI4S_ITREADY ( GND_net ), // tied to 1'b0 from definition
.TXCLK ( TXCLK ),
.RXCLK ( RXCLK ),
.RXDV ( GND_net ), // tied to 1'b0 from definition
.RXD ( RXD_const_net_0 ), // tied to 8'h00 from definition
.RXER ( GND_net ), // tied to 1'b0 from definition
.CRS ( GND_net ), // tied to 1'b0 from definition
.COL ( GND_net ), // tied to 1'b0 from definition
.TBI_TX_CLK ( TBI_TX_CLK ),
.TBI_RX_CLK ( TBI_RX_CLK ),
.RCG ( RCG ),
.TBI_RX_VALID ( GND_net ), // tied to 1'b0 from definition
.TBI_RX_READY ( GND_net ), // tied to 1'b0 from definition
.SIGNAL_DETECT ( SIGNAL_DETECT ),
.MDI ( MDI ),
.PCLK ( PCLK ),
.PRESETN ( PRESETN ),
.PADDR ( PADDR ),
.PSEL ( PSEL ),
.PENABLE ( PENABLE ),
.PWRITE ( PWRITE ),
.PWDATA ( PWDATA ),
// Outputs
.MTXACPT ( MTXACPT_net_0 ),
.MTXHWM ( MTXHWM_net_0 ),
.MRXRDY ( MRXRDY_net_0 ),
.MRXSOF ( MRXSOF_net_0 ),
.MRXEOF ( MRXEOF_net_0 ),
.MRXDAT ( MRXDAT_net_0 ),
.MRXBYTEVALID ( MRXBYTEVALID_net_0 ),
.AXI4S_TTREADY ( ),
.AXI4S_ITVALID ( ),
.AXI4S_ITLAST ( ),
.AXI4S_ITDATA ( ),
.AXI4S_ITKEEP ( ),
.AXI4S_ITUSER ( ),
.TXEN ( ),
.TXD ( ),
.TXER ( ),
.TCG ( TCG_net_0 ),
.TBI_TX_VALID ( TBI_TX_VALID_net_0 ),
.RX_SLIP ( ),
.SYNC ( SYNC_net_0 ),
.ANX_STATE ( ANX_STATE_net_0 ),
.RCG_ERROR ( RCG_ERROR_net_0 ),
.MDC ( MDC_net_0 ),
.MDO ( MDO_net_0 ),
.MDOEN ( MDOEN_net_0 ),
.PREADY ( APBS_PREADY ),
.PRDATA ( APBS_PRDATA ),
.PSLVERR ( APBS_PSLVERR ),
.TSM_INTR ( ),
.TSM_CONTROL ( TSM_CONTROL_net_0 ),
.TSM_TX_INTR ( TSM_TX_INTR_net_0 ),
.TSM_RX_INTR ( TSM_RX_INTR_net_0 ),
.TX_ECC_SEC ( ),
.TX_ECC_DED ( ),
.RX_ECC_SEC ( ),
.RX_ECC_DED ( )
);
endmodule

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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:12 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : CORETSE_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/CoreTSE.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/core_evaluation/include.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CORETSE_0/CORETSE_0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/coreparameters.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/mti/scripts/wave.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/test/user/tbi/testbench.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/test/user/tbi/CoreTSE_tb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORETSE/4.0.124/rtl/vlog/test/user/tbi/CoreTSE_AXI4S_tb.v

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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:03 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CoreAPB3_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CoreAPB3_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_0} -params {\
"APB_DWIDTH:32" \
"APBSLOT0ENABLE:true" \
"APBSLOT1ENABLE:true" \
"APBSLOT2ENABLE:true" \
"APBSLOT3ENABLE:false" \
"APBSLOT4ENABLE:false" \
"APBSLOT5ENABLE:false" \
"APBSLOT6ENABLE:false" \
"APBSLOT7ENABLE:false" \
"APBSLOT8ENABLE:false" \
"APBSLOT9ENABLE:false" \
"APBSLOT10ENABLE:false" \
"APBSLOT11ENABLE:false" \
"APBSLOT12ENABLE:false" \
"APBSLOT13ENABLE:false" \
"APBSLOT14ENABLE:false" \
"APBSLOT15ENABLE:false" \
"IADDR_OPTION:0" \
"MADDR_BITS:16" \
"SC_0:false" \
"SC_1:false" \
"SC_2:false" \
"SC_3:false" \
"SC_4:false" \
"SC_5:false" \
"SC_6:false" \
"SC_7:false" \
"SC_8:false" \
"SC_9:false" \
"SC_10:false" \
"SC_11:false" \
"SC_12:false" \
"SC_13:false" \
"SC_14:false" \
"SC_15:false" \
"UPR_NIBBLE_POSN:6" }
# Exporting Component Description of CoreAPB3_0 to TCL done
*/
// CoreAPB3_0
module CoreAPB3_0(
// Inputs
PADDR,
PENABLE,
PRDATAS0,
PRDATAS1,
PRDATAS2,
PREADYS0,
PREADYS1,
PREADYS2,
PSEL,
PSLVERRS0,
PSLVERRS1,
PSLVERRS2,
PWDATA,
PWRITE,
// Outputs
PADDRS,
PENABLES,
PRDATA,
PREADY,
PSELS0,
PSELS1,
PSELS2,
PSLVERR,
PWDATAS,
PWRITES
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [31:0] PADDR;
input PENABLE;
input [31:0] PRDATAS0;
input [31:0] PRDATAS1;
input [31:0] PRDATAS2;
input PREADYS0;
input PREADYS1;
input PREADYS2;
input PSEL;
input PSLVERRS0;
input PSLVERRS1;
input PSLVERRS2;
input [31:0] PWDATA;
input PWRITE;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] PADDRS;
output PENABLES;
output [31:0] PRDATA;
output PREADY;
output PSELS0;
output PSELS1;
output PSELS2;
output PSLVERR;
output [31:0] PWDATAS;
output PWRITES;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [31:0] PADDR;
wire PENABLE;
wire [31:0] APB3mmaster_PRDATA;
wire APB3mmaster_PREADY;
wire PSEL;
wire APB3mmaster_PSLVERR;
wire [31:0] PWDATA;
wire PWRITE;
wire [31:0] APBmslave0_PADDR;
wire APBmslave0_PENABLE;
wire [31:0] PRDATAS0;
wire PREADYS0;
wire APBmslave0_PSELx;
wire PSLVERRS0;
wire [31:0] APBmslave0_PWDATA;
wire APBmslave0_PWRITE;
wire [31:0] PRDATAS1;
wire PREADYS1;
wire APBmslave1_PSELx;
wire PSLVERRS1;
wire [31:0] PRDATAS2;
wire PREADYS2;
wire APBmslave2_PSELx;
wire PSLVERRS2;
wire [31:0] APB3mmaster_PRDATA_net_0;
wire APB3mmaster_PREADY_net_0;
wire APB3mmaster_PSLVERR_net_0;
wire [31:0] APBmslave0_PADDR_net_0;
wire APBmslave0_PSELx_net_0;
wire APBmslave0_PENABLE_net_0;
wire APBmslave0_PWRITE_net_0;
wire [31:0] APBmslave0_PWDATA_net_0;
wire APBmslave1_PSELx_net_0;
wire APBmslave2_PSELx_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire VCC_net;
wire [31:0] IADDR_const_net_0;
wire [31:0] PRDATAS3_const_net_0;
wire [31:0] PRDATAS4_const_net_0;
wire [31:0] PRDATAS5_const_net_0;
wire [31:0] PRDATAS6_const_net_0;
wire [31:0] PRDATAS7_const_net_0;
wire [31:0] PRDATAS8_const_net_0;
wire [31:0] PRDATAS9_const_net_0;
wire [31:0] PRDATAS10_const_net_0;
wire [31:0] PRDATAS11_const_net_0;
wire [31:0] PRDATAS12_const_net_0;
wire [31:0] PRDATAS13_const_net_0;
wire [31:0] PRDATAS14_const_net_0;
wire [31:0] PRDATAS15_const_net_0;
wire [31:0] PRDATAS16_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
assign IADDR_const_net_0 = 32'h00000000;
assign PRDATAS3_const_net_0 = 32'h00000000;
assign PRDATAS4_const_net_0 = 32'h00000000;
assign PRDATAS5_const_net_0 = 32'h00000000;
assign PRDATAS6_const_net_0 = 32'h00000000;
assign PRDATAS7_const_net_0 = 32'h00000000;
assign PRDATAS8_const_net_0 = 32'h00000000;
assign PRDATAS9_const_net_0 = 32'h00000000;
assign PRDATAS10_const_net_0 = 32'h00000000;
assign PRDATAS11_const_net_0 = 32'h00000000;
assign PRDATAS12_const_net_0 = 32'h00000000;
assign PRDATAS13_const_net_0 = 32'h00000000;
assign PRDATAS14_const_net_0 = 32'h00000000;
assign PRDATAS15_const_net_0 = 32'h00000000;
assign PRDATAS16_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign APB3mmaster_PRDATA_net_0 = APB3mmaster_PRDATA;
assign PRDATA[31:0] = APB3mmaster_PRDATA_net_0;
assign APB3mmaster_PREADY_net_0 = APB3mmaster_PREADY;
assign PREADY = APB3mmaster_PREADY_net_0;
assign APB3mmaster_PSLVERR_net_0 = APB3mmaster_PSLVERR;
assign PSLVERR = APB3mmaster_PSLVERR_net_0;
assign APBmslave0_PADDR_net_0 = APBmslave0_PADDR;
assign PADDRS[31:0] = APBmslave0_PADDR_net_0;
assign APBmslave0_PSELx_net_0 = APBmslave0_PSELx;
assign PSELS0 = APBmslave0_PSELx_net_0;
assign APBmslave0_PENABLE_net_0 = APBmslave0_PENABLE;
assign PENABLES = APBmslave0_PENABLE_net_0;
assign APBmslave0_PWRITE_net_0 = APBmslave0_PWRITE;
assign PWRITES = APBmslave0_PWRITE_net_0;
assign APBmslave0_PWDATA_net_0 = APBmslave0_PWDATA;
assign PWDATAS[31:0] = APBmslave0_PWDATA_net_0;
assign APBmslave1_PSELx_net_0 = APBmslave1_PSELx;
assign PSELS1 = APBmslave1_PSELx_net_0;
assign APBmslave2_PSELx_net_0 = APBmslave2_PSELx;
assign PSELS2 = APBmslave2_PSELx_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CoreAPB3 - Actel:DirectCore:CoreAPB3:4.2.100
CoreAPB3 #(
.APB_DWIDTH ( 32 ),
.APBSLOT0ENABLE ( 1 ),
.APBSLOT1ENABLE ( 1 ),
.APBSLOT2ENABLE ( 1 ),
.APBSLOT3ENABLE ( 0 ),
.APBSLOT4ENABLE ( 0 ),
.APBSLOT5ENABLE ( 0 ),
.APBSLOT6ENABLE ( 0 ),
.APBSLOT7ENABLE ( 0 ),
.APBSLOT8ENABLE ( 0 ),
.APBSLOT9ENABLE ( 0 ),
.APBSLOT10ENABLE ( 0 ),
.APBSLOT11ENABLE ( 0 ),
.APBSLOT12ENABLE ( 0 ),
.APBSLOT13ENABLE ( 0 ),
.APBSLOT14ENABLE ( 0 ),
.APBSLOT15ENABLE ( 0 ),
.FAMILY ( 19 ),
.IADDR_OPTION ( 0 ),
.MADDR_BITS ( 16 ),
.SC_0 ( 0 ),
.SC_1 ( 0 ),
.SC_2 ( 0 ),
.SC_3 ( 0 ),
.SC_4 ( 0 ),
.SC_5 ( 0 ),
.SC_6 ( 0 ),
.SC_7 ( 0 ),
.SC_8 ( 0 ),
.SC_9 ( 0 ),
.SC_10 ( 0 ),
.SC_11 ( 0 ),
.SC_12 ( 0 ),
.SC_13 ( 0 ),
.SC_14 ( 0 ),
.SC_15 ( 0 ),
.UPR_NIBBLE_POSN ( 6 ) )
CoreAPB3_0_0(
// Inputs
.PRESETN ( GND_net ), // tied to 1'b0 from definition
.PCLK ( GND_net ), // tied to 1'b0 from definition
.PADDR ( PADDR ),
.PWRITE ( PWRITE ),
.PENABLE ( PENABLE ),
.PWDATA ( PWDATA ),
.PSEL ( PSEL ),
.PRDATAS0 ( PRDATAS0 ),
.PREADYS0 ( PREADYS0 ),
.PSLVERRS0 ( PSLVERRS0 ),
.PRDATAS1 ( PRDATAS1 ),
.PREADYS1 ( PREADYS1 ),
.PSLVERRS1 ( PSLVERRS1 ),
.PRDATAS2 ( PRDATAS2 ),
.PREADYS2 ( PREADYS2 ),
.PSLVERRS2 ( PSLVERRS2 ),
.PRDATAS3 ( PRDATAS3_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS3 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS3 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS4 ( PRDATAS4_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS4 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS4 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS5 ( PRDATAS5_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS5 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS5 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS6 ( PRDATAS6_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS6 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS6 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS7 ( PRDATAS7_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS7 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS7 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS8 ( PRDATAS8_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS8 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS8 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS9 ( PRDATAS9_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS9 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS9 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS10 ( PRDATAS10_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS10 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS10 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS11 ( PRDATAS11_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS11 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS11 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS12 ( PRDATAS12_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS12 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS12 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS13 ( PRDATAS13_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS13 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS13 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS14 ( PRDATAS14_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS14 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS14 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS15 ( PRDATAS15_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS15 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS15 ( GND_net ), // tied to 1'b0 from definition
.PRDATAS16 ( PRDATAS16_const_net_0 ), // tied to 32'h00000000 from definition
.PREADYS16 ( VCC_net ), // tied to 1'b1 from definition
.PSLVERRS16 ( GND_net ), // tied to 1'b0 from definition
.IADDR ( IADDR_const_net_0 ), // tied to 32'h00000000 from definition
// Outputs
.PRDATA ( APB3mmaster_PRDATA ),
.PREADY ( APB3mmaster_PREADY ),
.PSLVERR ( APB3mmaster_PSLVERR ),
.PADDRS ( APBmslave0_PADDR ),
.PWRITES ( APBmslave0_PWRITE ),
.PENABLES ( APBmslave0_PENABLE ),
.PWDATAS ( APBmslave0_PWDATA ),
.PSELS0 ( APBmslave0_PSELx ),
.PSELS1 ( APBmslave1_PSELx ),
.PSELS2 ( APBmslave2_PSELx ),
.PSELS3 ( ),
.PSELS4 ( ),
.PSELS5 ( ),
.PSELS6 ( ),
.PSELS7 ( ),
.PSELS8 ( ),
.PSELS9 ( ),
.PSELS10 ( ),
.PSELS11 ( ),
.PSELS12 ( ),
.PSELS13 ( ),
.PSELS14 ( ),
.PSELS15 ( ),
.PSELS16 ( )
);
endmodule

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component/work/CoreAPB3_0/CoreAPB3_0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:03 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : CoreAPB3_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreAPB3_0/CoreAPB3_0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/wave_user.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec_compile.tcl
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec.exe
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/bfmtovec.lin
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/mti/scripts/coreapb3_usertb_master.bfm
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/coreparameters.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_main.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_ahbtoapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apbslaveext.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/amba_bfm/bfm_apbslave.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/test/user/testbench.v

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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:13 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CoreUARTapb_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CoreUARTapb_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -component_name {CoreUARTapb_0} -params {\
"BAUD_VAL_FRCTN:0" \
"BAUD_VAL_FRCTN_EN:false" \
"BAUD_VALUE:1" \
"FIXEDMODE:0" \
"PRG_BIT8:0" \
"PRG_PARITY:0" \
"RX_FIFO:0" \
"RX_LEGACY_MODE:0" \
"TX_FIFO:0" \
"USE_SOFT_FIFO:0" }
# Exporting Component Description of CoreUARTapb_0 to TCL done
*/
// CoreUARTapb_0
module CoreUARTapb_0(
// Inputs
PADDR,
PCLK,
PENABLE,
PRESETN,
PSEL,
PWDATA,
PWRITE,
RX,
// Outputs
FRAMING_ERR,
OVERFLOW,
PARITY_ERR,
PRDATA,
PREADY,
PSLVERR,
RXRDY,
TX,
TXRDY
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [4:0] PADDR;
input PCLK;
input PENABLE;
input PRESETN;
input PSEL;
input [7:0] PWDATA;
input PWRITE;
input RX;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output FRAMING_ERR;
output OVERFLOW;
output PARITY_ERR;
output [7:0] PRDATA;
output PREADY;
output PSLVERR;
output RXRDY;
output TX;
output TXRDY;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [4:0] PADDR;
wire PENABLE;
wire [7:0] APB_bif_PRDATA;
wire APB_bif_PREADY;
wire PSEL;
wire APB_bif_PSLVERR;
wire [7:0] PWDATA;
wire PWRITE;
wire FRAMING_ERR_net_0;
wire OVERFLOW_net_0;
wire PARITY_ERR_net_0;
wire PCLK;
wire PRESETN;
wire RX;
wire RXRDY_net_0;
wire TX_net_0;
wire TXRDY_net_0;
wire TXRDY_net_1;
wire RXRDY_net_1;
wire PARITY_ERR_net_1;
wire OVERFLOW_net_1;
wire TX_net_1;
wire FRAMING_ERR_net_1;
wire [7:0] APB_bif_PRDATA_net_0;
wire APB_bif_PREADY_net_0;
wire APB_bif_PSLVERR_net_0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TXRDY_net_1 = TXRDY_net_0;
assign TXRDY = TXRDY_net_1;
assign RXRDY_net_1 = RXRDY_net_0;
assign RXRDY = RXRDY_net_1;
assign PARITY_ERR_net_1 = PARITY_ERR_net_0;
assign PARITY_ERR = PARITY_ERR_net_1;
assign OVERFLOW_net_1 = OVERFLOW_net_0;
assign OVERFLOW = OVERFLOW_net_1;
assign TX_net_1 = TX_net_0;
assign TX = TX_net_1;
assign FRAMING_ERR_net_1 = FRAMING_ERR_net_0;
assign FRAMING_ERR = FRAMING_ERR_net_1;
assign APB_bif_PRDATA_net_0 = APB_bif_PRDATA;
assign PRDATA[7:0] = APB_bif_PRDATA_net_0;
assign APB_bif_PREADY_net_0 = APB_bif_PREADY;
assign PREADY = APB_bif_PREADY_net_0;
assign APB_bif_PSLVERR_net_0 = APB_bif_PSLVERR;
assign PSLVERR = APB_bif_PSLVERR_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb - Actel:DirectCore:CoreUARTapb:5.7.100
CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb #(
.BAUD_VAL_FRCTN ( 0 ),
.BAUD_VAL_FRCTN_EN ( 0 ),
.BAUD_VALUE ( 1 ),
.FAMILY ( 26 ),
.FIXEDMODE ( 0 ),
.PRG_BIT8 ( 0 ),
.PRG_PARITY ( 0 ),
.RX_FIFO ( 0 ),
.RX_LEGACY_MODE ( 0 ),
.TX_FIFO ( 0 ) )
CoreUARTapb_0_0(
// Inputs
.PCLK ( PCLK ),
.PRESETN ( PRESETN ),
.PADDR ( PADDR ),
.PSEL ( PSEL ),
.PENABLE ( PENABLE ),
.PWRITE ( PWRITE ),
.PWDATA ( PWDATA ),
.RX ( RX ),
// Outputs
.PRDATA ( APB_bif_PRDATA ),
.TXRDY ( TXRDY_net_0 ),
.RXRDY ( RXRDY_net_0 ),
.PARITY_ERR ( PARITY_ERR_net_0 ),
.OVERFLOW ( OVERFLOW_net_0 ),
.TX ( TX_net_0 ),
.PREADY ( APB_bif_PREADY ),
.PSLVERR ( APB_bif_PSLVERR ),
.FRAMING_ERR ( FRAMING_ERR_net_0 )
);
endmodule

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb</name><vendor/><library/><version/><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/><requireUniquify/></vendorExtensions></file><file fileid="1"><name>rtl\vlog\amba_bfm\bfm_ahbl.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="2"><name>rtl\vlog\amba_bfm\bfm_ahblapb.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="3"><name>rtl\vlog\amba_bfm\bfm_ahbslave.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="4"><name>rtl\vlog\amba_bfm\bfm_ahbslaveext.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="5"><name>rtl\vlog\amba_bfm\bfm_ahbtoapb.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="6"><name>rtl\vlog\amba_bfm\bfm_apb.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="7"><name>rtl\vlog\amba_bfm\bfm_apbslave.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="8"><name>rtl\vlog\amba_bfm\bfm_apbslaveext.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="9"><name>rtl\vlog\amba_bfm\bfm_apbtoapb.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="10"><name>rtl\vlog\amba_bfm\bfm_main.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="11"><name>rtl\vlog\test\user\testbench.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="12"><name>mti\scripts\bfmtovec_compile.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file><file fileid="13"><name>mti\scripts\coreuart_usertb_apb_master.bfm</name><userFileType>BFM</userFileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="14"><name>mti\scripts\coreuart_usertb_include.bfm</name><userFileType>BFM</userFileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="15"><name>mti\scripts\wave_vlog_amba.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="16"><name>rtl\vlog\core\Clock_gen.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="17"><name>rtl\vlog\core\Rx_async.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="18"><name>rtl\vlog\core\Tx_async.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="19"><name>rtl\vlog\core\CoreUART.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="20"><name>rtl\vlog\core\CoreUARTapb.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file><file fileid="21"><name>rtl\vlog\core\fifo_256x8_g5.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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//--------------------------------------------------------------------
// Created by Microsemi SmartDesign Mon Apr 13 21:41:13 2026
// Parameters for CoreUARTapb
//--------------------------------------------------------------------
parameter BAUD_VAL_FRCTN = 0;
parameter BAUD_VAL_FRCTN_EN = 0;
parameter BAUD_VALUE = 1;
parameter FAMILY = 26;
parameter FIXEDMODE = 0;
parameter HDL_license = "U";
parameter PRG_BIT8 = 0;
parameter PRG_PARITY = 0;
parameter RX_FIFO = 0;
parameter RX_LEGACY_MODE = 0;
parameter testbench = "User";
parameter TX_FIFO = 0;
parameter USE_SOFT_FIFO = 0;

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component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/bfmtovec_compile.do Normal file
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### script to compile Actel AMBA BFM source file into vector file for simulation
# 12Jan09 Production Release Version 3.0
quietly set linux_exe "./bfmtovec.lin"
quietly set windows_exe "./bfmtovec.exe"
quietly set bfm_src_in "./coreuart_usertb_apb_master.bfm"
quietly set bfm_vec_out "./coreuart_usertb_apb_master.vec"
# check OS type and use appropriate executable
if {$tcl_platform(os) == "Linux"} {
echo "--- Using Linux Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe "./bfmtovec.lin"
if {![file executable $bfmtovec_exe]} {
quietly set cmds "chmod +x $bfmtovec_exe"
eval $cmds
}
} else {
echo "--- Using Windows Actel DirectCore AMBA BFM compiler"
quietly set bfmtovec_exe "./bfmtovec.exe"
}
# compile BFM source files into vector outputs
echo "--- Compiling Actel DirectCore AMBA BFM source files ..."
quietly set cmd1 "exec $bfmtovec_exe -in $bfm_src_in -out $bfm_vec_out"
eval $cmd1
# echo "--- Done Compiling Actel DirectCore AMBA BFM source files."

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component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/coreuart_usertb_apb_master.bfm Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: Verification testbench APB master BFM script for CoreAI
//
// Revision Information:
// Date Description
//
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4"
// 2. Most of the behavior is driven from the BFM script for the APB master.
// Consult the Actel AMBA BFM documentation for more information.
// 3. All procedures, variables, and constants used by the 'main' procedure
// are declared in the include file "coreai_veriftb_include.bfm"
//
// History: 11/05/08 - TFB created
//
// *********************************************************************
// include constants, and miscellaneous procedures used in this main file
include "coreuart_usertb_include.bfm"
procedure main
header "User Testbench for CoreUART: BFM APB Master Test Harness"
print "(c) Copyright 2009 Actel Corporation. All rights reserved."
print "AS: 03/23/09"
call pr_underscores
debug 1 // only text strings printed
//timeout 2000000 // timeout in cycles, in case BFM stalls
//wait 1
call init_parameter_vars
wait 1
// framing error test
ifnot FIXEDMODE
call set_config 0 0 0 5 1
call set_config 1 0 0 5 1
call framing_err_test
endif
// overflow test
call overflow_test
ifnot FIXEDMODE
// TEST FOR ALL CONFIGURATIONS (matching b/w DUTs)
// configure UART1 and 2 to the same config
print "FIXEDMODE=0: testing for all configurations"
call pr_underscores
loop x 0 1 1 // parity_en
loop y 0 1 1 // parity
loop z 0 1 1 // bit_num
call set_config 0 x y 1 z
call set_config 1 x y 1 z
call data_stream
call set_config 0 x y 3 z
call set_config 1 x y 3 z
call data_stream
endloop
endloop
endloop
endif
if FIXEDMODE
// TEST FOR ONE CONFIGURATION (FIXED)
print "FIXEDMODE=1: testing for current configuration only (as follows)"
print "BAUD_VALUE:%0d" BAUD_VALUE
print "PRG_BIT8:%0d" PRG_BIT8
print "PRG_PARITY:%0d" PRG_PARITY
call data_stream
endif
// parity error test
ifnot FIXEDMODE
call parity_err_test
endif
call pr_underscores
// enable
print "End of CoreUART User testbench."
return

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component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/coreuart_usertb_include.bfm Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation All rights reserved
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING
//
// Description: User testbench include file for CoreAI - contains
// various constants procedures etc used by main BFM script
//
// Revision Information:
// Date Description
// 19Jan09 Production Release Version 3 0
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1 best viewed with tabstops set to "4"
//
// History:
//
// *********************************************************************
// PSEL[0] HSEL[0] used to access the AHB-to-APB bridge in the BFM_APB mod
// (for UART Transmitter)
memmap BASE1 0x10000000
// PSEL[1] HSEL[1] used to access the AHB-to-APB bridge in the BFM_APB mod
// (for UART Receiver)
memmap BASE2 0x11000000
// variables to store passed parameter values
int FAMILY
int TX_FIFO
int RX_FIFO
int FIXEDMODE
int BAUD_VALUE
int PRG_BIT8
int PRG_PARITY
int RX_LEGACY_MODE
int USE_SOFT_FIFO
// derived parameters
int FIFO_DEPTH
int TIMEOUT_VAL
int BYTE_WAIT_TIME
int BYTE_WAIT_256
int BYTE_WAIT_16
int BYTE_WAIT_8
// data variables
int rdata[256]
// other variables
int PRINT_VARS
int BITVAR
int data
// temp vars
int i j k l w x y z tc rc
int cmp
// CoreGPIO internal addresses
constant TXDATA 0x00
constant RXDATA 0x04
constant CTRL1 0x08
constant CTRL2 0x0C
constant STA 0x10
constant CRTL3 0x14
//BFM GPIN bit defs
constant RXRDY1 0
constant TXRDY1 1
constant PARITY_ERR1 2
constant OVERFLOW1 3
constant RXRDY2 4
constant TXRDY2 5
constant PARITY_ERR2 6
constant OVERFLOW2 7
//---------------------------------------------------------------------------
// procedures
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
// initialize local variables from the ARGVALUE* BFM parameters passed
// down from the testbench HDL
//---------------------------------------------------------------------------
procedure init_parameter_vars
set FAMILY $ARGVALUE0
set TX_FIFO $ARGVALUE1
set RX_FIFO $ARGVALUE2
set FIXEDMODE $ARGVALUE3
set BAUD_VALUE $ARGVALUE4
set PRG_BIT8 $ARGVALUE5
set PRG_PARITY $ARGVALUE6
set RX_LEGACY_MODE $ARGVALUE7
set USE_SOFT_FIFO $ARGVALUE8
// derived parameters
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 255
endif
// check for SX or RTSX or RTAXS
// and set FIFO depth accordingly
// (these 3 have soft FIFOs)
set cmp FAMILY == 8
if cmp
set FIFO_DEPTH 15
endif
set cmp FAMILY == 9
if cmp
set FIFO_DEPTH 15
endif
// set cmp FAMILY == 12
// if cmp
// set FIFO_DEPTH 15
// endif
//check for SmartFusion2 or Igloo2 or RTG4
//and set FIFO depth accordingly
set cmp FAMILY == 19
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 127
endif
endif
set cmp FAMILY == 24
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 127
endif
endif
set cmp FAMILY == 25
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 127
endif
endif
//check for PolarFire
//and set FIFO depth accordingly
set cmp FAMILY == 26
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 255
endif
endif
//check for ProASICplus
//and set FIFO depth accordingly
set cmp FAMILY == 14
if cmp
if USE_SOFT_FIFO
set FIFO_DEPTH 15
else
set FIFO_DEPTH 254
endif
endif
set BYTE_WAIT_TIME BAUD_VALUE * 250
set BYTE_WAIT_256 BYTE_WAIT_TIME * 256
set BYTE_WAIT_16 BYTE_WAIT_TIME * 16
set BYTE_WAIT_8 BYTE_WAIT_TIME * 8
set TIMEOUT_VAL BYTE_WAIT_256 + 1
timeout TIMEOUT_VAL
set PRINT_VARS 1
if PRINT_VARS
header " Begin printing variables from APB Master BFM Script ..."
print "FAMILY:%0d" FAMILY
print "TX_FIFO:%0d" TX_FIFO
print "RX_FIFO:%0d" RX_FIFO
print "FIXEDMODE:%0d" FIXEDMODE
print "BAUD_VALUE:%0d" BAUD_VALUE
print "PRG_BIT8:%0d" PRG_BIT8
print "PRG_PARITY:%0d" PRG_PARITY
print "RX_LEGACY_MODE:%0d" RX_LEGACY_MODE
print "FIFO_DEPTH:%0d" FIFO_DEPTH
header " Done printing variables from APB Master BFM Script."
header " "
endif
return
//---------------------------------------------------------------------------
// get bit number (bnum) from given wval integer
//---------------------------------------------------------------------------
procedure get_bit wval bnum
int d01
set d01 wval >> bnum
// set global BITVAR variable
set BITVAR d01 & 0x1
return
//---------------------------------------------------------------------------
// print line of underscores
//---------------------------------------------------------------------------
procedure pr_underscores
print "____________________________________________________________________"
print " "
return
//---------------------------------------------------------------------------
// test procedures
//---------------------------------------------------------------------------
procedure set_config dn pe p bv bn
int dut_num // 1 = RX(DUT2), 0 = TX(DUT1)
int par_en // 1 = enabled, 0 = disabled
int par // 1 = odd, 0 = even
int baud_val // 13-bit baud-value (split into 2 config registers)
int bit_num // 1 = 8 bits, 0 = 7 bits
// temp vars
int baud1
int baud2
int ctrl2_val
set dut_num dn
set par_en pe
set par p
set baud_val bv
set bit_num bn
print "Configuring UART:%0d with par_en:%0d parity:%0d baud_val:%0d bit_num:%0d" dut_num par_en par baud_val bit_num
// Set config regsiter data
set baud1 baud_val << 8 >> 8 // CONFIG REG 1
set baud2 baud_val >> 8 // CONFIG REG 2
set par par << 2
set par_en par_en << 1
set baud2 baud2 << 3
set ctrl2_val par
set ctrl2_val ctrl2_val | par_en
set ctrl2_val ctrl2_val | baud2
set ctrl2_val ctrl2_val | bit_num
// set base address based on DUT selected
if dut_num == 1
// write control registers
//print "Writing %0d to CTRL1 and %0d to CTRL2" baud1 ctrl2_val
write b BASE2 CTRL1 baud1
write b BASE2 CTRL2 ctrl2_val
else
// write control registers
//print "Writing %0d to CTRL1 and %0d to CTRL2" baud1 ctrl2_val
write b BASE1 CTRL1 baud1
write b BASE1 CTRL2 ctrl2_val
endif
return
procedure data_stream
call pr_underscores
print "Testing Continuous Data Stream UART1 to UART2"
set rc 0
loop tc 0 FIFO_DEPTH 1
//print "Sending byte %0d" tc
iowaitbit TXRDY1 1 // wait until TXRDY
set data tc & 0x7F // mask byte
//print "Got TXRDY %0d times" tc
write b BASE1 TXDATA data // transmit a byte
ifnot TX_FIFO
iowaitbit TXRDY1 0 // wait until TXRDY deasserted
endif
ifnot RX_FIFO // must read immediately
iowaitbit RXRDY2 1 // wait until RXRDY
//print "Receiving byte %0d" tc
readstore b BASE2 RXDATA rdata[rc] // read received byte
set rc rc + 1
endif
endloop
if RX_FIFO // test out FIFO operation
wait BYTE_WAIT_16 // wait for data to be received
loop rc 0 FIFO_DEPTH 1
iowaitbit RXRDY2 1 // wait until RXRDY
readstore b BASE2 RXDATA rdata[rc] // read received byte
endloop
endif
// check data
loop i 0 FIFO_DEPTH 1
set j i & 0x7F
if rdata[i] != j
call pr_underscores
print "TEST FAILED"
print "Expected %0d, got %0d" i rdata[i]
setfail
endif
endloop
print "Continuous data stream successfull"
call pr_underscores
return
procedure framing_err_test
call pr_underscores
print "Performing framing error test by setting input to DUT2 low"
// set the input to UART2 RX line low
// (no stop bit)
iowrite 0x01
wait BYTE_WAIT_16
ifnot RX_FIFO
// back to normal:
iowrite 0x00
wait BYTE_WAIT_16
readmask b BASE2 STA 0x10 0x10 // check for framing_err bit set
read b BASE2 RXDATA // doing a read should clear this
readmask b BASE2 STA 0x00 0x10 // check for framing_err bit cleared
else
readmask b BASE2 STA 0x10 0x10 // check for framing_err bit set
iowrite 0x00
// transmit a byte to clear the framing error
iowaitbit TXRDY1 1 // wait until TXRDY
write b BASE1 TXDATA 0xAA
wait BYTE_WAIT_16
readmask b BASE2 STA 0x00 0x10 // check for framing_err bit cleared
//loop i 0 FIFO_DEPTH 1 // probably caused an overflow,
readstore b BASE2 STA x // read status
set x x & 0x02
set cmp x == 2
while cmp
iowaitbit RXRDY2 1 // wait until RXRDY
read b BASE2 RXDATA // need to clear
iowaitbit RXRDY2 0 // wait until RXRDY clear
wait 4
readstore b BASE2 STA x // read status
set x x & 0x02
set cmp x == 2
endwhile
endif
wait 10
print "Framing error test completed"
call pr_underscores
return
procedure overflow_test
call pr_underscores
print "Overflow test"
if RX_FIFO
loop tc 0 FIFO_DEPTH 1
iowaitbit TXRDY1 1 // wait until TXRDY
set data tc & 0x7F // mask byte
write b BASE1 TXDATA data // transmit a byte
ifnot TX_FIFO
iowaitbit TXRDY1 0 // wait until TXRDY deasserted
endif
endloop
iowaitbit TXRDY1 1 // wait until TXRDY
wait BYTE_WAIT_256
iotstbit OVERFLOW2 0 // check that overflow not set
write b BASE1 TXDATA 0xab // transmit a byte (0xab)
wait BYTE_WAIT_256 // worst case: 3 blocks (BAUD_VAL=1)
wait BYTE_WAIT_256
wait BYTE_WAIT_256
iotstbit OVERFLOW2 1 // check that overflow set
// read RX data
loop rc 0 FIFO_DEPTH 1
if rc == 1
iotstbit OVERFLOW2 0 // check
endif
iowaitbit RXRDY2 1 // wait until RXRDY
readstore b BASE2 RXDATA rdata[rc] // read received byte
endloop
// check data
loop i 0 FIFO_DEPTH 1
set j i & 0x7F
if rdata[i] != j
call pr_underscores
print "TEST FAILED"
print "Expected %0d, got %0d" i rdata[i]
setfail
endif
endloop
endif
call pr_underscores
return
procedure parity_err_test
call pr_underscores
print "Performing Parity Error Test"
call set_config 0 1 0 1 1
call set_config 1 1 1 1 1
// -- transmit a byte --
iotstbit PARITY_ERR2 0 // check that parity error is 0
iowaitbit txrdy1 1 // wait until txrdy
write b base1 txdata 0xab // transmit a byte (0xab)
iowaitbit PARITY_ERR2 1 // check that parity error asserted
if RX_FIFO
iowaitbit PARITY_ERR2 0 // check that parity error deasserted
call set_config 0 1 1 1 1 // match parity
iowaitbit txrdy1 1 // wait until txrdy
write b base1 txdata 0xac // transmit a new byte (0xab)
iowaitbit RXRDY2 1 // read byte
iotstbit PARITY_ERR2 0 // check that parity error NOT asserted
readstore b BASE2 RXDATA x // store
if x != 0xac
call pr_underscores
print "TEST FAILED"
print "Expected 0xac, got %0h" x
setfail
endif
else
// NO RX_FIFO
// clear parity error
read b BASE2 RXDATA // read should clear
wait 4
iotstbit PARITY_ERR2 0 // the parity error
call set_config 0 1 1 1 1 // match parity
iowaitbit txrdy1 1 // wait until txrdy
write b base1 txdata 0xac // transmit a new byte (0xab)
iowaitbit RXRDY2 1 // read byte
iotstbit PARITY_ERR2 0 // check that parity error NOT asserted
readstore b BASE2 RXDATA x // store
if x != 0xac
call pr_underscores
print "TEST FAILED"
print "Expected 0xac, got %0h" x
setfail
endif
endif
print "Parity Error Test Complete"
call pr_underscores
return

46
component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/wave_vlog_amba.do Normal file
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider APB
add wave -noupdate -format Logic /testbench/SYSCLK_apb
add wave -noupdate -format Logic /testbench/PCLK
add wave -noupdate -format Literal /testbench/PADDR
add wave -noupdate -format Logic /testbench/PENABLE
add wave -noupdate -format Literal /testbench/PRDATA
add wave -noupdate -format Literal /testbench/PRDATA1
add wave -noupdate -format Literal /testbench/PRDATA2
add wave -noupdate -format Logic /testbench/PRESETN
add wave -noupdate -format Logic /testbench/PSEL1
add wave -noupdate -format Logic /testbench/PSEL2
add wave -noupdate -format Literal /testbench/PWDATA
add wave -noupdate -format Logic /testbench/PWRITE
add wave -noupdate -divider {UART1 (TX)}
add wave -noupdate -format Logic /testbench/DUT1/TXRDY
add wave -noupdate -format Logic /testbench/DUT1/TX
add wave -noupdate -format Logic /testbench/DUT1/RXRDY
add wave -noupdate -format Logic /testbench/DUT1/RX
add wave -noupdate -format Logic /testbench/DUT1/PARITY_ERR
add wave -noupdate -format Logic /testbench/DUT1/OVERFLOW
add wave -noupdate -divider UART2(RX)
add wave -noupdate -format Logic /testbench/DUT2/TXRDY
add wave -noupdate -format Logic /testbench/DUT2/TX
add wave -noupdate -format Logic /testbench/DUT2/RXRDY
add wave -noupdate -format Logic /testbench/DUT2/RX
add wave -noupdate -format Logic /testbench/DUT2/PARITY_ERR
add wave -noupdate -format Logic /testbench/DUT2/OVERFLOW
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {553305200 ps} 0}
configure wave -namecolwidth 365
configure wave -valuecolwidth 120
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {543429100 ps} {546721100 ps}

1279
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbl.v Normal file
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component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahblapb.v Normal file
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399
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbslave.v Normal file
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// Actel Corporation Proprietary and Confidential
// Copyright 2007 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 6419 $
// SVN $Date: 2009-02-04 04:34:22 -0800 (Wed, 04 Feb 2009) $
`timescale 1ns/100ps
module
CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBSLAVE
(
HCLK
,
HRESETN
,
HSEL
,
HWRITE
,
HADDR
,
HWDATA
,
HRDATA
,
HREADYIN
,
HREADYOUT
,
HTRANS
,
HSIZE
,
HBURST
,
HMASTLOCK
,
HPROT
,
HRESP
)
;
parameter
AWIDTH
=
10
;
parameter
DEPTH
=
256
;
parameter
INITFILE
=
" "
;
parameter
ID
=
0
;
parameter
ENFUNC
=
0
;
parameter
TPD
=
1
;
parameter
DEBUG
=
-
1
;
localparam
ENFIFO
=
0
;
localparam
EXT_SIZE
=
2
;
input
HCLK
;
input
HRESETN
;
input
HSEL
;
input
HWRITE
;
input
[
AWIDTH
-
1
:
0
]
HADDR
;
input
[
31
:
0
]
HWDATA
;
output
[
31
:
0
]
HRDATA
;
input
HREADYIN
;
output
HREADYOUT
;
input
[
1
:
0
]
HTRANS
;
input
[
2
:
0
]
HSIZE
;
input
[
2
:
0
]
HBURST
;
input
HMASTLOCK
;
input
[
3
:
0
]
HPROT
;
output
HRESP
;
wire
EXT_EN
;
wire
EXT_WR
;
wire
EXT_RD
;
wire
[
AWIDTH
-
1
:
0
]
EXT_ADDR
;
wire
[
31
:
0
]
EXT_DATA
;
assign
EXT_EN
=
1
'b
0
;
assign
EXT_WR
=
1
'b
0
;
assign
EXT_RD
=
1
'b
0
;
assign
EXT_ADDR
=
0
;
assign
EXT_DATA
=
{
32
{
1
'b
z
}
}
;
CoreUARTapb_0_CoreUARTapb_0_0_BFM_AHBSLAVEEXT
#
(
.AWIDTH
(
AWIDTH
)
,
.DEPTH
(
DEPTH
)
,
.EXT_SIZE
(
EXT_SIZE
)
,
.INITFILE
(
INITFILE
)
,
.ID
(
ID
)
,
.ENFUNC
(
ENFUNC
)
,
.ENFIFO
(
ENFIFO
)
,
.TPD
(
TPD
)
,
.DEBUG
(
DEBUG
)
)
BFMA1OI1II
(
.HCLK
(
HCLK
)
,
.HRESETN
(
HRESETN
)
,
.HSEL
(
HSEL
)
,
.HWRITE
(
HWRITE
)
,
.HADDR
(
HADDR
)
,
.HWDATA
(
HWDATA
)
,
.HRDATA
(
HRDATA
)
,
.HREADYIN
(
HREADYIN
)
,
.HREADYOUT
(
HREADYOUT
)
,
.HTRANS
(
HTRANS
)
,
.HSIZE
(
HSIZE
)
,
.HBURST
(
HBURST
)
,
.HMASTLOCK
(
HMASTLOCK
)
,
.HPROT
(
HPROT
)
,
.HRESP
(
HRESP
)
,
.TXREADY
(
BFMA1II1II
)
,
.RXREADY
(
BFMA1II1II
)
,
.EXT_EN
(
EXT_EN
)
,
.EXT_WR
(
EXT_WR
)
,
.EXT_RD
(
EXT_RD
)
,
.EXT_ADDR
(
EXT_ADDR
)
,
.EXT_DATA
(
EXT_DATA
)
)
;
endmodule

8337
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbslaveext.v Normal file
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816
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbtoapb.v Normal file
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`timescale 1ns/100ps
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 6419 $
// SVN $Date: 2009-02-04 04:34:22 -0800 (Wed, 04 Feb 2009) $
module
CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII
(
HCLK
,
HRESETN
,
HSEL
,
HWRITE
,
HADDR
,
HWDATA
,
HRDATA
,
HREADYIN
,
HREADYOUT
,
HTRANS
,
HSIZE
,
HBURST
,
HMASTLOCK
,
HPROT
,
HRESP
,
PSEL
,
PADDR
,
PWRITE
,
PENABLE
,
PWDATA
,
PRDATA
,
PREADY
,
PSLVERR
)
;
parameter
TPD
=
1
;
input
HCLK
;
input
HRESETN
;
input
HSEL
;
input
HWRITE
;
input
[
31
:
0
]
HADDR
;
input
[
31
:
0
]
HWDATA
;
output
[
31
:
0
]
HRDATA
;
wire
[
31
:
0
]
HRDATA
;
input
HREADYIN
;
output
HREADYOUT
;
wire
HREADYOUT
;
input
[
1
:
0
]
HTRANS
;
input
[
2
:
0
]
HSIZE
;
input
[
2
:
0
]
HBURST
;
input
HMASTLOCK
;
input
[
3
:
0
]
HPROT
;
output
HRESP
;
wire
HRESP
;
output
[
15
:
0
]
PSEL
;
wire
[
15
:
0
]
PSEL
;
output
[
31
:
0
]
PADDR
;
wire
[
31
:
0
]
PADDR
;
output
PWRITE
;
wire
PWRITE
;
output
PENABLE
;
wire
PENABLE
;
output
[
31
:
0
]
PWDATA
;
wire
[
31
:
0
]
PWDATA
;
input
[
31
:
0
]
PRDATA
;
input
PREADY
;
input
PSLVERR
;
parameter
[
1
:
0
]
BFMA1OOIII
=
0
;
parameter
[
1
:
0
]
BFMA1IOIII
=
1
;
parameter
[
1
:
0
]
BFMA1lOIII
=
2
;
parameter
[
1
:
0
]
BFMA1OIIII
=
3
;
reg
[
1
:
0
]
BFMA1IIIII
;
reg
BFMA1lIIII
;
reg
BFMA1OlIII
;
reg
[
15
:
0
]
BFMA1IlIII
;
reg
[
31
:
0
]
BFMA1llIII
;
reg
BFMA1O0III
;
reg
BFMA1I0III
;
reg
[
31
:
0
]
BFMA1l0III
;
wire
[
31
:
0
]
BFMA1O1III
;
reg
BFMA1I1III
;
reg
BFMA1l1III
;
always
@
(
posedge
HCLK
or
negedge
HRESETN
)
begin
if
(
HRESETN
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1llIII
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1O0III
<=
1
'b
0
;
BFMA1I0III
<=
1
'b
0
;
BFMA1OlIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
end
else
begin
BFMA1OlIII
<=
1
'b
0
;
BFMA1lIIII
<=
1
'b
0
;
BFMA1I1III
<=
1
'b
0
;
case
(
BFMA1IIIII
)
BFMA1OOIII
:
begin
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1l0III
<=
HWDATA
;
BFMA1I0III
<=
1
'b
0
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
else
begin
BFMA1lIIII
<=
1
'b
1
;
end
end
BFMA1IOIII
:
begin
BFMA1I0III
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1lOIII
;
end
BFMA1lOIII
:
begin
if
(
PREADY
==
1
'b
1
)
begin
BFMA1I0III
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
if
(
PSLVERR
==
1
'b
0
)
begin
BFMA1IIIII
<=
BFMA1OOIII
;
if
(
HSEL
==
1
'b
1
&
HREADYIN
==
1
'b
1
&
(
HTRANS
[
1
]
)
==
1
'b
1
)
begin
BFMA1IIIII
<=
BFMA1IOIII
;
BFMA1llIII
<=
HADDR
;
BFMA1O0III
<=
HWRITE
;
BFMA1I1III
<=
HWRITE
;
BFMA1l1III
<=
1
'b
1
;
end
end
else
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OIIII
;
end
end
end
BFMA1OIIII
:
begin
BFMA1OlIII
<=
1
'b
1
;
BFMA1lIIII
<=
1
'b
1
;
BFMA1IIIII
<=
BFMA1OOIII
;
end
endcase
if
(
BFMA1I1III
==
1
'b
1
)
begin
BFMA1l0III
<=
HWDATA
;
end
end
end
always
@
(
BFMA1llIII
or
BFMA1l1III
)
begin
BFMA1IlIII
<=
{
16
{
1
'b
0
}
}
;
if
(
BFMA1l1III
==
1
'b
1
)
begin
begin
:
BFMA1IO10
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1IlIII
[
BFMA1I0I0
]
<=
(
BFMA1llIII
[
27
:
24
]
==
BFMA1I0I0
)
;
end
end
end
end
assign
BFMA1O1III
=
(
BFMA1I1III
==
1
'b
1
)
?
HWDATA
:
BFMA1l0III
;
assign
#
TPD
HRDATA
=
PRDATA
;
assign
#
TPD
HREADYOUT
=
BFMA1lIIII
|
(
PREADY
&
BFMA1l1III
&
BFMA1I0III
&
~
PSLVERR
)
;
assign
#
TPD
HRESP
=
BFMA1OlIII
;
assign
#
TPD
PSEL
=
BFMA1IlIII
;
assign
#
TPD
PADDR
=
BFMA1llIII
;
assign
#
TPD
PWRITE
=
BFMA1O0III
;
assign
#
TPD
PENABLE
=
BFMA1I0III
;
assign
#
TPD
PWDATA
=
BFMA1O1III
;
endmodule

1434
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apb.v Normal file
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4140
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apbslave.v Normal file
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File diff suppressed because it is too large Load Diff

6140
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apbslaveext.v Normal file
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File diff suppressed because it is too large Load Diff

788
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apbtoapb.v Normal file
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@@ -0,0 +1,788 @@
`timescale 1ns/100ps
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
// Revision Information:
// SVN Revision Information:
// SVN $Revision: 6419 $
// SVN $Date: 2009-02-04 04:34:22 -0800 (Wed, 04 Feb 2009) $
module
CoreUARTapb_0_CoreUARTapb_0_0_BFM_APB2APB
(
PCLK_PM
,
PRESETN_PM
,
PADDR_PM
,
PWRITE_PM
,
PENABLE_PM
,
PWDATA_PM
,
PRDATA_PM
,
PREADY_PM
,
PSLVERR_PM
,
PCLK_SC
,
PSEL_SC
,
PADDR_SC
,
PWRITE_SC
,
PENABLE_SC
,
PWDATA_SC
,
PRDATA_SC
,
PREADY_SC
,
PSLVERR_SC
)
;
parameter
[
9
:
0
]
TPD
=
1
;
localparam
BFMA1Il1
=
TPD
*
1
;
input
PCLK_PM
;
input
PRESETN_PM
;
input
[
31
:
0
]
PADDR_PM
;
input
PWRITE_PM
;
input
PENABLE_PM
;
input
[
31
:
0
]
PWDATA_PM
;
output
[
31
:
0
]
PRDATA_PM
;
reg
[
31
:
0
]
PRDATA_PM
;
output
PREADY_PM
;
reg
PREADY_PM
;
output
PSLVERR_PM
;
reg
PSLVERR_PM
;
input
PCLK_SC
;
output
[
15
:
0
]
PSEL_SC
;
wire
[
15
:
0
]
#
BFMA1Il1
PSEL_SC
;
output
[
31
:
0
]
PADDR_SC
;
wire
[
31
:
0
]
#
BFMA1Il1
PADDR_SC
;
output
PWRITE_SC
;
wire
#
BFMA1Il1
PWRITE_SC
;
output
PENABLE_SC
;
wire
#
BFMA1Il1
PENABLE_SC
;
output
[
31
:
0
]
PWDATA_SC
;
wire
[
31
:
0
]
#
BFMA1Il1
PWDATA_SC
;
input
[
31
:
0
]
PRDATA_SC
;
input
PREADY_SC
;
input
PSLVERR_SC
;
parameter
[
0
:
0
]
BFMA1OOlII
=
0
;
parameter
[
0
:
0
]
BFMA1IOlII
=
1
;
reg
[
0
:
0
]
BFMA1lOlII
;
parameter
[
1
:
0
]
BFMA1OOIII
=
0
;
parameter
[
1
:
0
]
BFMA1OIlII
=
1
;
parameter
[
1
:
0
]
BFMA1IOIII
=
2
;
reg
[
1
:
0
]
BFMA1IIlII
;
reg
[
15
:
0
]
BFMA1IlIII
;
reg
[
31
:
0
]
BFMA1llIII
;
reg
BFMA1O0III
;
reg
BFMA1I0III
;
reg
[
31
:
0
]
BFMA1l0III
;
reg
BFMA1l1III
;
reg
[
31
:
0
]
BFMA1lIlII
;
reg
BFMA1OllII
;
reg
BFMA1IllII
;
reg
BFMA1lllII
;
reg
BFMA1O0lII
;
always
@
(
posedge
PCLK_PM
or
negedge
PRESETN_PM
)
begin
if
(
PRESETN_PM
==
1
'b
0
)
begin
BFMA1lOlII
<=
BFMA1OOlII
;
BFMA1lllII
<=
1
'b
0
;
PREADY_PM
<=
1
'b
0
;
PSLVERR_PM
<=
1
'b
0
;
PRDATA_PM
<=
{
32
{
1
'b
0
}
}
;
BFMA1IllII
<=
1
'b
0
;
end
else
begin
PREADY_PM
<=
1
'b
0
;
BFMA1IllII
<=
PENABLE_PM
;
case
(
BFMA1lOlII
)
BFMA1OOlII
:
begin
if
(
PENABLE_PM
==
1
'b
1
&
BFMA1IllII
==
1
'b
0
)
begin
BFMA1lllII
<=
1
'b
1
;
BFMA1lOlII
<=
BFMA1IOlII
;
end
end
BFMA1IOlII
:
begin
if
(
BFMA1O0lII
==
1
'b
1
)
begin
BFMA1lOlII
<=
BFMA1OOlII
;
BFMA1lllII
<=
1
'b
0
;
PREADY_PM
<=
1
'b
1
;
PSLVERR_PM
<=
BFMA1OllII
;
PRDATA_PM
<=
BFMA1lIlII
;
end
end
endcase
end
end
always
@
(
posedge
PCLK_SC
or
negedge
BFMA1lllII
)
begin
if
(
BFMA1lllII
==
1
'b
0
)
begin
BFMA1IIlII
<=
BFMA1OOIII
;
BFMA1O0lII
<=
1
'b
0
;
BFMA1lIlII
<=
{
32
{
1
'b
0
}
}
;
BFMA1OllII
<=
1
'b
0
;
BFMA1l1III
<=
1
'b
0
;
BFMA1I0III
<=
1
'b
0
;
BFMA1llIII
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1O0III
<=
1
'b
0
;
end
else
begin
case
(
BFMA1IIlII
)
BFMA1OOIII
:
begin
BFMA1IIlII
<=
BFMA1OIlII
;
BFMA1llIII
<=
PADDR_PM
;
BFMA1l0III
<=
PWDATA_PM
;
BFMA1O0III
<=
PWRITE_PM
;
BFMA1l1III
<=
1
'b
1
;
BFMA1I0III
<=
1
'b
0
;
BFMA1O0lII
<=
1
'b
0
;
end
BFMA1OIlII
:
begin
BFMA1IIlII
<=
BFMA1IOIII
;
BFMA1I0III
<=
1
'b
1
;
end
BFMA1IOIII
:
begin
if
(
PREADY_SC
==
1
'b
1
)
begin
BFMA1O0lII
<=
1
'b
1
;
BFMA1lIlII
<=
PRDATA_SC
;
BFMA1OllII
<=
PSLVERR_SC
;
BFMA1l1III
<=
1
'b
0
;
BFMA1I0III
<=
1
'b
0
;
BFMA1llIII
<=
{
32
{
1
'b
0
}
}
;
BFMA1l0III
<=
{
32
{
1
'b
0
}
}
;
BFMA1O0III
<=
1
'b
0
;
end
end
endcase
end
end
always
@
(
BFMA1llIII
or
BFMA1l1III
)
begin
BFMA1IlIII
<=
{
16
{
1
'b
0
}
}
;
if
(
BFMA1l1III
==
1
'b
1
)
begin
begin
:
BFMA1I0lII
integer
BFMA1I0I0
;
for
(
BFMA1I0I0
=
0
;
BFMA1I0I0
<=
15
;
BFMA1I0I0
=
BFMA1I0I0
+
1
)
begin
BFMA1IlIII
[
BFMA1I0I0
]
<=
(
BFMA1llIII
[
27
:
24
]
==
BFMA1I0I0
)
;
end
end
end
end
assign
PSEL_SC
=
BFMA1IlIII
;
assign
PADDR_SC
=
BFMA1llIII
;
assign
PWRITE_SC
=
BFMA1O0III
;
assign
PENABLE_SC
=
BFMA1I0III
;
assign
PWDATA_SC
=
BFMA1l0III
;
endmodule

20978
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_main.v Normal file
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338
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Clock_gen.v Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreUART/ CoreUARTapb UART core
//
//
// Revision Information:
// Date Description
// Jun09 Revision 4.1
// Aug10 Revision 4.2
//
//
// SVN Revision Information:
// SVN $Revision: 8508 $
// SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
//
// Resolved SARs
// SAR Date Who Description
// 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
// sys clk (not baud clock). See note below.
//
// Notes:
// best viewed with tabstops set to "4"
`define false 1'b 0
`define FALSE 1'b 0
`define true 1'b 1
`define TRUE 1'b 1
`timescale 1 ns / 1 ns // timescale for following modules
module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen (clk,
reset_n,
baud_val,
baud_clock,
xmit_pulse,
BAUD_VAL_FRACTION);
parameter BAUD_VAL_FRCTN_EN = 0;
parameter SYNC_RESET = 0;
input clk; // system clock
input reset_n; // active low async reset
input [12:0] baud_val; // value loaded into cntr
input [2:0] BAUD_VAL_FRACTION; // used to modify baud value when BAUD_VAL_FRCTN_EN = 1
output baud_clock; // 16x baud clock pulse
output xmit_pulse;
// transmit pulse
wire baud_clock;
wire xmit_pulse;
reg [12:0] baud_cntr; // 16x clock division counter reg.
reg baud_clock_int; // internal 16x baud clock pulse
reg xmit_clock;
// ------------------------------------------------
// generate a x16 baud clock pulse
// ------------------------------------------------
reg [3:0] xmit_cntr; // baud tx counter reg.
// ------------------------------------------------
// Sync/Async Reset Mode
// ------------------------------------------------
wire aresetn;
wire sresetn;
assign aresetn = (SYNC_RESET==1) ? 1'b1 : reset_n;
assign sresetn = (SYNC_RESET==1) ? reset_n : 1'b1;
generate
if(BAUD_VAL_FRCTN_EN == 1'b1)
begin
// Add one cycle 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 of the time by freezing
// baud_cntr for one cycle when count reaches 0 for certain xmit_cntr values.
// xmit_cntr values are identifed by looking for bits of this counter
// being certain combinations.
reg baud_cntr_one;
always @(posedge clk or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
baud_cntr_one <= 1'b0;
end
else
begin
if (baud_cntr == 13'b0000000000001)
begin
baud_cntr_one <= 1'b1;
end
else
begin
baud_cntr_one <= 1'b0;
end
end
end
always @(posedge clk or negedge aresetn)
begin : make_baud_cntr
if ((!aresetn) || (!sresetn))
begin
baud_cntr <= 13'b0000000000000;
baud_clock_int <= 1'b0;
end
else
begin
case(BAUD_VAL_FRACTION)
3'b000: begin
if (baud_cntr === 13'b0000000000000) //0
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
else
begin
baud_cntr <= baud_cntr - 1'b 1;
baud_clock_int <= 1'b0;
end
end
3'b001: begin
if (baud_cntr == 13'b0000000000000)
begin
if ((xmit_cntr[2:0] == 3'b111) && (baud_cntr_one == 1'b1)) //0.125
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
3'b010:begin
if (baud_cntr == 13'b0000000000000)
begin
if ((xmit_cntr[1:0] == 2'b11) && (baud_cntr_one == 1'b1)) //0.25
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
3'b011: begin
if (baud_cntr == 13'b0000000000000)
begin
if ((((xmit_cntr[2] == 1'b1) || (xmit_cntr[1] == 1'b1)) && (xmit_cntr[0] == 1'b1)) && (baud_cntr_one == 1'b1)) //0.375
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
3'b100: begin
if (baud_cntr == 13'b0000000000000)
begin
if ((xmit_cntr[0] == 1'b1) && (baud_cntr_one == 1'b1)) //0.5
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
3'b101: begin
if (baud_cntr == 13'b0000000000000)
begin
if ((((xmit_cntr[2] == 1'b1) && (xmit_cntr[1] == 1'b1)) || (xmit_cntr[0] == 1'b1)) && (baud_cntr_one == 1'b1)) //0.625
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
3'b110: begin
if (baud_cntr == 13'b0000000000000)
begin
if (((xmit_cntr[1] == 1'b1) || (xmit_cntr[0] == 1'b1)) && (baud_cntr_one == 1'b1)) //0.75
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
3'b111: begin
if (baud_cntr == 13'b0000000000000)
begin
if ((((xmit_cntr[1] == 1'b1) || (xmit_cntr[0] == 1'b1)) || (xmit_cntr[2:0] == 3'b100)) && (baud_cntr_one == 1'b1)) //0.875
begin
baud_cntr <= baud_cntr;
baud_clock_int <= 1'b0;
end
else
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
end
else
begin
baud_cntr <= baud_cntr - 1'b1;
baud_clock_int <= 1'b0;
end
end
default: begin
if (baud_cntr === 13'b0000000000000)
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
else
begin
baud_cntr <= baud_cntr - 1'b 1;
baud_clock_int <= 1'b0;
end
end
endcase
end
end
end
else if(BAUD_VAL_FRCTN_EN == 1'b0)
begin
always @(posedge clk or negedge aresetn)
begin : make_baud_cntr
if ((!aresetn) || (!sresetn))
begin
baud_cntr <= 13'b0000000000000;
baud_clock_int <= 1'b0;
end
else
begin
if (baud_cntr === 13'b0000000000000)
begin
baud_cntr <= baud_val;
baud_clock_int <= 1'b1;
end
else
begin
baud_cntr <= baud_cntr - 1'b 1;
baud_clock_int <= 1'b0;
end
end
end
end
endgenerate
// --------------------------------------------------
// generate a transmit clock pulse
// --------------------------------------------------
always @(posedge clk or negedge aresetn)
begin : make_xmit_clock
if ((!aresetn) || (!sresetn))
begin
xmit_cntr <= 4'b 0000;
xmit_clock <= 1'b 0;
end
else
begin
if (baud_clock_int === 1'b 1)
begin
xmit_cntr <= xmit_cntr + 1'b 1;
if (xmit_cntr === 4'b 1111)
begin
xmit_clock <= 1'b 1;
end
else
begin
xmit_clock <= 1'b 0;
end
end
end
end
assign xmit_pulse = xmit_clock & baud_clock_int;
assign baud_clock = baud_clock_int;
endmodule // module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen

494
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUART.v Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: COREUART/ CoreUARTapb UART core
//
//
// Revision Information:
// Date Description
// Jun09 Revision 4.1
// Aug10 Revision 4.2
//
//
// SVN Revision Information:
// SVN $Revision: 8508 $
// SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
//
// Resolved SARs
// SAR Date Who Description
// 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
// sys clk (not baud clock). See note below.
//
// Notes:
// best viewed with tabstops set to "4"
`timescale 1 ns / 1 ns // timescale for following modules
module CoreUARTapb_0_CoreUARTapb_0_0_COREUART (RESET_N,
CLK,
WEN,
OEN,
CSN,
DATA_IN,
RX,
BAUD_VAL,
BIT8,
PARITY_EN,
ODD_N_EVEN,
PARITY_ERR,
OVERFLOW,
TXRDY,
RXRDY,
DATA_OUT,
TX,
FRAMING_ERR,
BAUD_VAL_FRACTION
);
// TX Parameters
parameter TX_FIFO = 0; // 0=without tx fifo
// 1=with tx fifo
// RX Parameters
parameter RX_FIFO = 0; // 0=without rx fifo
// 1=with rx fifo
parameter RX_LEGACY_MODE = 0;
// DEVICE FAMILY
parameter FAMILY = 15;
//Baud Fraction Enable
parameter BAUD_VAL_FRCTN_EN = 0; // 1 = enable baud fraction, 0 = disable baud fraction
// Sync/Async Parameter
parameter SYNC_RESET = (FAMILY == 25) ? 1 : 0; // Sync/Async Resets selected by family parameter
input RESET_N;
input CLK;
input WEN;
input OEN;
input CSN;
input [7:0] DATA_IN;
input RX;
input [12:0] BAUD_VAL;
input BIT8; // if set to one 8 data bits otherwise 7 data bits
input PARITY_EN; // if set to one parity is enabled otherwise disabled
input ODD_N_EVEN; // if set to one odd parity otherwise even parity
input [2:0] BAUD_VAL_FRACTION; // used to add extra precision to baud value when BAUD_VAL_FRCTN_EN = 1
output PARITY_ERR; // parity error indicator on recieved data
output OVERFLOW; // receiver overflow
output TXRDY; // transmit ready for another byte
output RXRDY; // receiver has a byte ready
output [7:0] DATA_OUT;
output TX;
output FRAMING_ERR;
// State name constant definitions
`define S0 2'b00
`define S1 2'b01
`define S2 2'b10
`define S3 2'b11
// Configuration bits
// Status bits
wire PARITY_ERR;
wire FRAMING_ERR;
wire OVERFLOW;
wire overflow_legacy;
wire TXRDY;
reg RXRDY;
wire receive_full;
wire fifo_write_rx;
wire fifo_write;
reg [7:0] DATA_OUT;
wire TX;
wire xmit_pulse; // transmit pulse
wire baud_clock; // 8x baud clock pulse
wire rst_tx_empty; // reset transmit empty
reg [7:0] tx_hold_reg; // transmit byte hold register
wire [7:0] tx_dout_reg; // transmit byte hold register
wire [7:0] rx_dout; // receive data out
wire read_rx_byte; // read rx byte register
reg [7:0] rx_dout_reg; // receive data out
wire [7:0] rx_byte; // receive byte register
wire [7:0] rx_byte_in; // receive byte register
wire fifo_empty_tx;
wire fifo_empty_rx;
reg fifo_read_rx;
reg fifo_write_tx;
wire fifo_read_tx;
wire fifo_full_tx;
wire fifo_full_rx;
wire clear_parity;
wire clear_framing_error;
wire clear_parity_en;
reg clear_parity_reg0;
reg clear_parity_reg;
// AS, added framing error self-clear mechanism (RX FIFO mode)
wire clear_framing_error_en;
reg clear_framing_error_reg0;
reg clear_framing_error_reg;
reg data_en;
reg data_ready;
reg rx_dout_reg_empty;
reg rx_dout_reg_empty_q;
reg [1:0] rx_state;
reg [1:0] next_rx_state;
// Added by AS, enable signal for sync'ing:
wire stop_strobe;
wire rx_idle;
reg overflow_reg;
wire clear_overflow;
// TS, sync/async mode select
wire aresetn;
wire sresetn;
assign aresetn = (SYNC_RESET==1) ? 1'b1 : RESET_N;
assign sresetn = (SYNC_RESET==1) ? RESET_N : 1'b1;
// ----------------------------------------------------------------------------
// Transmit related code
// ----------------------------------------------------------------------------
always @(posedge CLK or negedge aresetn)
begin : reg_write
if ((!aresetn) || (!sresetn))
begin
tx_hold_reg <= {8{1'b0}};
fifo_write_tx <= 1'b1;
end
else
begin
fifo_write_tx <= 1'b1;
if (CSN == 1'b0 & WEN == 1'b0)
begin
tx_hold_reg <= DATA_IN;
fifo_write_tx <= 1'b0;
end
end
end
assign rst_tx_empty = WEN == 1'b0 & CSN == 1'b0 ? 1'b1 : 1'b0;
// ----------------------------------------------------------------------------
// Receive related code
// ----------------------------------------------------------------------------
// Added by Hari
// Modified Sep 2006, ROK
always @(rx_byte or rx_dout_reg or PARITY_ERR)
begin
if (RX_FIFO == 1'b0)
begin
DATA_OUT = rx_byte;
end
else
begin
if (PARITY_ERR == 1'b1)
begin
DATA_OUT = rx_byte;
end
else
begin
DATA_OUT = rx_dout_reg;
end
end
end
assign read_rx_byte = (RX_FIFO == 1'b0) ? ((CSN == 1'b0 & OEN == 1'b0) ? 1'b1 : 1'b0) : !fifo_full_rx;
assign clear_parity = (RX_FIFO == 1'b0) ?
((CSN == 1'b0 & OEN == 1'b0) ? 1'b1 : 1'b0) : clear_parity_reg;
//assign clear_framing_error = (RX_FIFO == 1'b0) ? ((CSN == 1'b0 & OEN == 1'b0) ? 1'b1 : 1'b0) : clear_framing_error_reg;
assign clear_framing_error = (RX_FIFO == 1'b0) ? ((CSN == 1'b0 & OEN == 1'b0) ? 1'b1 : 1'b0) :((CSN == 1'b0 & OEN == 1'b0) ? 1'b1 : clear_framing_error_reg) ;
assign clear_overflow = (CSN == 1'b0 & OEN == 1'b0) ? 1'b1 : 1'b0;
assign rx_byte_in = (PARITY_ERR == 1'b0) ? rx_byte : 8'b0;
generate
if (RX_LEGACY_MODE == 1'b1)
begin
always @ (receive_full or rx_dout_reg_empty)
begin
if (RX_FIFO == 1'b0)
begin
RXRDY = receive_full;
end
else
begin
RXRDY = !rx_dout_reg_empty;
end
end
end
else // sync to stop_strobe (stop bit and framing error)
begin
// always @ (receive_full or rx_dout_reg_empty or stop_strobe)
always @ (posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn)) begin
RXRDY <= 1'b0;
end
else begin
if (RX_FIFO == 1'b0)
begin
if (stop_strobe == 1'b1 || receive_full == 1'b0)
begin
RXRDY <= receive_full;
end
end
else
begin
// AS: filter out single clock cycle empty flag (might just be reading
// from fifo, waiting for next data byte
// if (stop_strobe == 1'b1 || (rx_dout_reg_empty == 1'b1))
if (stop_strobe == 1'b1 || (rx_dout_reg_empty == 1'b1) || ((rx_dout_reg_empty == 1'b0) && (rx_idle == 1'b1 || RX_FIFO==1)))
begin
RXRDY <= !rx_dout_reg_empty;
end
end
end
end // end process
end // RX_LEGACY_MODE == 0
endgenerate
always @(posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
clear_parity_reg <= 1'b0;
clear_parity_reg0 <= 1'b0;
end
else
begin
clear_parity_reg0 <= clear_parity_en;
clear_parity_reg <= clear_parity_reg0;
end
end
// AS: added self-clearing framing error
always @(posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
clear_framing_error_reg <= 1'b0;
clear_framing_error_reg0 <= 1'b0;
end
else
begin
clear_framing_error_reg0 <= clear_framing_error_en;
clear_framing_error_reg <= clear_framing_error_reg0;
end
end
// state machine to control reading from the rx fifo
always @(posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
rx_state <= `S0;
end
else
begin
rx_state <= next_rx_state;
end
end
always @(rx_state, rx_dout_reg_empty, fifo_empty_rx)
begin
next_rx_state = rx_state;
fifo_read_rx = 1'b1;
data_en = 1'b0;
case (rx_state)
`S0 : if (rx_dout_reg_empty == 1'b1 && fifo_empty_rx == 1'b0)
begin
next_rx_state = `S1;
fifo_read_rx = 1'b0; // active low
end
`S1 : next_rx_state = `S2;
`S2 : next_rx_state = `S3;
`S3 : begin
next_rx_state = `S0;
data_en = 1'b1;
end
endcase
end
always @(posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
rx_dout_reg <= {8{1'b0}};
end
else
begin
if (data_en == 1'b1)
begin
rx_dout_reg <= rx_dout;
end
end
end
always @(posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
rx_dout_reg_empty <= 1'b1;
rx_dout_reg_empty_q <= 1'b1;
end
else
begin
if (data_en == 1'b1)
begin
rx_dout_reg_empty <= 1'b0;
end
else
begin
if (CSN == 1'b0 && OEN == 1'b0)
begin
if(RX_FIFO == 1)
begin
if(!PARITY_ERR)
begin
rx_dout_reg_empty <= 1'b1;
end
end
else
begin
rx_dout_reg_empty <= 1'b1;
end
end
end
rx_dout_reg_empty_q <= rx_dout_reg_empty;
end
end
// AS: Added OVERFLOW logic (see below)
always @(posedge CLK or negedge aresetn)
begin
if ((!aresetn) || (!sresetn))
begin
overflow_reg <= 1'b0;
end
else
begin
// Note: received byte will happen before OVERFLOW clear
if (fifo_write == 1'b0 && fifo_full_rx == 1'b1)
overflow_reg <= 1'b1;
else if (clear_overflow == 1'b1)
overflow_reg <= 1'b0;
else
overflow_reg <= overflow_reg;
end
end
// AS: Changed OVERFLOW condition
// - We should not be assigning OVERFLOW to FIFO_FULL;
// instead, we should be asserting OVERFLOW if a write is
// requested while fifo_full_rx is high
//assign OVERFLOW = (RX_FIFO == 1'b0) ? overflow_legacy : fifo_full_rx;
assign OVERFLOW = (RX_FIFO == 1'b0) ? overflow_legacy : overflow_reg;
// AS: 16Jun09
// Added FRAMING_ERR to write condition for RX FIFO (removed)
// AS: 24Jun09
// Added OVERFLOW error condition: don't write when OVERFLOW is asserted
assign fifo_write_rx = ((PARITY_ERR == 1'b1) || fifo_full_rx == 1'b1) ? 1'b1 : fifo_write;
// ---------------------------------------------------------
// COMPONENT DECLARATIONS
// ---------------------------------------------------------
CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen #(.BAUD_VAL_FRCTN_EN(BAUD_VAL_FRCTN_EN),
.SYNC_RESET(SYNC_RESET)
) make_CLOCK_GEN ( .clk(CLK),
.reset_n(RESET_N),
.baud_val(BAUD_VAL),
.baud_clock(baud_clock),
.xmit_pulse(xmit_pulse),
.BAUD_VAL_FRACTION(BAUD_VAL_FRACTION)
);
CoreUARTapb_0_CoreUARTapb_0_0_Tx_async #( .TX_FIFO(TX_FIFO),
.SYNC_RESET(SYNC_RESET)
) make_TX (.clk(CLK),
.xmit_pulse(xmit_pulse),
.reset_n(RESET_N),
.rst_tx_empty(rst_tx_empty),
.tx_hold_reg(tx_hold_reg),
.tx_dout_reg(tx_dout_reg),
.fifo_empty(fifo_empty_tx),
.fifo_full(fifo_full_tx),
.bit8(BIT8),
.parity_en(PARITY_EN),
.odd_n_even(ODD_N_EVEN),
.txrdy(TXRDY),
.tx(TX),
.fifo_read_tx(fifo_read_tx)
);
CoreUARTapb_0_CoreUARTapb_0_0_Rx_async #( .RX_FIFO(RX_FIFO),
.SYNC_RESET(SYNC_RESET)
) make_RX ( .clk(CLK),
.baud_clock(baud_clock),
.reset_n(RESET_N),
.bit8(BIT8),
.parity_en(PARITY_EN),
.odd_n_even(ODD_N_EVEN),
.read_rx_byte(read_rx_byte),
.clear_parity(clear_parity),
.framing_error(FRAMING_ERR),
.clear_framing_error(clear_framing_error),
.stop_strobe(stop_strobe),
.rx_idle(rx_idle),
.rx(RX),
.overflow(overflow_legacy),
.parity_err(PARITY_ERR),
.clear_parity_en(clear_parity_en),
.clear_framing_error_en(clear_framing_error_en),
.receive_full(receive_full),
.rx_byte(rx_byte),
.fifo_write(fifo_write)
);
generate
if (TX_FIFO == 1'b1)
begin
CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8 #(.SYNC_RESET(SYNC_RESET)) tx_fifo (.DO(tx_dout_reg), .RCLOCK(CLK), .WCLOCK(CLK), .DI(tx_hold_reg), .WRB(fifo_write_tx), .RDB(fifo_read_tx),
.RESET(RESET_N), .FULL(fifo_full_tx), .EMPTY(fifo_empty_tx));
end
else
begin
assign fifo_full_tx = 1'b0;
assign fifo_empty_tx = 1'b0;
assign tx_dout_reg = 8'b0;
end
endgenerate
generate
if (RX_FIFO == 1'b1)
begin
CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8 #(.SYNC_RESET(SYNC_RESET)) rx_fifo (.DO(rx_dout), .RCLOCK(CLK), .WCLOCK(CLK), .DI(rx_byte_in), .WRB(fifo_write_rx), .RDB(fifo_read_rx),
.RESET(RESET_N), .FULL(fifo_full_rx), .EMPTY(fifo_empty_rx));
end
else
begin
assign fifo_full_rx = 1'b0;
assign fifo_empty_rx = 1'b0;
assign rx_dout = 8'b0;
end
endgenerate
endmodule // module UART

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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: COREUART/ CoreUARTapb UART core
//
//
// Revision Information:
// Date Description
// Jun09 Revision 4.1
// Aug10 Revision 4.2
//
//
// SVN Revision Information:
// SVN $Revision: 8508 $
// SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
//
// Resolved SARs
// SAR Date Who Description
// 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
// sys clk (not baud clock). See note below.
// 22093 4Sep10 AS Added PSLVERR and PREADY, missing APB3 signals
// (unused)
//
// Notes:
// best viewed with tabstops set to "4"
//
//
//
//==============================================================================
// AMBA APB wrapped COREUART
//
// Three control registers and one status register are implemented in this file
// i.e. at the wrapper level.
// Transmit and receive data registers are located in the UART module which is
// instantiated in this file.
//
// A separate word location is used for each (8-bit) register.
//
//
// Address Map:
//
// Offset Register Name Read/Write Width
// -------------------------------------------------------
// 0x00 Transmit data (Write only) 8 bits
// 0x04 Receive data (Read only) 8 bits
// 0x08 Control Register 1 (R/W) 8 bits
// 0x0C Control Register 2 (R/W) 8 bits
// 0x10 Status Register (Read Only) 4 bits
// 0x14 Control Register 3 (R/W) 3 bits
//==============================================================================
`timescale 1 ns / 1 ns
module CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb (
// APB interface
PCLK,
PRESETN,
PADDR,
PSEL,
PENABLE,
PWRITE,
PWDATA,
PRDATA,
// AS: Added PREADY and PSLVERR
PREADY,
PSLVERR,
// transmit-ready and receive-full indicators
TXRDY,
RXRDY,
// Flags
PARITY_ERR,
FRAMING_ERR,
OVERFLOW,
// Serial receive and transmit
RX,
TX
);
// DEVICE FAMILY
parameter FAMILY = 15;
// UART configuration parameters
parameter TX_FIFO = 0; // 1 = with tx fifo, 0 = without tx fifo
parameter RX_FIFO = 0; // 1 = with rx fifo, 0 = without rx fifo
parameter BAUD_VALUE = 0; // Baud value is set only when fixed buad rate is selected
parameter FIXEDMODE = 0; // fixed or programmable mode, 0: programmable; 1:fixed
parameter PRG_BIT8 = 0; // This bit value is selected only when FIXEDMODE is set to 1
parameter PRG_PARITY = 0; // This bit value is selected only when FIXEDMODE is set to 1
parameter RX_LEGACY_MODE = 0; // legacy mode for RXRDY signal operation
parameter BAUD_VAL_FRCTN = 0; // 0 = +0.0, 1 = +0.125, 2 = +0.25, 3 = +0.375, 4 = +0.5, 5 = +0.625, 6 = +0.75, 7 = +0.875,
parameter BAUD_VAL_FRCTN_EN = 0; // 1 = enable baudval fraction, 0 = disable baudval fraction
parameter SYNC_RESET = (FAMILY == 25) ? 1 : 0; // Sync/Async Resets selected by family parameter
// Inputs and Outputs
// APB signals
input PCLK; // APB system clock
input PRESETN; // APB system reset
input [4:0] PADDR; // Address
input PSEL; // Peripheral select signal
input PENABLE; // Enable (data valid strobe)
input PWRITE; // Write/nRead signal
input [7:0] PWDATA; // 8 bit write data
output [7:0] PRDATA; // 8 bit read data
output PREADY;
output PSLVERR;
// transmit ready and receive full indicators
output TXRDY;
output RXRDY;
// Serial receive and transmit data
input RX;
output TX;
// FLAGS
output FRAMING_ERR;
output PARITY_ERR;
output OVERFLOW;
//----------------------------------------------------------------------
// Constant declarations
//----------------------------------------------------------------------
`define UARTTXDATAA 3'b000
`define UARTRXDATAA 3'b001
`define UARTCTRLREG1A 3'b010
`define UARTCTRLREG2A 3'b011
`define UARTSTATUSREGA 3'b100
`define UARTCTRLREG3A 3'b101
//----------------------------------------------------------------------
// Signal declarations
//----------------------------------------------------------------------
// I/O signals
wire PCLK;
wire PRESETN;
wire [4:0] PADDR;
wire PSEL;
wire PENABLE;
wire PWRITE;
wire [7:0] PWDATA;
wire [7:0] PRDATA;
wire TXRDY;
wire RXRDY;
wire RX;
wire TX;
wire PREADY;
wire PSLVERR;
// Internal signals
reg [7:0] controlReg1;
reg [7:0] controlReg2;
reg [2:0] controlReg3;
reg [7:0] NxtPrdata;
reg [7:0] iPRDATA;
wire NxtPrdataEn; // valid read
wire [7:0] data_in;
wire [7:0] data_out;
wire [12:0] baud_val;
wire bit8;
wire parity_en;
wire odd_n_even;
wire WEn;
wire OEn;
wire csn;
wire OVERFLOW;
wire PARITY_ERR;
wire [1:0] gen_parity_en;
wire prg_parity_en;
wire prg_odd_even;
wire FRAMING_ERR;
wire [2:0] fixed_baudval_fraction;
wire [2:0] baudval_fraction;
wire aresetn;
wire sresetn;
assign aresetn = (SYNC_RESET==1) ? 1'b1 : PRESETN;
assign sresetn = (SYNC_RESET==1) ? PRESETN : 1'b1;
// AS: Added APB3 signals, tied off
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
//----------------------------------------------------------------------
// Write enable, output enable and select signals for UART
//----------------------------------------------------------------------
// WEn only asserted (low) when writing transmit data
assign WEn = !(PENABLE && PWRITE && (PADDR[4:2] == `UARTTXDATAA));
// OEn only asserted (low) when reading received data
assign OEn = !(PENABLE && !PWRITE && (PADDR[4:2] == `UARTRXDATAA));
assign csn = !PSEL;
// data_in input to UART is used for transmit data
assign data_in = PWDATA;
//----------------------------------------------------------------------
// APB read data
//----------------------------------------------------------------------
// NxtPrdataEn is asserted during the first cycle of a valid read
assign NxtPrdataEn = (PSEL & !PWRITE & (!PENABLE || PARITY_ERR));
always @(PADDR or NxtPrdataEn or iPRDATA or data_out or controlReg1
or controlReg2 or OVERFLOW or PARITY_ERR or RXRDY
or TXRDY or FRAMING_ERR or controlReg3)
begin : p_NxtPrdataComb
if (NxtPrdataEn)
case (PADDR[4:2])
`UARTTXDATAA : NxtPrdata = 8'b0; // transmit data location reads as 0x00
`UARTRXDATAA : NxtPrdata = data_out; // received data
`UARTCTRLREG1A : NxtPrdata = controlReg1; // control reg 1 - baud value
`UARTCTRLREG2A : NxtPrdata = controlReg2; // control reg 2 - bit8, parity_en, odd_n_even
`UARTSTATUSREGA : NxtPrdata = {3'b0, FRAMING_ERR, OVERFLOW, PARITY_ERR, RXRDY, TXRDY}; // status register
`UARTCTRLREG3A : NxtPrdata = {5'b0, controlReg3}; // control reg 3 - fractional part of baud value
default : NxtPrdata = iPRDATA;
endcase
else
NxtPrdata = iPRDATA;
end // block: p_NxtPrdataComb
assign gen_parity_en = PRG_PARITY;
// AS, fixed 01DEC08:
//assign prg_parity_en = (gen_parity_en == (2'd1 || 2'd2)) ? 1'b1 : 1'b0;
assign prg_parity_en = (gen_parity_en == 2'd1 || gen_parity_en == 2'd2) ? 1'b1 : 1'b0;
assign prg_odd_even = (gen_parity_en == 2'd1) ? 1'b1 : 1'b0;
// PRDATA output register
always @ (posedge PCLK or negedge aresetn)
begin : p_iPRDATASeq
if ((!aresetn) || (!sresetn))
iPRDATA <= 8'b0;
else
iPRDATA <= NxtPrdata;
end // block: p_iPRDATASeq
// Drive output with internal version.
assign PRDATA = ((RX_FIFO == 1) && (PARITY_ERR == 1'b1)) ? data_out : iPRDATA;
//----------------------------------------------------------------------
// Control register 1
// Holds 8-bit value to set baud rate.
//----------------------------------------------------------------------
always @(posedge PCLK or negedge aresetn)
begin : p_CtrlReg1Seq
if((!aresetn) || (!sresetn))
controlReg1 <= 8'b0;
else
if (PSEL && PENABLE && PWRITE && (PADDR[4:2] == `UARTCTRLREG1A))
controlReg1 <= PWDATA;
else
controlReg1 <= controlReg1;
end // block: p_CtrlReg1Seq
assign baud_val = FIXEDMODE ? BAUD_VALUE:{controlReg2[7:3],controlReg1};
//----------------------------------------------------------------------
// Control register 2
// Contents as follows:
// Bit 0: bit8 Data width is 8 bits when '1', 7 bits otherwise.
// Bit 1: parity_en Parity enabled when '1'.
// Bit 2: odd_n_even Odd parity when '1', even parity when '0'.
// Bits 3 to 7: Unused.
//----------------------------------------------------------------------
always @(posedge PCLK or negedge aresetn)
begin : p_CtrlReg2Seq
if ((!aresetn) || (!sresetn))
controlReg2 <= 8'b0;
else
if (PSEL && PENABLE && PWRITE && (PADDR[4:2] == `UARTCTRLREG2A))
controlReg2 <= PWDATA[7:0];
else
controlReg2 <= controlReg2;
end // block: p_CtrlReg2Seq
//----------------------------------------------------------------------
// Control register 3
// Controls the fractional baud value as follows:
// 000: Baud Value = baud_val + 0.0
// 001: Baud Value = baud_val + 0.125
// 010: Baud Value = baud_val + 0.25
// 011: Baud Value = baud_val + 0.375
// 100: Baud Value = baud_val + 0.5
// 101: Baud Value = baud_val + 0.625
// 110: Baud Value = baud_val + 0.75
// 111: Baud Value = baud_val + 0.875
//----------------------------------------------------------------------
generate
if(BAUD_VAL_FRCTN_EN == 1)
begin
always @(posedge PCLK or negedge aresetn)
begin : p_CtrlReg3Seq
if ((!aresetn) || (!sresetn))
controlReg3 <= 3'b0;
else
if (PSEL && PENABLE && PWRITE && (PADDR[4:2] == `UARTCTRLREG3A))
controlReg3 <= PWDATA[2:0];
else
controlReg3 <= controlReg3;
end //block: p_CtrlReg3Seq
end
endgenerate
assign fixed_baudval_fraction = (BAUD_VAL_FRCTN == 0) ? 3'b000 :
(BAUD_VAL_FRCTN == 1) ? 3'b001 :
(BAUD_VAL_FRCTN == 2) ? 3'b010 :
(BAUD_VAL_FRCTN == 3) ? 3'b011 :
(BAUD_VAL_FRCTN == 4) ? 3'b100 :
(BAUD_VAL_FRCTN == 5) ? 3'b101 :
(BAUD_VAL_FRCTN == 6) ? 3'b110 :
(BAUD_VAL_FRCTN == 7) ? 3'b111 : 3'b000;
assign bit8 = FIXEDMODE ? PRG_BIT8:controlReg2[0];
assign parity_en = FIXEDMODE ? prg_parity_en:controlReg2[1];
assign odd_n_even = FIXEDMODE ? prg_odd_even:controlReg2[2];
assign baudval_fraction = FIXEDMODE ? fixed_baudval_fraction : BAUD_VAL_FRCTN_EN ? controlReg3 : 3'b000;
//----------------------------------------------------------------------
// Instantiation of UART
//----------------------------------------------------------------------
CoreUARTapb_0_CoreUARTapb_0_0_COREUART
#(
.TX_FIFO (TX_FIFO),
.RX_FIFO (RX_FIFO),
.RX_LEGACY_MODE(RX_LEGACY_MODE),
.BAUD_VAL_FRCTN_EN(BAUD_VAL_FRCTN_EN),
.FAMILY(FAMILY)
)
uUART (
.RESET_N (PRESETN),
.CLK (PCLK),
.WEN (WEn),
.OEN (OEn),
.CSN (csn),
.DATA_IN (data_in),
.RX (RX),
.BAUD_VAL (baud_val),
.BIT8 (bit8),
.PARITY_EN (parity_en),
.ODD_N_EVEN (odd_n_even),
.FRAMING_ERR (FRAMING_ERR),
.PARITY_ERR (PARITY_ERR),
.OVERFLOW (OVERFLOW),
.TXRDY (TXRDY),
.RXRDY (RXRDY),
.DATA_OUT (data_out),
.TX (TX),
.BAUD_VAL_FRACTION (baudval_fraction)
);
endmodule
// ============================== End ==========================================

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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreUART/ CoreUARTapb UART core
//
//
// Revision Information:
// Date Description
// Jun09 Revision 4.1
// Aug10 Revision 4.2
//
// SVN Revision Information:
// SVN $Revision: 8508 $
// SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
//
// Resolved SARs
// SAR Date Who Description
// 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
// sys clk (not baud clock). See note below.
//
// Notes:
// best viewed with tabstops set to "4"
`timescale 1 ns / 1 ns // timescale for following modules
module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async (clk,
baud_clock,
reset_n,
bit8,
parity_en,
odd_n_even,
read_rx_byte,
clear_parity,
rx,
overflow,
parity_err,
clear_parity_en,
receive_full,
rx_byte,
fifo_write,
framing_error,
clear_framing_error,
clear_framing_error_en,
stop_strobe,
rx_idle
);
parameter SYNC_RESET = 0;
// RX Parameters
parameter RX_FIFO = 0; // 0=without rx fifo, 1=with rx fifo
// TYPE receive_states:
parameter receive_states_rx_idle = 0;
parameter receive_states_rx_data_bits = 1;
parameter receive_states_rx_stop_bit = 2;
parameter receive_states_rx_wait_state = 3;
input clk; // system clock
input baud_clock; // 8x baud clock pulse
input reset_n; // active low async reset
input bit8; // if set to one 8 data bits otherwise 7 data bits
input parity_en; // if set to one parity is enabled otherwise disabled
input odd_n_even; // if set to one odd parity otherwise even parity
input read_rx_byte; // read rx byte register
input clear_parity; // clear parity error
input clear_framing_error; // clear framing error signal (AS)
input rx;
output overflow; // receiver overflow
output parity_err; // parity error indicator on recieved data
output clear_parity_en; // clear parity error enable
output receive_full; // receiver has a byte ready
output [7:0] rx_byte;
output fifo_write;
output framing_error; // stop bit not detected flag (AS)
output clear_framing_error_en; // clear framing error enable (AS)
output stop_strobe; // stop bit strobe (for RX legacy mode) (AS)
// AS: added idle wire for framing_err assigmnet using
// stop_strobe
output rx_idle;
reg framing_error; // stop bit not detected flag (AS)
reg stop_strobe; // stop bit strobe (for RX legacy mode) (AS)
reg overflow;
reg parity_err;
reg fifo_write;
// receive byte register
wire receive_full;
reg [7:0] rx_byte;
reg [1:0] rx_state; // receive state machine
reg [3:0] receive_count; // counts bits received
reg rx_filtered; // filtered rx data
reg [8:0] rx_shift; // receive shift register
reg rx_parity_calc; // received parity, calculated
reg [3:0] rx_bit_cnt; // count of received bits
reg receive_full_int; // receiver has a byte ready
reg [2:0] samples;
reg overflow_int;
reg framing_error_int; // internal framing error bit (AS)
reg clear_parity_en;
reg clear_framing_error_en; // clear framing error enable (AS)
reg [3:0] last_bit;
wire [1:0] shift_choice;
wire [1:0] parity_choice;
// ----------------------------------------------------------------------------
wire aresetn;
wire sresetn;
assign aresetn = (SYNC_RESET==1) ? 1'b1 : reset_n;
assign sresetn = (SYNC_RESET==1) ? reset_n : 1'b1;
// filter the receive data
// ----------------------------------------------------------------------------
// The receive data filter is a simple majority voter that accepts three
// samples of the "raw" data and reports the most populus result. This
// provides a simple single-cycle glitch filter.
// This input needs to go to both the state machine start bit detector as
// well as the data shift register as this filter introduces a three-clock
// delay and we need to keep the phases lined up.
//
always @(posedge clk or negedge aresetn)
begin : majority
if ((!aresetn) || (!sresetn))
begin
samples <= 3'b111;
end
else
begin
if (baud_clock == 1'b1)
begin
samples[1:0] <= samples[2:1];
samples[2] <= rx;
end
end
end
// our voter
always @(samples)
begin
case (samples)
3'b000:
begin
rx_filtered <= 1'b0;
end
3'b001:
begin
rx_filtered <= 1'b0;
end
3'b010:
begin
rx_filtered <= 1'b0;
end
3'b011:
begin
rx_filtered <= 1'b1;
end
3'b100:
begin
rx_filtered <= 1'b0;
end
3'b101:
begin
rx_filtered <= 1'b1;
end
3'b110:
begin
rx_filtered <= 1'b1;
end
default:
begin
rx_filtered <= 1'b1;
end
endcase
end
// ----------------------------------------------------------------------------
// receive bit counter
// ----------------------------------------------------------------------------
always @(posedge clk or negedge aresetn)
begin : rcv_cnt
if ((!aresetn) || (!sresetn))
begin
receive_count <= 4'b0000;
end
else
begin
// no start bit yet or begin sample period for data
if (baud_clock == 1'b1)
begin
if ((rx_state == receive_states_rx_idle & (rx_filtered == 1'b1 | receive_count == 4'b1000)) || ((rx_state == receive_states_rx_wait_state) && (receive_count == 4'b0110)))
begin
receive_count <= 4'b0000;
end
else
begin
receive_count <= receive_count + 1'b1;
end
end
end
end
// ----------------------------------------------------------------------------
// registering of the overflow signal
// ----------------------------------------------------------------------------
always @(posedge clk or negedge aresetn)
begin : make_overflow
if ((!aresetn) || (!sresetn))
begin
overflow <= 1'b0;
end
else
begin
if (baud_clock == 1'b1)
begin
if (overflow_int == 1'b1)
begin
overflow <= 1'b1;
end
end
if (read_rx_byte == 1'b1)
begin
overflow <= 1'b0;
end
end
end
// ----------------------------------------------------------------------------
// registering of the framing_error signal
// ----------------------------------------------------------------------------
always @(posedge clk or negedge aresetn)
begin : make_framing_error
if ((!aresetn) || (!sresetn))
begin
framing_error <= 1'b0;
end
else if (baud_clock == 1'b1)
begin
if (framing_error_int == 1'b1)
begin
framing_error <= 1'b1;
end
else if (clear_framing_error == 1'b1)
begin
framing_error <= 1'b0;
end
end
else if (clear_framing_error == 1'b1)
begin
framing_error <= 1'b0;
end
else
begin
framing_error <= framing_error;
end
end
// ----------------------------------------------------------------------------
// receive state machine & byte register
// ----------------------------------------------------------------------------
always @(posedge clk or negedge aresetn)
begin
if((!aresetn) || (!sresetn))
begin
last_bit <= 4'b1001;
end
else
begin
if((rx_state == receive_states_rx_idle) && (receive_count == 4'b1000))
begin
case({bit8,parity_en})
2'b00 : last_bit <= 4'b0111;
2'b01 : last_bit <= 4'b1000;
2'b10 : last_bit <= 4'b1000;
2'b11 : last_bit <= 4'b1001;
endcase
end
else
begin
last_bit <= last_bit;
end
end
end
assign rx_idle = (rx_state == receive_states_rx_idle);
always @(posedge clk or negedge aresetn)
begin : rcv_sm
if ((!aresetn) || (!sresetn))
begin
rx_state <= receive_states_rx_idle;
rx_byte <= 8'b00000000;
overflow_int <= 1'b0;
framing_error_int <= 1'b0;
stop_strobe <= 1'b0;
end
else
begin
if (baud_clock == 1'b1)
begin
overflow_int <= 1'b0;
stop_strobe <= 1'b0;
framing_error_int <= 1'b0;
case (rx_state)
receive_states_rx_idle:
begin
if (receive_count == 4'b1000)
begin
rx_state <= receive_states_rx_data_bits;
end
else
begin
rx_state <= receive_states_rx_idle;
end
end
receive_states_rx_data_bits:
begin
// last bit has been received
if (rx_bit_cnt == last_bit )
begin
// overflow
rx_state <= receive_states_rx_stop_bit ;
overflow_int <= receive_full_int;
if (receive_full_int == 1'b0)
begin
rx_byte <= {(bit8 & rx_shift[7]), rx_shift[6:0]};
end
end
else
begin
rx_state <= receive_states_rx_data_bits; // still clocking in bits
end
end
receive_states_rx_stop_bit :
begin
// framing error
if (receive_count == 4'b1110)
begin
if (rx_filtered == 1'b0)
begin
framing_error_int <= 1'b1;
end
end
else if (receive_count == 4'b1111)
begin
stop_strobe <= 1'b1;
rx_state <= receive_states_rx_wait_state;
end
else
begin
rx_state <= receive_states_rx_stop_bit;
end
end
receive_states_rx_wait_state :
begin
if ((rx_filtered == 1'b1) || (receive_count == 4'b0110))
begin
rx_state <= receive_states_rx_idle;
end
else
begin
rx_state <= receive_states_rx_wait_state;
end
end
default:
begin
rx_state <= receive_states_rx_idle;
end
endcase
end
end
end
// ----------------------------------------------------------------------------
// receive shift register and parity calculation
// ----------------------------------------------------------------------------
assign shift_choice = {bit8, parity_en};
always @(posedge clk or negedge aresetn)
begin : receive_shift
if ((!aresetn) || (!sresetn))
begin
rx_shift[8:0] <= 9'b000000000;
rx_bit_cnt <= 4'b0000;
end
else
begin
if (baud_clock == 1'b1)
begin
if (rx_state == receive_states_rx_idle)
begin
rx_shift[8:0] <= 9'b000000000;
rx_bit_cnt <= 4'b0000;
end
else if (receive_count == 4'b1111 )
begin
// sample new data bit
rx_bit_cnt <= rx_bit_cnt + 1'b1;
case (shift_choice)
2'b00:
begin
rx_shift[5:0] <= rx_shift[6:1];
rx_shift[6] <= rx_filtered;
end
2'b11:
begin
rx_shift[7:0] <= rx_shift[8:1];
rx_shift[8] <= rx_filtered;
end
default:
begin
rx_shift[6:0] <= rx_shift[7:1];
rx_shift[7] <= rx_filtered;
end
endcase
end
end
end
end
// ----------------------------------------------------------------------------
// receiver parity calculation
// ----------------------------------------------------------------------------
always @(posedge clk or negedge aresetn)
begin : rx_par_calc
if ((!aresetn) || (!sresetn))
begin
rx_parity_calc <= 1'b0;
end
else
begin
if (baud_clock == 1'b1)
begin
if (receive_count == 4'b1111 & parity_en == 1'b1)
begin
rx_parity_calc <= rx_parity_calc ^ rx_filtered;
end
if (rx_state == receive_states_rx_stop_bit)
begin
rx_parity_calc <= 1'b0;
end
end
end
end
// ----------------------------------------------------------------------------
// latch parity error for even or odd parity
// ----------------------------------------------------------------------------
assign parity_choice = {bit8, odd_n_even};
always @(posedge clk or negedge aresetn)
begin : make_parity_err
if ((!aresetn) || (!sresetn))
begin
parity_err <= 1'b0;
end
else
begin
if (baud_clock == 1'b1 & parity_en == 1'b1 & receive_count == 4'b1111)
begin
case (parity_choice)
2'b00:
begin
if (rx_bit_cnt == 4'b0111)
begin
parity_err <= rx_parity_calc ^ rx_filtered;
end
end
2'b01:
begin
if (rx_bit_cnt == 4'b0111)
begin
parity_err <= ~(rx_parity_calc ^ rx_filtered);
end
end
2'b10:
begin
if (rx_bit_cnt == 4'b1000)
begin
parity_err <= rx_parity_calc ^ rx_filtered;
end
end
2'b11:
begin
if (rx_bit_cnt == 4'b1000)
begin
parity_err <= ~(rx_parity_calc ^ rx_filtered);
end
end
default:
begin
parity_err <= 1'b0;
end
endcase
end
if (clear_parity == 1'b1)
begin
parity_err <= 1'b0;
end
end
end
// ----------------------------------------------------------------------------
// receive full indicator process
// ----------------------------------------------------------------------------
always @(posedge clk or negedge aresetn)
begin : receive_full_indicator
if ((!aresetn) || (!sresetn))
begin
receive_full_int <= 1'b0;
fifo_write <= 1'b1;
clear_parity_en <= 1'b0;
clear_framing_error_en <= 1'b0;
end
else
begin
fifo_write <= 1'b1;
clear_parity_en <= 1'b0;
clear_framing_error_en <= 1'b0;
if (baud_clock == 1'b1)
// last bit has been received
begin
if (bit8 == 1'b1)
begin
if (parity_en == 1'b1)
begin
if (rx_bit_cnt == 4'b1001 & rx_state == receive_states_rx_data_bits)
begin
fifo_write <= 1'b0;
clear_parity_en <= 1'b1;
clear_framing_error_en <= 1'b1;
if (RX_FIFO == 1'b0)
begin
receive_full_int <= 1'b1;
end
end
end
else
begin
if (rx_bit_cnt == 4'b1000 & rx_state == receive_states_rx_data_bits)
begin
fifo_write <= 1'b0;
clear_parity_en <= 1'b1;
clear_framing_error_en <= 1'b1;
if (RX_FIFO == 1'b0)
begin
receive_full_int <= 1'b1;
end
end
end
end
else
begin
if (parity_en == 1'b1)
begin
if (rx_bit_cnt == 4'b1000 & rx_state == receive_states_rx_data_bits)
begin
fifo_write <= 1'b0;
clear_parity_en <= 1'b1;
clear_framing_error_en <= 1'b1;
if (RX_FIFO == 1'b0)
begin
receive_full_int <= 1'b1;
end
end
end
else
begin
if (rx_bit_cnt == 4'b0111 & rx_state == receive_states_rx_data_bits)
begin
fifo_write <= 1'b0;
clear_parity_en <= 1'b1;
clear_framing_error_en <= 1'b1;
if (RX_FIFO == 1'b0)
begin
receive_full_int <= 1'b1;
end
end
end
end
end
if (read_rx_byte == 1'b1)
begin
receive_full_int <= 1'b0;
end
end
end
assign receive_full = receive_full_int;
endmodule // module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async

368
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Tx_async.v Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreUART/ CoreUARTapb UART core
//
//
// Revision Information:
// Date Description
// Jun09 Revision 4.1
// Aug10 Revision 4.2
//
// SVN Revision Information:
// SVN $Revision: 8508 $
// SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
//
// Resolved SARs
// SAR Date Who Description
// 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
// sys clk (not baud clock). See note below.
//
// Notes:
// best viewed with tabstops set to "4"
`timescale 1 ns / 1 ns // timescale for following modules
module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async (clk, xmit_pulse, reset_n, rst_tx_empty, tx_hold_reg, tx_dout_reg, fifo_empty, fifo_full, bit8,
parity_en, odd_n_even, txrdy, tx, fifo_read_tx);
parameter SYNC_RESET = 0;
// TX Parameters
parameter TX_FIFO = 0; // 0=without tx fifo
// 1=with tx fifo
input clk;
input xmit_pulse;
input reset_n;
input rst_tx_empty;
input[7:0] tx_hold_reg;
input[7:0] tx_dout_reg;
input fifo_empty;
input fifo_full;
input bit8;
input parity_en;
input odd_n_even;
output txrdy;
wire txrdy;
output tx;
output fifo_read_tx;
reg tx;
parameter tx_idle = 0;
parameter tx_load = 1;
parameter start_bit = 2;
parameter tx_data_bits = 3;
parameter parity_bit = 4;
parameter tx_stop_bit = 5;
parameter delay_state = 6;
integer xmit_state; // transmit state machine
reg txrdy_int; // transmit ready for another byte
reg[7:0] tx_byte; // transmit byte
reg[3:0] xmit_bit_sel; // selects transmit bit
reg tx_parity; // transmit parity
// AS: changed to wire
// removed unused signals
//reg fifo_read_tx;
wire fifo_read_tx;
reg fifo_read_en0;
//reg fifo_read_en1;
//wire fifo_read_en;
// ----------------------------------------------------------------------------
wire aresetn;
wire sresetn;
assign aresetn = (SYNC_RESET==1) ? 1'b1 : reset_n;
assign sresetn = (SYNC_RESET==1) ? reset_n : 1'b1;
// Modified Sep 2006, ROK
// ----------------------------------------------------------
// AS, Sep10: synchronized to start bit, rather than load bit
// since txload now happens on start bit state
always @(posedge clk or negedge aresetn)
begin : make_txrdy
if ((!aresetn) || (!sresetn))
begin
txrdy_int <= 1'b1 ;
end
else
begin
if (TX_FIFO == 1'b0)
begin
if (xmit_pulse)
begin
if (xmit_state == start_bit)
begin
txrdy_int <= 1'b1;
end
end
if (rst_tx_empty)
begin
txrdy_int <= 1'b0;
end
end
else
begin
txrdy_int <= !fifo_full;
end
end
end
// Modified Sep10, AS
// FIFO load state transitions and outputs and outputs registered on system
// clock (clk):
always @(posedge clk or negedge aresetn)
begin : xmit_sm
if ((!aresetn) || (!sresetn))
begin
xmit_state <= tx_idle ;
tx_byte <= 8'b0 ;
fifo_read_en0 <= 1'b1;
end
else
begin
// AS:
// (1) state on sysclk for tx_idle, tx_load, delay_state since these operations run
// off the system clock, not the baud clock
// (2) perform tx byte load on start bit state to ensure that data is
// valid at that point
if (xmit_pulse || (xmit_state == tx_idle) || (xmit_state == delay_state) || (xmit_state == tx_load))
begin
fifo_read_en0 <= 1'b1;
case (xmit_state)
tx_idle :
begin
if (TX_FIFO == 1'b0)
begin
if (!txrdy_int)
begin
xmit_state <= tx_load ;
end
else
begin
xmit_state <= tx_idle ;
end
end
else
begin
if (fifo_empty == 1'b0)
begin
fifo_read_en0 <= 1'b0;
xmit_state <= delay_state;
end
else
begin
xmit_state <= tx_idle ;
fifo_read_en0 <= 1'b1;
end
end
end
tx_load :
begin
xmit_state <= start_bit ;
end
start_bit :
begin
xmit_state <= tx_data_bits ;
if (TX_FIFO == 1'b0)
begin
tx_byte <= tx_hold_reg ;
end
else
begin
tx_byte <= tx_dout_reg ;
end
end
tx_data_bits :
begin
if (bit8)
begin
if (xmit_bit_sel == 4'b0111)
begin
if (parity_en)
begin
xmit_state <= parity_bit ;
end
else
begin
xmit_state <= tx_stop_bit ;
end
end
else
begin
xmit_state <= tx_data_bits ;
end
end
else
begin
if (xmit_bit_sel == 4'b0110)
begin
if (parity_en)
begin
xmit_state <= parity_bit ;
end
else
begin
xmit_state <= tx_stop_bit ;
end
end
else
begin
xmit_state <= tx_data_bits ;
end
end
end
parity_bit :
begin
xmit_state <= tx_stop_bit ;
end
tx_stop_bit :
begin
xmit_state <= tx_idle ;
end
delay_state :
begin
xmit_state <= tx_load ;
end
default :
begin
xmit_state <= tx_idle ;
end
endcase
end
end
end
// AS: Need to remove clock delay of fifo read, since tx_load state is
// registered on sys clk now and fifo_read_en needs to be made available
// immediately
// Added by Hari
//always @(posedge clk or negedge reset_n)
//begin : read_fifo
// if (!reset_n)
// begin
// fifo_read_tx <= 1'b1;
// fifo_read_en1 <= 1'b1;
// end
// else
// begin
// fifo_read_tx <= 1'b1;
// fifo_read_en1 <= fifo_read_en0;
// if (fifo_read_en == 1'b0)
// begin
// fifo_read_tx <= 1'b0;
// end
// end
//end
//assign fifo_read_en = (!fifo_read_en1 | fifo_read_en0);
//assign fifo_read_en = fifo_read_en0;
assign fifo_read_tx = fifo_read_en0;
always @(posedge clk or negedge aresetn)
begin : xmit_cnt
if ((!aresetn) || (!sresetn))
begin
xmit_bit_sel <= 4'b0000 ;
end
else
begin
if (xmit_pulse)
begin
if (xmit_state != tx_data_bits)
begin
xmit_bit_sel <= 4'b0000 ;
end
else
begin
xmit_bit_sel <= xmit_bit_sel + 1'b1 ;
end
end
end
end
always @(posedge clk or negedge aresetn)
begin : xmit_sel
if ((!aresetn) || (!sresetn))
begin
tx <= 1'b1 ;
end
else
begin
// AS:
// state on sysclk for tx_idle, tx_load, delay_state since these operations run
// off the system clock, no the baud clock
if (xmit_pulse || (xmit_state == tx_idle) || (xmit_state == delay_state) || (xmit_state == tx_load))
begin
case (xmit_state)
tx_idle :
begin
tx <= 1'b1 ;
end
tx_load :
begin
tx <= 1'b1 ;
end
start_bit :
begin
tx <= 1'b0 ;
end
tx_data_bits :
begin
//tx <= tx_byte[conv_integer(xmit_bit_sel)] ;
tx <= tx_byte[xmit_bit_sel] ;
end
parity_bit :
begin
tx <= odd_n_even ^ tx_parity ;
end
tx_stop_bit :
begin
tx <= 1'b1 ;
end
default :
begin
tx <= 1'b1 ;
end
endcase
end
end
end
always @(posedge clk or negedge aresetn)
begin : xmit_par_calc
if ((!aresetn) || (!sresetn))
begin
tx_parity <= 1'b0 ;
end
else
begin
if (xmit_pulse & parity_en)
begin
if (xmit_state == tx_data_bits)
begin
//tx_parity <= tx_parity ^ tx_byte[conv_integer(xmit_bit_sel)] ;
tx_parity <= tx_parity ^ tx_byte[xmit_bit_sel] ;
end
else
begin
tx_parity <= tx_parity ;
end
end
if (xmit_state == tx_stop_bit)
begin
tx_parity <= 1'b0 ;
end
end
end
assign txrdy = txrdy_int ;
endmodule

280
component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/fifo_256x8_g5.v Normal file
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// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2008 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: CoreUART/ CoreUARTapb UART core
//
//
// Revision Information:
// Date Description
// Jun09 Revision 4.1
// Aug10 Revision 4.2
//
//
// SVN Revision Information:
// SVN $Revision: 8508 $
// SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
//
// Resolved SARs
// SAR Date Who Description
// 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
// sys clk (not baud clock). See note below.
//
// Notes:
// best viewed with tabstops set to "4"
`timescale 1 ns/100 ps
module CoreUARTapb_0_CoreUARTapb_0_0_fifo_256x8(DO, RCLOCK, WCLOCK, DI, WRB, RDB, RESET, FULL, EMPTY);
output [7:0] DO;
input RCLOCK;
input WCLOCK;
input [7:0] DI;
input WRB;
input RDB;
input RESET;
output FULL;
output EMPTY;
parameter SYNC_RESET = 0;
parameter [6:0] LEVEL = 128;
wire [7:0] DO;
wire AEMPTY, AFULL, FULL, EMPTY;
CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256 #(.SYNC_RESET(SYNC_RESET)) fifo_256x8_g5 (.data_in(DI), .data_out(DO), .write_n(WRB), .read_n(RDB), .clock(WCLOCK),
.full(FULL), .empty(EMPTY), .half(GEQTH), .reset_n(RESET), .LEVEL(LEVEL) );
endmodule
/*********************************************************/
// MODULE: Synchronous FIFO
//
// FILE NAME: fifo_ctl.v
//
// CODE TYPE: Register Transfer Level
//
// DESCRIPTION: This module defines a Synchronous FIFO. The
// FIFO memory is implemented as a ring buffer. The read
// pointer points to the beginning of the buffer, while the
// write pointer points to the end of the buffer. Note that
// in this RTL version, the memory has one more location than
// the FIFO needs in order to calculate the FIFO count
// correctly.
//
/*********************************************************/
// fifo control logic
module CoreUARTapb_0_CoreUARTapb_0_0_fifo_ctrl_256(
clock,
reset_n,
data_in,
read_n,
write_n,
LEVEL,
data_out,
full,
empty,
half);
parameter SYNC_RESET = 0;
parameter FIFO_DEPTH = 256; // Depth of FIFO (number of bytes)
parameter FIFO_BITS = 8; // Number of bits required to
parameter FIFO_WIDTH = 8; // Width of FIFO data
// INPUTS
input clock; // Clock input
input reset_n; // Active low reset
input [FIFO_WIDTH-1:0] data_in; // Data input to FIFO
input read_n; // Read FIFO (active low)
input write_n; // Write FIFO (active low)
input [6:0] LEVEL;
// OUTPUTS
output [FIFO_WIDTH-1:0] data_out; // FIFO output data
output full; // FIFO is full
output empty; // FIFO is empty
output half; // FIFO is half full
// or more
// INOUTS
// SIGNAL DECLARATIONS
wire clock;
wire reset_n;
wire [FIFO_WIDTH-1:0] data_in;
wire read_n;
wire write_n;
reg [FIFO_WIDTH-1:0] data_out;
wire full;
wire empty;
wire half;
wire [FIFO_WIDTH-1:0] data_out_0;
reg read_n_hold;
// How many locations in the FIFO
// are occupied?
reg [FIFO_BITS-1:0] counter;
// FIFO read pointer points to
// the location in the FIFO to
// read from next
reg [FIFO_BITS-1:0] rd_pointer;
// FIFO write pointer points to
// the location in the FIFO to
// write to next
reg [FIFO_BITS-1:0] wr_pointer;
wire aresetn;
wire sresetn;
// ASSIGN STATEMENTS
assign aresetn = (SYNC_RESET==1) ? 1'b1 : reset_n;
assign sresetn = (SYNC_RESET==1) ? reset_n : 1'b1;
assign full = (counter == FIFO_DEPTH-1) ? 1'b1 : 1'b0;
assign empty = (counter == 0) ? 1'b1 : 1'b0;
assign half = (counter >= LEVEL) ? 1'b1 : 1'b0;
// MAIN CODE
// This block contains all devices affected by the clock
// and reset inputs
always @(posedge clock or negedge aresetn ) begin
if ((!aresetn) || (!sresetn)) begin
// Reset the FIFO pointer
rd_pointer <= {FIFO_BITS{1'b0}};
wr_pointer <= {FIFO_BITS{1'b0}};
counter <= {FIFO_BITS{1'b0}};
end
else begin
if (~read_n) begin
// If we are doing a simultaneous read and write,
// there is no change to the counter
if (write_n) begin
// Decrement the FIFO counter
counter <= counter - 1;
end
// Increment the read pointer
// Check if the read pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (rd_pointer == FIFO_DEPTH-1)
rd_pointer <= {FIFO_BITS{1'b0}};
else
rd_pointer <= rd_pointer + 1;
end
if (~write_n) begin
// Check for FIFO overflow
if (counter >= FIFO_DEPTH) begin
$display("\nERROR at time %0t:", $time);
$display("FIFO Overflow\n");
// Use $stop for debugging
$stop;
end
// If we are doing a simultaneous read and write,
// there is no change to the counter
if (read_n) begin
// Increment the FIFO counter
counter <= counter + 1;
end
// Increment the write pointer
// Check if the write pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (wr_pointer == FIFO_DEPTH-1)
wr_pointer <= {FIFO_BITS{1'b0}};
else
wr_pointer <= wr_pointer + 1;
end
end
end
always @(posedge clock or negedge aresetn )
begin
if ((!aresetn) || (!sresetn))
begin
read_n_hold <= 1'b0;
data_out <= 1'b0;
end
else
begin
read_n_hold <= read_n;
if (read_n_hold == 1'b0)
begin
data_out <= data_out_0;
end
else
begin
data_out <= data_out;
end
end
end
CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5 ram256x8_g5(.Data(data_in), .Q(data_out_0), .WAddress(wr_pointer),
.RAddress(rd_pointer), .WE(write_n), .RE(read_n), .WClock(clock),
.RClock(clock), .reset_n(reset_n) );
endmodule
module CoreUARTapb_0_CoreUARTapb_0_0_ram256x8_g5(Data,Q,WAddress,RAddress,WE,RE,WClock,RClock,reset_n);
input [7:0] Data;
input [7:0] WAddress, RAddress;
input WE, RE, WClock, RClock, reset_n;
output [7:0] Q;
wire [19:0] DOUT_RAM_0;
wire [13:0] RADDR_int;
wire [13:0] WADDR_int;
wire INV_0_Y, VCC, GND;
VCC VCC_1_net(.Y(VCC));
GND GND_1_net(.Y(GND));
INV INV_0(.A(WE), .Y(INV_0_Y));
INV INV_1(.A(RE), .Y(INV_1_Y));
assign Q = DOUT_RAM_0[7:0];
assign RADDR_int = {2'b0, RAddress[7:0], 4'b0};
assign WADDR_int = {2'b0, WAddress[7:0], 4'b0};
RAM1K20
RAM_R0C0 ( .A_DOUT (DOUT_RAM_0),
.B_DOUT (/*NC*/),
.ACCESS_BUSY (/*NC*/),
.BUSY_FB (1'b1),
.ECC_EN (1'b0),
.ECC_BYPASS (1'b0),
.DB_DETECT (/*NC*/),
.SB_CORRECT (/*NC*/),
.A_CLK (RClock),
.A_DOUT_EN (1'b1),
.A_DOUT_SRST_N (1'b1),
.A_DOUT_ARST_N (1'b1),
.A_BYPASS (1'b1),
.A_BLK_EN ({INV_1_Y, 2'b11}),
.A_DIN (20'b0),
.A_ADDR (RADDR_int),
.A_WEN (2'b00),
.A_REN (1'b1),
.A_WIDTH (3'b100),
.A_WMODE (2'b0),
.B_CLK (WClock),
.B_DOUT_EN (1'b1),
.B_DOUT_SRST_N (1'b1),
.B_DOUT_ARST_N (1'b1),
.B_BYPASS (1'b1),
.B_BLK_EN ({INV_0_Y, 2'b11}),
.B_DIN ({12'b0, Data[7:0]}),
.B_ADDR (WADDR_int),
.B_WEN (2'b11),
.B_REN (1'b0),
.B_WIDTH (3'b100),
.B_WMODE (2'b0)
);
endmodule

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`timescale 1 ns / 1 ns
// ********************************************************************
// Actel Corporation Proprietary and Confidential
// Copyright 2009 Actel Corporation. All rights reserved.
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// Description: User testbench for CoreAI (Analog Interface)
//
// Revision Information:
// Date Description
// ---- -----------------------------------------
// 03Mar09 Initial Version 2.0
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 1. best viewed with tabstops set to "4"
// 2. Most of the behavior is driven from the BFM scripts for the APB master.
// Consult the Actel AMBA BFM documentation for more information.
//
// History: 04/22/09 - AS created
//
// *********************************************************************
module testbench;
//`include "coreparameters.v"
//`include "../../../coreparameters.v"
`include "../../../../coreparameters.v"
// vector file for driving the APB master BFM
// NOTE: location of the following files can be overridden at run time
parameter APB_MASTER_VECTFILE = "coreuart_usertb_apb_master.vec";
// propagation delay in ns
parameter TPD = 3;
//-----------------------------------------------------------------------------
// constants
//-----------------------------------------------------------------------------
parameter APB_MASTER_CLK_CYCLE = 100;
parameter APB_MASTER_CLK_CYCLE_LO_TIME = (APB_MASTER_CLK_CYCLE/2);
// add 1 if APB_MASTER_CLK_CYCLE is odd number to compensate for PCLK period
parameter APB_MASTER_CLK_CYCLE_HI_TIME = (APB_MASTER_CLK_CYCLE/2);
parameter [31:0] ADDR_IN = 32'h00000000;
parameter [31:0] ADDR_OUT = 32'h00000001;
parameter [31:0] ADDR_INT = 32'h00000002;
parameter [31:0] ADDR_OE = 32'h00000003;
//----------------------------------------------------------------------------
// signals
//-----------------------------------------------------------------------------
// system
reg SYSRSTN_apb;
reg SYSCLK_apb;
// APB
wire PCLK;
wire PRESETN;
wire [31:0] PADDR_apb_bfm_wide;
wire [4:0] PADDR;
wire [15:0] PSEL_apb_bfm_wide;
wire PSEL1; // DUT1 PSEL
wire PSEL2; // DUT2 PSEL
wire PENABLE;
wire PWRITE;
wire [31:0] PWDATA_apb_bfm_wide;
wire [7:0] PWDATA;
// BFM
wire [31:0] PRDATA_apb_bfm_wide;
wire [7:0] PRDATA;
wire [7:0] PRDATA1;
wire [7:0] PRDATA2;
wire PREADY;
wire PSLVERR;
wire [31:0] GP_IN_apb_bfm;
wire [31:0] GP_OUT_apb_bfm;
wire FINISHED_apb_bfm;
wire FAILED_apb_bfm;
// DUT1
wire TXRDY1;
wire RXRDY1;
wire TX1;
wire RX1;
wire PARITY_ERR1;
wire FRAMING_ERR1;
wire OVERFLOW1;
// DUT2
wire TXRDY2;
wire RXRDY2;
wire TX2;
wire RX2;
wire PARITY_ERR2;
wire FRAMING_ERR2;
wire OVERFLOW2;
wire RX_SEL;
// BFM memory interface
// not used
wire [31:0] BFM_ADDR;
wire [31:0] BFM_DATA;
wire [31:0] BFM_DATA_i;
wire BFM_RD;
wire BFM_WR;
// misc. signals
wire [255:0] GND256;
wire [31:0] GND32;
wire [7:0] GND8;
wire [4:0] GND5;
wire [3:0] GND4;
wire GND1;
reg [0:0] stopsim;
// APB ASSIGNS
assign PADDR = PADDR_apb_bfm_wide[4:0];
assign PSEL1 = PSEL_apb_bfm_wide[0];
assign PSEL2 = PSEL_apb_bfm_wide[1];
assign PWDATA = PWDATA_apb_bfm_wide[7:0];
assign PRDATA = ((PSEL1 == 1'b1)) ? PRDATA1 :
((PSEL2 == 1'b1)) ? PRDATA2 :
8'h00;
assign PRDATA_apb_bfm_wide[31:0] = {24'h000000, PRDATA[7:0]};
// PREADY and PSLVERR not used, tie off
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
// DUT
// pull-down for Framing Error Test
assign RX2 = ((RX_SEL == 1'b0)) ? TX1 :
1'b0;
// monitor flags / select signals in BFM
assign GP_IN_apb_bfm = {24'h000000, OVERFLOW2, PARITY_ERR2, TXRDY2, RXRDY2, OVERFLOW1, PARITY_ERR1, TXRDY1, RXRDY1};
assign RX_SEL = GP_OUT_apb_bfm[0];
// System clock
// System clock
initial SYSCLK_apb = 1'b0;
always
begin
#APB_MASTER_CLK_CYCLE_LO_TIME SYSCLK_apb = 1'b1;
#APB_MASTER_CLK_CYCLE_HI_TIME SYSCLK_apb = 1'b0;
end
// Main simulation
initial
begin: main_sim
SYSRSTN_apb = 0;
@ (posedge SYSCLK_apb); #TPD;
SYSRSTN_apb = 1;
@ (posedge SYSCLK_apb); #TPD;
// wait until BFM is finished
while (!(FINISHED_apb_bfm===1'b1))
begin
@ (posedge SYSCLK_apb); #TPD;
end
stopsim=1;
#1;
$stop;
end
// ------------------------------------------------------
// BFM register interface
// not used for this core
// End BFM register interface RTL
// ------------------------------------------------------
// BFM instantiation
// passing testbench parameters to BFM ARGVALUE* parameters
CoreUARTapb_0_CoreUARTapb_0_0_BFM_APB #(
.VECTFILE(APB_MASTER_VECTFILE),
.TPD(TPD),
.ARGVALUE0(FAMILY),
.ARGVALUE1(TX_FIFO),
.ARGVALUE2(RX_FIFO),
.ARGVALUE3(FIXEDMODE),
.ARGVALUE4(BAUD_VALUE),
.ARGVALUE5(PRG_BIT8),
.ARGVALUE6(PRG_PARITY),
.ARGVALUE7(RX_LEGACY_MODE),
.ARGVALUE8(USE_SOFT_FIFO)
) U_APB_MASTER(
.SYSCLK(SYSCLK_apb),
.SYSRSTN(SYSRSTN_apb),
.PCLK(PCLK),
.PRESETN(PRESETN),
.PADDR(PADDR_apb_bfm_wide),
.PSEL(PSEL_apb_bfm_wide),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PWDATA(PWDATA_apb_bfm_wide),
.PRDATA(PRDATA_apb_bfm_wide),
.PREADY(PREADY),
.PSLVERR(PSLVERR),
.INTERRUPT(GND256),
// NEED TO ADD GPIN
.GP_OUT(GP_OUT_apb_bfm),
.GP_IN(GP_IN_apb_bfm),
.EXT_WR(BFM_WR),
.EXT_RD(BFM_RD),
.EXT_ADDR(BFM_ADDR),
.EXT_DATA(BFM_DATA),
.EXT_WAIT(GND1),
.FINISHED(FINISHED_apb_bfm),
.FAILED(FAILED_apb_bfm)
);
// DUT1 (TX)
CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb #(
.FAMILY(FAMILY),
.TX_FIFO(TX_FIFO),
.RX_FIFO(RX_FIFO),
.FIXEDMODE(FIXEDMODE),
.BAUD_VALUE(BAUD_VALUE),
.PRG_BIT8(PRG_BIT8),
.PRG_PARITY(PRG_PARITY),
.RX_LEGACY_MODE(RX_LEGACY_MODE),
.BAUD_VAL_FRCTN(BAUD_VAL_FRCTN),
.BAUD_VAL_FRCTN_EN(BAUD_VAL_FRCTN_EN)
) DUT1(
.PRESETN(PRESETN),
.PCLK(PCLK),
.PSEL(PSEL1),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PRDATA(PRDATA1),
.PREADY(),
.PSLVERR(),
// OTHER SIGNALS
.TXRDY(TXRDY1),
.RXRDY(RXRDY1),
.PARITY_ERR(PARITY_ERR1),
.FRAMING_ERR(FRAMING_ERR1),
.OVERFLOW(OVERFLOW1),
.RX(RX1),
.TX(TX1)
);
// DUT2 (RX)
CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb #(
.FAMILY(FAMILY),
.TX_FIFO(TX_FIFO),
.RX_FIFO(RX_FIFO),
.FIXEDMODE(FIXEDMODE),
.BAUD_VALUE(BAUD_VALUE),
.PRG_BIT8(PRG_BIT8),
.PRG_PARITY(PRG_PARITY),
.RX_LEGACY_MODE(RX_LEGACY_MODE),
.BAUD_VAL_FRCTN(BAUD_VAL_FRCTN),
.BAUD_VAL_FRCTN_EN(BAUD_VAL_FRCTN_EN)
) DUT2(
.PRESETN(PRESETN),
.PCLK(PCLK),
.PSEL(PSEL2),
.PENABLE(PENABLE),
.PWRITE(PWRITE),
.PADDR(PADDR),
.PWDATA(PWDATA),
.PRDATA(PRDATA2),
.PREADY(),
.PSLVERR(),
// OTHER SIGNALS
.TXRDY(TXRDY2),
.RXRDY(RXRDY2),
.PARITY_ERR(PARITY_ERR2),
.FRAMING_ERR(FRAMING_ERR2),
.OVERFLOW(OVERFLOW2),
.RX(RX2),
.TX(TX2)
);
endmodule
// testbench

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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:13 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : CoreUARTapb_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Clock_gen.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Rx_async.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/Tx_async.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUART.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/CoreUARTapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core/fifo_256x8_g5.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/bfmtovec_compile.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/coreuart_usertb_apb_master.bfm
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/coreuart_usertb_include.bfm
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/mti/scripts/wave_vlog_amba.do
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/coreparameters.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbl.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahblapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbslave.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbslaveext.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_ahbtoapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apbslave.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apbslaveext.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_apbtoapb.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/amba_bfm/bfm_main.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/test/user/testbench.v

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component/work/Core_reset_pf/Core_reset_pf.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>Core_reset_pf</name><vendor/><library/><version/><fileSets><fileSet fileSetId="COMPONENT_FILESET"><file fileid="0"><name>../../Actel/DirectCore/CORERESET_PF/2.3.100/CORERESET_PF.cxf</name><userFileType>CXF</userFileType></file><file fileid="1"><name>./Core_reset_pf_0/Core_reset_pf_Core_reset_pf_0_CORERESET_PF.cxf</name><userFileType>CXF</userFileType></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="2"><name>./Core_reset_pf.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="OTHER_FILESET"><file fileid="3"><name>./Core_reset_pf.sdb</name><userFileType>SDB</userFileType></file><file fileid="4"><name>./Core_reset_pf_manifest.txt</name><userFileType>LOG</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>COMPONENT_FILESET</fileSetRef><fileSetRef>OTHER_FILESET</fileSetRef><name>OTHER</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel><category>SpiritDesign</category><function/><variation>SpiritDesign</variation><vendor>Actel</vendor><version>1.0</version><vendorExtension><type>SpiritDesign</type></vendorExtension><vendorExtension><state value="GENERATED"/></vendorExtension><vendorExtensions><componentRef library="DirectCore" name="CORERESET_PF" vendor="Actel" version="2.3.100"/><configuration><configurableElement referenceId="FAMILY" value="26"/><configurableElement referenceId="testbench" value="User"/></configuration></vendorExtensions><model><signals><signal><name>CLK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>EXT_RST_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>BANK_x_VDDI_STATUS</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>BANK_y_VDDI_STATUS</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>PLL_LOCK</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>SS_BUSY</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>INIT_DONE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FF_US_RESTORE</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FPGA_POR_N</name><direction>in</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>PLL_POWERDOWN_B</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal><signal><name>FABRIC_RESET_N</name><direction>out</direction><export>false</export><vendorExtensions><pad>false</pad><used>true</used></vendorExtensions></signal></signals></model></Component>

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component/work/Core_reset_pf/Core_reset_pf.sdb Normal file
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component/work/Core_reset_pf/Core_reset_pf.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:02 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of Core_reset_pf to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component Core_reset_pf
create_and_configure_core -core_vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -component_name {Core_reset_pf} -params { }
# Exporting Component Description of Core_reset_pf to TCL done
*/
// Core_reset_pf
module Core_reset_pf(
// Inputs
BANK_x_VDDI_STATUS,
BANK_y_VDDI_STATUS,
CLK,
EXT_RST_N,
FF_US_RESTORE,
FPGA_POR_N,
INIT_DONE,
PLL_LOCK,
SS_BUSY,
// Outputs
FABRIC_RESET_N,
PLL_POWERDOWN_B
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input BANK_x_VDDI_STATUS;
input BANK_y_VDDI_STATUS;
input CLK;
input EXT_RST_N;
input FF_US_RESTORE;
input FPGA_POR_N;
input INIT_DONE;
input PLL_LOCK;
input SS_BUSY;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output FABRIC_RESET_N;
output PLL_POWERDOWN_B;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire BANK_x_VDDI_STATUS;
wire BANK_y_VDDI_STATUS;
wire CLK;
wire EXT_RST_N;
wire FABRIC_RESET_N_net_0;
wire FF_US_RESTORE;
wire FPGA_POR_N;
wire INIT_DONE;
wire PLL_LOCK;
wire PLL_POWERDOWN_B_net_0;
wire SS_BUSY;
wire PLL_POWERDOWN_B_net_1;
wire FABRIC_RESET_N_net_1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign PLL_POWERDOWN_B_net_1 = PLL_POWERDOWN_B_net_0;
assign PLL_POWERDOWN_B = PLL_POWERDOWN_B_net_1;
assign FABRIC_RESET_N_net_1 = FABRIC_RESET_N_net_0;
assign FABRIC_RESET_N = FABRIC_RESET_N_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------Core_reset_pf_Core_reset_pf_0_CORERESET_PF - Actel:DirectCore:CORERESET_PF:2.3.100
Core_reset_pf_Core_reset_pf_0_CORERESET_PF Core_reset_pf_0(
// Inputs
.CLK ( CLK ),
.EXT_RST_N ( EXT_RST_N ),
.BANK_x_VDDI_STATUS ( BANK_x_VDDI_STATUS ),
.BANK_y_VDDI_STATUS ( BANK_y_VDDI_STATUS ),
.PLL_LOCK ( PLL_LOCK ),
.SS_BUSY ( SS_BUSY ),
.INIT_DONE ( INIT_DONE ),
.FF_US_RESTORE ( FF_US_RESTORE ),
.FPGA_POR_N ( FPGA_POR_N ),
// Outputs
.PLL_POWERDOWN_B ( PLL_POWERDOWN_B_net_0 ),
.FABRIC_RESET_N ( FABRIC_RESET_N_net_0 )
);
endmodule

1
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>Core_reset_pf_Core_reset_pf_0_CORERESET_PF</name><vendor/><library/><version/><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>test\corereset_pf_tb.v</name><userFileType>Verilog</userFileType><vendorExtensions><ModuleUnderTest>corereset_pf_tb</ModuleUnderTest><SimulationTime>-all</SimulationTime><requireUniquify/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="1"><name>core\corereset_pf.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: corereset_pf.v
// File history:
// <Revision number>: <Date>: <Comments>
// <Revision number>: <Date>: <Comments>
// <Revision number>: <Date>: <Comments>
//
// Description:
//
// <Description here>
//
// Targeted device: <Family::PolarFire> <Die::MPF300T_ES> <Package::FCG1152>
// Author: <Name>
//
///////////////////////////////////////////////////////////////////////////////////////////////////
//`timescale <time_units> / <precision>
module Core_reset_pf_Core_reset_pf_0_CORERESET_PF(CLK, EXT_RST_N, BANK_x_VDDI_STATUS,BANK_y_VDDI_STATUS,PLL_LOCK,SS_BUSY, INIT_DONE, FF_US_RESTORE,FPGA_POR_N, PLL_POWERDOWN_B, FABRIC_RESET_N);
input CLK,EXT_RST_N, BANK_x_VDDI_STATUS, PLL_LOCK, SS_BUSY, INIT_DONE, FF_US_RESTORE, BANK_y_VDDI_STATUS, FPGA_POR_N;
output PLL_POWERDOWN_B, FABRIC_RESET_N;
wire A;
wire B;
wire C;
wire D;
wire INTERNAL_RST;
reg dff_0 = 1'b1;
reg dff_1 = 1'b1;
reg dff_2 = 1'b1;
reg dff_3 = 1'b1;
reg dff_4 = 1'b1;
reg dff_5 = 1'b1;
reg dff_6 = 1'b1;
reg dff_7 = 1'b1;
reg dff_8 = 1'b1;
reg dff_9 = 1'b1;
reg dff_10 = 1'b1;
reg dff_11 = 1'b1;
reg dff_12 = 1'b1;
reg dff_13 = 1'b1;
reg dff_14 = 1'b1;
reg dff_15 = 1'b1;
assign A = !(!EXT_RST_N | !BANK_x_VDDI_STATUS);
assign B = !(!A | !PLL_LOCK);
assign C = !(!B & !SS_BUSY);
assign D = !(!C | !INIT_DONE);
assign INTERNAL_RST = !(!D & !FF_US_RESTORE);
assign PLL_POWERDOWN_B = !(!BANK_y_VDDI_STATUS | !FPGA_POR_N);
always@(posedge CLK or negedge INTERNAL_RST)
begin
if (!INTERNAL_RST)
begin
dff_0 <= 1'b0;
dff_1 <= 1'b0;
dff_2 <= 1'b0;
dff_3 <= 1'b0;
dff_3 <= 1'b0;
dff_4 <= 1'b0;
dff_5 <= 1'b0;
dff_6 <= 1'b0;
dff_7 <= 1'b0;
dff_8 <= 1'b0;
dff_9 <= 1'b0;
dff_10 <= 1'b0;
dff_11 <= 1'b0;
dff_12 <= 1'b0;
dff_13 <= 1'b0;
dff_14 <= 1'b0;
dff_15 <= 1'b0;
end
else
begin
dff_0 <= 1'b1;
dff_1 <= dff_0;
dff_2 <= dff_1;
dff_3 <= dff_2;
dff_4 <= dff_3;
dff_5 <= dff_4;
dff_6 <= dff_5;
dff_7 <= dff_6;
dff_8 <= dff_7;
dff_9 <= dff_8;
dff_10 <= dff_9;
dff_11 <= dff_10;
dff_12 <= dff_11;
dff_13 <= dff_12;
dff_14 <= dff_13;
dff_15 <= dff_14;
end
end
assign FABRIC_RESET_N = !(!dff_15 & !FF_US_RESTORE);
endmodule

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`timescale 1ns/100ps
module corereset_pf_tb;
parameter SYSCLK_PERIOD = 100;// 10MHZ
reg SYSCLK;
reg EXT_RST_N;
reg PLL_LOCK;
reg BANK_x_VDDI_STATUS;
reg BANK_y_VDDI_STATUS;
reg FPGA_POR_N;
reg SS_BUSY;
reg INIT_DONE;
reg FF_US_RESTORE;
wire FABRIC_RESET_N;
wire PLL_POWERDOWN_B;
initial
begin
SYSCLK = 1'b0;
end
//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
ext_rst();
PLL_LOCK_rst();
init_done_rst();
pll_powerdown();
$stop;
end
task ext_rst;
begin
$display("External Reset test :: time is %0t",$time);
EXT_RST_N = 1'b1;
PLL_LOCK = 1'b1;
SS_BUSY = 1'b1;
FF_US_RESTORE = 1'b1;
BANK_x_VDDI_STATUS = 1'b1;
BANK_y_VDDI_STATUS = 1'b1;
FPGA_POR_N= 1'b1;
INIT_DONE = 1'b1;
#100;
EXT_RST_N = 1'b0;
#100;
FF_US_RESTORE = 1'b0;
#100;
SS_BUSY = 1'b0;
#100;
if (FABRIC_RESET_N == 1'b0)
begin
$display("External Reset Test Success :: time is %0t",$time);
end
else
begin
$display("External Reset Test Failed :: time is %0t",$time);
end
#100;
EXT_RST_N = 1'b1;
begin
repeat(32)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
end
if (FABRIC_RESET_N == 1'b1)
begin
$display("External reset deassertion Success :: time is %0t",$time);
end
else
begin
$display("External reset deassertion error:: time is %0t",$time);
end
end
endtask
task PLL_LOCK_rst;
begin
$display("PLL_LOCK Reset test :: time is %0t",$time);
EXT_RST_N = 1'b1;
PLL_LOCK = 1'b1;
SS_BUSY = 1'b1;
FF_US_RESTORE = 1'b1;
BANK_x_VDDI_STATUS = 1'b1;
BANK_y_VDDI_STATUS = 1'b1;
FPGA_POR_N= 1'b1;
INIT_DONE = 1'b1;
#100;
PLL_LOCK = 1'b0;
#100;
FF_US_RESTORE = 1'b0;
#100;
SS_BUSY = 1'b0;
#100;
if (FABRIC_RESET_N == 1'b0)
begin
$display("PLL Lock Reset Test Success :: time is %0t",$time);
end
else
begin
$display("PLL Lock Reset Test Failed :: time is %0t",$time);
end
#100;
PLL_LOCK = 1'b1;
begin
repeat(32)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
end
if (FABRIC_RESET_N == 1'b1)
begin
$display("PLL lock deassertion Success :: time is %0t",$time);
end
else
begin
$display("PLL lock deassertion error:: time is %0t",$time);
end
end
endtask
task init_done_rst;
begin
$display("Init Done Reset test :: time is %0t",$time);
EXT_RST_N = 1'b1;
PLL_LOCK = 1'b1;
SS_BUSY = 1'b1;
FF_US_RESTORE = 1'b1;
BANK_x_VDDI_STATUS = 1'b1;
BANK_y_VDDI_STATUS = 1'b1;
FPGA_POR_N= 1'b1;
INIT_DONE = 1'b1;
#100;
INIT_DONE = 1'b0;
#100;
FF_US_RESTORE = 1'b0;
#100;
SS_BUSY = 1'b0;
#100;
if (FABRIC_RESET_N == 1'b0)
begin
$display("Init Done Reset Test Success :: time is %0t",$time);
end
else
begin
$display("Init Done Reset Test Failed :: time is %0t",$time);
end
#100
INIT_DONE = 1'b1;
begin
repeat(32)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
end
if (FABRIC_RESET_N == 1'b1)
begin
$display("INIT Done deassertion Success :: time is %0t",$time);
end
else
begin
$display("INIT Done deassertion error:: time is %0t",$time);
end
end
endtask
task pll_powerdown;
begin
$display("PLL_POWERDOWN_B TEST :: time is %0t",$time);
#100 BANK_y_VDDI_STATUS = 1'b0;
FPGA_POR_N= 1'b0;
#1;
if(PLL_POWERDOWN_B == 1'b0)
begin
$display("PLL POWERDOWN Success");
end
else
begin
$display("PLL POWERDOWN Error");
end
#100 BANK_y_VDDI_STATUS = 1'b1;
#1;
if(PLL_POWERDOWN_B == 1'b0)
begin
$display("PLL POWERDOWN Success");
end
else
begin
$display("PLL POWERDOWN Error");
end
#100 FPGA_POR_N = 1'b1;
#1;
if(PLL_POWERDOWN_B == 1'b1)
begin
$display("PLL POWERDOWN Success");
end
else
begin
$display("PLL POWERDOWN Error");
end
#100 BANK_y_VDDI_STATUS = 1'b0;
#1;
if(PLL_POWERDOWN_B == 1'b0)
begin
$display("PLL POWERDOWN Success");
end
else
begin
$display("PLL POWERDOWN Error");
end
end
endtask
//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
#(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;
//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test: CORERESET_PF
//////////////////////////////////////////////////////////////////////
Core_reset_pf_Core_reset_pf_0_CORERESET_PF CORERESET_PF_0 (
.CLK(SYSCLK),
.EXT_RST_N(EXT_RST_N),
.PLL_LOCK(PLL_LOCK),
.BANK_x_VDDI_STATUS(BANK_x_VDDI_STATUS),
.BANK_y_VDDI_STATUS(BANK_y_VDDI_STATUS),
.FPGA_POR_N(FPGA_POR_N),
.SS_BUSY(SS_BUSY),
.INIT_DONE(INIT_DONE),
.FF_US_RESTORE(FF_US_RESTORE),
// Outputs
.FABRIC_RESET_N(FABRIC_RESET_N ),
.PLL_POWERDOWN_B(PLL_POWERDOWN_B)
);
endmodule

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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:02 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : Core_reset_pf
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/Core_reset_pf/Core_reset_pf_0/core/corereset_pf.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/Core_reset_pf/Core_reset_pf.v
Stimulus files for all Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/Core_reset_pf/Core_reset_pf_0/test/corereset_pf_tb.v

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component/work/MIV_RV32_C0/MIV_RV32_C0.sdb Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:14 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of MIV_RV32_C0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component MIV_RV32_C0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -component_name {MIV_RV32_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:0" \
"AHB_START_ADDR_0:0x0" \
"AHB_START_ADDR_1:0x8000" \
"AHB_TARGET_MIRROR:false" \
"APB_END_ADDR_0:0xffff" \
"APB_END_ADDR_1:0x6fff" \
"APB_INITIATOR_TYPE:1" \
"APB_START_ADDR_0:0x0" \
"APB_START_ADDR_1:0x6000" \
"APB_TARGET_MIRROR:false" \
"AXI_END_ADDR_0:0xffff" \
"AXI_END_ADDR_1:0x6fff" \
"AXI_INITIATOR_TYPE:0" \
"AXI_START_ADDR_0:0x0" \
"AXI_START_ADDR_1:0x6000" \
"AXI_TARGET_MIRROR:false" \
"BOOTROM_DEST_ADDR_LOWER:0x0" \
"BOOTROM_DEST_ADDR_UPPER:0x4000" \
"BOOTROM_PRESENT:false" \
"BOOTROM_SRC_END_ADDR_LOWER:0x3fff" \
"BOOTROM_SRC_END_ADDR_UPPER:0x8000" \
"BOOTROM_SRC_START_ADDR_LOWER:0x0" \
"BOOTROM_SRC_START_ADDR_UPPER:0x8000" \
"C_EXT:true" \
"DEBUGGER:true" \
"ECC_ENABLE:false" \
"F_EXT:false" \
"FWD_REGS:false" \
"GEN_MUL_TYPE:0" \
"GPR_REGS:false" \
"I_REGS:false" \
"I_TRACE:false" \
"ICACHE_EN:false" \
"INTERNAL_MTIME:true" \
"INTERNAL_MTIME_IRQ:true" \
"M_EXT:true" \
"MI_I_MEM:false" \
"MIV_HART_ID:0x0" \
"MTIME_PRESCALER:100" \
"NO_MACC_BLK:false" \
"NUM_EXT_IRQS:0" \
"RECONFIG_BOOTROM:false" \
"RESET_VECTOR_ADDR_0:0x0" \
"RESET_VECTOR_ADDR_1:0x8000" \
"TAS_END_ADDR_0:0x3fff" \
"TAS_END_ADDR_1:0x4000" \
"TAS_START_ADDR_0:0x0" \
"TAS_START_ADDR_1:0x4000" \
"TCM_END_ADDR_0:0x8fff" \
"TCM_END_ADDR_1:0x8000" \
"TCM_PRESENT:true" \
"TCM_REGS:false" \
"TCM_START_ADDR_0:0x0" \
"TCM_START_ADDR_1:0x8000" \
"TCM_TAS_PRESENT:false" \
"VECTORED_INTERRUPTS:false" }
# Exporting Component Description of MIV_RV32_C0 to TCL done
*/
// MIV_RV32_C0
module MIV_RV32_C0(
// Inputs
APB_PRDATA,
APB_PREADY,
APB_PSLVERR,
CLK,
EXT_IRQ,
JTAG_TCK,
JTAG_TDI,
JTAG_TMS,
JTAG_TRSTN,
RESETN,
// Outputs
APB_PADDR,
APB_PENABLE,
APB_PSEL,
APB_PWDATA,
APB_PWRITE,
EXT_RESETN,
JTAG_TDO,
JTAG_TDO_DR,
TIME_COUNT_OUT
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input [31:0] APB_PRDATA;
input APB_PREADY;
input APB_PSLVERR;
input CLK;
input EXT_IRQ;
input JTAG_TCK;
input JTAG_TDI;
input JTAG_TMS;
input JTAG_TRSTN;
input RESETN;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [31:0] APB_PADDR;
output APB_PENABLE;
output APB_PSEL;
output [31:0] APB_PWDATA;
output APB_PWRITE;
output EXT_RESETN;
output JTAG_TDO;
output JTAG_TDO_DR;
output [63:0] TIME_COUNT_OUT;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire [31:0] APB_INITIATOR_PADDR;
wire APB_INITIATOR_PENABLE;
wire [31:0] APB_PRDATA;
wire APB_PREADY;
wire APB_INITIATOR_PSELx;
wire APB_PSLVERR;
wire [31:0] APB_INITIATOR_PWDATA;
wire APB_INITIATOR_PWRITE;
wire CLK;
wire EXT_IRQ;
wire EXT_RESETN_net_0;
wire JTAG_TCK;
wire JTAG_TDI;
wire JTAG_TDO_net_0;
wire JTAG_TDO_DR_net_0;
wire JTAG_TMS;
wire JTAG_TRSTN;
wire RESETN;
wire [63:0] TIME_COUNT_OUT_net_0;
wire EXT_RESETN_net_1;
wire [63:0] TIME_COUNT_OUT_net_1;
wire [31:0] APB_INITIATOR_PADDR_net_0;
wire APB_INITIATOR_PENABLE_net_0;
wire APB_INITIATOR_PWRITE_net_0;
wire [31:0] APB_INITIATOR_PWDATA_net_0;
wire APB_INITIATOR_PSELx_net_0;
wire JTAG_TDO_net_1;
wire JTAG_TDO_DR_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire [63:0] TIME_COUNT_IN_const_net_0;
wire GND_net;
wire VCC_net;
wire [5:0] MSYS_EI_const_net_0;
wire [1:0] AXI_BRESP_const_net_0;
wire [31:0] AXI_RDATA_const_net_0;
wire [1:0] AXI_RRESP_const_net_0;
wire [31:0] TAS_PADDR_const_net_0;
wire [31:0] TAS_PWDATA_const_net_0;
wire [31:0] AHB_HRDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign TIME_COUNT_IN_const_net_0 = 64'h0000000000000000;
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
assign MSYS_EI_const_net_0 = 6'h00;
assign AXI_BRESP_const_net_0 = 2'h0;
assign AXI_RDATA_const_net_0 = 32'h00000000;
assign AXI_RRESP_const_net_0 = 2'h0;
assign TAS_PADDR_const_net_0 = 32'h00000000;
assign TAS_PWDATA_const_net_0 = 32'h00000000;
assign AHB_HRDATA_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign EXT_RESETN_net_1 = EXT_RESETN_net_0;
assign EXT_RESETN = EXT_RESETN_net_1;
assign TIME_COUNT_OUT_net_1 = TIME_COUNT_OUT_net_0;
assign TIME_COUNT_OUT[63:0] = TIME_COUNT_OUT_net_1;
assign APB_INITIATOR_PADDR_net_0 = APB_INITIATOR_PADDR;
assign APB_PADDR[31:0] = APB_INITIATOR_PADDR_net_0;
assign APB_INITIATOR_PENABLE_net_0 = APB_INITIATOR_PENABLE;
assign APB_PENABLE = APB_INITIATOR_PENABLE_net_0;
assign APB_INITIATOR_PWRITE_net_0 = APB_INITIATOR_PWRITE;
assign APB_PWRITE = APB_INITIATOR_PWRITE_net_0;
assign APB_INITIATOR_PWDATA_net_0 = APB_INITIATOR_PWDATA;
assign APB_PWDATA[31:0] = APB_INITIATOR_PWDATA_net_0;
assign APB_INITIATOR_PSELx_net_0 = APB_INITIATOR_PSELx;
assign APB_PSEL = APB_INITIATOR_PSELx_net_0;
assign JTAG_TDO_net_1 = JTAG_TDO_net_0;
assign JTAG_TDO = JTAG_TDO_net_1;
assign JTAG_TDO_DR_net_1 = JTAG_TDO_DR_net_0;
assign JTAG_TDO_DR = JTAG_TDO_DR_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32 - Microsemi:MiV:MIV_RV32:3.1.200
MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32 #(
.AHB_END_ADDR_0 ( 'hffff ),
.AHB_END_ADDR_1 ( 'h8fff ),
.AHB_INITIATOR_TYPE ( 0 ),
.AHB_START_ADDR_0 ( 'h0 ),
.AHB_START_ADDR_1 ( 'h8000 ),
.AHB_TARGET_MIRROR ( 0 ),
.APB_END_ADDR_0 ( 'hffff ),
.APB_END_ADDR_1 ( 'h6fff ),
.APB_INITIATOR_TYPE ( 1 ),
.APB_START_ADDR_0 ( 'h0 ),
.APB_START_ADDR_1 ( 'h6000 ),
.APB_TARGET_MIRROR ( 0 ),
.AXI_END_ADDR_0 ( 'hffff ),
.AXI_END_ADDR_1 ( 'h6fff ),
.AXI_INITIATOR_TYPE ( 0 ),
.AXI_START_ADDR_0 ( 'h0 ),
.AXI_START_ADDR_1 ( 'h6000 ),
.AXI_TARGET_MIRROR ( 0 ),
.BOOTROM_DEST_ADDR_LOWER ( 'h0 ),
.BOOTROM_DEST_ADDR_UPPER ( 'h4000 ),
.BOOTROM_PRESENT ( 0 ),
.BOOTROM_SRC_END_ADDR_LOWER ( 'h3fff ),
.BOOTROM_SRC_END_ADDR_UPPER ( 'h8000 ),
.BOOTROM_SRC_START_ADDR_LOWER ( 'h0 ),
.BOOTROM_SRC_START_ADDR_UPPER ( 'h8000 ),
.C_EXT ( 1 ),
.DEBUGGER ( 1 ),
.ECC_ENABLE ( 0 ),
.F_EXT ( 0 ),
.FAMILY ( 26 ),
.FWD_REGS ( 0 ),
.GEN_MUL_TYPE ( 0 ),
.GPR_REGS ( 0 ),
.I_REGS ( 0 ),
.I_TRACE ( 0 ),
.ICACHE_EN ( 0 ),
.INTERNAL_MTIME ( 1 ),
.INTERNAL_MTIME_IRQ ( 1 ),
.M_EXT ( 1 ),
.MI_I_MEM ( 0 ),
.MIV_HART_ID ( 'h0 ),
.MTIME_PRESCALER ( 100 ),
.NO_MACC_BLK ( 0 ),
.NUM_EXT_IRQS ( 0 ),
.RECONFIG_BOOTROM ( 0 ),
.RESET_VECTOR_ADDR_0 ( 'h0 ),
.RESET_VECTOR_ADDR_1 ( 'h8000 ),
.TAS_END_ADDR_0 ( 'h3fff ),
.TAS_END_ADDR_1 ( 'h4000 ),
.TAS_START_ADDR_0 ( 'h0 ),
.TAS_START_ADDR_1 ( 'h4000 ),
.TCM_END_ADDR_0 ( 'h8fff ),
.TCM_END_ADDR_1 ( 'h8000 ),
.TCM_PRESENT ( 1 ),
.TCM_REGS ( 0 ),
.TCM_START_ADDR_0 ( 'h0 ),
.TCM_START_ADDR_1 ( 'h8000 ),
.TCM_TAS_PRESENT ( 0 ),
.VECTORED_INTERRUPTS ( 0 ) )
MIV_RV32_C0_0(
// Inputs
.TIME_COUNT_IN ( TIME_COUNT_IN_const_net_0 ), // tied to 64'h0000000000000000 from definition
.TMR_IRQ ( GND_net ), // tied to 1'b0 from definition
.EXT_IRQ ( EXT_IRQ ),
.JTAG_TRSTN ( JTAG_TRSTN ),
.JTAG_TCK ( JTAG_TCK ),
.JTAG_TDI ( JTAG_TDI ),
.JTAG_TMS ( JTAG_TMS ),
.APB_PREADY ( APB_PREADY ),
.APB_PRDATA ( APB_PRDATA ),
.APB_PSLVERR ( APB_PSLVERR ),
.TCM_CPU_ACCESS_DISABLE ( GND_net ), // tied to 1'b0 from definition
.TCM_TAS_ACCESS_DISABLE ( VCC_net ), // tied to 1'b1 from definition
.TAS_PADDR ( TAS_PADDR_const_net_0 ), // tied to 32'h00000000 from definition
.TAS_PSEL ( GND_net ), // tied to 1'b0 from definition
.TAS_PENABLE ( GND_net ), // tied to 1'b0 from definition
.TAS_PWRITE ( GND_net ), // tied to 1'b0 from definition
.TAS_PWDATA ( TAS_PWDATA_const_net_0 ), // tied to 32'h00000000 from definition
.AXI_ARREADY ( GND_net ), // tied to 1'b0 from definition
.AXI_RRESP ( AXI_RRESP_const_net_0 ), // tied to 2'h0 from definition
.AXI_RDATA ( AXI_RDATA_const_net_0 ), // tied to 32'h00000000 from definition
.AXI_RLAST ( GND_net ), // tied to 1'b0 from definition
.AXI_RID ( GND_net ), // tied to 1'b0 from definition
.AXI_RVALID ( GND_net ), // tied to 1'b0 from definition
.AXI_AWREADY ( GND_net ), // tied to 1'b0 from definition
.AXI_WREADY ( GND_net ), // tied to 1'b0 from definition
.AXI_BRESP ( AXI_BRESP_const_net_0 ), // tied to 2'h0 from definition
.AXI_BID ( GND_net ), // tied to 1'b0 from definition
.AXI_BVALID ( GND_net ), // tied to 1'b0 from definition
.AHB_HRDATA ( AHB_HRDATA_const_net_0 ), // tied to 32'h00000000 from definition
.AHB_HREADY ( VCC_net ), // tied to 1'b1 from definition
.AHB_HRESP ( GND_net ), // tied to 1'b0 from definition
.CLK ( CLK ),
.RESETN ( RESETN ),
.MSYS_EI ( MSYS_EI_const_net_0 ), // tied to 6'h00 from definition
// Outputs
.JTAG_TDO ( JTAG_TDO_net_0 ),
.JTAG_TDO_DR ( JTAG_TDO_DR_net_0 ),
.APB_PADDR ( APB_INITIATOR_PADDR ),
.APB_PSEL ( APB_INITIATOR_PSELx ),
.APB_PENABLE ( APB_INITIATOR_PENABLE ),
.APB_PWRITE ( APB_INITIATOR_PWRITE ),
.APB_PWDATA ( APB_INITIATOR_PWDATA ),
.TAS_PREADY ( ),
.TAS_PRDATA ( ),
.TAS_PSLVERR ( ),
.AXI_ARID ( ),
.AXI_ARADDR ( ),
.AXI_ARLEN ( ),
.AXI_ARSIZE ( ),
.AXI_ARBURST ( ),
.AXI_ARLOCK ( ),
.AXI_ARCACHE ( ),
.AXI_ARVALID ( ),
.AXI_RREADY ( ),
.AXI_AWID ( ),
.AXI_AWADDR ( ),
.AXI_AWLEN ( ),
.AXI_AWSIZE ( ),
.AXI_AWBURST ( ),
.AXI_AWLOCK ( ),
.AXI_AWCACHE ( ),
.AXI_AWPROT ( ),
.AXI_AWVALID ( ),
.AXI_WDATA ( ),
.AXI_WSTRB ( ),
.AXI_WLAST ( ),
.AXI_WID ( ),
.AXI_WVALID ( ),
.AXI_BREADY ( ),
.AHB_HADDR ( ),
.AHB_HBURST ( ),
.AHB_HMASTLOCK ( ),
.AHB_HPROT ( ),
.AHB_HSIZE ( ),
.AHB_HTRANS ( ),
.AHB_HWDATA ( ),
.AHB_HWRITE ( ),
.AXI_ARPROT ( ),
.AHB_HSEL ( ),
.EXT_RESETN ( EXT_RESETN_net_0 ),
.TIME_COUNT_OUT ( TIME_COUNT_OUT_net_0 ),
.TRACE_VALID ( ),
.TRACE_IADDR ( ),
.TRACE_INSN ( ),
.TRACE_PRIV ( ),
.TRACE_EXCEPTION ( ),
.TRACE_INTERRUPT ( ),
.TRACE_CAUSE ( ),
.TRACE_TVAL ( )
);
endmodule

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\miv_rv32.v</name><fileType>verilogSource</fileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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// Copyright (c) 2023, Microchip Corporation
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the <organization> nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL MICROCHIP CORPORATIONM BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// APACHE LICENSE
// Copyright (c) 2023, Microchip Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
// SVN Revision Information:
// SVN $Revision: $
// SVN $Date: $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
// 3.0.102 - development enhancement for MIV_WDT, HALTED top level o/p added (debug mode), to stall WDT when core halted during debug
//
////////////////////////////////////////////////////////////////////////////////
//`define RVFI
`timescale 1ns/10ps
module MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32
//********************************************************************************
// Parameter description
#(
parameter FAMILY = 26,
parameter [15:0] RESET_VECTOR_ADDR_1 = 16'h8000,
parameter [15:0] RESET_VECTOR_ADDR_0 = 16'h0000,
parameter DEBUGGER = 1'b1,
parameter I_TRACE = 1'b0,
parameter AXI_INITIATOR_TYPE = 0,
parameter AXI_TARGET_MIRROR = 0,
parameter [15:0] AXI_START_ADDR_1 = 16'h6000,
parameter [15:0] AXI_START_ADDR_0 = 16'h0000,
parameter [15:0] AXI_END_ADDR_1 = 16'h6FFF,
parameter [15:0] AXI_END_ADDR_0 = 16'hFFFF,
parameter AHB_INITIATOR_TYPE = 1,
parameter AHB_TARGET_MIRROR = 0,
parameter [15:0] AHB_START_ADDR_1 = 16'h8000,
parameter [15:0] AHB_START_ADDR_0 = 16'h0000,
parameter [15:0] AHB_END_ADDR_1 = 16'h8FFF,
parameter [15:0] AHB_END_ADDR_0 = 16'hFFFF,
parameter APB_INITIATOR_TYPE = 1,
parameter APB_TARGET_MIRROR = 0,
parameter [15:0] APB_START_ADDR_1 = 16'h7000,
parameter [15:0] APB_START_ADDR_0 = 16'h0000,
parameter [15:0] APB_END_ADDR_1 = 16'h7FFF,
parameter [15:0] APB_END_ADDR_0 = 16'hFFFF,
parameter TCM_PRESENT = 0,
parameter [15:0] TCM_START_ADDR_1 = 16'h4000,
parameter [15:0] TCM_START_ADDR_0 = 16'h0000,
parameter [15:0] TCM_END_ADDR_1 = 16'h4000,
parameter [15:0] TCM_END_ADDR_0 = 16'h3FFF,
parameter TCM_TAS_PRESENT = 0,
parameter [15:0] TAS_START_ADDR_1 = 16'h4000,
parameter [15:0] TAS_START_ADDR_0 = 16'h0000,
parameter [15:0] TAS_END_ADDR_1 = 16'h4000,
parameter [15:0] TAS_END_ADDR_0 = 16'h3FFF,
parameter C_EXT = 0,
parameter F_EXT = 0,
parameter M_EXT = 0,
parameter GEN_MUL_TYPE = 0,
parameter VECTORED_INTERRUPTS = 0,
parameter NUM_EXT_IRQS = 0,
parameter FWD_REGS = 0,
parameter ECC_ENABLE = 0,
parameter NO_MACC_BLK = 0,
parameter INTERNAL_MTIME = 1,
parameter INTERNAL_MTIME_IRQ = 1,
parameter MTIME_PRESCALER = 16'd100,
parameter GPR_REGS = 0,
parameter BOOTROM_PRESENT = 0,
parameter RECONFIG_BOOTROM = 0,
parameter [15:0] BOOTROM_SRC_START_ADDR_UPPER = 16'h8000,
parameter [15:0] BOOTROM_SRC_START_ADDR_LOWER = 16'h0000,
parameter [15:0] BOOTROM_SRC_END_ADDR_UPPER = 16'h8000,
parameter [15:0] BOOTROM_SRC_END_ADDR_LOWER = 16'h3FFF,
parameter [15:0] BOOTROM_DEST_ADDR_UPPER = 16'h4000,
parameter [15:0] BOOTROM_DEST_ADDR_LOWER = 16'h0000,
parameter ICACHE_EN = 0,
parameter MI_I_MEM = 0,
parameter TCM_REGS = 0,
parameter I_REGS = 0,
parameter MIV_HART_ID = 0
)
//********************************************************************************
// Port description
(
input CLK,
input RESETN,
output EXT_RESETN,
output TRACE_VALID,
output [31:0] TRACE_IADDR,
output [31:0] TRACE_INSN,
output [2:0] TRACE_PRIV,
output TRACE_EXCEPTION,
output TRACE_INTERRUPT,
output [5:0] TRACE_CAUSE,
output [31:0] TRACE_TVAL,
// CPU controls
input [63:0] TIME_COUNT_IN,
input TMR_IRQ,
input EXT_IRQ,
input [NUM_EXT_IRQS-1:0] MSYS_EI,
input JTAG_TRSTN,
input JTAG_TCK,
input JTAG_TDI,
input JTAG_TMS,
output [63:0] TIME_COUNT_OUT,
output JTAG_TDO,
output JTAG_TDO_DR,
// APB Initiator interface
input APB_PREADY,
input [31:0] APB_PRDATA,
input APB_PSLVERR,
output [31:0] APB_PADDR,
output APB_PSEL,
output APB_PENABLE,
output APB_PWRITE,
output [31:0] APB_PWDATA,
// TCM ACCESS
input TCM_CPU_ACCESS_DISABLE,
input TCM_TAS_ACCESS_DISABLE,
// APB Target interface (TCM direct access port)
input [31:0] TAS_PADDR,
input TAS_PSEL,
input TAS_PENABLE,
input TAS_PWRITE,
input [31:0] TAS_PWDATA,
output TAS_PREADY,
output [31:0] TAS_PRDATA,
output TAS_PSLVERR,
// AXI Initiator interface
output AXI_ARID,
output [31:0] AXI_ARADDR,
output [(AXI_INITIATOR_TYPE*4)-1:0] AXI_ARLEN,
output [2:0] AXI_ARSIZE,
output [1:0] AXI_ARBURST,
output [2-AXI_INITIATOR_TYPE:0] AXI_ARLOCK,
output [3:0] AXI_ARCACHE,
output [2:0] AXI_ARPROT,
input AXI_ARREADY,
output AXI_ARVALID,
input [1:0] AXI_RRESP,
input [31:0] AXI_RDATA,
input AXI_RLAST,
input AXI_RID,
output AXI_RREADY,
input AXI_RVALID,
output AXI_AWID,
output [31:0] AXI_AWADDR,
output [(AXI_INITIATOR_TYPE*4)-1:0] AXI_AWLEN,
output [2:0] AXI_AWSIZE,
output [1:0] AXI_AWBURST,
output [2-AXI_INITIATOR_TYPE:0] AXI_AWLOCK,
output [3:0] AXI_AWCACHE,
output [2:0] AXI_AWPROT,
input AXI_AWREADY,
output AXI_AWVALID,
output [31:0] AXI_WDATA,
output [3:0] AXI_WSTRB,
output AXI_WLAST,
output AXI_WID,
input AXI_WREADY,
output AXI_WVALID,
input [1:0] AXI_BRESP,
input AXI_BID,
output AXI_BREADY,
input AXI_BVALID,
// AHB Initiator interface
output AHB_HSEL, // Only used in mirrored i/f
output [31:0] AHB_HADDR,
output [2:0] AHB_HBURST,
output AHB_HMASTLOCK,
output [3:0] AHB_HPROT,
output [2:0] AHB_HSIZE,
output [1:0] AHB_HTRANS,
output [31:0] AHB_HWDATA,
output AHB_HWRITE,
input [31:0] AHB_HRDATA,
input AHB_HREADY,
input AHB_HRESP
);
//********************************************************************************
// Declarations
//miv_rv32 verison
localparam l_miv_rv32_version = 32'h030100C8;
//top level
localparam USE_BUS_PARITY = 0;
localparam TCM0_UDMA_PRESENT = 0;
localparam APB_REGISTER_IO = 1;
localparam CPU_ADDR_WIDTH = 32;
localparam AXI_ADDR_WIDTH = 32;
localparam APB_ADDR_WIDTH = 32;
localparam AHB_ADDR_WIDTH = 32;
localparam UDMA_PRESENT = 0;
localparam UDMA_CTRL_ADDR_WIDTH = 32;
localparam SUBSYS_CFG_ADDR_WIDTH = 32;
localparam TCM0_ADDR_WIDTH = 32;
localparam TCM0_CPU_I_PRESENT = 1;
localparam TCM0_CPU_D_PRESENT = 1;
localparam TCM0_USE_RAM_PARITY_BITS = 0;
localparam TCM_TAS_ADDR_WIDTH = 32;
localparam MAX_EXT_IRQS = 8;
localparam TCM1_ADDR_WIDTH = 32;
localparam TCM1_CPU_I_PRESENT = 1;
localparam TCM1_CPU_D_PRESENT = 1;
localparam TCM1_USE_RAM_PARITY_BITS = 0;
//subsys_package
localparam l_subsys_cfg_axi_present = (AXI_INITIATOR_TYPE != 0) ? 1: 0;
localparam l_subsys_cfg_ahb_present = (AHB_INITIATOR_TYPE != 0) ? 1: 0;
localparam l_subsys_cfg_apb_present = (APB_INITIATOR_TYPE != 0) ? 1: 0;
localparam l_subsys_cfg_hart_debug = DEBUGGER;
localparam l_hart_cfg_hw_debug = DEBUGGER;
localparam l_hart_cfg_num_triggers = (DEBUGGER) ? 2 : 0;
localparam l_subsys_cfg_tcm_tas_present = TCM_TAS_PRESENT;
localparam l_subsys_cfg_tcm0_tas_present = TCM_TAS_PRESENT;
localparam l_apb_start_addr = (APB_INITIATOR_TYPE != 0) ? {APB_START_ADDR_1, APB_START_ADDR_0} : 32'h0FFF_FFE0;
localparam l_apb_end_addr = (APB_INITIATOR_TYPE != 0) ? {APB_END_ADDR_1 , APB_END_ADDR_0 } : 32'h0FFF_FFE1;
localparam l_tcm0_start_addr = (TCM_PRESENT) ? {TCM_START_ADDR_1, TCM_START_ADDR_0} : 32'h0FFF_FFE2;
localparam l_tcm0_end_addr = (TCM_PRESENT) ? {TCM_END_ADDR_1 , TCM_END_ADDR_0 } : 32'h0FFF_FFE3;
localparam l_tcm_tas_tcm0_start_addr = (TCM_TAS_PRESENT) ? {TAS_START_ADDR_1, TAS_START_ADDR_0} : 32'h0FFF_FFE4;
localparam l_tcm_tas_tcm0_end_addr = (TCM_TAS_PRESENT) ? {TAS_END_ADDR_1 , TAS_END_ADDR_0} : 32'h0FFF_FFE5;
localparam l_axi_start_addr = (AXI_INITIATOR_TYPE != 0) ? {AXI_START_ADDR_1, AXI_START_ADDR_0} : 32'h0FFF_FFE6;
localparam l_axi_end_addr = (AXI_INITIATOR_TYPE != 0) ? {AXI_END_ADDR_1 , AXI_END_ADDR_0 } : 32'h0FFF_FFE7;
localparam l_ahb_start_addr = (AHB_INITIATOR_TYPE != 0) ? {AHB_START_ADDR_1, AHB_START_ADDR_0} : 32'h0FFF_FFE8;
localparam l_ahb_end_addr = (AHB_INITIATOR_TYPE != 0) ? {AHB_END_ADDR_1 , AHB_END_ADDR_0 } : 32'h0FFF_FFE9;
localparam l_tcm1_start_addr = 32'h0000_A000;
localparam l_tcm1_end_addr = 32'h0000_A200;
localparam l_tcm_tas_tcm1_start_addr = 32'h0FFF_FFEC;
localparam l_tcm_tas_tcm1_end_addr = 32'h0FFF_FFED;
localparam l_tcm_tas_udma_ctrl_start_addr = 32'h0FFF_FFEE;
localparam l_tcm_tas_udma_ctrl_end_addr = 32'h0FFF_FFEF;
localparam l_udma_ctrl_start_addr = 32'h0FFF_FFE0;
localparam l_udma_ctrl_end_addr = 32'h0FFF_FFF1;
localparam l_subsys_cfg_start_addr = 32'h0000_6000;
localparam l_subsys_cfg_end_addr = 32'h0000_6FFF;
localparam l_hart_cfg_time_count_width = 64;
localparam l_subsys_cfg_tcm0_present = TCM_PRESENT;
localparam l_subsys_cfg_tcm1_present = BOOTROM_PRESENT;
localparam BOOTROM_SRC_START_ADDR = {BOOTROM_SRC_START_ADDR_UPPER[15:0], BOOTROM_SRC_START_ADDR_LOWER[15:0]};
localparam BOOTROM_SRC_END_ADDR = {BOOTROM_SRC_END_ADDR_UPPER[15:0], BOOTROM_SRC_END_ADDR_LOWER[15:0]};
localparam BOOTROM_DEST_ADDR = {BOOTROM_DEST_ADDR_UPPER[15:0], BOOTROM_DEST_ADDR_LOWER[15:0]};
//core package
localparam reg[31:0] l_hart_reset_vector = (BOOTROM_PRESENT) ? l_tcm1_start_addr : {RESET_VECTOR_ADDR_1, RESET_VECTOR_ADDR_0};
localparam reg[27:0] l_hart_mtvec_offset = 28'h4;
localparam reg[31:0] l_hart_static_mtvec_base = (BOOTROM_PRESENT) ? BOOTROM_DEST_ADDR + l_hart_mtvec_offset : l_hart_reset_vector + l_hart_mtvec_offset;
localparam reg l_hart_cfg_static_mtvec_base = 1'b0; // SAR_125515
localparam reg l_hart_cfg_static_mtvec_mode = 1'b1;
localparam reg[1:0] l_hart_static_mtvec_mode = (VECTORED_INTERRUPTS) ? 2'b1 : 2'b0;
localparam l_hart_cfg_hw_compressed = C_EXT;
localparam l_hart_cfg_hw_sp_float = F_EXT;
localparam l_hart_cfg_hw_multiply_divide = M_EXT;
localparam l_hart_cfg_hw_macc_multiplier = (NO_MACC_BLK) ? 0 : GEN_MUL_TYPE;
localparam l_hart_num_sys_ext_irqs = NUM_EXT_IRQS;
localparam reg l_hart_cfg_lsu_fwd = FWD_REGS;
localparam reg l_hart_cfg_csr_fwd = FWD_REGS;
localparam reg l_hart_cfg_exu_fwd = FWD_REGS;
localparam reg l_hart_cfg_gpr_type = GPR_REGS;
// Other
localparam l_icache_en = ICACHE_EN & (l_subsys_cfg_axi_present | l_subsys_cfg_ahb_present);
localparam l_mi_i_mem = MI_I_MEM & (l_subsys_cfg_axi_present + l_subsys_cfg_ahb_present + l_subsys_cfg_tcm0_present > 1);
// Signals
wire debug_sys_reset;
wire [7:0] m_sys_ext_irq_int;
// Assignments
assign AHB_HSEL = 1'b1;
assign EXT_RESETN = RESETN & ~debug_sys_reset;
//Unused Signals
wire tcm_tas_udma_ctrl_irq;
wire APB_PADDR_P;
wire [3:0] APB_PWDATA_P;
wire [3:0] APB_PRDATA_P = 4'b0;
wire [3:0] APB_PSTRB;
wire [2:0] APB_PPROT;
wire AXI_AWADDR_P;
wire [3:0] AXI_WDATA_P;
wire AHB_HADDR_P;
wire [3:0] AHB_HWDATA_P;
wire AXI_ARADDR_P;
wire [3:0] TAS_PRDATA_P;
wire [2:0] TAS_PPROT = 3'b0;
wire tcm1_cpu_access_disable = 1'b0;
wire tcm1_dma_access_disable = 1'b0;
wire tcm1_tas_access_disable = 1'b0;
wire sys_parity_disable = 1'b0;
wire TAS_PADDR_P = 1'b0;
wire [3:0] TAS_PWDATA_P = 1'b0;
wire [3:0] AXI_RDATA_P = 4'b0;
wire [3:0] AHB_HRDATA_P = 4'b0;
wire [3:0] axi_arlen_int;
wire [3:0] axi_awlen_int;
wire axi_arlock_int;
wire axi_awlock_int;
assign AXI_ARLEN = (AXI_INITIATOR_TYPE == 2) ? {4'b0, axi_arlen_int} : (AXI_INITIATOR_TYPE == 1) ? axi_arlen_int : 2'b0; // always 1 beat from CPU
assign AXI_AWLEN = (AXI_INITIATOR_TYPE == 2) ? {4'b0, axi_awlen_int} : (AXI_INITIATOR_TYPE == 1) ? axi_awlen_int : 2'b0; // always 1 beat from CPU
assign AXI_ARLOCK = (AXI_INITIATOR_TYPE == 1) ? {1'b0, axi_arlock_int} : (AXI_INITIATOR_TYPE == 2) ? axi_arlock_int : 3'b0; // Always normal (no lock, no exclusive) for now
assign AXI_AWLOCK = (AXI_INITIATOR_TYPE == 1) ? {1'b0, axi_awlock_int} : (AXI_INITIATOR_TYPE == 2) ? axi_awlock_int : 3'b0; // Always normal (no lock, no exclusive) for now
generate
if(NUM_EXT_IRQS == MAX_EXT_IRQS) begin : gen_irq_8
assign m_sys_ext_irq_int = MSYS_EI[NUM_EXT_IRQS-1:0];
end else begin : ngen_gen_irq_8
assign m_sys_ext_irq_int = {{((MAX_EXT_IRQS)-NUM_EXT_IRQS){1'b0}}, MSYS_EI[NUM_EXT_IRQS-1:0]};
end
endgenerate
miv_rv32_ipcore
#(
.FAMILY (FAMILY ),
.CPU_ADDR_WIDTH (CPU_ADDR_WIDTH ),
.APB_ADDR_WIDTH (APB_ADDR_WIDTH ),
.APB_REGISTER_IO (APB_REGISTER_IO ),
.AHB_ADDR_WIDTH (AHB_ADDR_WIDTH ),
.UDMA_PRESENT (UDMA_PRESENT ),
.UDMA_CTRL_ADDR_WIDTH (UDMA_CTRL_ADDR_WIDTH ),
.SUBSYS_CFG_ADDR_WIDTH (SUBSYS_CFG_ADDR_WIDTH ),
.TCM0_ADDR_WIDTH (TCM0_ADDR_WIDTH ),
.TCM0_UDMA_PRESENT (TCM0_UDMA_PRESENT ),
.TCM0_CPU_I_PRESENT (TCM0_CPU_I_PRESENT ),
.TCM0_CPU_D_PRESENT (TCM0_CPU_D_PRESENT ),
.TCM0_USE_RAM_PARITY_BITS (TCM0_USE_RAM_PARITY_BITS ),
.TCM_TAS_ADDR_WIDTH (TCM_TAS_ADDR_WIDTH ),
.TCM1_ADDR_WIDTH (TCM1_ADDR_WIDTH ),
.TCM1_CPU_I_PRESENT (TCM1_CPU_I_PRESENT ),
.TCM1_CPU_D_PRESENT (TCM1_CPU_D_PRESENT ),
.TCM1_USE_RAM_PARITY_BITS (TCM1_USE_RAM_PARITY_BITS ),
.USE_BUS_PARITY (USE_BUS_PARITY ),
.l_subsys_cfg_axi_present (l_subsys_cfg_axi_present ),
.l_subsys_cfg_ahb_present (l_subsys_cfg_ahb_present ),
.l_subsys_cfg_apb_present (l_subsys_cfg_apb_present ),
.l_subsys_cfg_hart_debug (l_subsys_cfg_hart_debug ),
.l_hart_cfg_hw_debug (l_hart_cfg_hw_debug ),
.l_hart_cfg_num_triggers (l_hart_cfg_num_triggers ),
.l_subsys_cfg_tcm0_present (l_subsys_cfg_tcm0_present ),
.l_subsys_cfg_tcm1_present (l_subsys_cfg_tcm1_present ),
.l_axi_start_addr (l_axi_start_addr ),
.l_axi_end_addr (l_axi_end_addr ),
.l_apb_start_addr (l_apb_start_addr ),
.l_apb_end_addr (l_apb_end_addr ),
.l_ahb_start_addr (l_ahb_start_addr ),
.l_ahb_end_addr (l_ahb_end_addr ),
.l_udma_ctrl_start_addr (l_udma_ctrl_start_addr ),
.l_udma_ctrl_end_addr (l_udma_ctrl_end_addr ),
.l_subsys_cfg_start_addr (l_subsys_cfg_start_addr ),
.l_subsys_cfg_end_addr (l_subsys_cfg_end_addr ),
.l_tcm0_start_addr (l_tcm0_start_addr ),
.l_tcm0_end_addr (l_tcm0_end_addr ),
.l_tcm1_start_addr (l_tcm1_start_addr ),
.l_tcm1_end_addr (l_tcm1_end_addr ),
.l_tcm_tas_udma_ctrl_start_addr (l_tcm_tas_udma_ctrl_start_addr ),
.l_tcm_tas_udma_ctrl_end_addr (l_tcm_tas_udma_ctrl_end_addr ),
.l_tcm_tas_tcm0_start_addr (l_tcm_tas_tcm0_start_addr ),
.l_tcm_tas_tcm0_end_addr (l_tcm_tas_tcm0_end_addr ),
.l_tcm_tas_tcm1_start_addr (l_tcm_tas_tcm1_start_addr ),
.l_tcm_tas_tcm1_end_addr (l_tcm_tas_tcm1_end_addr ),
.l_subsys_cfg_tcm_tas_present (l_subsys_cfg_tcm_tas_present ),
.l_subsys_cfg_tcm0_tas_present (l_subsys_cfg_tcm0_tas_present ),
.l_hart_reset_vector (l_hart_reset_vector ),
.l_hart_cfg_hw_multiply_divide (l_hart_cfg_hw_multiply_divide ),
.l_hart_cfg_hw_compressed (l_hart_cfg_hw_compressed ),
.l_hart_cfg_hw_sp_float (l_hart_cfg_hw_sp_float ),
.l_hart_static_mtvec_base (l_hart_static_mtvec_base ),
.l_hart_cfg_static_mtvec_base (l_hart_cfg_static_mtvec_base ),
.l_hart_cfg_static_mtvec_mode (l_hart_cfg_static_mtvec_mode ),
.l_hart_static_mtvec_mode (l_hart_static_mtvec_mode ),
.l_hart_num_sys_ext_irqs (l_hart_num_sys_ext_irqs ),
.l_hart_cfg_hw_macc_multiplier (l_hart_cfg_hw_macc_multiplier ),
.l_hart_cfg_time_count_width (l_hart_cfg_time_count_width ),
.l_hart_cfg_lsu_fwd (l_hart_cfg_lsu_fwd ),
.l_hart_cfg_csr_fwd (l_hart_cfg_csr_fwd ),
.l_hart_cfg_exu_fwd (l_hart_cfg_exu_fwd ),
.l_hart_cfg_gpr_type (l_hart_cfg_gpr_type ),
.RAM_SB_IN_WIDTH (4 ),
.RAM_SB_OUT_WIDTH (4 ),
.ECC_ENABLE (ECC_ENABLE ),
.NO_MACC_BLK (NO_MACC_BLK ),
.INTERNAL_MTIME (INTERNAL_MTIME ),
.INTERNAL_MTIME_IRQ (INTERNAL_MTIME_IRQ ),
.MTIME_PRESCALER (MTIME_PRESCALER ),
.BOOTROM_SRC_START_ADDR (BOOTROM_SRC_START_ADDR ),
.BOOTROM_SRC_END_ADDR (BOOTROM_SRC_END_ADDR ),
.BOOTROM_DEST_ADDR (BOOTROM_DEST_ADDR ),
.RECONFIG_BOOTROM (RECONFIG_BOOTROM ),
.ICACHE_EN (l_icache_en ),
.MI_I_MEM (MI_I_MEM ),
.TCM_REGS (TCM_REGS ),
.I_REGS (I_REGS ),
.l_miv_rv32_version (l_miv_rv32_version )
)
u_ipcore_0
( .clk (CLK),
.resetn (RESETN),
.trace_valid (TRACE_VALID),
.trace_iaddr (TRACE_IADDR),
.trace_insn (TRACE_INSN),
.trace_priv (TRACE_PRIV),
.trace_exception (TRACE_EXCEPTION),
.trace_interrupt (TRACE_INTERRUPT),
.trace_cause (TRACE_CAUSE),
.trace_tval (TRACE_TVAL),
.mtime_count (TIME_COUNT_IN),
.m_timer_irq (TMR_IRQ),
.m_external_irq (EXT_IRQ),
.m_sys_ext_irq (m_sys_ext_irq_int),
.debug_sys_reset (debug_sys_reset),
.jtag_trst (JTAG_TRSTN),
.jtag_tck (JTAG_TCK),
.jtag_tdi (JTAG_TDI),
.jtag_tms (JTAG_TMS),
.jtag_tdo (JTAG_TDO),
.jtag_tdo_dr (JTAG_TDO_DR),
.apb_paddr (APB_PADDR),
.apb_paddr_p (APB_PADDR_P),
.apb_pprot (APB_PPROT),
.apb_psel (APB_PSEL),
.apb_penable (APB_PENABLE),
.apb_pwrite (APB_PWRITE),
.apb_pwdata (APB_PWDATA),
.apb_pwdata_p (APB_PWDATA_P),
.apb_pstrb (APB_PSTRB),
.apb_pready (APB_PREADY),
.apb_prdata (APB_PRDATA),
.apb_prdata_p (APB_PRDATA_P),
.apb_pslverr (APB_PSLVERR),
.tcm0_cpu_access_disable (TCM_CPU_ACCESS_DISABLE),
.tcm0_dma_access_disable (1'b1),
.tcm0_tas_access_disable (TCM_TAS_ACCESS_DISABLE),
.tcm1_cpu_access_disable (tcm1_cpu_access_disable),
.tcm1_dma_access_disable (tcm1_dma_access_disable),
.tcm1_tas_access_disable (tcm1_tas_access_disable),
.tcm_tas_paddr (TAS_PADDR),
.tcm_tas_paddr_p (TAS_PADDR_P),
.tcm_tas_pprot (TAS_PPROT),
.tcm_tas_psel (TAS_PSEL),
.tcm_tas_penable (TAS_PENABLE),
.tcm_tas_pwrite (TAS_PWRITE),
.tcm_tas_pwdata (TAS_PWDATA),
.tcm_tas_pwdata_p (TAS_PWDATA_P),
.tcm_tas_pready (TAS_PREADY),
.tcm_tas_prdata (TAS_PRDATA),
.tcm_tas_prdata_p (TAS_PRDATA_P),
.tcm_tas_pslverr (TAS_PSLVERR),
.tcm_tas_udma_ctrl_irq (TCM_TAS_UDMA_CTRL_IRQ),
.axi_aclk_en (1'b1),
.axi_arid (AXI_ARID),
.axi_araddr (AXI_ARADDR),
.axi_arlen (axi_arlen_int),
.axi_arsize (AXI_ARSIZE),
.axi_arburst (AXI_ARBURST),
.axi_arlock (axi_arlock_int),
.axi_arcache (AXI_ARCACHE),
.axi_arprot (AXI_ARPROT),
.axi_arready (AXI_ARREADY),
.axi_arvalid (AXI_ARVALID),
.axi_ar_addr_p (AXI_ARADDR_P),
.axi_rresp (AXI_RRESP),
.axi_rdata (AXI_RDATA),
.axi_rlast (AXI_RLAST),
.axi_rid (AXI_RID),
.axi_rready (AXI_RREADY),
.axi_rvalid (AXI_RVALID),
.axi_r_data_p (AXI_RDATA_P),
.axi_awid (AXI_AWID),
.axi_awaddr (AXI_AWADDR),
.axi_awlen (axi_awlen_int),
.axi_awsize (AXI_AWSIZE),
.axi_awburst (AXI_AWBURST),
.axi_awlock (axi_awlock_int),
.axi_awcache (AXI_AWCACHE),
.axi_awprot (AXI_AWPROT),
.axi_aw_addr_p (AXI_AWADDR_P),
.axi_awready (AXI_AWREADY),
.axi_awvalid (AXI_AWVALID),
.axi_wdata (AXI_WDATA),
.axi_wstrb (AXI_WSTRB),
.axi_wlast (AXI_WLAST),
.axi_wid (AXI_WID),
.axi_wready (AXI_WREADY),
.axi_wvalid (AXI_WVALID),
.axi_w_data_p (AXI_WDATA_P),
.axi_bresp (AXI_BRESP),
.axi_bid (AXI_BID),
.axi_bready (AXI_BREADY),
.axi_bvalid (AXI_BVALID),
.ahb_haddr (AHB_HADDR),
.ahb_haddr_p (AHB_HADDR_P),
.ahb_hburst (AHB_HBURST),
.ahb_hmastlock (AHB_HMASTLOCK),
.ahb_hprot (AHB_HPROT),
.ahb_hsize (AHB_HSIZE),
.ahb_htrans (AHB_HTRANS),
.ahb_hwdata (AHB_HWDATA),
.ahb_hwdata_p (AHB_HWDATA_P),
.ahb_hwrite (AHB_HWRITE),
.ahb_hrdata (AHB_HRDATA),
.ahb_hrdata_p (AHB_HRDATA_P),
.ahb_hready (AHB_HREADY),
.ahb_hresp (AHB_HRESP),
.tcm0_uncorrectable_ecc_error (),
.tcm1_uncorrectable_ecc_error (),
.gpr_uncorrectable_ecc_error (),
.hart_id (MIV_HART_ID),
.sys_parity_disable (sys_parity_disable),
.tcm0_ram_sb_out (),
.tcm0_ram_sb_in (4'b0),
.tcm1_ram_sb_out (),
.tcm1_ram_sb_in (4'b0),
.mtime_count_out (TIME_COUNT_OUT)
);
endmodule

19
component/work/MIV_RV32_C0/MIV_RV32_C0_manifest.txt Normal file
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@@ -0,0 +1,19 @@
Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:14 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : MIV_RV32_C0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_hart_cfg_pkg.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_pkg.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/pkg/miv_rv32_subsys_pkg.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/subsys_merged/miv_rv32_subsys_merged.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/hart_merged/miv_rv32_hart_merged.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.1.200/memory/miv_rv32_ram_singleport_lp_ecc.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/MIV_RV32_C0/MIV_RV32_C0_0/rtl/miv_rv32.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/MIV_RV32_C0/MIV_RV32_C0.v

1
component/work/PF_CCC_0/PF_CCC_0.cxf Normal file
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BIN
component/work/PF_CCC_0/PF_CCC_0.sdb Normal file
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333
component/work/PF_CCC_0/PF_CCC_0.v Normal file
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//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Apr 13 21:41:54 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////
// Component Description (Tcl)
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of PF_CCC_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component PF_CCC_0
create_and_configure_core -core_vlnv {Actel:SgCore:PF_CCC:2.2.220} -component_name {PF_CCC_0} -params {\
"DLL_CLK_0_BANKCLK_EN:false" \
"DLL_CLK_0_DEDICATED_EN:false" \
"DLL_CLK_0_FABCLK_EN:false" \
"DLL_CLK_1_BANKCLK_EN:false" \
"DLL_CLK_1_DEDICATED_EN:false" \
"DLL_CLK_1_FABCLK_EN:false" \
"DLL_CLK_P_EN:false" \
"DLL_CLK_P_OPTIONS_EN:false" \
"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
"DLL_CLK_REF_OPTIONS_EN:false" \
"DLL_CLK_S_EN:false" \
"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
"DLL_CLK_S_OPTIONS_EN:false" \
"DLL_DELAY4:0" \
"DLL_DYNAMIC_CODE_EN:false" \
"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
"DLL_EXPORT_PWRDWN:false" \
"DLL_FB_CLK:Primary" \
"DLL_FB_EN:false" \
"DLL_FINE_PHASE_CODE:0" \
"DLL_IN:1" \
"DLL_JITTER:0" \
"DLL_MODE:PHASE_REF_MODE" \
"DLL_ONLY_EN:false" \
"DLL_OUT_0:1" \
"DLL_OUT_1:1" \
"DLL_PRIM_PHASE:90" \
"DLL_PRIM_PHASE_CODE:0" \
"DLL_SEC_PHASE:90" \
"DLL_SEC_PHASE_CODE:0" \
"DLL_SELECTED_IN:Output2" \
"FF_REQUIRES_LOCK_EN_0:0" \
"GL0_0_BANKCLK_USED:false" \
"GL0_0_BYPASS:0" \
"GL0_0_BYPASS_EN:false" \
"GL0_0_DEDICATED_USED:false" \
"GL0_0_DIV:15" \
"GL0_0_DIVSTART:0" \
"GL0_0_DYNAMIC_PH:false" \
"GL0_0_EXPOSE_EN:false" \
"GL0_0_FABCLK_GATED_USED:false" \
"GL0_0_FABCLK_USED:true" \
"GL0_0_FREQ_SEL:false" \
"GL0_0_IS_USED:true" \
"GL0_0_OUT_FREQ:80" \
"GL0_0_PHASE_INDEX:0" \
"GL0_0_PHASE_SEL:false" \
"GL0_0_PLL_PHASE:0" \
"GL0_1_BANKCLK_USED:false" \
"GL0_1_BYPASS:0" \
"GL0_1_BYPASS_EN:false" \
"GL0_1_DEDICATED_USED:false" \
"GL0_1_DIV:1" \
"GL0_1_DIVSTART:0" \
"GL0_1_DYNAMIC_PH:false" \
"GL0_1_EXPOSE_EN:false" \
"GL0_1_FABCLK_USED:false" \
"GL0_1_FREQ_SEL:false" \
"GL0_1_IS_USED:true" \
"GL0_1_OUT_FREQ:100" \
"GL0_1_PHASE_INDEX:0" \
"GL0_1_PHASE_SEL:false" \
"GL0_1_PLL_PHASE:0" \
"GL1_0_BANKCLK_USED:false" \
"GL1_0_BYPASS:0" \
"GL1_0_BYPASS_EN:false" \
"GL1_0_DEDICATED_USED:false" \
"GL1_0_DIV:1" \
"GL1_0_DIVSTART:0" \
"GL1_0_DYNAMIC_PH:false" \
"GL1_0_EXPOSE_EN:false" \
"GL1_0_FABCLK_GATED_USED:false" \
"GL1_0_FABCLK_USED:true" \
"GL1_0_FREQ_SEL:false" \
"GL1_0_IS_USED:false" \
"GL1_0_OUT_FREQ:100" \
"GL1_0_PHASE_INDEX:0" \
"GL1_0_PHASE_SEL:false" \
"GL1_0_PLL_PHASE:0" \
"GL1_1_BANKCLK_USED:false" \
"GL1_1_BYPASS:0" \
"GL1_1_BYPASS_EN:false" \
"GL1_1_DEDICATED_USED:false" \
"GL1_1_DIV:1" \
"GL1_1_DIVSTART:0" \
"GL1_1_DYNAMIC_PH:false" \
"GL1_1_EXPOSE_EN:false" \
"GL1_1_FABCLK_USED:false" \
"GL1_1_FREQ_SEL:false" \
"GL1_1_IS_USED:false" \
"GL1_1_OUT_FREQ:0" \
"GL1_1_PHASE_INDEX:0" \
"GL1_1_PHASE_SEL:false" \
"GL1_1_PLL_PHASE:0" \
"GL2_0_BANKCLK_USED:false" \
"GL2_0_BYPASS:0" \
"GL2_0_BYPASS_EN:false" \
"GL2_0_DEDICATED_USED:false" \
"GL2_0_DIV:1" \
"GL2_0_DIVSTART:0" \
"GL2_0_DYNAMIC_PH:false" \
"GL2_0_EXPOSE_EN:false" \
"GL2_0_FABCLK_GATED_USED:false" \
"GL2_0_FABCLK_USED:true" \
"GL2_0_FREQ_SEL:false" \
"GL2_0_IS_USED:false" \
"GL2_0_OUT_FREQ:100" \
"GL2_0_PHASE_INDEX:0" \
"GL2_0_PHASE_SEL:false" \
"GL2_0_PLL_PHASE:0" \
"GL2_1_BANKCLK_USED:false" \
"GL2_1_BYPASS:0" \
"GL2_1_BYPASS_EN:false" \
"GL2_1_DEDICATED_USED:false" \
"GL2_1_DIV:1" \
"GL2_1_DIVSTART:0" \
"GL2_1_DYNAMIC_PH:false" \
"GL2_1_EXPOSE_EN:false" \
"GL2_1_FABCLK_USED:false" \
"GL2_1_FREQ_SEL:false" \
"GL2_1_IS_USED:false" \
"GL2_1_OUT_FREQ:0" \
"GL2_1_PHASE_INDEX:0" \
"GL2_1_PHASE_SEL:false" \
"GL2_1_PLL_PHASE:0" \
"GL3_0_BANKCLK_USED:false" \
"GL3_0_BYPASS:0" \
"GL3_0_BYPASS_EN:false" \
"GL3_0_DEDICATED_USED:false" \
"GL3_0_DIV:1" \
"GL3_0_DIVSTART:0" \
"GL3_0_DYNAMIC_PH:false" \
"GL3_0_EXPOSE_EN:false" \
"GL3_0_FABCLK_GATED_USED:false" \
"GL3_0_FABCLK_USED:true" \
"GL3_0_FREQ_SEL:false" \
"GL3_0_IS_USED:false" \
"GL3_0_OUT_FREQ:100" \
"GL3_0_PHASE_INDEX:0" \
"GL3_0_PHASE_SEL:false" \
"GL3_0_PLL_PHASE:0" \
"GL3_1_BANKCLK_USED:false" \
"GL3_1_BYPASS:0" \
"GL3_1_BYPASS_EN:false" \
"GL3_1_DEDICATED_USED:false" \
"GL3_1_DIV:1" \
"GL3_1_DIVSTART:0" \
"GL3_1_DYNAMIC_PH:false" \
"GL3_1_EXPOSE_EN:false" \
"GL3_1_FABCLK_USED:false" \
"GL3_1_FREQ_SEL:false" \
"GL3_1_IS_USED:false" \
"GL3_1_OUT_FREQ:0" \
"GL3_1_PHASE_INDEX:0" \
"GL3_1_PHASE_SEL:false" \
"GL3_1_PLL_PHASE:0" \
"PLL_ALLOW_CCC_EXT_FB:false" \
"PLL_BANDWIDTH_0:0" \
"PLL_BANDWIDTH_1:1" \
"PLL_BYPASS_GO_B_0:false" \
"PLL_BYPASS_GO_B_1:false" \
"PLL_BYPASS_POST_0:0" \
"PLL_BYPASS_POST_0_0:false" \
"PLL_BYPASS_POST_0_1:false" \
"PLL_BYPASS_POST_0_2:false" \
"PLL_BYPASS_POST_0_3:false" \
"PLL_BYPASS_POST_1:0" \
"PLL_BYPASS_POST_1_0:false" \
"PLL_BYPASS_POST_1_1:false" \
"PLL_BYPASS_POST_1_2:false" \
"PLL_BYPASS_POST_1_3:false" \
"PLL_BYPASS_PRE_0:0" \
"PLL_BYPASS_PRE_0_0:false" \
"PLL_BYPASS_PRE_0_1:false" \
"PLL_BYPASS_PRE_0_2:false" \
"PLL_BYPASS_PRE_0_3:false" \
"PLL_BYPASS_PRE_1:0" \
"PLL_BYPASS_PRE_1_0:false" \
"PLL_BYPASS_PRE_1_1:false" \
"PLL_BYPASS_PRE_1_2:false" \
"PLL_BYPASS_PRE_1_3:false" \
"PLL_BYPASS_SEL_0:0" \
"PLL_BYPASS_SEL_0_0:false" \
"PLL_BYPASS_SEL_0_1:false" \
"PLL_BYPASS_SEL_0_2:false" \
"PLL_BYPASS_SEL_0_3:false" \
"PLL_BYPASS_SEL_1:0" \
"PLL_BYPASS_SEL_1_0:false" \
"PLL_BYPASS_SEL_1_1:false" \
"PLL_BYPASS_SEL_1_2:false" \
"PLL_BYPASS_SEL_1_3:false" \
"PLL_DELAY_LINE_REF_FB_0:false" \
"PLL_DELAY_LINE_REF_FB_1:false" \
"PLL_DELAY_LINE_USED_0:false" \
"PLL_DELAY_LINE_USED_1:false" \
"PLL_DELAY_STEPS_0:1" \
"PLL_DELAY_STEPS_1:1" \
"PLL_DLL_CASCADED_EN:false" \
"PLL_DYNAMIC_CONTROL_EN_0:true" \
"PLL_DYNAMIC_CONTROL_EN_1:false" \
"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
"PLL_EXPORT_PWRDWN:true" \
"PLL_EXT_MAX_ADDR_0:128" \
"PLL_EXT_MAX_ADDR_1:128" \
"PLL_EXT_WAVE_SEL_0:0" \
"PLL_EXT_WAVE_SEL_1:0" \
"PLL_FB_CLK_0:GL0_0" \
"PLL_FB_CLK_1:GL0_1" \
"PLL_FEEDBACK_MODE_0:Post-VCO" \
"PLL_FEEDBACK_MODE_1:Post-VCO" \
"PLL_IN_FREQ_0:50" \
"PLL_IN_FREQ_1:100" \
"PLL_INT_MODE_EN_0:false" \
"PLL_INT_MODE_EN_1:false" \
"PLL_LOCK_COUNT_0:8" \
"PLL_LOCK_COUNT_1:8" \
"PLL_LP_REQUIRES_LOCK_EN_0:false" \
"PLL_LP_REQUIRES_LOCK_EN_1:false" \
"PLL_PLL_CASCADED_EN:false" \
"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
"PLL_REF_CLK_SEL_0:false" \
"PLL_REF_CLK_SEL_1:false" \
"PLL_REFDIV_0:1" \
"PLL_REFDIV_1:1" \
"PLL_RESET_ON_LOCK_0:true" \
"PLL_SPREAD_MODE_0:false" \
"PLL_SPREAD_MODE_1:false" \
"PLL_SSM_DEPTH_0:5" \
"PLL_SSM_DEPTH_1:5" \
"PLL_SSM_DIVVAL_0:1" \
"PLL_SSM_DIVVAL_1:1" \
"PLL_SSM_FREQ_0:32" \
"PLL_SSM_FREQ_1:32" \
"PLL_SSM_RAND_PATTERN_0:2" \
"PLL_SSM_RAND_PATTERN_1:2" \
"PLL_SSMD_EN_0:false" \
"PLL_SSMD_EN_1:false" \
"PLL_SYNC_CORNER_PLL:false" \
"PLL_SYNC_EN:false" \
"PLL_VCO_MODE_0:MIN_JITTER" \
"PLL_VCO_MODE_1:MIN_JITTER" }
# Exporting Component Description of PF_CCC_0 to TCL done
*/
// PF_CCC_0
module PF_CCC_0(
// Inputs
PLL_POWERDOWN_N_0,
REF_CLK_0,
// Outputs
OUT0_FABCLK_0,
PLL_LOCK_0
);
//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input PLL_POWERDOWN_N_0;
input REF_CLK_0;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output OUT0_FABCLK_0;
output PLL_LOCK_0;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire OUT0_FABCLK_0_net_0;
wire PLL_LOCK_0_net_0;
wire PLL_POWERDOWN_N_0;
wire REF_CLK_0;
wire OUT0_FABCLK_0_net_1;
wire PLL_LOCK_0_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire GND_net;
wire [10:0]DRI_CTRL_0_const_net_0;
wire [32:0]DRI_WDATA_0_const_net_0;
wire [10:0]DRI_CTRL_1_const_net_0;
wire [32:0]DRI_WDATA_1_const_net_0;
wire [10:0]DLL_DRI_CTRL_const_net_0;
wire [32:0]DLL_DRI_WDATA_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign DRI_CTRL_0_const_net_0 = 11'h000;
assign DRI_WDATA_0_const_net_0 = 33'h000000000;
assign DRI_CTRL_1_const_net_0 = 11'h000;
assign DRI_WDATA_1_const_net_0 = 33'h000000000;
assign DLL_DRI_CTRL_const_net_0 = 11'h000;
assign DLL_DRI_WDATA_const_net_0 = 33'h000000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign OUT0_FABCLK_0_net_1 = OUT0_FABCLK_0_net_0;
assign OUT0_FABCLK_0 = OUT0_FABCLK_0_net_1;
assign PLL_LOCK_0_net_1 = PLL_LOCK_0_net_0;
assign PLL_LOCK_0 = PLL_LOCK_0_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------PF_CCC_0_PF_CCC_0_0_PF_CCC - Actel:SgCore:PF_CCC:2.2.220
PF_CCC_0_PF_CCC_0_0_PF_CCC PF_CCC_0_0(
// Inputs
.REF_CLK_0 ( REF_CLK_0 ),
.PLL_POWERDOWN_N_0 ( PLL_POWERDOWN_N_0 ),
// Outputs
.OUT0_FABCLK_0 ( OUT0_FABCLK_0_net_0 ),
.PLL_LOCK_0 ( PLL_LOCK_0_net_0 )
);
endmodule

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_CCC_0_PF_CCC_0_0_PF_CCC</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_CCC_0_PF_CCC_0_0_PF_CCC.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
</fileSets>
</component>

8
component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc Normal file
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set_component PF_CCC_0_PF_CCC_0_0_PF_CCC
# Microchip Technology Inc.
# Date: 2026-Apr-13 21:41:54
#
# Base clock for PLL #0
create_clock -period 20 [ get_pins { pll_inst_0/REF_CLK_0 } ]
create_generated_clock -multiply_by 8 -divide_by 5 -source [ get_pins { pll_inst_0/REF_CLK_0 } ] -phase 0 [ get_pins { pll_inst_0/OUT0 } ]

68
component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_CCC_0_PF_CCC_0_0_PF_CCC(
OUT0_FABCLK_0,
PLL_LOCK_0,
REF_CLK_0,
PLL_POWERDOWN_N_0
);
output OUT0_FABCLK_0;
output PLL_LOCK_0;
input REF_CLK_0;
input PLL_POWERDOWN_N_0;
wire gnd_net, vcc_net, pll_inst_0_clkint_0;
CLKINT clkint_0 (.A(pll_inst_0_clkint_0), .Y(OUT0_FABCLK_0));
PLL #( .VCOFREQUENCY(4800), .DELAY_LINE_SIMULATION_MODE(""), .DATA_RATE(0.0)
, .FORMAL_NAME(""), .INTERFACE_NAME(""), .INTERFACE_LEVEL(3'b0)
, .SOFTRESET(1'b0), .SOFT_POWERDOWN_N(1'b1), .RFDIV_EN(1'b1), .OUT0_DIV_EN(1'b1)
, .OUT1_DIV_EN(1'b0), .OUT2_DIV_EN(1'b0), .OUT3_DIV_EN(1'b0), .SOFT_REF_CLK_SEL(1'b0)
, .RESET_ON_LOCK(1'b1), .BYPASS_CLK_SEL(4'b0), .BYPASS_GO_EN_N(1'b1)
, .BYPASS_PLL(4'b0), .BYPASS_OUT_DIVIDER(4'b0), .FF_REQUIRES_LOCK(1'b0)
, .FSE_N(1'b0), .FB_CLK_SEL_0(2'b00), .FB_CLK_SEL_1(1'b0), .RFDIV(6'b000001)
, .FRAC_EN(1'b0), .FRAC_DAC_EN(1'b0), .DIV0_RST_DELAY(3'b000)
, .DIV0_VAL(7'b0001111), .DIV1_RST_DELAY(3'b0), .DIV1_VAL(7'b1)
, .DIV2_RST_DELAY(3'b0), .DIV2_VAL(7'b1), .DIV3_RST_DELAY(3'b0)
, .DIV3_VAL(7'b1), .DIV3_CLK_SEL(1'b0), .BW_INT_CTRL(2'b0), .BW_PROP_CTRL(2'b11)
, .IREF_EN(1'b1), .IREF_TOGGLE(1'b0), .LOCK_CNT(4'b1000), .DESKEW_CAL_CNT(3'b110)
, .DESKEW_CAL_EN(1'b1), .DESKEW_CAL_BYPASS(1'b0), .SYNC_REF_DIV_EN(1'b0)
, .SYNC_REF_DIV_EN_2(1'b0), .OUT0_PHASE_SEL(3'b000), .OUT1_PHASE_SEL(3'b0)
, .OUT2_PHASE_SEL(3'b0), .OUT3_PHASE_SEL(3'b0), .SOFT_LOAD_PHASE_N(1'b1)
, .SSM_DIV_VAL(6'b1), .FB_FRAC_VAL(24'b0), .SSM_SPREAD_MODE(1'b0)
, .SSM_MODULATION(5'b00101), .FB_INT_VAL(12'b000001100000), .SSM_EN_N(1'b1)
, .SSM_EXT_WAVE_EN(2'b0), .SSM_EXT_WAVE_MAX_ADDR(8'b0), .SSM_RANDOM_EN(1'b0)
, .SSM_RANDOM_PATTERN_SEL(3'b0), .CDMUX0_SEL(2'b0), .CDMUX1_SEL(1'b1)
, .CDMUX2_SEL(1'b0), .CDELAY0_SEL(8'b0), .CDELAY0_EN(1'b0), .DRI_EN(1'b1)
) pll_inst_0 (.LOCK(PLL_LOCK_0), .SSCG_WAVE_TABLE_ADDR({nc0,
nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .DELAY_LINE_OUT_OF_RANGE()
, .POWERDOWN_N(PLL_POWERDOWN_N_0), .OUT0_EN(vcc_net), .OUT1_EN(
gnd_net), .OUT2_EN(gnd_net), .OUT3_EN(gnd_net), .REF_CLK_SEL(
gnd_net), .BYPASS_EN_N(vcc_net), .LOAD_PHASE_N(vcc_net),
.SSCG_WAVE_TABLE({gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net}), .PHASE_DIRECTION(gnd_net),
.PHASE_ROTATE(gnd_net), .PHASE_OUT0_SEL(gnd_net),
.PHASE_OUT1_SEL(gnd_net), .PHASE_OUT2_SEL(gnd_net),
.PHASE_OUT3_SEL(gnd_net), .DELAY_LINE_MOVE(gnd_net),
.DELAY_LINE_DIRECTION(gnd_net), .DELAY_LINE_WIDE(gnd_net),
.DELAY_LINE_LOAD(vcc_net), .REFCLK_SYNC_EN(gnd_net),
.REF_CLK_0(REF_CLK_0), .REF_CLK_1(gnd_net), .FB_CLK(gnd_net),
.OUT0(pll_inst_0_clkint_0), .OUT1(), .OUT2(), .OUT3(),
.DRI_CLK(gnd_net), .DRI_CTRL({gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net}), .DRI_WDATA({gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net, gnd_net,
gnd_net}), .DRI_ARST_N(vcc_net), .DRI_RDATA({nc8, nc9, nc10,
nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20,
nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30,
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40}),
.DRI_INTERRUPT());
VCC vcc_inst (.Y(vcc_net));
GND gnd_inst (.Y(gnd_net));
endmodule

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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:41:54 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : PF_CCC_0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0/PF_CCC_0.v
Constraint files:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.sdc

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.cxf Normal file
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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.sdb Normal file
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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.sdc Normal file
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set_component PF_IOD_CDR_C0
set_false_path -to [ get_pins { PF_LANECTRL_0/I_LANECTRL/RESET } ]
set_false_path -to [ get_pins { PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK_PAUSE } ]
set_false_path -to [ get_pins { PF_LANECTRL_0/I_LANECTRL/SWITCH } ]
set_false_path -to [ get_cells { CDR4_CNTL_TIP_0/dll_90_code*[*] } ]
set_false_path -to [ get_cells { CDR4_CNTL_TIP_0/valid_flag*[1] } ]
set_false_path -to [ get_cells { CDR4_CNTL_TIP_0/early_flag*[1] } ]
set_false_path -to [ get_cells { CDR4_CNTL_TIP_0/late_flag*[1] } ]
set_false_path -to [ get_pins { PF_IOD_CDR_TX_0/I_IOD_0/ARST_N } ]
set_false_path -to [ get_pins { PF_IOD_CDR_RX_P_0/I_IOD_0/ARST_N } ]
set_false_path -to [ get_pins { PF_IOD_CDR_RX_N_0/I_IOD_0/ARST_N } ]
set_false_path -to [ get_pins { PF_IOD_CDR_TX_0/I_IOD_0/RX_SYNC_RST } ]
set_false_path -to [ get_pins { PF_IOD_CDR_RX_P_0/I_IOD_0/RX_SYNC_RST } ]
set_false_path -to [ get_pins { PF_IOD_CDR_RX_N_0/I_IOD_0/RX_SYNC_RST } ]
set_false_path -to [ get_pins { PF_IOD_CDR_TX_0/I_IOD_0/TX_SYNC_RST } ]
set_false_path -to [ get_pins { PF_IOD_CDR_RX_P_0/I_IOD_0/TX_SYNC_RST } ]
set_false_path -to [ get_pins { PF_IOD_CDR_RX_N_0/I_IOD_0/TX_SYNC_RST } ]
set_false_path -from [ get_pins { PF_LANECTRL_0/I_LANECTRL/HS_IO_CLK* } ] -through [ get_pins { PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R } ]
set_false_path -through [ get_pins { PF_LANECTRL_0/I_LANECTRL/CDR_CLK } ]

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.v Normal file
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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0_cfg.sdb Normal file
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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0_manifest.txt Normal file
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Microchip Technology Inc. - Microchip Libero Software Release 2025.1 (Version 2025.1.0.14)
Date : Mon Apr 13 21:42:30 2026
Project : E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project
Component : PF_IOD_CDR_C0
Family : PolarFire
HDL source files for all Synthesis and Simulation tools:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/rtl/vlog/core/corecdr4_cntl_tip.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_LANECTRL_PAUSE_SYNC.v
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.v
Constraint files:
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0\PF_IOD_CDR_C0.sdc
E:/AbhishekV/rising/ethernet_reference_design/hw/Libero_Project/component/work/PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.sdc

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
</fileSets>
</component>

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD(
HS_IO_CLK,
TX_DATA_0,
OE_DATA_0,
RX_BIT_SLIP_0,
EYE_MONITOR_CLEAR_FLAGS_0,
DELAY_LINE_MOVE_0,
DELAY_LINE_DIRECTION_0,
DELAY_LINE_LOAD_0,
FAB_CLK,
CDR_CLK_A_SEL_8,
CDR_CLK_A_SEL_9,
CDR_CLK_A_SEL_10,
CDR_CLK_B_SEL,
CDR_CLR_NEXT_CLK_N,
SWITCH,
ODT_EN_0
);
input [0:0] HS_IO_CLK;
input [7:0] TX_DATA_0;
input [3:0] OE_DATA_0;
input RX_BIT_SLIP_0;
input EYE_MONITOR_CLEAR_FLAGS_0;
input DELAY_LINE_MOVE_0;
input DELAY_LINE_DIRECTION_0;
input DELAY_LINE_LOAD_0;
input FAB_CLK;
output CDR_CLK_A_SEL_8;
output CDR_CLK_A_SEL_9;
output CDR_CLK_A_SEL_10;
output [10:0] CDR_CLK_B_SEL;
output CDR_CLR_NEXT_CLK_N;
output SWITCH;
input ODT_EN_0;
wire GND_net, VCC_net;
VCC vcc_inst (.Y(VCC_net));
GND gnd_inst (.Y(GND_net));
IOD #( .DATA_RATE(1250.0), .FORMAL_NAME("LANECTRL_OVERLAY"), .INTERFACE_NAME("CDR4")
, .DELAY_LINE_SIMULATION_MODE("ENABLED"), .RESERVED_0(1'b0), .RX_CLK_EN(1'b0)
, .RX_CLK_INV(1'b0), .TX_CLK_EN(1'b0), .TX_CLK_INV(1'b0), .HS_IO_CLK_SEL(3'b000)
, .QDR_EN(1'b0), .EDGE_DETECT_EN(1'b0), .DELAY_LINE_MODE(2'b00)
, .RX_MODE(4'b0000), .EYE_MONITOR_MODE(1'b0), .DYN_DELAY_LINE_EN(1'b0)
, .FIFO_WR_EN(1'b0), .EYE_MONITOR_EN(1'b0), .TX_MODE(7'b0000000)
, .TX_CLK_SEL(2'b00), .TX_OE_MODE(3'b111), .TX_OE_CLK_INV(1'b0)
, .RX_DELAY_VAL(8'b00000000), .RX_DELAY_VAL_X2(1'b0), .TX_DELAY_VAL(8'b00000000)
, .EYE_MONITOR_WIDTH(3'b010), .EYE_MONITOR_WIDTH_SRC(1'b0), .RESERVED_1(1'b0)
, .DISABLE_LANECTRL_RESET(1'b1), .INPUT_DELAY_SEL(2'b00), .OEFF_EN_INV(1'b0)
, .INFF_EN_INV(1'b0), .OUTFF_EN_INV(1'b0) ) I_IOD_0 (
.EYE_MONITOR_EARLY(), .EYE_MONITOR_LATE(), .RX_DATA({nc0, nc1,
nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9}),
.DELAY_LINE_OUT_OF_RANGE(), .TX_DATA({TX_DATA_0[7],
TX_DATA_0[6], TX_DATA_0[5], TX_DATA_0[4], TX_DATA_0[3],
TX_DATA_0[2], TX_DATA_0[1], TX_DATA_0[0]}), .OE_DATA({
OE_DATA_0[3], OE_DATA_0[2], OE_DATA_0[1], OE_DATA_0[0]}),
.RX_BIT_SLIP(RX_BIT_SLIP_0), .EYE_MONITOR_CLEAR_FLAGS(
EYE_MONITOR_CLEAR_FLAGS_0), .DELAY_LINE_MOVE(DELAY_LINE_MOVE_0)
, .DELAY_LINE_DIRECTION(DELAY_LINE_DIRECTION_0),
.DELAY_LINE_LOAD(DELAY_LINE_LOAD_0), .RX_CLK(GND_net), .TX_CLK(
GND_net), .ODT_EN(ODT_EN_0), .INFF_SL(GND_net), .INFF_EN(
GND_net), .OUTFF_SL(GND_net), .OUTFF_EN(GND_net), .AL_N(
GND_net), .OEFF_LAT_N(GND_net), .OEFF_SD_N(GND_net),
.OEFF_AD_N(GND_net), .INFF_LAT_N(GND_net), .INFF_SD_N(GND_net),
.INFF_AD_N(GND_net), .OUTFF_LAT_N(GND_net), .OUTFF_SD_N(
GND_net), .OUTFF_AD_N(GND_net), .RX_P(), .RX_N(), .TX_DATA_9(
GND_net), .TX_DATA_8(GND_net), .ARST_N(VCC_net), .RX_SYNC_RST(
VCC_net), .TX_SYNC_RST(VCC_net), .HS_IO_CLK({GND_net, GND_net,
GND_net, GND_net, GND_net, HS_IO_CLK[0]}), .RX_DQS_90({GND_net,
GND_net}), .TX_DQS(GND_net), .TX_DQS_270(GND_net),
.FIFO_WR_PTR({GND_net, GND_net, GND_net}), .FIFO_RD_PTR({
GND_net, GND_net, GND_net}), .TX(), .OE(), .CDR_CLK(GND_net),
.CDR_NEXT_CLK(GND_net), .EYE_MONITOR_LANE_WIDTH({GND_net,
GND_net, GND_net}), .DDR_DO_READ(), .CDR_CLK_A_SEL_8(
CDR_CLK_A_SEL_8), .CDR_CLK_A_SEL_9(CDR_CLK_A_SEL_9),
.CDR_CLK_A_SEL_10(CDR_CLK_A_SEL_10), .CDR_CLK_B_SEL({
CDR_CLK_B_SEL[10], CDR_CLK_B_SEL[9], CDR_CLK_B_SEL[8],
CDR_CLK_B_SEL[7], CDR_CLK_B_SEL[6], CDR_CLK_B_SEL[5],
CDR_CLK_B_SEL[4], CDR_CLK_B_SEL[3], CDR_CLK_B_SEL[2],
CDR_CLK_B_SEL[1], CDR_CLK_B_SEL[0]}), .SWITCH(SWITCH),
.CDR_CLR_NEXT_CLK_N(CDR_CLR_NEXT_CLK_N), .TX_DATA_OUT_9(),
.TX_DATA_OUT_8(), .AL_N_OUT(), .OUTFF_SL_OUT(), .OUTFF_EN_OUT()
, .INFF_SL_OUT(), .INFF_EN_OUT(), .RX_CLK_OUT(), .TX_CLK_OUT());
endmodule

23
component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
</fileSets>
</component>

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD(
RX_N_0,
ARST_N,
RX_SYNC_RST,
TX_SYNC_RST,
HS_IO_CLK,
FIFO_WR_PTR,
FIFO_RD_PTR,
CDR_CLK,
EYE_MONITOR_CLEAR_FLAGS_0,
FAB_CLK,
EYE_MONITOR_EARLY_0,
EYE_MONITOR_LATE_0,
RX_DATA_0
);
input RX_N_0;
input ARST_N;
input RX_SYNC_RST;
input TX_SYNC_RST;
input [0:0] HS_IO_CLK;
input [2:0] FIFO_WR_PTR;
input [2:0] FIFO_RD_PTR;
input CDR_CLK;
input EYE_MONITOR_CLEAR_FLAGS_0;
input FAB_CLK;
output EYE_MONITOR_EARLY_0;
output EYE_MONITOR_LATE_0;
output [9:0] RX_DATA_0;
wire GND_net, VCC_net;
VCC vcc_inst (.Y(VCC_net));
GND gnd_inst (.Y(GND_net));
IOD #( .DATA_RATE(1250.0), .FORMAL_NAME("RX_N:NO_IOD_N_SIDE"), .INTERFACE_NAME("CDR4")
, .DELAY_LINE_SIMULATION_MODE("ENABLED"), .RESERVED_0(1'b0), .RX_CLK_EN(1'b1)
, .RX_CLK_INV(1'b0), .TX_CLK_EN(1'b0), .TX_CLK_INV(1'b0), .HS_IO_CLK_SEL(3'b110)
, .QDR_EN(1'b0), .EDGE_DETECT_EN(1'b0), .DELAY_LINE_MODE(2'b01)
, .RX_MODE(4'b0101), .EYE_MONITOR_MODE(1'b0), .DYN_DELAY_LINE_EN(1'b0)
, .FIFO_WR_EN(1'b1), .EYE_MONITOR_EN(1'b1), .TX_MODE(7'b0000000)
, .TX_CLK_SEL(2'b00), .TX_OE_MODE(3'b111), .TX_OE_CLK_INV(1'b0)
, .RX_DELAY_VAL(8'b00000000), .RX_DELAY_VAL_X2(1'b0), .TX_DELAY_VAL(8'b00000000)
, .EYE_MONITOR_WIDTH(3'b110), .EYE_MONITOR_WIDTH_SRC(1'b0), .RESERVED_1(1'b0)
, .DISABLE_LANECTRL_RESET(1'b0), .INPUT_DELAY_SEL(2'b01), .OEFF_EN_INV(1'b0)
, .INFF_EN_INV(1'b0), .OUTFF_EN_INV(1'b0) ) I_IOD_0 (
.EYE_MONITOR_EARLY(EYE_MONITOR_EARLY_0), .EYE_MONITOR_LATE(
EYE_MONITOR_LATE_0), .RX_DATA({RX_DATA_0[9], RX_DATA_0[8],
RX_DATA_0[7], RX_DATA_0[6], RX_DATA_0[5], RX_DATA_0[4],
RX_DATA_0[3], RX_DATA_0[2], RX_DATA_0[1], RX_DATA_0[0]}),
.DELAY_LINE_OUT_OF_RANGE(), .TX_DATA({GND_net, GND_net,
GND_net, GND_net, GND_net, GND_net, GND_net, GND_net}),
.OE_DATA({GND_net, GND_net, GND_net, GND_net}), .RX_BIT_SLIP(
GND_net), .EYE_MONITOR_CLEAR_FLAGS(EYE_MONITOR_CLEAR_FLAGS_0),
.DELAY_LINE_MOVE(GND_net), .DELAY_LINE_DIRECTION(GND_net),
.DELAY_LINE_LOAD(GND_net), .RX_CLK(FAB_CLK), .TX_CLK(GND_net),
.ODT_EN(GND_net), .INFF_SL(GND_net), .INFF_EN(GND_net),
.OUTFF_SL(GND_net), .OUTFF_EN(GND_net), .AL_N(GND_net),
.OEFF_LAT_N(GND_net), .OEFF_SD_N(GND_net), .OEFF_AD_N(GND_net),
.INFF_LAT_N(GND_net), .INFF_SD_N(GND_net), .INFF_AD_N(GND_net),
.OUTFF_LAT_N(GND_net), .OUTFF_SD_N(GND_net), .OUTFF_AD_N(
GND_net), .RX_P(), .RX_N(RX_N_0), .TX_DATA_9(GND_net),
.TX_DATA_8(GND_net), .ARST_N(ARST_N), .RX_SYNC_RST(RX_SYNC_RST)
, .TX_SYNC_RST(TX_SYNC_RST), .HS_IO_CLK({GND_net, GND_net,
GND_net, GND_net, GND_net, HS_IO_CLK[0]}), .RX_DQS_90({GND_net,
GND_net}), .TX_DQS(GND_net), .TX_DQS_270(GND_net),
.FIFO_WR_PTR({FIFO_WR_PTR[2], FIFO_WR_PTR[1], FIFO_WR_PTR[0]}),
.FIFO_RD_PTR({FIFO_RD_PTR[2], FIFO_RD_PTR[1], FIFO_RD_PTR[0]}),
.TX(), .OE(), .CDR_CLK(CDR_CLK), .CDR_NEXT_CLK(GND_net),
.EYE_MONITOR_LANE_WIDTH({GND_net, GND_net, GND_net}),
.DDR_DO_READ(), .CDR_CLK_A_SEL_8(), .CDR_CLK_A_SEL_9(),
.CDR_CLK_A_SEL_10(), .CDR_CLK_B_SEL({nc0, nc1, nc2, nc3, nc4,
nc5, nc6, nc7, nc8, nc9, nc10}), .SWITCH(),
.CDR_CLR_NEXT_CLK_N(), .TX_DATA_OUT_9(), .TX_DATA_OUT_8(),
.AL_N_OUT(), .OUTFF_SL_OUT(), .OUTFF_EN_OUT(), .INFF_SL_OUT(),
.INFF_EN_OUT(), .RX_CLK_OUT(), .TX_CLK_OUT());
endmodule

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
</fileSets>
</component>

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD(
RX_P_0,
ARST_N,
RX_SYNC_RST,
TX_SYNC_RST,
HS_IO_CLK,
FIFO_WR_PTR,
FIFO_RD_PTR,
CDR_CLK,
RX_BIT_SLIP_0,
EYE_MONITOR_CLEAR_FLAGS_0,
FAB_CLK,
EYE_MONITOR_EARLY_0,
EYE_MONITOR_LATE_0,
RX_DATA_0
);
input RX_P_0;
input ARST_N;
input RX_SYNC_RST;
input TX_SYNC_RST;
input [0:0] HS_IO_CLK;
input [2:0] FIFO_WR_PTR;
input [2:0] FIFO_RD_PTR;
input CDR_CLK;
input RX_BIT_SLIP_0;
input EYE_MONITOR_CLEAR_FLAGS_0;
input FAB_CLK;
output EYE_MONITOR_EARLY_0;
output EYE_MONITOR_LATE_0;
output [9:0] RX_DATA_0;
wire GND_net, VCC_net;
VCC vcc_inst (.Y(VCC_net));
GND gnd_inst (.Y(GND_net));
IOD #( .DATA_RATE(1250.0), .FORMAL_NAME("RX_P:NO_IOD_N_SIDE"), .INTERFACE_NAME("CDR4")
, .DELAY_LINE_SIMULATION_MODE("ENABLED"), .RESERVED_0(1'b0), .RX_CLK_EN(1'b1)
, .RX_CLK_INV(1'b0), .TX_CLK_EN(1'b0), .TX_CLK_INV(1'b0), .HS_IO_CLK_SEL(3'b110)
, .QDR_EN(1'b0), .EDGE_DETECT_EN(1'b0), .DELAY_LINE_MODE(2'b01)
, .RX_MODE(4'b0101), .EYE_MONITOR_MODE(1'b0), .DYN_DELAY_LINE_EN(1'b0)
, .FIFO_WR_EN(1'b1), .EYE_MONITOR_EN(1'b1), .TX_MODE(7'b0000000)
, .TX_CLK_SEL(2'b00), .TX_OE_MODE(3'b111), .TX_OE_CLK_INV(1'b0)
, .RX_DELAY_VAL(8'b00000000), .RX_DELAY_VAL_X2(1'b0), .TX_DELAY_VAL(8'b00000000)
, .EYE_MONITOR_WIDTH(3'b101), .EYE_MONITOR_WIDTH_SRC(1'b0), .RESERVED_1(1'b0)
, .DISABLE_LANECTRL_RESET(1'b0), .INPUT_DELAY_SEL(2'b00), .OEFF_EN_INV(1'b0)
, .INFF_EN_INV(1'b0), .OUTFF_EN_INV(1'b0) ) I_IOD_0 (
.EYE_MONITOR_EARLY(EYE_MONITOR_EARLY_0), .EYE_MONITOR_LATE(
EYE_MONITOR_LATE_0), .RX_DATA({RX_DATA_0[9], RX_DATA_0[8],
RX_DATA_0[7], RX_DATA_0[6], RX_DATA_0[5], RX_DATA_0[4],
RX_DATA_0[3], RX_DATA_0[2], RX_DATA_0[1], RX_DATA_0[0]}),
.DELAY_LINE_OUT_OF_RANGE(), .TX_DATA({GND_net, GND_net,
GND_net, GND_net, GND_net, GND_net, GND_net, GND_net}),
.OE_DATA({GND_net, GND_net, GND_net, GND_net}), .RX_BIT_SLIP(
RX_BIT_SLIP_0), .EYE_MONITOR_CLEAR_FLAGS(
EYE_MONITOR_CLEAR_FLAGS_0), .DELAY_LINE_MOVE(GND_net),
.DELAY_LINE_DIRECTION(GND_net), .DELAY_LINE_LOAD(GND_net),
.RX_CLK(FAB_CLK), .TX_CLK(GND_net), .ODT_EN(GND_net), .INFF_SL(
GND_net), .INFF_EN(GND_net), .OUTFF_SL(GND_net), .OUTFF_EN(
GND_net), .AL_N(GND_net), .OEFF_LAT_N(GND_net), .OEFF_SD_N(
GND_net), .OEFF_AD_N(GND_net), .INFF_LAT_N(GND_net),
.INFF_SD_N(GND_net), .INFF_AD_N(GND_net), .OUTFF_LAT_N(GND_net)
, .OUTFF_SD_N(GND_net), .OUTFF_AD_N(GND_net), .RX_P(RX_P_0),
.RX_N(), .TX_DATA_9(GND_net), .TX_DATA_8(GND_net), .ARST_N(
ARST_N), .RX_SYNC_RST(RX_SYNC_RST), .TX_SYNC_RST(TX_SYNC_RST),
.HS_IO_CLK({GND_net, GND_net, GND_net, GND_net, GND_net,
HS_IO_CLK[0]}), .RX_DQS_90({GND_net, GND_net}), .TX_DQS(
GND_net), .TX_DQS_270(GND_net), .FIFO_WR_PTR({FIFO_WR_PTR[2],
FIFO_WR_PTR[1], FIFO_WR_PTR[0]}), .FIFO_RD_PTR({FIFO_RD_PTR[2],
FIFO_RD_PTR[1], FIFO_RD_PTR[0]}), .TX(), .OE(), .CDR_CLK(
CDR_CLK), .CDR_NEXT_CLK(GND_net), .EYE_MONITOR_LANE_WIDTH({
GND_net, GND_net, GND_net}), .DDR_DO_READ(), .CDR_CLK_A_SEL_8()
, .CDR_CLK_A_SEL_9(), .CDR_CLK_A_SEL_10(), .CDR_CLK_B_SEL({nc0,
nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10}), .SWITCH(),
.CDR_CLR_NEXT_CLK_N(), .TX_DATA_OUT_9(), .TX_DATA_OUT_8(),
.AL_N_OUT(), .OUTFF_SL_OUT(), .OUTFF_EN_OUT(), .INFF_SL_OUT(),
.INFF_EN_OUT(), .RX_CLK_OUT(), .TX_CLK_OUT());
endmodule

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.cxf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<component>
<vendor></vendor>
<library></library>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD</name>
<version></version>
<hwModel>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
</views>
</hwModel>
<fileSets>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v</name>
<userFileType>verilogSource</userFileType>
</file>
</fileSet>
</fileSets>
</component>

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component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v Normal file
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`timescale 1 ns/100 ps
// Version: 2025.1 2025.1.0.14
module PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD(
ARST_N,
RX_SYNC_RST,
TX_SYNC_RST,
HS_IO_CLK,
TX_0,
OE_0,
TX_DATA_0,
OE_DATA_0,
FAB_CLK,
ODT_EN_0
);
input ARST_N;
input RX_SYNC_RST;
input TX_SYNC_RST;
input [0:0] HS_IO_CLK;
output TX_0;
output OE_0;
input [9:0] TX_DATA_0;
input [3:0] OE_DATA_0;
input FAB_CLK;
input ODT_EN_0;
wire GND_net, VCC_net, tx_data_0_9, tx_data_0_8;
IOD #( .DATA_RATE(1250.0), .FORMAL_NAME("TX:NO_IOD_N_SIDE"), .INTERFACE_NAME("CDR4")
, .DELAY_LINE_SIMULATION_MODE("ENABLED"), .RESERVED_0(1'b0), .RX_CLK_EN(1'b0)
, .RX_CLK_INV(1'b0), .TX_CLK_EN(1'b1), .TX_CLK_INV(1'b0), .HS_IO_CLK_SEL(3'b000)
, .QDR_EN(1'b0), .EDGE_DETECT_EN(1'b0), .DELAY_LINE_MODE(2'b00)
, .RX_MODE(4'b0000), .EYE_MONITOR_MODE(1'b0), .DYN_DELAY_LINE_EN(1'b0)
, .FIFO_WR_EN(1'b0), .EYE_MONITOR_EN(1'b0), .TX_MODE(7'b1000101)
, .TX_CLK_SEL(2'b01), .TX_OE_MODE(3'b000), .TX_OE_CLK_INV(1'b0)
, .RX_DELAY_VAL(8'b00000000), .RX_DELAY_VAL_X2(1'b0), .TX_DELAY_VAL(8'b00000000)
, .EYE_MONITOR_WIDTH(3'b010), .EYE_MONITOR_WIDTH_SRC(1'b0), .RESERVED_1(1'b0)
, .DISABLE_LANECTRL_RESET(1'b0), .INPUT_DELAY_SEL(2'b00), .OEFF_EN_INV(1'b0)
, .INFF_EN_INV(1'b0), .OUTFF_EN_INV(1'b0) ) I_IOD_98_0 (
.EYE_MONITOR_EARLY(), .EYE_MONITOR_LATE(), .RX_DATA({nc0, nc1,
nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9}),
.DELAY_LINE_OUT_OF_RANGE(), .TX_DATA({TX_DATA_0[9],
TX_DATA_0[8], GND_net, GND_net, GND_net, GND_net, GND_net,
GND_net}), .OE_DATA({GND_net, GND_net, GND_net, GND_net}),
.RX_BIT_SLIP(GND_net), .EYE_MONITOR_CLEAR_FLAGS(GND_net),
.DELAY_LINE_MOVE(GND_net), .DELAY_LINE_DIRECTION(GND_net),
.DELAY_LINE_LOAD(GND_net), .RX_CLK(GND_net), .TX_CLK(GND_net),
.ODT_EN(GND_net), .INFF_SL(), .INFF_EN(), .OUTFF_SL(),
.OUTFF_EN(), .AL_N(), .OEFF_LAT_N(), .OEFF_SD_N(), .OEFF_AD_N()
, .INFF_LAT_N(), .INFF_SD_N(), .INFF_AD_N(), .OUTFF_LAT_N(),
.OUTFF_SD_N(), .OUTFF_AD_N(), .RX_P(GND_net), .RX_N(),
.TX_DATA_9(GND_net), .TX_DATA_8(GND_net), .ARST_N(VCC_net),
.RX_SYNC_RST(), .TX_SYNC_RST(), .HS_IO_CLK({GND_net, GND_net,
GND_net, GND_net, GND_net, GND_net}), .RX_DQS_90({GND_net,
GND_net}), .TX_DQS(GND_net), .TX_DQS_270(GND_net),
.FIFO_WR_PTR({GND_net, GND_net, GND_net}), .FIFO_RD_PTR({
GND_net, GND_net, GND_net}), .TX(), .OE(), .CDR_CLK(GND_net),
.CDR_NEXT_CLK(), .EYE_MONITOR_LANE_WIDTH({GND_net, GND_net,
GND_net}), .DDR_DO_READ(), .CDR_CLK_A_SEL_8(),
.CDR_CLK_A_SEL_9(), .CDR_CLK_A_SEL_10(), .CDR_CLK_B_SEL({nc10,
nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20}),
.SWITCH(), .CDR_CLR_NEXT_CLK_N(), .TX_DATA_OUT_9(tx_data_0_9),
.TX_DATA_OUT_8(tx_data_0_8), .AL_N_OUT(), .OUTFF_SL_OUT(),
.OUTFF_EN_OUT(), .INFF_SL_OUT(), .INFF_EN_OUT(), .RX_CLK_OUT(),
.TX_CLK_OUT());
VCC vcc_inst (.Y(VCC_net));
GND gnd_inst (.Y(GND_net));
IOD #( .DATA_RATE(1250.0), .FORMAL_NAME("TX:NO_IOD_N_SIDE"), .INTERFACE_NAME("CDR4")
, .DELAY_LINE_SIMULATION_MODE("ENABLED"), .RESERVED_0(1'b0), .RX_CLK_EN(1'b0)
, .RX_CLK_INV(1'b0), .TX_CLK_EN(1'b1), .TX_CLK_INV(1'b0), .HS_IO_CLK_SEL(3'b000)
, .QDR_EN(1'b0), .EDGE_DETECT_EN(1'b0), .DELAY_LINE_MODE(2'b00)
, .RX_MODE(4'b0000), .EYE_MONITOR_MODE(1'b0), .DYN_DELAY_LINE_EN(1'b0)
, .FIFO_WR_EN(1'b0), .EYE_MONITOR_EN(1'b0), .TX_MODE(7'b1000101)
, .TX_CLK_SEL(2'b01), .TX_OE_MODE(3'b000), .TX_OE_CLK_INV(1'b0)
, .RX_DELAY_VAL(8'b00000000), .RX_DELAY_VAL_X2(1'b0), .TX_DELAY_VAL(8'b00000000)
, .EYE_MONITOR_WIDTH(3'b010), .EYE_MONITOR_WIDTH_SRC(1'b0), .RESERVED_1(1'b0)
, .DISABLE_LANECTRL_RESET(1'b0), .INPUT_DELAY_SEL(2'b00), .OEFF_EN_INV(1'b0)
, .INFF_EN_INV(1'b0), .OUTFF_EN_INV(1'b0) ) I_IOD_0 (
.EYE_MONITOR_EARLY(), .EYE_MONITOR_LATE(), .RX_DATA({nc21,
nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30}),
.DELAY_LINE_OUT_OF_RANGE(), .TX_DATA({TX_DATA_0[7],
TX_DATA_0[6], TX_DATA_0[5], TX_DATA_0[4], TX_DATA_0[3],
TX_DATA_0[2], TX_DATA_0[1], TX_DATA_0[0]}), .OE_DATA({
OE_DATA_0[3], OE_DATA_0[2], OE_DATA_0[1], OE_DATA_0[0]}),
.RX_BIT_SLIP(GND_net), .EYE_MONITOR_CLEAR_FLAGS(GND_net),
.DELAY_LINE_MOVE(GND_net), .DELAY_LINE_DIRECTION(GND_net),
.DELAY_LINE_LOAD(GND_net), .RX_CLK(GND_net), .TX_CLK(FAB_CLK),
.ODT_EN(ODT_EN_0), .INFF_SL(GND_net), .INFF_EN(GND_net),
.OUTFF_SL(GND_net), .OUTFF_EN(GND_net), .AL_N(GND_net),
.OEFF_LAT_N(GND_net), .OEFF_SD_N(GND_net), .OEFF_AD_N(GND_net),
.INFF_LAT_N(GND_net), .INFF_SD_N(GND_net), .INFF_AD_N(GND_net),
.OUTFF_LAT_N(GND_net), .OUTFF_SD_N(GND_net), .OUTFF_AD_N(
GND_net), .RX_P(), .RX_N(), .TX_DATA_9(tx_data_0_9),
.TX_DATA_8(tx_data_0_8), .ARST_N(ARST_N), .RX_SYNC_RST(
RX_SYNC_RST), .TX_SYNC_RST(TX_SYNC_RST), .HS_IO_CLK({GND_net,
GND_net, GND_net, GND_net, GND_net, HS_IO_CLK[0]}), .RX_DQS_90({
GND_net, GND_net}), .TX_DQS(GND_net), .TX_DQS_270(GND_net),
.FIFO_WR_PTR({GND_net, GND_net, GND_net}), .FIFO_RD_PTR({
GND_net, GND_net, GND_net}), .TX(TX_0), .OE(OE_0), .CDR_CLK(
GND_net), .CDR_NEXT_CLK(GND_net), .EYE_MONITOR_LANE_WIDTH({
GND_net, GND_net, GND_net}), .DDR_DO_READ(), .CDR_CLK_A_SEL_8()
, .CDR_CLK_A_SEL_9(), .CDR_CLK_A_SEL_10(), .CDR_CLK_B_SEL({
nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39, nc40,
nc41}), .SWITCH(), .CDR_CLR_NEXT_CLK_N(), .TX_DATA_OUT_9(),
.TX_DATA_OUT_8(), .AL_N_OUT(), .OUTFF_SL_OUT(), .OUTFF_EN_OUT()
, .INFF_SL_OUT(), .INFF_EN_OUT(), .RX_CLK_OUT(), .TX_CLK_OUT());
endmodule

1
component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.cxf Normal file
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@@ -0,0 +1 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL</name><vendor/><library/><version/><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>PF_LANECTRL_PAUSE_SYNC.v</name><userFileType>Verilog</userFileType><vendorExtensions><requireUniquify/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>

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