working FIFO and TPSRAM without packet flter
This commit is contained in:
1
component/Actel/DirectCore/CORETSE/4.0.124/CORETSE.cxf
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1
component/Actel/DirectCore/CORETSE/4.0.124/CORETSE.cxf
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@@ -0,0 +1 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CORETSE</name><vendor>Actel</vendor><library>DirectCore</library><version>4.0.124</version><fileSets><fileSet fileSetId="DESIGNER_FILESET"><file fileid="0"><name>Constraints\CoreTSE.sdc</name><userFileType>SDC</userFileType></file><file fileid="1"><name>Constraints\CoreTSE_mdc.sdc</name><userFileType>SDC</userFileType></file></fileSet><fileSet fileSetId="STIMULUS_FILESET"><file fileid="2"><name>rtl\vlog\test\user\tbi\testbench.v</name><fileType>verilogSource</fileType><vendorExtensions><ModuleUnderTest>testbench</ModuleUnderTest><SimulationTime>-all</SimulationTime></vendorExtensions></file><file fileid="3"><name>rtl\vlog\test\user\tbi\CoreTSE_tb.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"><file fileid="5"><name>coreparameters.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>mti\scripts\wave.do</name><userFileType>DO</userFileType><vendorExtensions><IncludeInRunDo/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="7"><name>rtl\vlog\core_evaluation\CoreTSE.v</name><userFileType>Verilog</userFileType></file><file fileid="8"><name>rtl\vlog\core_evaluation\include.v</name><fileType>verilogSource</fileType><vendorExtensions><isIncludeFile/></vendorExtensions></file></fileSet></fileSets><hwModel><views><view><fileSetRef>DESIGNER_FILESET</fileSetRef><name>DESIGNER</name></view><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>
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@@ -0,0 +1,27 @@
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set GMII 0
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if {$GMII == 1} {
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create_clock -name PCLK -period 12.5 [get_ports {PCLK}]
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create_clock -name MTXCLK -period 12.5 [get_ports {MTXCLK}]
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create_clock -name MRXCLK -period 12.5 [get_ports {MRXCLK}]
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create_clock -name TXCLK -period 8 [get_ports {TXCLK}]
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create_clock -name RXCLK -period 8 [get_ports {RXCLK}]
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set_clock_groups -asynchronous -group {TXCLK } \
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-group {RXCLK } \
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-group {PCLK} \
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-group {MTXCLK MRXCLK}
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} else {
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create_clock -name PCLK -period 12.5 [get_ports {PCLK}]
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create_clock -name MTXCLK -period 12.5 [get_ports {MTXCLK}]
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create_clock -name MRXCLK -period 12.5 [get_ports {MRXCLK}]
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create_clock -name TXCLK -period 8 [get_ports {TXCLK}]
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create_clock -name RXCLK -period 8 [get_ports {RXCLK}]
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create_clock -name TBI_TX_CLK -period 8 [get_ports {TBI_TX_CLK}]
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create_clock -name TBI_RX_CLK -period 8 [get_ports {TBI_RX_CLK}]
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set_clock_groups -asynchronous -group {TXCLK TBI_TX_CLK} \
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-group {RXCLK TBI_RX_CLK} \
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-group {PCLK MGMT_CLK} \
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-group {MTXCLK MRXCLK}
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}
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set_false_path -through [ get_nets {CORETSE_C0_0/CORETSE_C0_0/PRESETN } ]
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@@ -0,0 +1 @@
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create_generated_clock -name {MGMT_CLK} -add -master_clock PCLK -divide_by 8 -source [ get_ports { PCLK } ] [ get_pins { CORETSE_C0_0/CORETSE_C0_0/CoreTSE_TOP_INST/tsmac_top_U0/pe_mcxmac_U0/CTSE_PEMGT_1/mdc } ]
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19
component/Actel/DirectCore/CORETSE/4.0.124/coreparameters.v
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19
component/Actel/DirectCore/CORETSE/4.0.124/coreparameters.v
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@@ -0,0 +1,19 @@
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//--------------------------------------------------------------------
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// Created by Microsemi SmartDesign Mon Apr 13 21:41:11 2026
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// Parameters for CORETSE
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//--------------------------------------------------------------------
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parameter ECC_ENABLE = 0;
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parameter FAMILY = 26;
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parameter GMII_TBI = 1;
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parameter HDL_license = "E";
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parameter HOST_INTERFACE = 0;
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parameter MDIO_PHYID = 18;
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parameter PACKET_SIZE = 11;
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parameter SAL = 1;
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parameter SLIP_ENABLE = 0;
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parameter STATS = 1;
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parameter testbench = "User";
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parameter TXRX_INTR_ENABLE = 1;
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parameter WoL = 1;
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103
component/Actel/DirectCore/CORETSE/4.0.124/mti/scripts/wave.do
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103
component/Actel/DirectCore/CORETSE/4.0.124/mti/scripts/wave.do
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@@ -0,0 +1,103 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/FAMILY
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/GMII_TBI
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/PACKET_SIZE
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/SAL
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/WoL
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/STATS
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/MDIO_PHYID
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/SLIP_ENABLE
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add wave -noupdate -group Parameters -radix unsigned /testbench/dut_top/RXLEN_CNT
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXCLK
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXRDY
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXACPT
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXSOF
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXEOF
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXDAT
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXBYTEVALID
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXCFRM
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add wave -noupdate -expand -group {MAC TX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MTXHWM
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXCLK
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXRDY
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXACPT
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXSOF
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXEOF
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXDAT
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXBYTEVALID
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add wave -noupdate -expand -group {MAC RX DATA PATH I/F} -radix hexadecimal /testbench/dut_top/MRXLEN
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/GTXCLK
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXCLK
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXCLK
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXEN
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXD
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/TXER
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXDV
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXD
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/RXER
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/CRS
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add wave -noupdate -group {GMII I/F} -radix hexadecimal /testbench/dut_top/COL
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_TX_CLK
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_RX_CLK
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TCG
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/RCG
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_TX_VALID
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_RX_VALID
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/TBI_RX_READY
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/SIGNAL_DETECT
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/RX_SLIP
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/SYNC
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/ANX_STATE
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add wave -noupdate -group {TBI I/F} -radix hexadecimal /testbench/dut_top/RCG_ERROR
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add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDC
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add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDI
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add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDO
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add wave -noupdate -group {MDIO I/F} -radix hexadecimal /testbench/dut_top/MDOEN
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PCLK
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PRESETN
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PADDR
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PSEL
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PENABLE
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PWRITE
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PWDATA
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PREADY
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PRDATA
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add wave -noupdate -group {APB I/F} -radix hexadecimal /testbench/dut_top/PSLVERR
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TCLK
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTVALID
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTREADY
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTSOF
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTEOF
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTDATA
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTKEEP
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add wave -noupdate -group {AXI4S Target I/F} -radix hexadecimal /testbench/dut_top/AXI4S_TTLAST
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ICLK
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITVALID
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITLAST
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITREADY
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITSOF
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITEOF
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITDATA
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITKEEP
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add wave -noupdate -group {AXI4S Initiator I/F} -radix hexadecimal /testbench/dut_top/AXI4S_ITUSER
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add wave -noupdate -group {MISC Signals} -radix hexadecimal /testbench/dut_top/TSM_INTR
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add wave -noupdate -group {MISC Signals} -radix hexadecimal /testbench/dut_top/TSM_CONTROL
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add wave -noupdate -group {MISC Signals} -radix hexadecimal /testbench/dut_top/STBP
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {0 ps} 0}
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quietly wave cursor active 0
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configure wave -namecolwidth 227
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ps
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update
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WaveRestoreZoom {0 ps} {241501050 ps}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,167 @@
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//`define MCXMAC_SGMII_ON //Default mode enabled
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//`define MCXMAC_SAL_ON //enable SAL support in tsMac
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//`define MCXMAC_PTP_ON //enable PTP support in tsMac
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//`define MCXMAC_STATS_ON //enable Stats counter module
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//`define MCXMAC_WOL_ON //enable WakeOnLane feature of MAC core
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//`define MSGMII_PARALLEL_COMMA_ALIGNMENT //enable sgmii-CommaDetect logic
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//`define TABITS 12 //mac-fifo TxBuffer addr-width, For depth of the fifo
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//`define RABITS 12 //mac-fifo RxBuffer addr-width, For depth of the fifo
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//`define MII_PHYID 5'h1E //Address of local MDIO target, for registers in SGMII module
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//`define FPGA_TIMING_CLOSER
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`define HST_SELECT_MAHBE 3'b011 // HSTADX range 0x180 - 0x19C
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`define HST_SELECT_PTP 3'b100 // HSTADX range 0x200 - 0x27F
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`define HST_SELECT_EEE 5'b10_100 // HSTADX range 0x280 - 0x29F
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`define HST_SELECT_AVB 5'b10_101 // HSTADX range 0x2A0 - 0x
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// MAHBe address map
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`define ADDR_LEF_TXCTRL 0
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`define ADDR_LEF_TXDESC 1
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`define ADDR_LEF_TXSTAT 2
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`define ADDR_LEF_RXCTRL 3
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`define ADDR_LEF_RXDESC 4
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`define ADDR_LEF_RXSTAT 5
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`define ADDR_LEF_IMASK 6
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`define ADDR_LEF_INTR 7
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`define ADDR_AVB_TXCTRL 8
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`define ADDR_AVB_TXDESC 9
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`define ADDR_AVB_TXSTAT 10
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`define ADDR_AVB_RXCTRL 11
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`define ADDR_AVB_RXDESC 12
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`define ADDR_AVB_RXSTAT 13
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`define ADDR_AVB_IMASK 14
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`define ADDR_AVB_INTR 15
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//============================================
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// for 1 queue
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//============================================
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`define ADDR_TX_CMD_REG 0
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`define ADDR_TX_CDP_0 1
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`define ADDR_TX_STS_REG 2
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`define ADDR_RX_CMD_REG 3
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`define ADDR_RX_CDP_0 4
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`define ADDR_RX_STS_REG 5
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// `ifdef SGDMA_AXI_ON
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`define ADDR_IMASK 6
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`define ADDR_INTR 7
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// //`endif
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// `ifdef SGDMA_AHB_ON
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//`define ADDR_IMASK 6
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//`define ADDR_INTR 7
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`define H_IDLE 2'b00 // idle transfer
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`define H_BUSY 2'b01 // busy transfer
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`define H_NONSEQ 2'b10 // non-sequential transfer
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`define H_SEQ 2'b11 // sequential transfer
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// AHB responses
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`define H_OKAY 2'b00 // transfer completed successfully
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`define H_ERROR 2'b01 // an error has occurred
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`define H_RETRY 2'b10 // transfer cannot be completed yet
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`define H_SPLIT 2'b11 // split (not used in this design)
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// AHB size encodings
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`define H_BYTE 2'b00 // byte wide
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`define H_HWORD 2'b01 // half-word (16-bits) wide
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`define H_WORD 2'b10 // word (32-bits) wide
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`define MAX_PKT_SIZE 1536 // maximum packet size
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//======================================================================
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||||
// Sibridge Technologies
|
||||
// Proprietary and Confidential
|
||||
// All Rights Reserved
|
||||
//======================================================================
|
||||
// FILE : $Source: $
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||||
// REVISION : $Revision: 46073 $
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||||
// LAST UPDATE : $Date: 2024-02-13 12:34:42 +0530 (Tue, 13 Feb 2024) $
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//======================================================================
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// AUTHOR : Sibridge Technologies
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// MODULE NAME : ptp_hstif
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// DESCRIPTION : PTP-1588 Module Host Interface which interacts with the AHB
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||||
// target Interface. All the Registers and FIFOs are implemented in this module.
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||||
//======================================================================
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||||
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||||
//`define ASYNC_RESET // Type of reset used for FIFO used in ptp_hstif.
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||||
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||||
//Register Address Map.
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`define TS_RD_REG1_ADDR 5'b00000
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`define TS_RD_REG2_ADDR 5'b00001
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`define TS_RD_REG3_ADDR 5'b00010
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||||
`define TS_WR_REG1_ADDR 5'b00011
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||||
`define TS_WR_REG2_ADDR 5'b00100
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||||
`define TS_WR_REG3_ADDR 5'b00101
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||||
`define EVNT1_REG1_ADDR 5'b00110
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||||
`define EVNT1_REG2_ADDR 5'b00111
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||||
`define EVNT1_REG3_ADDR 5'b01000
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||||
`define EVNT2_REG1_ADDR 5'b01001
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||||
`define EVNT2_REG2_ADDR 5'b01010
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||||
`define EVNT2_REG3_ADDR 5'b01011
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||||
`define EVNT1_PLS_WDTH_REG_ADDR 5'b01100
|
||||
`define EVNT2_PLS_WDTH_REG_ADDR 5'b01101
|
||||
`define CMD_REG_ADDR 5'b01110
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||||
`define CNFG_REG_ADDR 5'b01111
|
||||
`define INTRPT_REG_ADDR 5'b10000
|
||||
`define INTRPT_MASK_REG_ADDR 5'b10001
|
||||
`define RTC_CLK1SEL_REG_ADDR 5'b10010
|
||||
`define RTC_CLK2SEL_REG_ADDR 5'b10011
|
||||
`define RX_RCRD_FIFO_ADDR 5'b10100
|
||||
`define TX_RCRD_FIFO_ADDR 5'b10101
|
||||
`define ADJST_REG_ADDR 5'b10110
|
||||
`define LT0L_REG_ADDR 5'b10111
|
||||
`define LT0M_REG_ADDR 5'b11000
|
||||
`define LT1L_REG_ADDR 5'b11001
|
||||
`define LT1M_REG_ADDR 5'b11010
|
||||
`define LT2L_REG_ADDR 5'b11011
|
||||
`define LT2M_REG_ADDR 5'b11100
|
||||
|
||||
|
||||
//Register Fields.
|
||||
`define FLD_INTRP_REG_PPS 0 // Time stamp write interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_MODE_ERR 1 // MODE ERROR interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_TS_WRDONE 2 // TS WRITE DONE interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_TX_RCRDDONE 3 // PTP MSG TRANSMIT DONE interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_RX_RCRDDONE 4 // PTP MSG RECEIVE DONE interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_TX_THSHLD 5 // TX FIFO THRSHLD FULL interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_RX_THSHLD 6 // RX FIFO THRSHLD FULL interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_LTOINT 7 // LATCH 0 interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_LT1INT 8 // LATCH 1 interrupt bit in INTERRUPT REG.
|
||||
`define FLD_INTRP_REG_LT2INT 9 // LATCH 2 interrupt bit in INTERRUPT REG.
|
||||
|
||||
`define FLD_INTRP_MASK_REG_INT_EN 0 // Glabal interupt Mask.
|
||||
`define FLD_INTRP_MASK_REG_PPS 1 // Time stamp write interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_MODE_ERR 2 // MODE ERROR interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_TS_WRDONE 3 // TS WRITE DONE interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_TX_RCRDDONE 4 // PTP MSG TRANSMIT DONE interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_RX_RCRDDONE 5 // PTP MSG RECEIVE DONE interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_TX_THSHLD 6 // TX FIFO THRSHLD FULL interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_RX_THSHLD 7 // RX FIFO THRSHLD FULL interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_LTOINT 8 // LATCH 0 interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_LT1INT 9 // LATCH 1 interrupt mask bit in INTERRUPT MASK REG.
|
||||
`define FLD_INTRP_MASK_REG_LT2INT 10 // LATCH 2 interrupt mask bit in INTERRUPT MASK REG.
|
||||
|
||||
`define FLD_CNFG_REG_EN 0 // MODULE ENABLE bit in CONFIGURATION REG.
|
||||
`define FLD_CNFG_REG_RTCEN 1 // RTC ENABLE bit in CONFIGURATION REG.
|
||||
`define FLD_CNFG_REG_MODE 2 // MODE bit in CONFIGURATION REG.
|
||||
`define FLD_CNFG_REG_WRCMDEN 3 // TIME STAMP WRITE COMMAND ENABLE bit in CONFIGURATION REG.
|
||||
`define FLD_CNFG_REG_EVNT1_TRGEN 4 // TIME TRIGGERED EVENT1 ENBALE bit in CONFIGURATION REG.
|
||||
`define FLD_CNFG_REG_EVNT2_TRGEN 5 // TIME TRIGGERED EVENT2 ENBALE bit in CONFIGURATION REG.
|
||||
`define FLD_CNFG_REG_RTCFREQ 6 // FREQ of REAL TIME COUNTER. 0 - 125 MHz, 1 - 250 MHz
|
||||
`define FLD_CNFG_REG_TSWRMODE 7 // MODE OF TIME STAMP WRITE 0 - On Rising Edge of 1Hz CLK, 1 - DONOT wait for 1Hz clock rising edge.
|
||||
`define FLD_CNFG_REG_DRIFTCRCT 8 // MODE OF TIME STAMP WRITE 0 - On Rising Edge of 1Hz CLK, 1 - DONOT wait for 1Hz clock rising edge.
|
||||
`define FLD_CNFG_REG_LT0EN 9 // RTC LATCH 0 ENABLE BIT.
|
||||
`define FLD_CNFG_REG_LT1EN 10 // RTC LATCH 1 ENABLE BIT.
|
||||
`define FLD_CNFG_REG_LT2EN 11 // RTC LATCH 2 ENABLE BIT.
|
||||
`define FLD_CNFG_REG_SFTRST 12 // SOFT RESET FOR PTP MODULE.
|
||||
|
||||
`define FLD_CMD_REG_TSWRCMD 0 // TIME STAMP WRITE COMMAND bit in COMMAND REG.
|
||||
|
||||
`define FLD_ADJST_REG_EN 0 // RTC FREQUENCY ADJUSTMENT ENABLE BIT.
|
||||
`define FLD_ADJST_REG_VLU_LSB 1 // RTC FREQUENCY ADJUSTMENT VALUE LSB.
|
||||
`define FLD_ADJST_REG_VLU_MSB 7 // RTC FREQUENCY ADJUSTMENT VALUE MSB.
|
||||
`define FLD_ADJST_REG_FREQ_LSB 8 // RTC FREQUENCY ADJUSTMENT FREQUENCY VALUE LSB.
|
||||
`define FLD_ADJST_REG_FREQ_MSB 31 // RTC FREQUENCY ADJUSTMENT FREQUENCY VALUE MSB.
|
||||
//`define ASYNC_1HZ_CLK // Represents 1Hz clock is asynchronous to RTC clock.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,364 @@
|
||||
// **************************************************************************
|
||||
// Microchip Corporation Proprietary and Confidential
|
||||
// Copyright 2021 Microchip Corporation. All rights reserved.
|
||||
//
|
||||
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
|
||||
// ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
|
||||
// IN ADVANCE IN WRITING.
|
||||
//
|
||||
// Description : CoreTSE testbench top level module for TBI mode.
|
||||
//
|
||||
// SVN Revision Information :
|
||||
// SVN $Revision : $
|
||||
// SVN $Date : $
|
||||
//
|
||||
// Revision Information :
|
||||
// Date SAR Description
|
||||
//
|
||||
// Notes :
|
||||
//
|
||||
// **************************************************************************
|
||||
`timescale 1 ns / 100 ps
|
||||
|
||||
// ==========================================================================
|
||||
// testbench
|
||||
// ==========================================================================
|
||||
module testbench ;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// coreparameters file
|
||||
`include "coreparameters.v"
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Internal Signal
|
||||
wire ftclk ;
|
||||
wire ftrdy ;
|
||||
wire ftacpt ;
|
||||
wire ftsof ;
|
||||
wire fteof ;
|
||||
wire [31:0] ftdat ;
|
||||
wire [ 1:0] ftdatnvld ;
|
||||
wire ftcfrm ;
|
||||
wire fthwm ;
|
||||
|
||||
wire frclk ;
|
||||
wire frrdy ;
|
||||
wire fracpt ;
|
||||
wire frsof ;
|
||||
wire freof ;
|
||||
wire [31:0] frdat ;
|
||||
wire [ 1:0] frdatnvld ;
|
||||
reg [ 1:0] frdatnvld_axi4s ;
|
||||
|
||||
wire mac_tx_clk;
|
||||
wire mac_rx_clk;
|
||||
|
||||
wire axi4s_tclk ;
|
||||
wire axi4s_ttvalid ;
|
||||
wire axi4s_ttready ;
|
||||
wire axi4s_ttsof ;
|
||||
wire axi4s_tteof ;
|
||||
wire [31:0] axi4s_ttdata ;
|
||||
reg [ 3:0] axi4s_ttkeep ;
|
||||
wire axi4s_ttlast ;
|
||||
|
||||
wire axi4s_iclk ;
|
||||
wire axi4s_itvalid ;
|
||||
wire axi4s_itready ;
|
||||
wire axi4s_itsof ;
|
||||
wire axi4s_iteof ;
|
||||
wire [31:0] axi4s_itdata ;
|
||||
reg [ 3:0] axi4s_itkeep ;
|
||||
wire axi4s_itlast ;
|
||||
wire [ 7:0] axi4s_ituser ;
|
||||
|
||||
wire tx_clk ;
|
||||
wire rx_clk ;
|
||||
|
||||
wire tbi_tx_clk ;
|
||||
wire tbi_rx_clk ;
|
||||
wire [ 9:0] tcg_dut ;
|
||||
wire [ 9:0] rcg_dut ;
|
||||
|
||||
wire mdc ;
|
||||
wire mdi ;
|
||||
wire mdo ;
|
||||
wire mdoen ;
|
||||
|
||||
wire pclk ;
|
||||
wire presetn ;
|
||||
wire [31:0] paddr ;
|
||||
wire psel ;
|
||||
wire penable ;
|
||||
wire pwrite ;
|
||||
wire [31:0] pwdata ;
|
||||
wire pready ;
|
||||
wire [31:0] prdata ;
|
||||
wire pslverr ;
|
||||
|
||||
wire rstbp ;
|
||||
|
||||
reg axi4s_itsop_det_en = 1'b1;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// DUT Instantiation
|
||||
CORETSE
|
||||
# (
|
||||
.FAMILY ( FAMILY ) ,
|
||||
.GMII_TBI ( GMII_TBI ) ,
|
||||
.PACKET_SIZE ( PACKET_SIZE ) ,
|
||||
.SAL ( SAL ) ,
|
||||
.WoL ( WoL ) ,
|
||||
.STATS ( STATS ) ,
|
||||
.MDIO_PHYID ( MDIO_PHYID ) ,
|
||||
.SLIP_ENABLE ( SLIP_ENABLE ) ,
|
||||
.ECC_ENABLE ( ECC_ENABLE ) ,
|
||||
.TXRX_INTR_ENABLE ( TXRX_INTR_ENABLE ) ,
|
||||
.HOST_INTERFACE ( HOST_INTERFACE )
|
||||
) dut_top (
|
||||
.MTXCLK ( mac_tx_clk ) ,
|
||||
.MTXRDY ( ftrdy ) ,
|
||||
.MTXACPT ( ftacpt ) ,
|
||||
.MTXSOF ( ftsof ) ,
|
||||
.MTXEOF ( fteof ) ,
|
||||
.MTXDAT ( ftdat ) ,
|
||||
.MTXBYTEVALID ( ftdatnvld ) ,
|
||||
.MTXCFRM ( ftcfrm ) ,
|
||||
.MTXHWM ( fthwm ) ,
|
||||
|
||||
.MRXCLK ( mac_rx_clk ) ,
|
||||
.MRXRDY ( frrdy ) ,
|
||||
.MRXACPT ( fracpt ) ,
|
||||
.MRXSOF ( frsof ) ,
|
||||
.MRXEOF ( freof ) ,
|
||||
.MRXDAT ( frdat ) ,
|
||||
.MRXBYTEVALID ( frdatnvld ) ,
|
||||
|
||||
.AXI4S_TCLK ( axi4s_tclk ) ,
|
||||
.AXI4S_TTVALID ( axi4s_ttvalid ) ,
|
||||
.AXI4S_TTREADY ( axi4s_ttready ) ,
|
||||
//.AXI4S_TTSOF ( axi4s_ttsof ) ,
|
||||
//.AXI4S_TTEOF ( axi4s_tteof ) ,
|
||||
.AXI4S_TTDATA ( axi4s_ttdata ) ,
|
||||
.AXI4S_TTKEEP ( axi4s_ttkeep ) ,
|
||||
.AXI4S_TTLAST ( axi4s_ttlast ) ,
|
||||
|
||||
.AXI4S_ICLK ( axi4s_iclk ) ,
|
||||
.AXI4S_ITVALID ( axi4s_itvalid ) ,
|
||||
.AXI4S_ITREADY ( axi4s_itready ) ,
|
||||
//.AXI4S_ITSOF ( axi4s_itsof ) ,
|
||||
//.AXI4S_ITEOF ( axi4s_iteof ) ,
|
||||
.AXI4S_ITDATA ( axi4s_itdata ) ,
|
||||
.AXI4S_ITKEEP ( axi4s_itkeep ) ,
|
||||
.AXI4S_ITLAST ( axi4s_itlast ) ,
|
||||
.AXI4S_ITUSER ( axi4s_ituser ) ,
|
||||
|
||||
//.GTXCLK ( ) ,
|
||||
.TXCLK ( tx_clk ) ,
|
||||
.RXCLK ( rx_clk ) ,
|
||||
.TXEN ( ) ,
|
||||
.TXD ( ) ,
|
||||
.TXER ( ) ,
|
||||
.RXDV ( ) ,
|
||||
.RXD ( ) ,
|
||||
.RXER ( ) ,
|
||||
.CRS ( ) ,
|
||||
.COL ( ) ,
|
||||
|
||||
.TBI_TX_CLK ( tbi_tx_clk ) ,
|
||||
.TBI_RX_CLK ( tbi_rx_clk ) ,
|
||||
.TCG ( tcg_dut ) ,
|
||||
.RCG ( rcg_dut ) ,
|
||||
|
||||
.TBI_TX_VALID ( ) ,
|
||||
.TBI_RX_VALID ( ) ,
|
||||
.TBI_RX_READY ( 1'b1 ) ,
|
||||
.SIGNAL_DETECT ( 1'b1 ) ,
|
||||
.RX_SLIP ( ) ,
|
||||
.SYNC ( ) ,
|
||||
.ANX_STATE ( ) ,
|
||||
.RCG_ERROR ( ) ,
|
||||
|
||||
.MDC ( mdc ) ,
|
||||
.MDI ( mdi ) ,
|
||||
.MDO ( mdo ) ,
|
||||
.MDOEN ( mdoen ) ,
|
||||
|
||||
.PCLK ( pclk ) ,
|
||||
.PRESETN ( presetn ) ,
|
||||
.PADDR ( paddr ) ,
|
||||
.PSEL ( psel ) ,
|
||||
.PENABLE ( penable ) ,
|
||||
.PWRITE ( pwrite ) ,
|
||||
.PWDATA ( pwdata ) ,
|
||||
.PRDATA ( prdata ) ,
|
||||
.PSLVERR ( pslverr ) ,
|
||||
.PREADY ( pready ) ,
|
||||
|
||||
.TSM_INTR ( ) ,
|
||||
.TSM_CONTROL ( ) ,
|
||||
.FAULT_DET ( )
|
||||
//.STBP ( rstbp )
|
||||
) ;
|
||||
|
||||
// --------------------------------------------------------------------------
|
||||
// Frame Generator and Checker Instantiation
|
||||
generate if (HOST_INTERFACE == 0) begin : NATIVE
|
||||
CoreTSE_tb
|
||||
# (
|
||||
.MDIO_PHYID ( MDIO_PHYID )
|
||||
) frame_gen_chk (
|
||||
.ftclk ( ftclk ) ,
|
||||
.ftrdy ( ftrdy ) ,
|
||||
.ftacpt ( ftacpt ) ,
|
||||
.ftsof ( ftsof ) ,
|
||||
.fteof ( fteof ) ,
|
||||
.ftdat ( ftdat ) ,
|
||||
.ftdatnvld ( ftdatnvld ) ,
|
||||
.fthwm ( fthwm ) ,
|
||||
.ftcfrm ( ftcfrm ) ,
|
||||
|
||||
.frclk ( frclk ) ,
|
||||
.frrdy ( frrdy ) ,
|
||||
.fracpt ( fracpt ) ,
|
||||
.frsof ( frsof ) ,
|
||||
.freof ( freof ) ,
|
||||
.frdat ( frdat ) ,
|
||||
.frdatnvld ( frdatnvld ) ,
|
||||
|
||||
.tx_clk ( tx_clk ) ,
|
||||
.rx_clk ( rx_clk ) ,
|
||||
|
||||
.tbi_tx_clk ( tbi_tx_clk ) ,
|
||||
.tbi_rx_clk ( tbi_rx_clk ) ,
|
||||
.tcg_dut ( tcg_dut ) ,
|
||||
.rcg_dut ( rcg_dut ) ,
|
||||
|
||||
.mdc ( mdc ) ,
|
||||
.mdi ( mdi ) ,
|
||||
.mdo ( mdo ) ,
|
||||
.mdoen ( mdoen ) ,
|
||||
|
||||
.pclk ( pclk ) ,
|
||||
.presetn ( presetn ) ,
|
||||
.paddr ( paddr ) ,
|
||||
.psel ( psel ) ,
|
||||
.penable ( penable ) ,
|
||||
.pwrite ( pwrite ) ,
|
||||
.pwdata ( pwdata ) ,
|
||||
.pready ( pready ) ,
|
||||
.prdata ( prdata ) ,
|
||||
.pslverr ( pslverr ) ,
|
||||
|
||||
.rstbp ( rstbp )
|
||||
) ;
|
||||
|
||||
assign mac_tx_clk = ftclk ;
|
||||
assign mac_rx_clk = frclk ;
|
||||
|
||||
assign axi4s_tclk = 0 ;
|
||||
assign axi4s_ttvalid = ftrdy ;
|
||||
assign axi4s_ttsof = ftsof ;
|
||||
assign axi4s_tteof = fteof ;
|
||||
assign axi4s_ttdata = ftdat ;
|
||||
assign axi4s_ttkeep = 4'd0 ;
|
||||
assign axi4s_ttlast = 1'd0 ;
|
||||
|
||||
assign axi4s_iclk = 0 ;
|
||||
assign axi4s_itready = fracpt ;
|
||||
|
||||
|
||||
end else begin : AXI4Stream
|
||||
CoreTSE_AXI4S_tb
|
||||
# (
|
||||
.MDIO_PHYID ( MDIO_PHYID )
|
||||
) frame_gen_chk (
|
||||
.ftclk ( ftclk ) ,
|
||||
.ftrdy ( ftrdy ) ,
|
||||
.ftacpt ( axi4s_ttready ) ,
|
||||
.ftsof ( ftsof ) ,
|
||||
.fteof ( fteof ) ,
|
||||
.ftdat ( ftdat ) ,
|
||||
.ftdatnvld ( ftdatnvld ) ,
|
||||
.fthwm ( fthwm ) ,
|
||||
.ftcfrm ( ftcfrm ) ,
|
||||
|
||||
.frclk ( frclk ) ,
|
||||
.frrdy ( axi4s_itvalid ) ,
|
||||
.fracpt ( axi4s_itready ) ,
|
||||
.frsof ( axi4s_itsof ) ,
|
||||
.freof ( axi4s_iteof ) ,
|
||||
.frdat ( axi4s_itdata ) ,
|
||||
.frdatnvld ( frdatnvld_axi4s ) ,
|
||||
|
||||
.tx_clk ( tx_clk ) ,
|
||||
.rx_clk ( rx_clk ) ,
|
||||
|
||||
.tbi_tx_clk ( tbi_tx_clk ) ,
|
||||
.tbi_rx_clk ( tbi_rx_clk ) ,
|
||||
.tcg_dut ( tcg_dut ) ,
|
||||
.rcg_dut ( rcg_dut ) ,
|
||||
|
||||
.mdc ( mdc ) ,
|
||||
.mdi ( mdi ) ,
|
||||
.mdo ( mdo ) ,
|
||||
.mdoen ( mdoen ) ,
|
||||
|
||||
.pclk ( pclk ) ,
|
||||
.presetn ( presetn ) ,
|
||||
.paddr ( paddr ) ,
|
||||
.psel ( psel ) ,
|
||||
.penable ( penable ) ,
|
||||
.pwrite ( pwrite ) ,
|
||||
.pwdata ( pwdata ) ,
|
||||
.pready ( pready ) ,
|
||||
.prdata ( prdata ) ,
|
||||
.pslverr ( pslverr ) ,
|
||||
|
||||
.rstbp ( rstbp )
|
||||
) ;
|
||||
|
||||
assign mac_tx_clk = 0 ;
|
||||
assign mac_rx_clk = 0 ;
|
||||
|
||||
assign axi4s_tclk = ftclk ;
|
||||
assign axi4s_ttvalid = ftrdy ;
|
||||
assign axi4s_ttsof = ftsof ;
|
||||
assign axi4s_tteof = fteof ;
|
||||
assign axi4s_ttdata = ftdat ;
|
||||
always @(*) begin
|
||||
case(ftdatnvld)
|
||||
4'b0001 : frdatnvld_axi4s = 2'b11;
|
||||
4'b0011 : frdatnvld_axi4s = 2'b10;
|
||||
4'b0111 : frdatnvld_axi4s = 2'b01;
|
||||
default : frdatnvld_axi4s = 2'b00;
|
||||
endcase
|
||||
end
|
||||
always @(*) begin
|
||||
case(ftdatnvld)
|
||||
2'b11 : axi4s_ttkeep = 4'b0001;
|
||||
2'b10 : axi4s_ttkeep = 4'b0011;
|
||||
2'b01 : axi4s_ttkeep = 4'b0111;
|
||||
default : axi4s_ttkeep = 4'b1111;
|
||||
endcase
|
||||
end
|
||||
assign axi4s_ttlast = fteof ;
|
||||
|
||||
assign axi4s_iclk = frclk ;
|
||||
assign axi4s_itready = fracpt ;
|
||||
|
||||
// Initiator SOF & EOF Generation
|
||||
always @(posedge axi4s_iclk) begin
|
||||
if (axi4s_itsof & axi4s_itready)
|
||||
axi4s_itsop_det_en <= 1'b0;
|
||||
else if (axi4s_itlast & axi4s_itready)
|
||||
axi4s_itsop_det_en <= 1'b1;
|
||||
end
|
||||
|
||||
assign axi4s_itsof = axi4s_itsop_det_en & axi4s_itvalid;
|
||||
assign axi4s_iteof = axi4s_itvalid & axi4s_itlast;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
// --------------------------------------------------------------------------
|
||||
Reference in New Issue
Block a user