working FIFO and TPSRAM without packet flter
This commit is contained in:
1
component/Actel/DirectCore/COREFIFO/3.1.101/COREFIFO.cxf
Normal file
1
component/Actel/DirectCore/COREFIFO/3.1.101/COREFIFO.cxf
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREFIFO</name><vendor>Actel</vendor><library>DirectCore</library><version>3.1.101</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\test\user\clock_driver.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\test\user\fifo_driver.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>rtl\vlog\test\user\fifo_monitor.v</name><fileType>verilogSource</fileType></file><file fileid="3"><name>rtl\vlog\test\user\g4_dp_ext_mem.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\test\user\MEM_WeqR.v</name><fileType>verilogSource</fileType></file><file fileid="5"><name>rtl\vlog\test\user\MEM_WgtR.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>rtl\vlog\test\user\MEM_WltR.v</name><fileType>verilogSource</fileType></file></fileSet><fileSet fileSetId="ANY_SIMULATION_FILESET"/><fileSet fileSetId="HDL_FILESET"/></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><fileSetRef>ANY_SIMULATION_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>
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@@ -0,0 +1,126 @@
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module MEM_WeqR (
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clk,
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wclk,
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rclk,
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rst_n,
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waddr,
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raddr,
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data,
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we,
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re,
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q
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);
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// Memory parameters
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parameter SYNC = 0;
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parameter RAM_RW = 18;
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parameter RAM_WW = 18;
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parameter RAM_WD = 10;
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parameter RAM_RD = 10;
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parameter WRITE_ADDRESS_END = 1024;
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parameter READ_ADDRESS_END = 1024;
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parameter WRITE_CLK = 1;
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parameter READ_CLK = 1;
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parameter WRITE_ENABLE = 1;
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parameter READ_ENABLE = 1;
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parameter RESET_POLARITY = 0;
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parameter PIPE = 1;
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// local inputs
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input clk;
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input wclk;
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input rclk;
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input rst_n;
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// local inputs - memory functional bus
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input [RAM_WD-1:0] waddr;
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input [RAM_WW-1:0] data;
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input [RAM_RD-1:0] raddr;
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input we;
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input re;
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//OUTPUTS
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//======
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output [RAM_RW-1:0] q;
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reg [RAM_RW-1:0] q_d0, q_d1,q_d2;
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wire wclk_int,rclk_int,we_int,re_int, rst_int;
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wire f_wclk, f_rclk;
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// ** MEM DECLARATION **
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reg [RAM_WW-1:0] MEM [WRITE_ADDRESS_END-1:0];
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reg [RAM_RW-1:0] MEMR [READ_ADDRESS_END-1:0];
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integer i;
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assign q = (PIPE == 1) ? q_d0 :(PIPE == 2) ? q_d1 : MEM[raddr] ;
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assign f_wclk = SYNC ? clk : wclk;
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assign f_rclk = SYNC ? clk : rclk;
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assign wclk_int = WRITE_CLK ? f_wclk : ~f_wclk;
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assign rclk_int = READ_CLK ? f_rclk : ~f_rclk;
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assign we_int = we;
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assign re_int = re;
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assign rst_int = RESET_POLARITY ? ~rst_n : rst_n;
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initial
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begin
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//q = {RAM_RW{1'b0}};
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end
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always @ (posedge wclk_int or negedge rst_int)
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begin
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if (~rst_int) begin
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end
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else
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begin
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if (we_int=== 1'b1)
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begin
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MEM[waddr] = data;
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end
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end
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end
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always @ (posedge rclk_int or negedge rst_int)
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begin
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if (~rst_int)
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begin
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q_d0 <= {RAM_RD{1'b0}};
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end
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else
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begin
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if (re_int === 1'b1)
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begin
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q_d0 <= MEM[raddr];
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end
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end
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end
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always @ (posedge rclk_int or negedge rst_int)
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begin
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if (~rst_int)
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begin
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q_d1 <= {RAM_RD{1'b0}};
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q_d2 <= {RAM_RD{1'b0}};
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end
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else
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begin
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q_d1 <= q_d0;
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q_d2 <= q_d1;
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end
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end
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endmodule
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@@ -0,0 +1,123 @@
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module MEM_WgtR (
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clk,
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wclk,
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rclk,
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rst_n,
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waddr,
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raddr,
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data,
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we,
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re,
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q
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);
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// Memory parameters
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parameter SYNC = 0;
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parameter RAM_RW = 18;
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parameter RAM_WW = 18;
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parameter RAM_WD = 10;
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parameter RAM_RD = 10;
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parameter WRITE_ADDRESS_END = 1024;
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parameter READ_ADDRESS_END = 1024;
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parameter WRITE_CLK = 1;
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parameter READ_CLK = 1;
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parameter WRITE_ENABLE = 1;
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parameter READ_ENABLE = 1;
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parameter RESET_POLARITY = 0;
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parameter PIPE = 1;
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// local inputs
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input clk;
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input wclk;
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input rclk;
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input rst_n;
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// local inputs - memory functional bus
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input [RAM_WD-1:0] waddr;
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input [RAM_WW-1:0] data;
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input [RAM_RD-1:0] raddr;
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input we;
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input re;
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//OUTPUTS
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//======
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output [RAM_RW-1:0] q;
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wire wclk_int,rclk_int,we_int,re_int, rst_int;
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wire f_wclk, f_rclk;
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// ** MEM DECLARATION **
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reg [RAM_WW-1:0] MEM [WRITE_ADDRESS_END-1:0];
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reg [RAM_RW-1:0] MEMR [READ_ADDRESS_END-1:0];
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integer i;
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reg [RAM_RW-1:0] q;
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assign f_wclk = SYNC ? clk : wclk;
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assign f_rclk = SYNC ? clk : rclk;
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assign wclk_int = WRITE_CLK ? f_wclk : ~f_wclk;
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assign rclk_int = READ_CLK ? f_rclk : ~f_rclk;
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assign we_int = we;
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assign re_int = re;
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assign rst_int = RESET_POLARITY ? ~rst_n : rst_n;
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/*
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assign wclk_int = wclk;
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assign rclk_int = rclk;
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*/
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initial
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begin
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q = {RAM_RW{1'b0}};
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end
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always @ (posedge wclk_int or negedge rst_int)
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begin
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if (~rst_int) begin
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end
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else
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begin
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if (we_int=== 1'b1)
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begin
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MEM[waddr] = data;
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/*if (RAM_WW > RAM_RW) begin
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MEMR[waddr*2] = data[RAM_RW-1:0];
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MEMR[waddr*2+1] = data[RAM_WW-1:RAM_RW];
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end*/
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end
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end
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end
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always @ (posedge rclk_int or negedge rst_int)
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begin
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if (~rst_int)
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begin
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q <= {RAM_RD{1'b0}};
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end
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else
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begin
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if (re_int === 1'b1)
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begin
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// if (RAM_WW > RAM_RW) begin
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//q <= MEMR[raddr];
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if (raddr%2 ==0)
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q <= MEM[raddr/2][RAM_RW-1 :0];
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else
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q <= MEM[raddr/2][(RAM_WW-1):RAM_RW];
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end
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end
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end
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endmodule
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@@ -0,0 +1,114 @@
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module MEM_WltR (
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clk,
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wclk,
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rclk,
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rst_n,
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waddr,
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raddr,
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data,
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we,
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re,
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q
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);
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// Memory parameters
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parameter SYNC = 0;
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parameter RAM_RW = 18;
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parameter RAM_WW = 18;
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parameter RAM_WD = 10;
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parameter RAM_RD = 10;
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parameter WRITE_ADDRESS_END = 1024;
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parameter READ_ADDRESS_END = 1024;
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parameter WRITE_CLK = 1;
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parameter READ_CLK = 1;
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parameter WRITE_ENABLE = 1;
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parameter READ_ENABLE = 1;
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parameter RESET_POLARITY = 0;
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parameter PIPE = 1;
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// local inputs
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input clk;
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input wclk;
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input rclk;
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input rst_n;
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// local inputs - memory functional bus
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input [RAM_WD-1:0] waddr;
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input [RAM_WW-1:0] data;
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input [RAM_RD-1:0] raddr;
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input we;
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input re;
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//OUTPUTS
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//======
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output [RAM_RW-1:0] q;
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wire wclk_int,rclk_int,we_int,re_int, rst_int;
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wire f_wclk, f_rclk;
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// ** MEM DECLARATION **
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reg [RAM_WW-1:0] MEM [WRITE_ADDRESS_END-1:0];
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reg [RAM_RW-1:0] MEMR [READ_ADDRESS_END-1:0];
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integer i;
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reg [RAM_RW-1:0] q;
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assign f_wclk = SYNC ? clk : wclk;
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assign f_rclk = SYNC ? clk : rclk;
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assign wclk_int = WRITE_CLK ? f_wclk : ~f_wclk;
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assign rclk_int = READ_CLK ? f_rclk : ~f_rclk;
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assign we_int = we;
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assign re_int = re;
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assign rst_int = RESET_POLARITY ? ~rst_n : rst_n;
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/*
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assign wclk_int = wclk;
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assign rclk_int = rclk;
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*/
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initial
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begin
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q = {RAM_RW{1'b0}};
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end
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always @ (posedge wclk_int or negedge rst_int)
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begin
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if (~rst_int) begin
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end
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else
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begin
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if (we_int=== 1'b1)
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begin
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MEM[waddr] = data;
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end
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end
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end
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always @ (posedge rclk_int or negedge rst_int)
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begin
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if (~rst_int)
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begin
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q <= {RAM_RD{1'b0}};
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end
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else
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begin
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if (re_int === 1'b1)
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begin
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//(RAM_WW < RAM_RW)
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q <= {MEM[raddr*2+1],MEM[raddr*2]};
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end
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end
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end
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endmodule
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@@ -0,0 +1,58 @@
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`timescale 1 ns / 100 ps
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module clock_driver ( clk1, wclk1, rclk1);
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output clk1;
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output wclk1,rclk1;
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parameter CLKPERIOD = 15;
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parameter WCLKPERIOD = 15;
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parameter RCLKPERIOD = 15;
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reg clk1, wclk1, rclk1;
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reg enable;
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initial begin
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clk1 = 1'b0;
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wclk1 = 1'b0;
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rclk1 = 1'b0;
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enable = 1'b1;
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end
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always @(clk1 or enable)
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begin
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if (enable)
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clk1 <= #(CLKPERIOD) ~clk1;
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end
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always @(wclk1 or enable)
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begin
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if (enable)
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wclk1 <= #(WCLKPERIOD) ~wclk1;
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end
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always @(rclk1 or enable)
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begin
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if (enable)
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rclk1 <= #(RCLKPERIOD) ~rclk1;
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end
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task clk_on;
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begin
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enable = 1'b1;
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end
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endtask
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task clk_off;
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begin
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enable = 1'b0;
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end
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endtask
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endmodule // clock_driver
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@@ -0,0 +1,459 @@
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`timescale 1 ns / 100 ps
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module fifo_driver (
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// inputs
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clk,
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wclk,
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rclk,
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waddr,
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raddr,
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full,
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empty,
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dvld,
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q,
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// outputs
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reset,
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we,
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re,
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wdata
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);
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parameter SYNC = 0;
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parameter CTRL_TYPE = 1;
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parameter WRITE_WIDTH = 18;
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parameter WRITE_DEPTH = 1024;
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parameter FULL_WRITE_DEPTH = 10;
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parameter READ_WIDTH = 18;
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parameter READ_DEPTH = 1024;
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parameter FULL_READ_DEPTH = 10;
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parameter WE_POLARITY = 1;
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parameter RE_POLARITY = 1;
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parameter RESET_POLARITY = 0;
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parameter RCLK_EDGE = 1;
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parameter WCLK_EDGE = 1;
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parameter ESTOP = 1;
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parameter FSTOP = 1;
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parameter PIPE = 1;
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parameter ECC = 0;
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parameter PREFETCH = 1;
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parameter FWFT = 0;
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input clk;
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input wclk;
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input rclk;
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input full;
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input empty;
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input dvld;
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input [FULL_WRITE_DEPTH-1 :0] waddr;
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input [FULL_READ_DEPTH-1 :0] raddr;
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input [READ_WIDTH-1 :0] q;
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output reset;
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output we;
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output re;
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output [WRITE_WIDTH-1:0] wdata;
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reg check_q;
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reg reset;
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reg we;
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reg re;
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reg [FULL_READ_DEPTH :0] rdepth;
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reg [FULL_WRITE_DEPTH:0] wdepth;
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reg [FULL_READ_DEPTH-1 :0] raddr_top;
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integer i,j,k,m;
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integer cnt, cnt_rd, cnt_eq, rderr_cnt;
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reg [WRITE_WIDTH-1:0] wdata;
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reg [WRITE_WIDTH-1:0] mem_arrayA [0:(2<<FULL_WRITE_DEPTH)];
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reg [READ_WIDTH-1:0] mem_arrayB [0:(2<<FULL_READ_DEPTH)];
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wire f_wclk,f_rclk,fifo_wclk,fifo_rclk, fifo_reset;
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assign f_wclk = SYNC ? clk : wclk;
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assign f_rclk = SYNC ? clk : rclk;
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assign fifo_wclk = WCLK_EDGE ? f_wclk : ~f_wclk;
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assign fifo_rclk = SYNC ? RCLK_EDGE ? f_rclk : ~f_rclk : RCLK_EDGE ? f_rclk : ~f_rclk;
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assign fifo_reset = RESET_POLARITY ? ~reset : reset;
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||||
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initial begin
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rderr_cnt = 0;
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if (RESET_POLARITY) begin
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reset = 1'b1;
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end else begin
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||||
reset = 1'b0;
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end
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||||
check_q = 1'b0;
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||||
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||||
if (WE_POLARITY == 1'b1)
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we <= 1'b1;
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||||
else
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||||
we <= 1'b0;
|
||||
|
||||
if (RE_POLARITY == 1'b1)
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||||
re <= 1'b1;
|
||||
else
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||||
re <= 1'b0;
|
||||
|
||||
end
|
||||
|
||||
initial begin
|
||||
if (WRITE_WIDTH > READ_WIDTH) begin
|
||||
for(cnt = 0; cnt < WRITE_DEPTH; cnt = cnt + 1) begin
|
||||
//mem_arrayA[cnt] = $random;
|
||||
mem_arrayA[cnt] = cnt;
|
||||
//$display("memory array A = %h", mem_arrayA[cnt]);
|
||||
end
|
||||
end
|
||||
else if (READ_WIDTH > WRITE_WIDTH ) begin
|
||||
for(cnt_rd = 0; cnt_rd < READ_DEPTH; cnt_rd = cnt_rd + 1) begin
|
||||
//mem_arrayA[cnt_rd] = $random;
|
||||
mem_arrayA[cnt_rd] = cnt_rd;
|
||||
//$display("memory array A = %h", mem_arrayA[cnt_rd]);
|
||||
end
|
||||
end
|
||||
else begin
|
||||
for(cnt_eq = 0; cnt_eq < WRITE_DEPTH; cnt_eq = cnt_eq + 1) begin
|
||||
//mem_arrayA[cnt_eq] = $random;
|
||||
mem_arrayA[cnt_eq] = cnt_eq;
|
||||
//$display("memory array A = %h", mem_arrayA[cnt_eq]);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
task reset_asserted;
|
||||
begin
|
||||
if (RESET_POLARITY)
|
||||
reset = 1'b1;
|
||||
else
|
||||
reset = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
task reset_negated;
|
||||
begin
|
||||
if (RESET_POLARITY)
|
||||
reset = 1'b0;
|
||||
else
|
||||
reset = 1'b1;
|
||||
end
|
||||
endtask
|
||||
|
||||
task initialize;
|
||||
begin
|
||||
|
||||
if (WE_POLARITY == 1'b1)
|
||||
we <= 1'b1;
|
||||
else
|
||||
we <= 1'b0;
|
||||
|
||||
if (RE_POLARITY == 1'b1)
|
||||
re <= 1'b1;
|
||||
else
|
||||
re <= 1'b0;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
task write_assert;
|
||||
begin
|
||||
@ (posedge fifo_wclk);
|
||||
if (WE_POLARITY == 1'b1)
|
||||
we <= 1'b0;
|
||||
else
|
||||
we <= 1'b1;
|
||||
end
|
||||
endtask
|
||||
|
||||
task write_deassert;
|
||||
begin
|
||||
// @ (posedge fifo_wclk);
|
||||
if (WE_POLARITY == 1'b1)
|
||||
we <= 1'b1;
|
||||
else
|
||||
we <= 1'b0;
|
||||
end
|
||||
endtask
|
||||
reg active;
|
||||
task push;
|
||||
input[(FULL_WRITE_DEPTH) :0] fifo_wdepth;
|
||||
begin
|
||||
wdepth = fifo_wdepth;
|
||||
if (full == 1 && FSTOP == 0 )begin
|
||||
write_assert;
|
||||
#1;
|
||||
wdata = mem_arrayA[waddr];
|
||||
mem_arrayB[waddr] = mem_arrayA[waddr];
|
||||
|
||||
end
|
||||
else begin
|
||||
for (i=0;i<=wdepth; i=i+1)
|
||||
begin
|
||||
write_assert;
|
||||
#1;
|
||||
//wdata = mem_arrayA[waddr];
|
||||
wdata = mem_arrayA[i];
|
||||
if (WRITE_WIDTH < READ_WIDTH) begin
|
||||
mem_arrayB[waddr] = {mem_arrayA[waddr*2+1],mem_arrayA[waddr*2]};
|
||||
end
|
||||
else if (WRITE_WIDTH > READ_WIDTH) begin
|
||||
//mem_arrayB[waddr*2] = wdata[READ_WIDTH-1:0];
|
||||
//mem_arrayB[waddr*2+1] = wdata[WRITE_WIDTH-1:READ_WIDTH];
|
||||
end
|
||||
else
|
||||
mem_arrayB[waddr] = mem_arrayA[waddr];
|
||||
end
|
||||
write_deassert;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task read_assert;
|
||||
begin
|
||||
@ (posedge fifo_rclk);
|
||||
if (RE_POLARITY == 1'b1)
|
||||
re <= 1'b0;
|
||||
else
|
||||
re <= 1'b1;
|
||||
end
|
||||
endtask
|
||||
|
||||
reg [FULL_READ_DEPTH-1 :0] raddr_t1,raddr_t2,raddr_t3,raddr_t4 ;
|
||||
|
||||
always @ (posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
raddr_t1<=0;
|
||||
raddr_t2 <=0;
|
||||
raddr_t3 <=0;
|
||||
raddr_t4 <=0;
|
||||
end
|
||||
else begin
|
||||
if ((re == 1 && RE_POLARITY == 1'b0) || (re == 0 && RE_POLARITY == 1'b1)) begin
|
||||
raddr_t1 <=raddr;
|
||||
raddr_t2 <=raddr_t1;
|
||||
raddr_t3 <=raddr_t2;
|
||||
raddr_t4 <=raddr_t3;
|
||||
end
|
||||
end
|
||||
end
|
||||
always @ (posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
raddr_top <=0;
|
||||
end
|
||||
else begin
|
||||
if ((re == 1 && RE_POLARITY == 1'b0) || (re == 0 && RE_POLARITY == 1'b1)) begin
|
||||
raddr_top <= raddr_top + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
task read_deassert;
|
||||
begin
|
||||
// @ (posedge fifo_rclk);
|
||||
|
||||
if (RE_POLARITY == 1'b1)
|
||||
re <= 1'b1;
|
||||
else
|
||||
re <= 1'b0;
|
||||
end
|
||||
endtask
|
||||
wire [FULL_READ_DEPTH-1 :0] raddr_temp1,raddr_temp2 ;
|
||||
assign raddr_temp1 = (raddr <=1) ? 0 : (raddr-1);
|
||||
assign raddr_temp2 = (raddr <=2) ? 0 : (raddr-2);
|
||||
|
||||
task pop;
|
||||
input[(FULL_READ_DEPTH) :0] fifo_rdepth;
|
||||
|
||||
reg [FULL_READ_DEPTH-1 :0] raddr_temp;
|
||||
begin
|
||||
rdepth = fifo_rdepth;
|
||||
active =0;
|
||||
read_assert;
|
||||
|
||||
repeat(PIPE) @ (posedge fifo_rclk);
|
||||
if(ECC == 1) begin repeat(ECC) @ (posedge fifo_rclk); end
|
||||
for (k=0 ;k<rdepth-1;k=k+1)
|
||||
begin
|
||||
if (empty == 0) begin
|
||||
@ (posedge fifo_rclk);
|
||||
if (WRITE_WIDTH < READ_WIDTH) begin
|
||||
if((mem_arrayB[raddr_temp] != q))
|
||||
begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
|
||||
end
|
||||
end
|
||||
else if (WRITE_WIDTH > READ_WIDTH) begin
|
||||
if (PREFETCH == 1)begin
|
||||
if (mem_arrayB[raddr_temp] != q)
|
||||
begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d fifo Q = %h - expected Q = %h ",raddr, q , mem_arrayB[raddr_temp]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr_temp]);
|
||||
end
|
||||
end
|
||||
else begin //if(PREFETCH == 0 && mem_arrayB[raddr_temp] != q)
|
||||
if (mem_arrayB[raddr_temp] != q)
|
||||
begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_temp = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_temp, q , mem_arrayB[raddr_temp]);
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin // (WRITE_WIDTH == READ_WIDTH)
|
||||
if ((PREFETCH == 1 || FWFT == 1) && CTRL_TYPE == 1)begin
|
||||
if((mem_arrayB[raddr_top] !== q))
|
||||
begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: TIME = %t At Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr_top, q , mem_arrayB[raddr_top]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr_t1]);
|
||||
end
|
||||
end
|
||||
else if ((PREFETCH == 1 || FWFT == 1) && CTRL_TYPE != 1)begin
|
||||
if((mem_arrayB[raddr] !== q))
|
||||
begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d fifo Q = %h - expected Q = %h ",raddr, q , mem_arrayB[raddr]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr]);
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if (PIPE == 2 && ECC == 0 ) begin
|
||||
if((mem_arrayB[raddr_t2] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 2 && ECC == 1 && CTRL_TYPE !==1) begin
|
||||
if((mem_arrayB[raddr_t3] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d raddr_t3 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t3, q , mem_arrayB[raddr_t3]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 2 && (ECC == 1 || ECC == 0) && CTRL_TYPE ==1) begin
|
||||
if((mem_arrayB[raddr_t2] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 2 && ECC == 2 ) begin
|
||||
if((mem_arrayB[raddr_t2] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t2, q , mem_arrayB[raddr_t2]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 1 && ECC== 0 ) begin
|
||||
if((mem_arrayB[raddr_t1] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ($realtime, "ERROR: At Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t1 , q , mem_arrayB[raddr_t1]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 1 && ECC== 1 && CTRL_TYPE!=1) begin
|
||||
if((mem_arrayB[raddr_t2] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ($realtime, "ERROR: At Raddr = %d raddr_t2 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t2 , q , mem_arrayB[raddr_t2]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 1 && ECC== 2) begin
|
||||
if((mem_arrayB[raddr_t1] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ($realtime, "ERROR: At Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t1 , q , mem_arrayB[raddr_t1]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
|
||||
end
|
||||
|
||||
end
|
||||
else if (PIPE == 1 && (ECC== 1 || ECC ==0) && CTRL_TYPE==1) begin
|
||||
if((mem_arrayB[raddr_t1] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ($realtime, "ERROR: Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",raddr, raddr_t1 , q , mem_arrayB[raddr_t1]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d raddr_t1 = %d fifo Q = %h - expected Q = %h ",$time, raddr, raddr_t1, q , mem_arrayB[raddr_t1]);
|
||||
end
|
||||
|
||||
end
|
||||
else begin
|
||||
if((mem_arrayB[raddr] !== q)) begin
|
||||
check_q = ~check_q;
|
||||
$display ("ERROR: else At Raddr = %d fifo Q = %h - expected Q = %h ",raddr, q , mem_arrayB[raddr]);
|
||||
rderr_cnt = rderr_cnt + 1;
|
||||
end
|
||||
else begin
|
||||
//$display ("PASS: At TIME = %t Raddr = %d fifo Q = %h - expected Q = %h ",$time, raddr, q , mem_arrayB[raddr]);
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
if (rderr_cnt == 0)
|
||||
$display ( "At", $time, " PASS: FIFO Q output match \n");
|
||||
end
|
||||
endtask
|
||||
|
||||
endmodule // fifo_driver
|
||||
@@ -0,0 +1,819 @@
|
||||
|
||||
`timescale 1ns / 100ps
|
||||
|
||||
module fifo_monitor (
|
||||
clk,
|
||||
rclk,
|
||||
wclk,
|
||||
reset,
|
||||
we,
|
||||
re,
|
||||
|
||||
wcnt,
|
||||
rcnt,
|
||||
|
||||
full,
|
||||
afull,
|
||||
empty,
|
||||
aempty,
|
||||
underflow,
|
||||
overflow,
|
||||
dvld,
|
||||
wack
|
||||
|
||||
);
|
||||
|
||||
|
||||
parameter SYNC = 0;
|
||||
parameter PIPE = 1;
|
||||
parameter PREFETCH = 1;
|
||||
parameter FWFT = 1;
|
||||
parameter WRITE_WIDTH = 18;
|
||||
parameter WRITE_DEPTH = 10;
|
||||
parameter FULL_WRITE_DEPTH = 1024;
|
||||
parameter READ_WIDTH = 18;
|
||||
parameter READ_DEPTH = 10;
|
||||
parameter FULL_READ_DEPTH = 1024;
|
||||
parameter AFVAL = 508;
|
||||
parameter AEVAL = 4;
|
||||
parameter AE_STATIC_EN = 1;
|
||||
parameter AF_STATIC_EN = 1;
|
||||
parameter ESTOP = 1;
|
||||
parameter FSTOP = 1;
|
||||
parameter OVERFLOW_EN = 1;
|
||||
parameter UNDERFLOW_EN = 1;
|
||||
parameter WRCNT_EN = 1;
|
||||
parameter RDCNT_EN = 1;
|
||||
parameter RCLK_EDGE = 1;
|
||||
parameter WCLK_EDGE = 1;
|
||||
parameter RE_POLARITY = 0;
|
||||
parameter WE_POLARITY = 0;
|
||||
parameter READ_DVALID = 0;
|
||||
parameter WRITE_ACK = 0;
|
||||
parameter RESET_POLARITY = 0;
|
||||
|
||||
|
||||
|
||||
input clk;
|
||||
input rclk;
|
||||
input wclk;
|
||||
input reset;
|
||||
|
||||
input we;
|
||||
input re;
|
||||
|
||||
input [WRITE_DEPTH:0] wcnt;
|
||||
input [READ_DEPTH:0] rcnt;
|
||||
|
||||
input full;
|
||||
input afull;
|
||||
|
||||
input empty;
|
||||
input aempty;
|
||||
|
||||
input underflow;
|
||||
input overflow;
|
||||
input dvld;
|
||||
input wack;
|
||||
|
||||
|
||||
reg [WRITE_DEPTH:0] wptr;
|
||||
reg [READ_DEPTH:0] rptr;
|
||||
reg [WRITE_DEPTH:0] wptr_r;
|
||||
reg [READ_DEPTH:0] rptr_r;
|
||||
reg full_r, full_reg;
|
||||
reg afull_r;
|
||||
reg empty_r,empty_rt,empty_reg;
|
||||
reg empty_r_fwft1;
|
||||
reg empty_r_fwft2;
|
||||
reg empty_r_fwft3;
|
||||
reg aempty_r;
|
||||
reg underflow_r;
|
||||
reg overflow_r;
|
||||
reg underflow_w;
|
||||
reg overflow_w;
|
||||
reg DVLD_d0,DVLD_d1,DVLD_d2;
|
||||
reg wack_r;
|
||||
reg [WRITE_DEPTH : 0] wptr_d1sync;
|
||||
reg [WRITE_DEPTH : 0] wptr_d2sync;
|
||||
reg [WRITE_DEPTH : 0] wptr_d3sync;
|
||||
reg [WRITE_DEPTH : 0] wptr_d4sync;
|
||||
reg [READ_DEPTH : 0] rptr_d1sync;
|
||||
reg [READ_DEPTH : 0] rptr_d2sync;
|
||||
reg [READ_DEPTH : 0] rptr_d3sync;
|
||||
reg [READ_DEPTH : 0] rptr_d4sync;
|
||||
|
||||
wire f_wclk;
|
||||
wire f_rclk;
|
||||
wire fifo_wclk;
|
||||
wire fifo_rclk;
|
||||
|
||||
wire fifo_we;
|
||||
wire fifo_re;
|
||||
wire fifo_reset;
|
||||
|
||||
wire [WRITE_DEPTH:0] tb_wcnt;
|
||||
wire [READ_DEPTH:0] tb_rcnt;
|
||||
|
||||
wire tb_full;
|
||||
wire tb_afull;
|
||||
|
||||
wire tb_empty;
|
||||
wire tb_empty_int;
|
||||
wire tb_aempty;
|
||||
|
||||
wire tb_underflow;
|
||||
wire tb_overflow;
|
||||
|
||||
wire tb_dvld;
|
||||
wire tb_wack;
|
||||
|
||||
wire [WRITE_DEPTH:0] wdiff_bus;
|
||||
wire [READ_DEPTH:0] rdiff_bus;
|
||||
wire full_w;
|
||||
wire afull_w;
|
||||
wire empty_w;
|
||||
wire aempty_w;
|
||||
wire aempty_w_assert;
|
||||
wire aempty_w_deassert;
|
||||
wire aempty_w_int;
|
||||
wire temp;
|
||||
wire dvld;
|
||||
|
||||
event check_wcnt;
|
||||
event check_rcnt;
|
||||
event check_full;
|
||||
event check_afull;
|
||||
event check_empty;
|
||||
event check_aempty;
|
||||
event check_overflow;
|
||||
event check_underflow;
|
||||
event check_dvld;
|
||||
event check_wack;
|
||||
|
||||
integer err_cnt;
|
||||
reg observe;
|
||||
wire full_w_async;
|
||||
wire full_w_sync;
|
||||
reg [READ_DEPTH:0] sc_r;
|
||||
|
||||
initial
|
||||
begin
|
||||
err_cnt = 0;
|
||||
end
|
||||
|
||||
assign f_wclk = SYNC ? clk : wclk;
|
||||
assign f_rclk = SYNC ? clk : rclk;
|
||||
|
||||
assign fifo_wclk = WCLK_EDGE ? f_wclk : ~f_wclk;
|
||||
assign fifo_rclk = SYNC ? WCLK_EDGE ? f_rclk : ~f_rclk : RCLK_EDGE ? f_rclk : ~f_rclk;
|
||||
|
||||
|
||||
assign fifo_we = WE_POLARITY ? ~we : we;
|
||||
assign fifo_re = RE_POLARITY ? ~re : re;
|
||||
|
||||
assign fifo_reset = RESET_POLARITY ? ~reset : reset;
|
||||
assign wdiff_bus = SYNC ? (wptr - rptr) : (wptr - rptr_d4sync);
|
||||
assign rdiff_bus = SYNC ? (wptr - rptr) : (wptr_d4sync- rptr);
|
||||
|
||||
//************************ Final output and flag assignments *******************************************/
|
||||
assign tb_wcnt = ((SYNC == 1) && (WRITE_WIDTH == READ_WIDTH) && (ESTOP == 1) && (FSTOP == 1)) ? wdiff_bus : wptr_r ;
|
||||
assign tb_rcnt = ((SYNC == 1) && (WRITE_WIDTH == READ_WIDTH) && (ESTOP == 1) && (FSTOP == 1)) ? rdiff_bus : rptr_r;
|
||||
|
||||
assign tb_full = SYNC ? full_w_sync : full_r;
|
||||
assign tb_afull = SYNC ? (fifo_we ? afull_w : afull_r) : afull_r;
|
||||
|
||||
assign tb_empty_int = ((SYNC == 1) && (WRITE_WIDTH == READ_WIDTH) && (ESTOP == 1) && (FSTOP == 1)) ? empty_w: empty_r ;
|
||||
assign tb_empty = ((FWFT == 1) || (PREFETCH == 1)) ? (tb_empty_int | empty_r_fwft3) : tb_empty_int ;
|
||||
|
||||
assign tb_aempty = aempty_r;
|
||||
|
||||
assign tb_underflow = (SYNC == 1) ? underflow_w : underflow_r;
|
||||
assign tb_overflow = overflow_r;
|
||||
|
||||
assign tb_dvld = (PIPE == 1) ? DVLD_d0 : (PIPE == 2) ? DVLD_d1 : (fifo_re && !empty);
|
||||
assign tb_wack = wack_r;
|
||||
|
||||
//******************************************************************************************************/
|
||||
//june 13
|
||||
// assign full_w = (wdiff_bus >= (FULL_WRITE_DEPTH)) ;
|
||||
assign full_w = SYNC ? full_w_sync : full_w_async;
|
||||
assign full_w_sync = ( sc_r == (FULL_WRITE_DEPTH)) ;
|
||||
assign full_w_async = we ? (wdiff_bus >= (FULL_WRITE_DEPTH-1)) : (wdiff_bus >= (FULL_WRITE_DEPTH)) ; // june 13
|
||||
|
||||
assign afull_w = SYNC ? (wdiff_bus >= AFVAL) : (wdiff_bus >= AFVAL-1);
|
||||
|
||||
assign empty_w = SYNC ? 0>= rdiff_bus : fifo_re ? (rdiff_bus<=1) : (rdiff_bus == 0) ;
|
||||
assign aempty_w_assert = AEVAL >= rdiff_bus;
|
||||
assign aempty_w_deassert = (AEVAL-1) >= rdiff_bus;
|
||||
assign aempty_w_int = fifo_re ? aempty_w_assert : aempty_w_deassert;
|
||||
assign aempty_w = aempty_w_int;
|
||||
|
||||
assign temp = (wptr >= FULL_WRITE_DEPTH-1 && rptr >= (FULL_READ_DEPTH -1)) ? 1 : 0;
|
||||
|
||||
always @(posedge fifo_wclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
wptr <= 0;
|
||||
observe = 0;
|
||||
end
|
||||
else if(fifo_we == 1'b1 && full_r == 1'b0) begin
|
||||
wptr <= wptr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// june 13
|
||||
always @(negedge fifo_reset or posedge fifo_wclk)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
sc_r <= 0;
|
||||
end
|
||||
else if ( fifo_we ^ fifo_re) begin
|
||||
if(fifo_we == 1'b1) begin
|
||||
sc_r <= (sc_r + 1);
|
||||
end
|
||||
else if(fifo_re == 1'b1) begin
|
||||
sc_r <= (sc_r - 1);
|
||||
end
|
||||
end
|
||||
end
|
||||
always @(posedge fifo_rclk or negedge fifo_reset )
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
rptr <= 0;
|
||||
observe = 0;
|
||||
end
|
||||
else if (fifo_re == 1'b1 && empty_reg == 1'b0 ) begin
|
||||
rptr <= rptr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
if (SYNC == 0) begin
|
||||
if (WRITE_WIDTH > READ_WIDTH) begin
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
wptr_d1sync<= 0;
|
||||
wptr_d2sync<= 0;
|
||||
wptr_d3sync<= 0;
|
||||
wptr_d4sync<= 0;
|
||||
end
|
||||
else begin
|
||||
wptr_d1sync<= wptr;
|
||||
wptr_d2sync<= wptr_d1sync;
|
||||
wptr_d3sync<= wptr_d2sync;
|
||||
if (wptr_d3sync < WRITE_WIDTH) begin
|
||||
wptr_d4sync<= ((wptr_d3sync)*(WRITE_WIDTH/READ_WIDTH));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_wclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
rptr_d1sync<= 0;
|
||||
rptr_d2sync<= 0;
|
||||
rptr_d3sync<= 0;
|
||||
rptr_d4sync<= 0;
|
||||
end
|
||||
else begin
|
||||
|
||||
rptr_d1sync<= rptr;
|
||||
rptr_d2sync<= rptr_d1sync;
|
||||
rptr_d3sync<= rptr_d2sync;
|
||||
if (rptr_d3sync < FULL_READ_DEPTH) begin
|
||||
rptr_d4sync<= ((rptr_d3sync) /(WRITE_WIDTH/READ_WIDTH));
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
/*******************************************/
|
||||
else if (WRITE_WIDTH < READ_WIDTH) begin
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
wptr_d1sync<= 0;
|
||||
wptr_d2sync<= 0;
|
||||
wptr_d3sync<= 0;
|
||||
wptr_d4sync<= 0;
|
||||
end
|
||||
else begin
|
||||
wptr_d1sync<= wptr;
|
||||
wptr_d2sync<= wptr_d1sync;
|
||||
wptr_d3sync<= wptr_d2sync;
|
||||
if (wptr_d3sync <= FULL_WRITE_DEPTH) begin
|
||||
wptr_d4sync<= ((wptr_d3sync)/(READ_WIDTH/WRITE_WIDTH));
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
rptr_d1sync<= 0;
|
||||
rptr_d2sync<= 0;
|
||||
rptr_d3sync<= 0;
|
||||
rptr_d4sync<= 0;
|
||||
end
|
||||
else begin
|
||||
|
||||
rptr_d1sync<= rptr;
|
||||
rptr_d2sync<= rptr_d1sync;
|
||||
rptr_d3sync<= rptr_d2sync;
|
||||
if (rptr_d3sync < READ_WIDTH) begin
|
||||
rptr_d4sync<= ((rptr_d3sync)*(READ_WIDTH/WRITE_WIDTH));
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
/*******************************************/
|
||||
else begin //(WRITE_WIDTH == READ_WIDTH)
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
wptr_d1sync<= 0;
|
||||
wptr_d2sync<= 0;
|
||||
wptr_d3sync<= 0;
|
||||
wptr_d4sync<= 0;
|
||||
end
|
||||
else begin
|
||||
wptr_d1sync<= wptr;
|
||||
wptr_d2sync<= wptr_d1sync;
|
||||
wptr_d3sync<= wptr_d2sync;
|
||||
wptr_d4sync<= wptr_d3sync;
|
||||
end
|
||||
end
|
||||
always @(posedge fifo_wclk or negedge fifo_reset)
|
||||
begin
|
||||
if (!fifo_reset) begin
|
||||
rptr_d1sync<= 0;
|
||||
rptr_d2sync<= 0;
|
||||
rptr_d3sync<= 0;
|
||||
rptr_d4sync<= 0;
|
||||
end
|
||||
else begin
|
||||
|
||||
rptr_d1sync<= rptr;
|
||||
rptr_d2sync<= rptr_d1sync;
|
||||
rptr_d3sync<= rptr_d2sync;
|
||||
rptr_d4sync<= rptr_d3sync;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_wclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
full_reg <= 0;
|
||||
end
|
||||
else
|
||||
full_reg <= full_r;
|
||||
end
|
||||
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
empty_reg <= 0;
|
||||
end
|
||||
else
|
||||
empty_reg <= empty_r;
|
||||
end
|
||||
|
||||
always @(posedge fifo_wclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
full_r <= 1'b0;
|
||||
afull_r <= 1'b0;
|
||||
wptr_r <= 0;
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
full_r <= full_w;
|
||||
afull_r <= afull_w;
|
||||
wptr_r <= wdiff_bus;
|
||||
|
||||
if(fifo_we == 1'b1 && full_reg == 1'b1 && OVERFLOW_EN == 1) begin
|
||||
overflow_r <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
overflow_r <= 1'b0;
|
||||
end
|
||||
if(fifo_we == 1'b1 && full_w == 1'b1 && OVERFLOW_EN == 1) begin
|
||||
overflow_w <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
overflow_w <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
empty_r <= 1'b1;
|
||||
empty_r_fwft1 <= 1'b1;
|
||||
empty_r_fwft2 <= 1'b1;
|
||||
empty_r_fwft3 <= 1'b1;
|
||||
empty_rt <= 1'b1;
|
||||
aempty_r <= 1'b1;
|
||||
rptr_r <= 0;
|
||||
end
|
||||
else begin
|
||||
empty_r <= empty_w;
|
||||
empty_r_fwft1 <= empty_r;
|
||||
empty_r_fwft2 <= empty_r_fwft1;
|
||||
empty_r_fwft3 <= empty_r_fwft2;
|
||||
empty_rt <= empty_w;
|
||||
aempty_r <= aempty_w;
|
||||
rptr_r <= rdiff_bus;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
underflow_r <= 1'b0;
|
||||
underflow_w <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if(fifo_re == 1'b1 && empty_r == 1'b1 && UNDERFLOW_EN == 1 && SYNC == 0) begin
|
||||
underflow_r <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
underflow_r <= 1'b0;
|
||||
end
|
||||
if(fifo_re == 1'b1 && empty_w == 1'b1 && UNDERFLOW_EN == 1 && SYNC == 1) begin
|
||||
underflow_w <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
underflow_w <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg underflow_start, overflow_start;
|
||||
always @(posedge underflow_w or underflow_r or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
underflow_start <=0;
|
||||
end
|
||||
else begin
|
||||
underflow_start <=1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge overflow_w or underflow_r or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
overflow_start <=0;
|
||||
end
|
||||
else begin
|
||||
overflow_start <=1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_rclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
DVLD_d0 <=0;
|
||||
DVLD_d1 <=0;
|
||||
DVLD_d2 <=0;
|
||||
end
|
||||
else begin
|
||||
DVLD_d0 <=(fifo_re && !empty);
|
||||
DVLD_d1 <=DVLD_d0;
|
||||
DVLD_d2 <=DVLD_d1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge fifo_wclk or negedge fifo_reset)
|
||||
begin
|
||||
if(!fifo_reset) begin
|
||||
wack_r <=0;
|
||||
end
|
||||
else begin
|
||||
wack_r <=(fifo_we && !full_r);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/**************** EVENT geneartion whenever flag asserted ************************************/
|
||||
|
||||
always @(tb_dvld or dvld)
|
||||
begin
|
||||
if ((fifo_reset ==1) && READ_DVALID == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH))
|
||||
#1
|
||||
-> check_dvld;
|
||||
end
|
||||
|
||||
always @(tb_wack or wack)
|
||||
begin
|
||||
if ((fifo_reset ==1) && WRITE_ACK == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH))
|
||||
#1
|
||||
-> check_wack;
|
||||
end
|
||||
|
||||
always @(tb_wcnt or wcnt)
|
||||
begin
|
||||
if ((fifo_reset ==1) && WRCNT_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_wcnt;
|
||||
end
|
||||
|
||||
always @(tb_rcnt or rcnt)
|
||||
begin
|
||||
if ((fifo_reset == 1) && RDCNT_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_rcnt;
|
||||
end
|
||||
|
||||
always @(tb_full or full)
|
||||
begin
|
||||
if ((fifo_reset == 1) && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_full;
|
||||
end
|
||||
|
||||
always @(tb_afull or afull)
|
||||
begin
|
||||
if ((fifo_reset == 1) && AF_STATIC_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_afull;
|
||||
end
|
||||
|
||||
always @(tb_empty or empty )
|
||||
begin
|
||||
if (fifo_reset == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_empty;
|
||||
end
|
||||
|
||||
always @(tb_aempty or aempty)
|
||||
begin
|
||||
if ((fifo_reset == 1) && AE_STATIC_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_aempty;
|
||||
end
|
||||
|
||||
always @(tb_overflow or overflow)
|
||||
begin
|
||||
if ((fifo_reset == 1) && OVERFLOW_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_overflow;
|
||||
end
|
||||
|
||||
always @(tb_underflow or underflow)
|
||||
begin
|
||||
if ((fifo_reset == 1) && UNDERFLOW_EN == 1 && FSTOP == 1 && ESTOP == 1 && (READ_DEPTH == WRITE_DEPTH) && FWFT == 0 && PREFETCH == 0)
|
||||
#1
|
||||
-> check_underflow;
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
/************************** Checker placed to compare with DUT signal status v/s expected signal status *********************/
|
||||
always @(check_wack)
|
||||
begin
|
||||
|
||||
//check_wack_out(tb_wack);
|
||||
|
||||
end
|
||||
|
||||
always @(check_dvld)
|
||||
begin
|
||||
|
||||
//check_dvld_out(tb_dvld);
|
||||
|
||||
end
|
||||
|
||||
always @(check_wcnt)
|
||||
begin
|
||||
|
||||
//check_wcnt_out(tb_wcnt);
|
||||
|
||||
end
|
||||
|
||||
always @(check_rcnt)
|
||||
begin
|
||||
|
||||
//check_rcnt_out(tb_rcnt);
|
||||
|
||||
end
|
||||
|
||||
always @(check_full)
|
||||
begin
|
||||
|
||||
check_full_flag(tb_full);
|
||||
|
||||
end
|
||||
|
||||
always @(check_afull)
|
||||
begin
|
||||
|
||||
check_afull_flag(tb_afull);
|
||||
|
||||
end
|
||||
|
||||
always @(check_empty)
|
||||
begin
|
||||
|
||||
check_empty_flag(tb_empty);
|
||||
|
||||
end
|
||||
|
||||
always @(check_aempty)
|
||||
begin
|
||||
|
||||
check_aempty_flag(tb_aempty);
|
||||
|
||||
end
|
||||
|
||||
always @(check_overflow)
|
||||
begin
|
||||
|
||||
check_overflow_flag(tb_overflow);
|
||||
|
||||
end
|
||||
|
||||
always @(check_underflow)
|
||||
begin
|
||||
|
||||
check_underflow_flag(tb_underflow);
|
||||
|
||||
end
|
||||
|
||||
/******************************* TASKS ********************************************************/
|
||||
|
||||
task check_reset;
|
||||
input expected_value;
|
||||
begin
|
||||
#1
|
||||
$display("fifo reset = %b", fifo_reset);
|
||||
if (fifo_reset != expected_value)
|
||||
begin
|
||||
$display("ERROR: fifo reset = %b - expected value= %b", fifo_reset, expected_value);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_wack_out;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((wack !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo wack = %d - expected value= %d ",$time, wack , expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: WACK match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
task check_dvld_out;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((dvld !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo dvld = %d - expected value= %d ",$time, dvld , expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: DVLD match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
task check_wcnt_out;
|
||||
input[WRITE_DEPTH:0] expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((wcnt !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo write_count = %d - expected value= %d ",$time, wcnt , expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: write_count match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_rcnt_out;
|
||||
input[READ_DEPTH:0] expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((rcnt !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo read_count = %d - expected value= %d ",$time, rcnt , expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: read_count match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
task check_full_flag;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((full !== expected_value ) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo full flag = %b - expected value= %b ",$time, full , expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
observe = ~observe;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: FULL flag match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_afull_flag;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((afull !== expected_value) && (underflow_start ==0 && overflow_start == 0) ) begin
|
||||
$display("ERROR: At %t fifo afull flag = %b - expected value = %b ",$time ,afull, expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
observe = ~observe;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: AFULL flag match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_empty_flag;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#2
|
||||
if ((empty !== expected_value) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo empty flag = %b - expected value = %b ",$time, empty, expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
observe = ~observe;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: EMPTY flag match \n");
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_aempty_flag;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if ((aempty !== expected_value) && (underflow_start ==0 && overflow_start == 0)) begin
|
||||
$display("ERROR: At %t fifo aempty flag = %b - expected value = %b",$time ,aempty, expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
observe = ~observe;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: AEMPTY flag match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_overflow_flag;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if (overflow !== expected_value ) begin
|
||||
$display("ERROR: At %t fifo overflow flag = %b - expected value = %b", $time, overflow, expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
observe = ~observe;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: OVERFLOW flag match \n");
|
||||
end
|
||||
endtask
|
||||
|
||||
task check_underflow_flag;
|
||||
input expected_value;
|
||||
|
||||
begin
|
||||
#1
|
||||
if (underflow !== expected_value) begin
|
||||
$display("ERROR: At %t fifo underflow flag = %b - expected value = %b", $time, underflow, expected_value);
|
||||
err_cnt = err_cnt +1;
|
||||
observe = ~observe;
|
||||
end
|
||||
else
|
||||
$display ( "At", $time, " PASS: UNDERFLOW flag match \n");
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,114 @@
|
||||
module g4_dp_ext_mem (
|
||||
clk,
|
||||
wclk,
|
||||
rclk,
|
||||
rst_n,
|
||||
waddr,
|
||||
raddr,
|
||||
data,
|
||||
we,
|
||||
re,
|
||||
q
|
||||
);
|
||||
|
||||
// Memory parameters
|
||||
parameter SYNC = 0;
|
||||
parameter RAM_RW = 18;
|
||||
parameter RAM_WW = 18;
|
||||
parameter RAM_WD = 10;
|
||||
parameter RAM_RD = 10;
|
||||
parameter WRITE_ADDRESS_END = 1024;
|
||||
parameter READ_ADDRESS_END = 1024;
|
||||
|
||||
parameter WRITE_CLK = 1;
|
||||
parameter READ_CLK = 1;
|
||||
parameter WRITE_ENABLE = 1;
|
||||
parameter READ_ENABLE = 1;
|
||||
parameter RESET_POLARITY = 0;
|
||||
parameter PIPE = 1;
|
||||
|
||||
|
||||
// local inputs
|
||||
input clk;
|
||||
input wclk;
|
||||
input rclk;
|
||||
input rst_n;
|
||||
|
||||
// local inputs - memory functional bus
|
||||
input [RAM_WD-1:0] waddr;
|
||||
input [RAM_WW-1:0] data;
|
||||
|
||||
input [RAM_RD-1:0] raddr;
|
||||
input we;
|
||||
input re;
|
||||
|
||||
|
||||
//OUTPUTS
|
||||
//======
|
||||
output [RAM_RW-1:0] q;
|
||||
|
||||
generate
|
||||
if (RAM_RW > RAM_WW) begin
|
||||
|
||||
MEM_WltR #(
|
||||
.SYNC(SYNC),
|
||||
.RAM_WW(RAM_WW),
|
||||
.RAM_RW(RAM_RW),
|
||||
.RAM_WD(RAM_WD),
|
||||
.RAM_RD(RAM_RD),
|
||||
.READ_ADDRESS_END(READ_ADDRESS_END),
|
||||
.WRITE_ADDRESS_END(WRITE_ADDRESS_END),
|
||||
.WRITE_CLK(WRITE_CLK),
|
||||
.READ_CLK(READ_CLK),
|
||||
.WRITE_ENABLE(WRITE_ENABLE),
|
||||
.READ_ENABLE(READ_ENABLE),
|
||||
.RESET_POLARITY(RESET_POLARITY),
|
||||
.PIPE(PIPE)
|
||||
)
|
||||
inst0 (.clk(clk),.wclk(wclk),.rclk(rclk),.rst_n(rst_n),.waddr(waddr),.raddr(raddr),.data(data),.we(we),.re(re),.q(q));
|
||||
|
||||
end
|
||||
else if (RAM_RW < RAM_WW) begin
|
||||
|
||||
MEM_WgtR #(
|
||||
.SYNC(SYNC),
|
||||
.RAM_WW(RAM_WW),
|
||||
.RAM_RW(RAM_RW),
|
||||
.RAM_WD(RAM_WD),
|
||||
.RAM_RD(RAM_RD),
|
||||
.READ_ADDRESS_END(READ_ADDRESS_END),
|
||||
.WRITE_ADDRESS_END(WRITE_ADDRESS_END),
|
||||
.WRITE_CLK(WRITE_CLK),
|
||||
.READ_CLK(READ_CLK),
|
||||
.WRITE_ENABLE(WRITE_ENABLE),
|
||||
.READ_ENABLE(READ_ENABLE),
|
||||
.RESET_POLARITY(RESET_POLARITY),
|
||||
.PIPE(PIPE)
|
||||
)
|
||||
inst1 (.clk(clk),.wclk(wclk),.rclk(rclk),.rst_n(rst_n),.waddr(waddr),.raddr(raddr),.data(data),.we(we),.re(re),.q(q));
|
||||
|
||||
end
|
||||
else if (RAM_RW == RAM_WW) begin
|
||||
MEM_WeqR # (
|
||||
.SYNC(SYNC),
|
||||
.RAM_WW(RAM_WW),
|
||||
.RAM_RW(RAM_RW),
|
||||
.RAM_WD(RAM_WD),
|
||||
.RAM_RD(RAM_RD),
|
||||
.READ_ADDRESS_END(READ_ADDRESS_END),
|
||||
.WRITE_ADDRESS_END(WRITE_ADDRESS_END),
|
||||
.WRITE_CLK(WRITE_CLK),
|
||||
.READ_CLK(READ_CLK),
|
||||
.WRITE_ENABLE(WRITE_ENABLE),
|
||||
.READ_ENABLE(READ_ENABLE),
|
||||
.RESET_POLARITY(RESET_POLARITY),
|
||||
.PIPE(PIPE)
|
||||
)
|
||||
inst2 (.clk(clk),.wclk(wclk),.rclk(rclk),.rst_n(rst_n),.waddr(waddr),.raddr(raddr),.data(data),.we(we),.re(re),.q(q));
|
||||
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user