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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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synthesis/synplify.log.bak.4
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@@ -22,7 +22,7 @@
Starting: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro\bin64\mbin\synbatch.exe
Install: E:\Microchip\Libero_SoC_2025.1\Libero_SoC\Synplify_Pro
Hostname: SOFTWARE-PC
Date: Mon Apr 13 21:43:58 2026
Date: Fri Apr 17 05:21:33 2026
Version: V-2023.09M-5
Arguments: -product synplify_base -licensetype synplifypro_actel -batch -log synplify.log top_syn.tcl
@@ -36,66 +36,38 @@ License Option: actel_oem
Running in Vendor Mode
Implementation not found: synthesis
log file: "E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr"
add_dut_hierarchy is not supported in current product.
prepare_readback is not supported in current product.
auto_infer_blackbox is not supported in current product.
log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\top.srr"
Running: synthesis in foreground
Running top_syn|synthesis
Running Flow: compile (Compile) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
# Fri Apr 17 05:21:34 2026
Running Flow: compile_flow (Compile Process) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
# Fri Apr 17 05:21:34 2026
Running: compiler (Compile Input) on top_syn|synthesis
# Mon Apr 13 21:43:59 2026
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_comp.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
# Fri Apr 17 05:21:34 2026
compiler exited with errors
Job failed on: top_syn|synthesis
compiler completed
# Mon Apr 13 21:47:56 2026
Job: "compiler" terminated with error status: 2
See log file: "E:\AbhishekV\rising\ethernet_tpsram_test\synthesis\synlog\top_compiler.srr"
# Fri Apr 17 05:25:49 2026
Return Code: 0
Run Time:00h:03m:56s
Running: multi_srs_gen (Multi-srs Generator) on top_syn|synthesis
# Mon Apr 13 21:47:56 2026
multi_srs_gen completed
# Mon Apr 13 21:47:59 2026
Return Code: 0
Run Time:00h:00m:03s
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_mult.srs to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srs
Return Code: 2
Run Time:00h:04m:14s
Complete: Compile Process on top_syn|synthesis
Running: premap (Premap) on top_syn|synthesis
# Mon Apr 13 21:47:59 2026
premap completed with warnings
# Mon Apr 13 21:48:16 2026
Return Code: 1
Run Time:00h:00m:17s
Complete: Compile on top_syn|synthesis
Running Flow: map (Map) on top_syn|synthesis
# Mon Apr 13 21:48:16 2026
License granted for 4 parallel jobs
Running: fpga_mapper (Map & Optimize) on top_syn|synthesis
# Mon Apr 13 21:48:16 2026
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\synwork\top_m.srm to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srm
fpga_mapper completed with warnings
# Mon Apr 13 21:52:16 2026
Return Code: 1
Run Time:00h:04m:00s
Complete: Map on top_syn|synthesis
Complete: Logic Synthesis on top_syn|synthesis
Copied E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\top.srr to E:\AbhishekV\rising\ethernet_reference_design\hw\Libero_Project\synthesis\backup\top.srr
Error: At line 2 while processing "top_syn.tcl"
2
TCL script complete: "top_syn.tcl"
exit status=0
exit status=0
TCL script had errors: "top_syn.tcl"
exit status=9
exit status=9
License checkin: synplifypro_actel