head tail filter testing done
This commit is contained in:
@@ -193,6 +193,68 @@ SIZE="5136"
|
||||
PARENT="<project>\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\COREDELAYCODE_TIP.cxf"
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||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf,actgen_cxf"
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||||
STATE="utd"
|
||||
TIME="1776257512"
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||||
SIZE="1298"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
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||||
ENDFILE
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||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
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||||
STATE="utd"
|
||||
TIME="1776225025"
|
||||
SIZE="697"
|
||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
IS_READONLY="TRUE"
|
||||
ENDFILE
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||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
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||||
STATE="utd"
|
||||
TIME="1776225025"
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||||
SIZE="13955"
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||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
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||||
STATE="utd"
|
||||
TIME="1776225025"
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||||
SIZE="22096"
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||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
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||||
STATE="utd"
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||||
TIME="1776225025"
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||||
SIZE="3801"
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||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
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STATE="utd"
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||||
TIME="1776225025"
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||||
SIZE="2194"
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||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
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STATE="utd"
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||||
TIME="1776225025"
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||||
SIZE="2287"
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||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
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||||
STATE="utd"
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||||
TIME="1776225025"
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||||
SIZE="1981"
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||||
PARENT="<project>\component\Actel\DirectCore\COREFIFO\3.1.101\COREFIFO.cxf"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\COREJTAGDEBUG.cxf,actgen_cxf"
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STATE="utd"
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||||
TIME="1776096661"
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||||
@@ -478,6 +540,12 @@ SIZE="364"
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PARENT="<project>\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.cxf"
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PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.cxf"
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ENDFILE
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VALUE "<project>\component\Actel\SgCore\PF_TPSRAM\1.1.108\PF_TPSRAM.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776384266"
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SIZE="246"
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PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
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ENDFILE
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||||
VALUE "<project>\component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v,hdl"
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STATE="utd"
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TIME="1776075084"
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@@ -545,6 +613,126 @@ SIZE="13295"
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PARENT="<project>\component\work\CoreAPB3_0\CoreAPB3_0.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776257514"
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SIZE="4447"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0.v,hdl"
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STATE="utd"
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TIME="1776257512"
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SIZE="5479"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf,actgen_cxf"
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STATE="utd"
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TIME="1776257512"
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SIZE="3861"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0.cxf"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
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STATE="utd"
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TIME="1776257512"
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SIZE="997"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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IS_INCLUDED="TRUE"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
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STATE="utd"
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TIME="1776257512"
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SIZE="23"
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PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
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STATE="utd"
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TIME="1776257512"
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||||
SIZE="3286"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v,hdl"
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STATE="utd"
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||||
TIME="1776257512"
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||||
SIZE="71458"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v,hdl"
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STATE="utd"
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||||
TIME="1776257512"
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||||
SIZE="55032"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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ENDFILE
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VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v,hdl"
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STATE="utd"
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||||
TIME="1776257512"
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SIZE="4400"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v,hdl"
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STATE="utd"
|
||||
TIME="1776257511"
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||||
SIZE="2224"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v,hdl"
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||||
STATE="utd"
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||||
TIME="1776257512"
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||||
SIZE="13313"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v,hdl"
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||||
STATE="utd"
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||||
TIME="1776257512"
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||||
SIZE="2549"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v,hdl"
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||||
STATE="utd"
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||||
TIME="1776257512"
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||||
SIZE="2332"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v,hdl"
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||||
STATE="utd"
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||||
TIME="1776257512"
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||||
SIZE="33348"
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||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
IS_READONLY="TRUE"
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||||
ENDFILE
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||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v,hdl"
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||||
STATE="utd"
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||||
TIME="1776257512"
|
||||
SIZE="23539"
|
||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
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||||
STATE="utd"
|
||||
TIME="1776257512"
|
||||
SIZE="19026"
|
||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
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||||
MODULE_UNDER_TEST="testbench"
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||||
SIMULATION_TIME=" -all"
|
||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
|
||||
STATE="utd"
|
||||
TIME="1776257512"
|
||||
SIZE="401"
|
||||
PARENT="<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\COREFIFO_C0_COREFIFO_C0_0_COREFIFO.cxf"
|
||||
IS_READONLY="TRUE"
|
||||
IS_INCLUDED="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.cxf,actgen_cxf"
|
||||
STATE="utd"
|
||||
TIME="1776096662"
|
||||
@@ -993,15 +1181,40 @@ SIZE="3712"
|
||||
PARENT="<project>\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.cxf"
|
||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf,actgen_cxf"
|
||||
STATE="utd"
|
||||
TIME="1776384267"
|
||||
SIZE="4881"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v,hdl"
|
||||
STATE="utd"
|
||||
TIME="1776384266"
|
||||
SIZE="3681"
|
||||
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
|
||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf,actgen_cxf"
|
||||
STATE="utd"
|
||||
TIME="1776384266"
|
||||
SIZE="772"
|
||||
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.cxf"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v,hdl"
|
||||
STATE="utd"
|
||||
TIME="1776384266"
|
||||
SIZE="7800"
|
||||
PARENT="<project>\component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.cxf"
|
||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\top\top.cxf,actgen_cxf"
|
||||
STATE="utd"
|
||||
TIME="1776096796"
|
||||
SIZE="6732"
|
||||
TIME="1776394606"
|
||||
SIZE="7212"
|
||||
ENDFILE
|
||||
VALUE "<project>\component\work\top\top.v,hdl"
|
||||
STATE="utd"
|
||||
TIME="1776096796"
|
||||
SIZE="23777"
|
||||
TIME="1776394606"
|
||||
SIZE="26020"
|
||||
PARENT="<project>\component\work\top\top.cxf"
|
||||
IS_READONLY="TRUE"
|
||||
ENDFILE
|
||||
@@ -1020,11 +1233,21 @@ STATE="utd"
|
||||
TIME="1776096825"
|
||||
SIZE="4809"
|
||||
ENDFILE
|
||||
VALUE "<project>\hdl\fifo_to_tpsram_bridge.v,hdl"
|
||||
STATE="utd"
|
||||
TIME="1776394591"
|
||||
SIZE="3691"
|
||||
ENDFILE
|
||||
VALUE "<project>\hdl\SSDetect.v,hdl"
|
||||
STATE="utd"
|
||||
TIME="1776096660"
|
||||
SIZE="1303"
|
||||
ENDFILE
|
||||
VALUE "<project>\simulation\bfmtovec_compile.log,log"
|
||||
STATE="utd"
|
||||
TIME="1776320914"
|
||||
SIZE="407"
|
||||
ENDFILE
|
||||
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
|
||||
STATE="utd"
|
||||
TIME="1776075074"
|
||||
@@ -1049,36 +1272,157 @@ TIME="1776096673"
|
||||
SIZE="13597"
|
||||
PARENT="<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb.cxf"
|
||||
ENDFILE
|
||||
VALUE "<project>\simulation\run.do,do"
|
||||
STATE="utd"
|
||||
TIME="1776320890"
|
||||
SIZE="1760"
|
||||
ENDFILE
|
||||
VALUE "<project>\simulation\user_tb.bfm,sim"
|
||||
STATE="utd"
|
||||
TIME="1776075075"
|
||||
SIZE="7303"
|
||||
PARENT="<project>\component\Actel\DirectCore\CORESPI\5.2.104\CORESPI.cxf"
|
||||
ENDFILE
|
||||
VALUE "<project>\synthesis\synwork\layer0.so,so"
|
||||
STATE="utd"
|
||||
TIME="1776384138"
|
||||
SIZE="159"
|
||||
ENDFILE
|
||||
VALUE "<project>\synthesis\top.so,so"
|
||||
STATE="utd"
|
||||
TIME="1776097335"
|
||||
SIZE="244"
|
||||
TIME="1776395162"
|
||||
SIZE="221"
|
||||
ENDFILE
|
||||
VALUE "<project>\synthesis\top.vm,syn_vm"
|
||||
STATE="utd"
|
||||
TIME="1776097331"
|
||||
SIZE="6195567"
|
||||
TIME="1776395157"
|
||||
SIZE="6235009"
|
||||
ENDFILE
|
||||
VALUE "<project>\synthesis\top_syn.prj,prj"
|
||||
STATE="utd"
|
||||
TIME="1776097336"
|
||||
SIZE="11812"
|
||||
TIME="1776395163"
|
||||
SIZE="12159"
|
||||
ENDFILE
|
||||
VALUE "<project>\synthesis\top_vm.sdc,syn_sdc"
|
||||
STATE="utd"
|
||||
TIME="1776097332"
|
||||
TIME="1776395158"
|
||||
SIZE="6962"
|
||||
ENDFILE
|
||||
ENDLIST
|
||||
LIST UsedFile
|
||||
ENDLIST
|
||||
LIST NewModulesInfo
|
||||
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work"
|
||||
FILE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work"
|
||||
FILE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CORETSE::work"
|
||||
FILE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\core_evaluation\CoreTSE.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work"
|
||||
FILE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
|
||||
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "top::work"
|
||||
FILE "<project>\component\work\top\top.v,hdl"
|
||||
LIST SynthesisConstraints
|
||||
@@ -1094,11 +1438,229 @@ VALUE "<project>\constraint\top_derived_constraints.sdc,sdc"
|
||||
VALUE "<project>\constraint\timing_user_constraints.sdc,sdc"
|
||||
VALUE "<project>\constraint\io\io_constraints.pdc,io_pdc"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSYNTHESIS(<project>\synthesis\top.vm,syn_vm)=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CoreAPB3::COREAPB3_LIB"
|
||||
FILE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
|
||||
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB"
|
||||
FILE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CORESPI::CORESPI_LIB"
|
||||
FILE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v,hdl"
|
||||
LIST Other_Association
|
||||
VALUE "<project>\simulation\user_tb.bfm,sim"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST AssociatedStimulus
|
||||
LIST COREJTAGDEBUG
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST CORESPI
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST CORETSE
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST CoreAPB3
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
ENDLIST
|
||||
LIST Core_reset_pf_Core_reset_pf_0_CORERESET_PF
|
||||
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST Other_Association
|
||||
LIST COREFIFO_C0_COREFIFO_C0_0_COREFIFO
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\top_define.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v,tb_hdl"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v,tb_hdl"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\wave.do,do"
|
||||
VALUE "<project>\component\work\COREFIFO_C0\COREFIFO_C0_0\mti\scripts\runall.do,do"
|
||||
ENDLIST
|
||||
LIST COREJTAGDEBUG
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_host_emulator.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_jtag_tap.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\rtl\vlog\test\corejtagdebug_testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\mti\corejtagdebug_wave.do,do"
|
||||
ENDLIST
|
||||
LIST CORESPI
|
||||
VALUE "<project>\simulation\user_tb.bfm,sim"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\amba_bfm\bfm_package.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\bfmtovec_compile.do,do"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORESPI\5.2.104\mti\wave.do,do"
|
||||
ENDLIST
|
||||
LIST CORETSE
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CORETSE\4.0.124\mti\scripts\wave.do,do"
|
||||
ENDLIST
|
||||
LIST CoreAPB3
|
||||
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
|
||||
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.2.100\mti\scripts\wave_user.do,do"
|
||||
ENDLIST
|
||||
LIST CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb
|
||||
VALUE "<project>\simulation\coreuart_usertb_apb_master.bfm,sim"
|
||||
VALUE "<project>\simulation\coreuart_usertb_include.bfm,sim"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\coreparameters.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbl.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahblapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apbtoapb.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v,tb_hdl"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\bfmtovec_compile.do,do"
|
||||
VALUE "<project>\component\work\CoreUARTapb_0\CoreUARTapb_0_0\mti\scripts\wave_vlog_amba.do,do"
|
||||
ENDLIST
|
||||
LIST Core_reset_pf_Core_reset_pf_0_CORERESET_PF
|
||||
VALUE "<project>\component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v,tb_hdl"
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST SimulationOptions
|
||||
UseAutomaticDoFile=true
|
||||
@@ -1196,6 +1758,90 @@ IS32BIT="1"
|
||||
EndProfile
|
||||
ENDLIST
|
||||
LIST ProjectState5.1
|
||||
LIST "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work"
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CORETSE::work"
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work"
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "top::work"
|
||||
LIST Impl1
|
||||
ideSYNTHESIS(<project>\synthesis\top.vm,syn_vm)=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CoreAPB3::COREAPB3_LIB"
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "COREJTAGDEBUG::COREJTAGDEBUG_LIB"
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST "CORESPI::CORESPI_LIB"
|
||||
LIST Impl1
|
||||
ideSTIMULUS=StateSuccess
|
||||
LIST FlowOptions
|
||||
UsePhySynth=FALSE
|
||||
UseSynth=TRUE
|
||||
UseFhbAutoInst=FALSE
|
||||
ENDLIST
|
||||
Used_File_List
|
||||
ENDUsed_File_List
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
ENDLIST
|
||||
LIST ExcludePackageForSimulation
|
||||
ENDLIST
|
||||
@@ -1225,6 +1871,29 @@ LIST "CORECDR4_CNTL_TIP::work","component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0
|
||||
ENDLIST
|
||||
LIST "COREDELAYCODE_TIP::work","component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0::work","component\work\COREFIFO_C0\COREFIFO_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_async::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_ram_wrapper::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_async::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_async.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_graytobinconv::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_graytobinconv.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_nstagessync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_nstagessync.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_LSRAM_top::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREJTAGDEBUG_C0::work","component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "COREJTAGDEBUG::COREJTAGDEBUG_LIB","component\Actel\DirectCore\COREJTAGDEBUG\4.0.100\core\corejtagdebug.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
@@ -1256,6 +1925,13 @@ LIST "CoreUARTapb_0_CoreUARTapb_0_0_Rx_async::work","component\work\CoreUARTapb_
|
||||
ENDLIST
|
||||
LIST "CoreUARTapb_0_CoreUARTapb_0_0_Tx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Tx_async.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_sync_scntr::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_sync_scntr.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_ram_wrapper::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_ram_wrapper.v","FALSE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_LSRAM_top::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO_C0_COREFIFO_C0_0_LSRAM_top.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "CoreUARTapb_0_CoreUARTapb_0_0_COREUART::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUART.v","FALSE","FALSE"
|
||||
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Clock_gen.v","FALSE","FALSE"
|
||||
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_Rx_async::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\Rx_async.v","FALSE","FALSE"
|
||||
@@ -1388,6 +2064,8 @@ LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.20
|
||||
ENDLIST
|
||||
LIST "miv_rv32_csr_gpr_state_reg::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "fifo_to_tpsram_bridge::work","hdl\fifo_to_tpsram_bridge.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "miv_rv32_axi_egress_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "miv_rv32_axi_egress_slip_buffer::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
||||
@@ -1461,8 +2139,8 @@ LIST "miv_rv32_bistdualdata_behav::work","component\Microsemi\MiV\MIV_RV32\3.1.2
|
||||
SUBBLOCK "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "miv_rv32_bistmux::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
||||
SUBBLOCK "pmc_logic_mux_behav::work","","FALSE","FALSE"
|
||||
SUBBLOCK "miv_rv32_logic_mux_behav_v2::work","component\Microsemi\MiV\MIV_RV32\3.1.200\hart_merged\miv_rv32_hart_merged.v","FALSE","FALSE"
|
||||
SUBBLOCK "pmc_logic_mux_behav::work","","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "miv_rv32_bootrom::work","component\Microsemi\MiV\MIV_RV32\3.1.200\subsys_merged\miv_rv32_subsys_merged.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
@@ -1754,6 +2432,11 @@ SUBBLOCK "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC::wo
|
||||
ENDLIST
|
||||
LIST "PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC::work","component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "PF_TPSRAM_C0::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0_0\PF_TPSRAM_C0_PF_TPSRAM_C0_0_PF_TPSRAM.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "pmc_logic_mux_behav::work","","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "pmc_sync_flop_behav_v3::work","","FALSE","FALSE"
|
||||
@@ -1763,6 +2446,7 @@ ENDLIST
|
||||
LIST "SSDetect::work","hdl\SSDetect.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "top::work","component\work\top\top.v","TRUE","FALSE"
|
||||
SUBBLOCK "COREFIFO_C0::work","component\work\COREFIFO_C0\COREFIFO_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "COREJTAGDEBUG_C0::work","component\work\COREJTAGDEBUG_C0\COREJTAGDEBUG_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "CORESPI_0::work","component\work\CORESPI_0\CORESPI_0.v","TRUE","FALSE"
|
||||
SUBBLOCK "CORETSE_0::work","component\work\CORETSE_0\CORETSE_0.v","TRUE","FALSE"
|
||||
@@ -1773,9 +2457,15 @@ SUBBLOCK "MIV_RV32_C0::work","component\work\MIV_RV32_C0\MIV_RV32_C0.v","TRUE","
|
||||
SUBBLOCK "PF_CCC_0::work","component\work\PF_CCC_0\PF_CCC_0.v","TRUE","FALSE"
|
||||
SUBBLOCK "PF_IOD_CDR_C0::work","component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "PF_IOD_CDR_CCC_C0::work","component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "PF_TPSRAM_C0::work","component\work\PF_TPSRAM_C0\PF_TPSRAM_C0.v","TRUE","FALSE"
|
||||
SUBBLOCK "SSDetect::work","hdl\SSDetect.v","FALSE","FALSE"
|
||||
SUBBLOCK "fifo_to_tpsram_bridge::work","hdl\fifo_to_tpsram_bridge.v","FALSE","FALSE"
|
||||
SUBBLOCK "pf_init_monitor_0::work","component\work\pf_init_monitor_0\pf_init_monitor_0.v","TRUE","FALSE"
|
||||
ENDLIST
|
||||
LIST "clock_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "COREFIFO_C0_COREFIFO_C0_0_corefifo_fwft::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\corefifo_fwft.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
LIST "corereset_pf_tb::work","component\work\Core_reset_pf\Core_reset_pf_0\test\corereset_pf_tb.v","FALSE","TRUE"
|
||||
SUBBLOCK "Core_reset_pf_Core_reset_pf_0_CORERESET_PF::work","component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v","FALSE","FALSE"
|
||||
ENDLIST
|
||||
@@ -1816,12 +2506,27 @@ LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_
|
||||
ENDLIST
|
||||
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFMA1l1OII::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "fifo_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "fifo_monitor::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "g4_dp_ext_mem::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v","FALSE","TRUE"
|
||||
SUBBLOCK "MEM_WgtR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v","FALSE","TRUE"
|
||||
SUBBLOCK "MEM_WltR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v","FALSE","TRUE"
|
||||
SUBBLOCK "MEM_WeqR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "MEM_WeqR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WeqR.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "CoreUARTapb_0_CoreUARTapb_0_0_BFM_MAIN::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "gl::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "MEM_WgtR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WgtR.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "MEM_WltR::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\MEM_WltR.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "ml::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
||||
@@ -1831,6 +2536,13 @@ SUBBLOCK "CORETSE::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\co
|
||||
SUBBLOCK "CoreTSE_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_tb.v","FALSE","TRUE"
|
||||
SUBBLOCK "CoreTSE_AXI4S_tb::work","component\Actel\DirectCore\CORETSE\4.0.124\rtl\vlog\test\user\tbi\CoreTSE_AXI4S_tb.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "testbench::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
|
||||
SUBBLOCK "COREFIFO_C0_COREFIFO_C0_0_COREFIFO::work","component\work\COREFIFO_C0\COREFIFO_C0_0\rtl\vlog\core\COREFIFO.v","FALSE","FALSE"
|
||||
SUBBLOCK "clock_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\clock_driver.v","FALSE","TRUE"
|
||||
SUBBLOCK "fifo_driver::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_driver.v","FALSE","TRUE"
|
||||
SUBBLOCK "fifo_monitor::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\fifo_monitor.v","FALSE","TRUE"
|
||||
SUBBLOCK "g4_dp_ext_mem::work","component\Actel\DirectCore\COREFIFO\3.1.101\rtl\vlog\test\user\g4_dp_ext_mem.v","FALSE","TRUE"
|
||||
ENDLIST
|
||||
LIST "testbench::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
|
||||
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core\CoreUARTapb.v","FALSE","FALSE"
|
||||
SUBBLOCK "CoreUARTapb_0_CoreUARTapb_0_0_BFM_APB::work","component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
|
||||
|
||||
Reference in New Issue
Block a user