abhishek/Ethernet-IP-Core
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head tail filter testing done

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abhishekpythons
2026-04-17 18:14:15 +05:30
parent e4b91625ea
commit a8e7c14f45
294 changed files with 209839 additions and 208687 deletions
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component/work/top/top.v
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@@ -1,5 +1,5 @@
//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Wed Apr 15 22:44:24 2026
// Created by SmartDesign Fri Apr 17 08:26:46 2026
// Version: 2025.1 2025.1.0.14
//////////////////////////////////////////////////////////////////////
@@ -107,10 +107,9 @@ wire [31:0] CORETSE_0_MRXDAT;
wire CORETSE_0_MRXEOF;
wire CORETSE_0_MRXRDY;
wire CORETSE_0_MRXSOF;
wire CORETSE_0_MTXACPT;
wire [9:0] CORETSE_0_TCG;
wire fifo_to_tpsram_bridge_0_fifo_rd_en;
wire [9:0] fifo_to_tpsram_bridge_0_ram_w_addr_1;
wire [10:0] fifo_to_tpsram_bridge_0_ram_w_addr_4;
wire [31:0] fifo_to_tpsram_bridge_0_ram_w_data;
wire fifo_to_tpsram_bridge_0_ram_w_en;
wire INBUF_DIFF_0_Y;
@@ -204,7 +203,8 @@ wire [9:0] ANX_STATE_net_0;
//--------------------------------------------------------------------
wire GND_net;
wire VCC_net;
wire [9:0] R_ADDR_const_net_0;
wire [31:0] MTXDAT_const_net_0;
wire [10:0] R_ADDR_const_net_0;
//--------------------------------------------------------------------
// Inverted Nets
//--------------------------------------------------------------------
@@ -230,7 +230,8 @@ wire [7:0] CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0;
//--------------------------------------------------------------------
assign GND_net = 1'b0;
assign VCC_net = 1'b1;
assign R_ADDR_const_net_0 = 10'h000;
assign MTXDAT_const_net_0 = 32'h00000000;
assign R_ADDR_const_net_0 = 11'h000;
//--------------------------------------------------------------------
// Inversions
//--------------------------------------------------------------------
@@ -433,11 +434,11 @@ CORESPI_0 CORESPI_0_0(
CORETSE_0 CORETSE_0_inst_0(
// Inputs
.MTXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.MTXRDY ( CORETSE_0_MRXRDY ),
.MTXRDY ( GND_net ),
.MTXSOF ( CORETSE_0_MRXSOF ),
.MTXEOF ( CORETSE_0_MRXEOF ),
.MRXCLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.MRXACPT ( CORETSE_0_MTXACPT ),
.MRXACPT ( VCC_net ),
.TXCLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
.RXCLK ( PF_IOD_CDR_C0_0_RX_CLK_R ),
.TBI_TX_CLK ( PF_IOD_CDR_CCC_C0_0_TX_CLK_G ),
@@ -449,13 +450,13 @@ CORETSE_0 CORETSE_0_inst_0(
.PENABLE ( CoreAPB3_0_0_APBmslave0_PENABLE ),
.PWRITE ( CoreAPB3_0_0_APBmslave0_PWRITE ),
.PSEL ( CoreAPB3_0_0_APBmslave0_PSELx ),
.MTXDAT ( CORETSE_0_MRXDAT ),
.MTXDAT ( MTXDAT_const_net_0 ),
.MTXBYTEVALID ( CORETSE_0_MRXBYTEVALID ),
.RCG ( PF_IOD_CDR_C0_0_RX_DATA ),
.PADDR ( CoreAPB3_0_0_APBmslave0_PADDR ),
.PWDATA ( CoreAPB3_0_0_APBmslave0_PWDATA ),
// Outputs
.MTXACPT ( CORETSE_0_MTXACPT ),
.MTXACPT ( ),
.MTXHWM ( ),
.MRXRDY ( CORETSE_0_MRXRDY ),
.MRXSOF ( CORETSE_0_MRXSOF ),
@@ -511,7 +512,7 @@ fifo_to_tpsram_bridge fifo_to_tpsram_bridge_0(
.transfer_enable ( VCC_net ),
// Outputs
.fifo_rd_en ( fifo_to_tpsram_bridge_0_fifo_rd_en ),
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
.ram_w_addr ( fifo_to_tpsram_bridge_0_ram_w_addr_4 ),
.ram_w_data ( fifo_to_tpsram_bridge_0_ram_w_data ),
.ram_w_en ( fifo_to_tpsram_bridge_0_ram_w_en ),
.buffer_full ( )
@@ -633,7 +634,7 @@ PF_TPSRAM_C0 PF_TPSRAM_C0_0(
.W_EN ( fifo_to_tpsram_bridge_0_ram_w_en ),
.CLK ( PF_CCC_0_0_OUT0_FABCLK_0 ),
.W_DATA ( fifo_to_tpsram_bridge_0_ram_w_data ),
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_1 ),
.W_ADDR ( fifo_to_tpsram_bridge_0_ram_w_addr_4 ),
.R_ADDR ( R_ADDR_const_net_0 ),
// Outputs
.R_DATA ( R_DATA_net_0 )